From 20620f0e241b60afe3a1575d9ea82cbf4654b4f2 Mon Sep 17 00:00:00 2001
From: Insun Song <isong@broadcom.com>
Date: Tue, 28 Jul 2015 14:29:04 -0700
Subject: [PATCH] net: wireless: bcmdhd: fix for PICe DPM timeout error

=> 1) bug:22657897
set correct sequence setting LTR/ASPM bit to prevent
DPM timeout error

Bug: 22916761
Change-Id: I33f23e4f43324c9c4dab0f0c0e0868c338f59ae2
Signed-off-by: Insun Song <isong@broadcom.com>
---
 arch/arm/mach-msm/pcie.c | 14 +++++++-------
 1 file changed, 7 insertions(+), 7 deletions(-)

diff --git a/arch/arm/mach-msm/pcie.c b/arch/arm/mach-msm/pcie.c
index d8df86e5f76e..ddc381bc40e4 100644
--- a/arch/arm/mach-msm/pcie.c
+++ b/arch/arm/mach-msm/pcie.c
@@ -895,19 +895,19 @@ static void msm_pcie_config_l1ss(struct msm_pcie_dev_t *dev)
 		msm_pcie_write_mask(dev->dm_core + PCIE20_L1SUB_CONTROL1, 0,
 			BIT(30)|BIT(23)|BIT(21)|BIT(3)|BIT(2)|BIT(1)|BIT(0));
 
-		/* EP: Set ASPM(0xbc) */
-		msm_pcie_write_mask(dev->conf + PCIE20_CAP_LINKCTRLSTATUS_BRCM, 0,
-			BIT(8)|BIT(6)|BIT(1)|BIT(0));
-		/* RC: Set ASPM and ComClkConfig */
-		msm_pcie_write_mask(dev->dm_core + PCIE20_CAP_LINKCTRLSTATUS, 0,
-			BIT(6)|BIT(1)|BIT(0));
-
 		/* EP: Set LTR Latency (0x1B4) */
 		msm_pcie_write_mask(dev->conf + PCIE20_LTR_MAX_SNOOP_LATENCY_BRCM, 0,
 			BIT(28)|BIT(17)|BIT(16)|BIT(12)|BIT(1)|BIT(0));
 		/* EP: Toggle LTR Enable(0xd4) */
 		msm_pcie_write_mask(dev->conf + PCIE20_DEVICE_CONTROL2_STATUS2_BRCM, 0, BIT(10));
 
+		/* RC: Set ASPM and ComClkConfig */
+		msm_pcie_write_mask(dev->dm_core + PCIE20_CAP_LINKCTRLSTATUS, 0,
+			BIT(6)|BIT(1)|BIT(0));
+		/* EP: Set ASPM(0xbc) */
+		msm_pcie_write_mask(dev->conf + PCIE20_CAP_LINKCTRLSTATUS_BRCM, 0,
+			BIT(8)|BIT(6)|BIT(1)|BIT(0));
+
 		PCIE_DBG(dev, "EP's CAP_LINKCTRLSTATUS:0x%x\n",
 			readl_relaxed(dev->conf + PCIE20_CAP_LINKCTRLSTATUS_BRCM));
 		PCIE_DBG(dev, "EP's L1SUB_CONTROL1:0x%x\n",
-- 
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