From 749b9ac83ab38dd7673d899f3a2d2d0d66d93cdd Mon Sep 17 00:00:00 2001
From: "sol.yu" <sol.yu@lge.com>
Date: Thu, 4 Dec 2014 17:09:48 +0900
Subject: [PATCH] arm/dt: lenok: Fix the flickering on display

This issue happens when POLED PANEL gate driving voltage is unstable.
Adjust the panel driving voltage level to avoid this issue.

Change VGL to -7.5V from -6.5V. It doesn't affect on power.

Bug: 18087424
Change-Id: I985531ef3d2424306ca2eca2d571174a80491cd4
Signed-off-by: sol.yu <sol.yu@lge.com>
Signed-off-by: Devin Kim <dojip.kim@lge.com>
---
 .../apq8026-lenok/apq8026-lenok-panel.dtsi    | 30 +++++++++----------
 1 file changed, 15 insertions(+), 15 deletions(-)

diff --git a/arch/arm/boot/dts/apq8026-lenok/apq8026-lenok-panel.dtsi b/arch/arm/boot/dts/apq8026-lenok/apq8026-lenok-panel.dtsi
index 49fee091e094..bfbee580b8ca 100644
--- a/arch/arm/boot/dts/apq8026-lenok/apq8026-lenok-panel.dtsi
+++ b/arch/arm/boot/dts/apq8026-lenok/apq8026-lenok-panel.dtsi
@@ -78,7 +78,7 @@
 					39 00 00 00 00 00 18 DB
 					01 A9 00 92 FF 11
 					1C 34 43 2F 84 85
-					40 65 27 28 12 12
+					40 67 27 28 12 12
 					12 00 00 29 10 /*40nit_30hz*/
 					05 01 00 00 80 00 01 39 /*Idle Mode On*/
 					05 01 00 00 40 00 01 29 /*Display On*/
@@ -86,85 +86,85 @@
 					39 01 00 00 20 00 18 DB
 					01 A9 40 92 FF 11
 					1C 34 43 2F 84 85
-					40 65 27 28 12 12
+					40 67 27 28 12 12
 					12 00 00 29 10 /*40nit_30hz*/
 
 					39 01 00 00 30 00 18 DB
 					01 A9 60 92 FF 11
 					1C 34 43 2F 84 85
-					40 65 27 28 12 12
+					40 67 27 28 12 12
 					12 00 00 29 10 /*40nit_30hz*/
 
 					39 01 00 00 30 00 18 DB
 					01 A9 80 92 FF 11
 					1C 34 43 2F 84 85
-					40 65 27 28 12 12
+					40 67 27 28 12 12
 					12 00 00 29 10 /*40nit_30hz*/
 
 					39 01 00 00 30 00 18 DB
 					01 A9 A0 92 FF 11
 					1C 34 43 2F 84 85
-					40 65 27 28 12 12
+					40 67 27 28 12 12
 					12 00 00 29 10 /*40nit_30hz*/
 
 					39 01 00 00 30 00 18 DB
 					01 A9 C0 92 FF 11
 					1C 34 43 2F 84 85
-					40 65 27 28 12 12
+					40 67 27 28 12 12
 					12 00 00 29 10 /*40nit_30hz*/
 
 					39 01 00 00 20 00 18 DB
 					01 A9 E0 92 FF 11
 					1C 34 43 2F 84 85
-					40 65 27 28 12 12
+					40 67 27 28 12 12
 					12 00 00 29 10 /*40nit_30hz*/
 
 					39 01 00 00 20 00 18 DB
 					01 A9 00 93 FF 11
 					1C 34 43 2F 84 85
-					40 65 27 28 12 12
+					40 67 27 28 12 12
 					12 00 00 29 10 /*40nit_30hz*/
 
 					39 01 00 00 20 00 18 DB
 					01 A9 10 93 FF 11
 					1C 34 43 2F 84 85
-					40 65 27 28 12 12
+					40 67 27 28 12 12
 					12 00 00 29 10 /*40nit_30hz*/
 
 					39 01 00 00 20 00 18 DB
 					01 A9 20 93 FF 11
 					1C 34 43 2F 84 85
-					40 65 27 28 12 12
+					40 67 27 28 12 12
 					12 00 00 29 10 /*40nit_30hz*/
 
 					39 01 00 00 20 00 18 DB
 					01 A9 30 93 FF 11
 					1C 34 43 2F 84 85
-					40 65 27 28 12 12
+					40 67 27 28 12 12
 					12 00 00 29 10 /*40nit_30hz*/
 
 					39 01 00 00 10 00 18 DB
 					01 A9 40 93 FF 11
 					1C 34 43 2F 84 85
-					40 65 27 28 12 12
+					40 67 27 28 12 12
 					12 00 00 29 10 /*40nit_30hz*/
 
 					39 01 00 00 10 00 18 DB
 					01 A9 50 93 FF 11
 					1C 34 43 2F 84 85
-					40 65 27 28 12 12
+					40 67 27 28 12 12
 					12 00 00 29 10 /*40nit_30hz*/
 
 					39 01 00 00 10 00 18 DB
 					01 A9 60 93 FF 11
 					1C 34 43 2F 84 85
-					40 65 27 28 12 12
+					40 67 27 28 12 12
 					12 00 00 29 10 /*40nit_30hz*/
 
 					39 01 00 00 00 00 18 DB
 					01 A9 80 93 FF 11
 					1C 34 43 2F 84 85
-					40 65 27 28 12 12
+					40 67 27 28 12 12
 					12 00 00 29 10 /*40nit_30hz*/
 					];
 		qcom,mdss-dsi-idle-on-command-state = "dsi_hs_mode";
-- 
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