diff --git a/include/llvm/CodeGen/Passes.h b/include/llvm/CodeGen/Passes.h index 5a3ba4e3496a62c070efed8a573af3ff38f233c8..74fd44c3b082ef995c2acc7d62aa54f9b56741dd 100644 --- a/include/llvm/CodeGen/Passes.h +++ b/include/llvm/CodeGen/Passes.h @@ -165,6 +165,8 @@ public: bool getEnableTailMerge() const { return EnableTailMerge; } void setEnableTailMerge(bool Enable) { setOpt(EnableTailMerge, Enable); } + bool isSerializing() const; + /// Allow the target to override a specific pass without overriding the pass /// pipeline. When passes are added to the standard pipeline at the /// point where StandardID is expected, add TargetID in its place. diff --git a/lib/CodeGen/BranchFolding.cpp b/lib/CodeGen/BranchFolding.cpp index 69b4b3dbf76bbedc408bbbf5fdfa2df075bd4caa..dcdb38f1a193bd1df267901f304be2949339cac3 100644 --- a/lib/CodeGen/BranchFolding.cpp +++ b/lib/CodeGen/BranchFolding.cpp @@ -99,6 +99,7 @@ bool BranchFolderPass::runOnMachineFunction(MachineFunction &MF) { bool EnableTailMerge = !MF.getTarget().requiresStructuredCFG() && PassConfig->getEnableTailMerge(); BranchFolder Folder(EnableTailMerge, /*CommonHoist=*/true, + PassConfig->isSerializing(), getAnalysis<MachineBlockFrequencyInfo>(), getAnalysis<MachineBranchProbabilityInfo>()); return Folder.OptimizeFunction(MF, MF.getSubtarget().getInstrInfo(), @@ -107,10 +108,11 @@ bool BranchFolderPass::runOnMachineFunction(MachineFunction &MF) { } BranchFolder::BranchFolder(bool defaultEnableTailMerge, bool CommonHoist, + bool supportSerializing, const MachineBlockFrequencyInfo &FreqInfo, const MachineBranchProbabilityInfo &ProbInfo) - : EnableHoistCommonCode(CommonHoist), MBBFreqInfo(FreqInfo), - MBPI(ProbInfo) { + : EnableHoistCommonCode(CommonHoist), SupportSerializing(supportSerializing), + MBBFreqInfo(FreqInfo), MBPI(ProbInfo) { switch (FlagEnableTailMerge) { case cl::BOU_UNSET: EnableTailMerge = defaultEnableTailMerge; break; case cl::BOU_TRUE: EnableTailMerge = true; break; @@ -909,7 +911,9 @@ bool BranchFolder::TryTailMergeBlocks(MachineBasicBlock *SuccBB, } DEBUG(dbgs() << "\n"); // Common tails do not have a sensible mapping to basic blocks - MBB->setBasicBlock(0); + if (SupportSerializing) { + MBB->setBasicBlock(0); + } // We leave commonTailIndex in the worklist in case there are other blocks // that match it with a smaller number of instructions. MadeChange = true; @@ -1288,9 +1292,9 @@ ReoptimizeBlock: PrevBB.removeSuccessor(PrevBB.succ_begin()); assert(PrevBB.succ_empty()); PrevBB.transferSuccessors(MBB); - // If previous block is not associated with MBB (e.g., because it was tail merged), - // set it to the MBB of this block - if(PrevBB.getBasicBlock() == 0) { + if (PrevBB.getBasicBlock() == 0) { + // If previous block is not associated with MBB (e.g., because it was tail merged), + // set it to the MBB of this block PrevBB.setBasicBlock(MBB->getBasicBlock()); } MadeChange = true; diff --git a/lib/CodeGen/BranchFolding.h b/lib/CodeGen/BranchFolding.h index d759d53e27f2f50346012aa17942eaebfc16e44b..fe46d0f5849e50ca5c130d9e2a52b59d01374c05 100644 --- a/lib/CodeGen/BranchFolding.h +++ b/lib/CodeGen/BranchFolding.h @@ -27,6 +27,7 @@ namespace llvm { class LLVM_LIBRARY_VISIBILITY BranchFolder { public: explicit BranchFolder(bool defaultEnableTailMerge, bool CommonHoist, + bool supportSerializing, const MachineBlockFrequencyInfo &MBFI, const MachineBranchProbabilityInfo &MBPI); @@ -93,6 +94,7 @@ namespace llvm { bool EnableTailMerge; bool EnableHoistCommonCode; + bool SupportSerializing; const TargetInstrInfo *TII; const TargetRegisterInfo *TRI; MachineModuleInfo *MMI; diff --git a/lib/CodeGen/IfConversion.cpp b/lib/CodeGen/IfConversion.cpp index e5143132d23014c343dafe3bf8b7d52c21b3d951..72608a584b2fe472924e49a811a9c3bb1632d536 100644 --- a/lib/CodeGen/IfConversion.cpp +++ b/lib/CodeGen/IfConversion.cpp @@ -164,6 +164,7 @@ namespace { const MachineBlockFrequencyInfo *MBFI; const MachineBranchProbabilityInfo *MBPI; MachineRegisterInfo *MRI; + bool SupportSerializing; LivePhysRegs Redefs; LivePhysRegs DontKill; @@ -183,6 +184,7 @@ namespace { void getAnalysisUsage(AnalysisUsage &AU) const override { AU.addRequired<MachineBlockFrequencyInfo>(); AU.addRequired<MachineBranchProbabilityInfo>(); + AU.addRequired<TargetPassConfig>(); MachineFunctionPass::getAnalysisUsage(AU); } @@ -284,6 +286,8 @@ bool IfConverter::runOnMachineFunction(MachineFunction &MF) { MBPI = &getAnalysis<MachineBranchProbabilityInfo>(); MRI = &MF.getRegInfo(); SchedModel.init(ST.getSchedModel(), &ST, TII); + TargetPassConfig *PassConfig = &getAnalysis<TargetPassConfig>(); + SupportSerializing = PassConfig->isSerializing(); if (!TII) return false; @@ -292,7 +296,7 @@ bool IfConverter::runOnMachineFunction(MachineFunction &MF) { bool BFChange = false; if (!PreRegAlloc) { // Tail merge tend to expose more if-conversion opportunities. - BranchFolder BF(true, false, *MBFI, *MBPI); + BranchFolder BF(true, false, SupportSerializing, *MBFI, *MBPI); BFChange = BF.OptimizeFunction(MF, TII, ST.getRegisterInfo(), getAnalysisIfAvailable<MachineModuleInfo>()); } @@ -425,7 +429,7 @@ bool IfConverter::runOnMachineFunction(MachineFunction &MF) { BBAnalysis.clear(); if (MadeChange && IfCvtBranchFold) { - BranchFolder BF(false, false, *MBFI, *MBPI); + BranchFolder BF(false, false, SupportSerializing, *MBFI, *MBPI); BF.OptimizeFunction(MF, TII, MF.getSubtarget().getRegisterInfo(), getAnalysisIfAvailable<MachineModuleInfo>()); } @@ -483,9 +487,6 @@ bool IfConverter::ValidSimple(BBInfo &TrueBBI, unsigned &Dups, if (TrueBBI.IsBrAnalyzable) return false; - // if (!TrueBBI.BB->succ_empty()) - // return false; - if (TrueBBI.BB->pred_size() > 1) { if (TrueBBI.CannotBeCopied || !TII->isProfitableToDupForIfCvt(*TrueBBI.BB, TrueBBI.NonPredSize, @@ -1649,8 +1650,10 @@ void IfConverter::CopyAndPredicateBlock(BBInfo &ToBBI, BBInfo &FromBBI, ToBBI.ClobbersPred |= FromBBI.ClobbersPred; ToBBI.IsAnalyzed = false; - // remove mapping from dupped block (no longer unique) - FromBBI.BB->setBasicBlock(0); + if (SupportSerializing) { + // remove mapping from dupped block (no longer unique) + FromBBI.BB->setBasicBlock(0); + } ++NumDupBBs; } @@ -1768,8 +1771,10 @@ void IfConverter::MergeBlocks(BBInfo &ToBBI, BBInfo &FromBBI, bool AddEdges) { ToBBI.HasFallThrough = FromBBI.HasFallThrough; ToBBI.IsAnalyzed = false; FromBBI.IsAnalyzed = false; - // remove mapping from merged block - FromBBI.BB->setBasicBlock(0); + if (SupportSerializing) { + // remove mapping from merged block + FromBBI.BB->setBasicBlock(0); + } } FunctionPass * diff --git a/lib/CodeGen/Passes.cpp b/lib/CodeGen/Passes.cpp index a5a9a4d3faa039357e60f74f6345462123d4da20..35eb3444ad086c5f65700a07bd4c14af79365a34 100644 --- a/lib/CodeGen/Passes.cpp +++ b/lib/CodeGen/Passes.cpp @@ -250,7 +250,7 @@ TargetPassConfig::TargetPassConfig(TargetMachine *tm, PassManagerBase &pm) : ImmutablePass(ID), PM(&pm), StartBefore(nullptr), StartAfter(nullptr), StopAfter(nullptr), Started(true), Stopped(false), AddingMachinePasses(false), TM(tm), Impl(nullptr), Initialized(false), - DisableVerify(false), EnableTailMerge(true) { + DisableVerify(false), EnableTailMerge(true) { Impl = new PassConfigImpl(); @@ -612,12 +612,17 @@ void TargetPassConfig::addMachinePasses() { addPass(&LiveDebugValuesID, false); // Serialize machine code - if (! SerializeMachineCode.empty()) + if (isSerializing()) { addSerializePass(SerializeMachineCode, SerializeRoots, SerializePreemitBitcode); + } AddingMachinePasses = false; } +bool TargetPassConfig::isSerializing() const { + return !SerializeMachineCode.empty(); +} + /// Add standard serialization to PML format void TargetPassConfig::addSerializePass(std::string& OutFile, ArrayRef<std::string> Roots,