main.tex

% vim:set spell
\section{Near-Memory-Computing}

% TODO spell checking

\begin{frame}[fragile]{Near-Memory-Computing}
    \begin{figure}
        \centering
        \resizebox{\textwidth}{!}{
            \input{figures/classictopology}
        }
        \caption{Classic CPU and memory topology}
    \end{figure}

    All data which does not fit in the cache has to be transferred from CPU to memory and vice versa.
\end{frame}

\begin{frame}[fragile]{Near-Memory-Computing}
    \begin{figure}
        \centering
        \frame{\includegraphics[width=200pt]{figures/memoryspeed.pdf}}
        \caption{Processor vs. memory performance \cite{carvalho2002gap}}
    \end{figure}

    Memory performance relative to processor speed worsened.
\end{frame}

\begin{frame}[fragile]{Near-Memory-Computing}
    \begin{figure}
        \centering
        \resizebox{\textwidth}{!}{
            \input{figures/cramtopology}
        }
        \caption{In-Memory-Computing topology}
    \end{figure}

    Data transfer cost can be avoided by not transferring data in the first place.

    The CPU only performs control tasks and delegates calculations to CRAM\footnote{Computational RAM has already been proposed in 1992 \cite{elliott1992computational}}
    which is memory that performs calculations on the same chip.
    %reduce energy consumption
    %unnecessary transfers are avoided
    %bandwidth is no longer limited to memory interface
\end{frame}

\begin{frame}[fragile]{Near-Memory-Computing}
    problems with IMC:

    \begin{itemize}[<+->]
        \item based on new chip technologies
        \item CRAM requires special programming
        \item research is mostly based on simulations
    \end{itemize}

    \alert{\uncover<4->{$\,\to\,$ adaption of IMC difficult}}
\end{frame}

\begin{frame}[fragile]{Near-Memory-Computing}
    \begin{figure}
        \centering
        \resizebox{\textwidth}{!}{
            \input{figures/nmctopology}
        }
        \caption{example of a Near-Memory-Computing topology}
    \end{figure}

    NMC can be used as compromise between IMC and a classic topology.

    A high speed accelerator, closely located to DRAM, is used for data intensive calculations.
    % TODO what's the difference to a graphics or other compute accelerator?
\end{frame}

\begin{frame}[fragile]{Near-Memory-Computing}
    Uncertainties:

    \begin{itemize}[<+->]
        \item Does NMC actually solve memory limitations?
        \item How does NMC integrate into software ecosystems?
        \item Can NMC compete with the performance of existing hardware?
        \item Is the step from simulation to hardware feasible?
    \end{itemize}

    \alert{\uncover<5->{No off-the-shelve NMC hardware available, custom hardware required!}}
\end{frame}


\begin{frame}[fragile]{Near-Memory-Computing}
    To solve the these problems with NMC, a dedicated platform is needed.

    We offer such a platform to ease development and evaluation of NMC-capable accelerators based on reconfigurable hardware.
\end{frame}

\section{NMC-platform}

\begin{frame}[fragile]{NMC-platform}
    NMC-platform requirements:

    \begin{itemize}[<+->]
        \item rapid prototyping
        \item possibility to easily evaluate different NMC-accelerators
        \item superior performance in memory intensive applications
        \item seamless integration into existing software stack
        \item basis for future real-world platforms
    \end{itemize}
\end{frame}

\begin{frame}[fragile]{NMC-platform}
    Manufacturing an ASICs for many different types of architectures is expensive.

    FPGAs are reconfigurable and can be used to evaluate many different designs at lower cost.

    Recent FPGAs like the Xilinx UltraScale+ series offer High Bandwidth Memory,
    ideal for data intensive applications!
\end{frame}

\begin{frame}[fragile]{NMC-platform}
    \textbf{Processor:} Multiple open RISC-V cores are available \cite{riscvcores}.
    The Rocket Chip is actively developed and maintained.

    % emphasize system aspect, NMC not so much in focus
    \textbf{Operating System:} Working bare metal makes development more difficult.
    Linux officially supports RISC-V and can be modified freely.

    \textbf{FPGA:} The Virtex UltraScale+ VU37P (ADM-PCIE-9H7) is a powerful FPGA with HBM,
    the Zynq 7020 (ZedBoard) with DDR3 can be used for comparison to a lower tier part.
\end{frame}

\section{Architecture}

\begin{frame}[fragile]{Architecture}
    The Rocket Chip generator is a SoC generator written in Chisel \cite{rocketchip}.

    It generates Verilog code for an in-order RISC-V core which can be synthesized with FPGA toolchains.

    A large set of configurations can be used to adjust for the requirements.
\end{frame}

\begin{frame}[fragile]{Architecture}
    The processor still needs peripherals:
    \begin{itemize}[<+->]
        \item UART connection for system console
        \item GPIOs to debug the bootrom
        \item AXI memory (HBM or DDR3)
    \end{itemize}
\end{frame}

\begin{frame}[fragile]{Architecture}
    \begin{figure}
        \centering
        \includegraphics[width=\textwidth]{figures/schematic.pdf}
        \caption{overview of the platform components}
    \end{figure}
\end{frame}

\begin{frame}[fragile]{Architecture}
    Processor has to execute code when leaving reset:
    \begin{itemize}[<+->]
        \item Rocket core contains boot-ROM that is executed on power-up
        \item necessary hardware and the memory have to be initialized
        \item vmlinux ELF and bbl\uncover<3->{\footnote<3->{Berkeley Boot Loader, required to provide the Supervisor Binary Interface (SBI)}} have to be loaded to memory
    \end{itemize}

    \uncover<4->{\textcolor{i4green}{Little hardware, so easy to initialize!}}

    \uncover<5->{\textcolor{i4red}{No persistent storage, where to load vmlinux from?}}
\end{frame}

\begin{frame}[fragile]{Architecture}
    \begin{figure}
        \centering
        \includegraphics[width=\textwidth]{figures/bootproc.pdf}
        \caption{boot procedure block diagram}
    \end{figure}
\end{frame}

\begin{frame}[fragile]{Architecture}
    Boot procedure summary:
    \begin{enumerate}[<+->]
        \item Rocket core powers up
        \item boot-ROM awaits UART connection from host PC
        \item rocketload sends commands and data to fill memory
        \item rocketload sends a boot command
        \item Rocket core jumps to start of memory
        \item bbl is executed and inits console
        \item bbl loads the vmlinux ELF and executes Linux
        \item Linux boots up and user programs can be executed
    \end{enumerate}
\end{frame}

\begin{frame}[fragile]{Architecture}
    How does Linux know about the hardware connected?
    \only<2>{
        It uses a device tree from boot-ROM!
        \begin{center}
            \frame{
                \resizebox{!}{80pt}{
                    \lstinputlisting[basicstyle=\ttfamily]{dtssample.txt}
                }
            }
        \end{center}
    }
\end{frame}

\begin{frame}[fragile]{Architecture}
    The platform does not have persistent storage. How can user programs be executed after the Kernel starts?

    \begin{itemize}[<+->]
        \item initramfs as the first kind of file system
        \item image with all required programs is created on developer machine
        \item BusyBox provides a large set of coreutils in a single small statically linked binary
        \item no way to provide initramfs via bootloader, so embed it into Kernel
    \end{itemize}
\end{frame}

\begin{frame}[fragile]{Architecture}
    \begin{verbatim}$ screen /dev/ttyUSB0 115200\end{verbatim}
    \begin{center}
        \frame{
            \resizebox{\textwidth}{!}{
                \lstinputlisting[basicstyle=\ttfamily,linewidth=400pt,breaklines=false]{riscvlinux.txt}
            }
        }
    \end{center}
\end{frame}

\section{Evaluation}

\begin{frame}[fragile]{Evaluation}
    Features of the proposed NMC-platform:
    \begin{itemize}[<+->]
        \item support for regular Linux RISC-V programs
        \item hardware components can be interchanged easily
        \item design avoids unnecessarily complicated boot steps
        \item high-speed memory for data intensive computing
    \end{itemize}
\end{frame}

\begin{frame}[fragile]{Evaluation}
    Without presence of an NMC-accelerator the final performance is difficult to predict.

    However, some CPU-based figures about the memory can be helpful for making correct design decisions for future accelerators.
\end{frame}

\begin{frame}[fragile]{Evaluation (test-tlb)}
    \input{figures/testtlb}
\end{frame}

\begin{frame}[fragile]{Evaluation}
    \begin{table}
        \centering
        \captionsetup[table]{position=bottom}
        \resizebox{\textwidth}{!}{
            \begin{tabular}{@{} lllll @{}}
                \toprule
                Board       &   LUTs            &   Block RAM   &   DSPs        &   Flip-Flops      \\
                \midrule
                ZedBoard    &   31534 (59.2\%)  &   12 (8.6\%)  &   17 (7.7\%)  &   16019 (15.1\%)  \\
                ADM-PCIE-9H7&   35664 (2.7\%)   &   15 (0.8\%)  &   17 (0.2\%)  &   20971 (0.8\%)   \\
                \bottomrule
            \end{tabular}
        }
        \caption{Rocket core FPGA resource utilization}
        \label{table:fpgares}
    \end{table}
\end{frame}

\begin{frame}[fragile]{Evaluation}
    The boot procedure over UART is very basic --- unfortunately too basic.

    Booting over UART is very slow which makes Kernel and software debugging an exceptionally time consuming process.

    Boot image size has to stay as small as possible to keep boot times low.
\end{frame}

\section{Summary}

\begin{frame}[fragile]{Summary}
    Topics covered:
    \begin{itemize}[<+->]
        \item NMC as a method to increase performance for data intensive workloads
        \item components required to create a platform that can host NMC accelerators
        \item booting Linux on the Rocket core with bbl
        \item performance of the Rocket core
    \end{itemize}
\end{frame}

\begin{frame}[fragile]{Future Work}
    For more comfortable development, a faster boot mechanism is required which might include persistent storage.

    NMC-accelerators have to be implemented and evaluated. Even simulating IMC capable chips is possible.

    For NMC, the performance of accelerators is more relevant than the CPU performance.
    However, replacing the Rocket core with a faster alternative like BOOM \cite{Celio:EECS-2015-167} might still be preferable.
\end{frame}

\begin{frame}[standout]
    Questions?
\end{frame}

\appendix

\begin{frame}[fragile]{Linux RISC-V history}
    \begin{figure}
        \centering
        \begin{tikzpicture}
            \begin{axis}[
                    mbarplot,
                    symbolic x coords={4.19,4.20,5.0,5.1,5.2,5.3,5.4},
                    xlabel={version},
                    ylabel={lines},
                    width=0.9\textwidth,
                    height=6cm,
                    xtick=data,
                    yticklabel style={/pgf/number format/fixed,/pgf/number format/precision=5},
                    scaled y ticks=false,
                    ymin=0,
                ]

                \addplot[fill=i4green] plot coordinates {(4.19, 12096) (4.20,878) (5.0, 724) (5.1, 2047) (5.2, 1049) (5.3, 724) (5.4, 576)};
                \addplot[fill=i4red]   plot coordinates {(4.19, 0)     (4.20,342) (5.0, 262)  (5.1, 247)  (5.2, 1216) (5.3, 258) (5.4, 201)};

                \legend{insertions, deletions}

            \end{axis}
        \end{tikzpicture}
        \caption{\texttt{git diff {-}{-}stat vX vY {-}{-} arch/riscv}}
    \end{figure}
\end{frame}

\begin{frame}[fragile]{LINPACK.C}
    \input{figures/linpackc}
\end{frame}

\begin{frame}[fragile]{Evaluation (STREAM)}
    \input{figures/streamc}

    Maximum burst transfer rate of 256 bit AXI HBM bus at 150 MHz should be 4.8 GB/s.
    The Rocket core does not even utilize 1\% of the bandwidth!
\end{frame}

%\begin{frame}[fragile]{Backup slides}
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%    refer to during audience questions.
%
%    The best way to do this is to include the \verb|appendixnumberbeamer|
%    package in your preamble and call \verb|\appendix| before your backup slides.
%
%    \themename will automatically turn off slide numbering and progress bars for
%    slides in the appendix.
%\end{frame}