change some things

figures/testtlb.tex

 \begin{figure}
+    \definecolor{mylred}{rgb}{0.7,0.7,0.7}
+    \definecolor{myred}{rgb}{0.3,0.3,0.3}
+    \definecolor{mylgrn}{rgb}{1.0,0.6,0.4}
+    \definecolor{mygrn}{rgb}{0.7,0.35,0.0}
+    \definecolor{mylblu}{rgb}{0.4,0.4,1.0}
+    \definecolor{myblu}{rgb}{0.0,0.0,0.7}
     \begin{center}
         \pgfplotsset{scaled y ticks=false}
         \resizebox{!}{150pt}{
@@ -23,12 +29,12 @@
                         legend style={at={(0.05, 0.95)},anchor=north west, legend cell align=left},
                         table/col sep=comma
                     ]
-                    \addplot[mark=triangle, color=purple, thick]    table[x=memsize, y=hbm150ordered] {figures/testtlb.csv};  \addlegendentry{HBM 150 MHz ordered};
-                    \addplot[mark=o, color=red, thick]              table[x=memsize, y=hbm150shuffled] {figures/testtlb.csv}; \addlegendentry{HBM 150 MHz shuffled};
-                    \addplot[mark=triangle, color=orange, thick]    table[x=memsize, y=hbm50ordered] {figures/testtlb.csv};   \addlegendentry{HBM 50 MHz ordered};
-                    \addplot[mark=o, color=green, thick]            table[x=memsize, y=hbm50shuffled] {figures/testtlb.csv};  \addlegendentry{HBM 50 MHz shuffled};
-                    \addplot[mark=triangle, color=blue, thick]      table[x=memsize, y=ddr50ordered] {figures/testtlb.csv};   \addlegendentry{DDR3 50 MHz ordered};
-                    \addplot[mark=o, color=black, thick]            table[x=memsize, y=ddr50shuffled] {figures/testtlb.csv};  \addlegendentry{DDR3 50 MHz shuffled};
+                    \addplot[mark=triangle, color=mylred, thick]    table[x=memsize, y=hbm150ordered] {figures/testtlb.csv};  \addlegendentry{HBM 150 MHz ordered};
+                    \addplot[mark=o, color=myred, thick]              table[x=memsize, y=hbm150shuffled] {figures/testtlb.csv}; \addlegendentry{HBM 150 MHz shuffled};
+                    \addplot[mark=triangle, color=mylgrn, thick]    table[x=memsize, y=hbm50ordered] {figures/testtlb.csv};   \addlegendentry{HBM 50 MHz ordered};
+                    \addplot[mark=o, color=mygrn, thick]            table[x=memsize, y=hbm50shuffled] {figures/testtlb.csv};  \addlegendentry{HBM 50 MHz shuffled};
+                    \addplot[mark=triangle, color=mylblu, thick]      table[x=memsize, y=ddr50ordered] {figures/testtlb.csv};   \addlegendentry{DDR3 50 MHz ordered};
+                    \addplot[mark=o, color=myblu, thick]            table[x=memsize, y=ddr50shuffled] {figures/testtlb.csv};  \addlegendentry{DDR3 50 MHz shuffled};
                     \addlegendimage{empty legend}
                 \end{axis}
             \end{tikzpicture}

main.tex

@@ -105,11 +105,11 @@
 \end{frame}
 
 \begin{frame}[fragile]{NMC-platform}
-    Manufacturing an ASICs for many different types of architectures is expensive.
+    Manufacturing ASICs for many different types of architectures is expensive.
 
     FPGAs are reconfigurable and can be used to evaluate many different designs at lower cost.
 
-    Recent FPGAs like the Xilinx UltraScale+ series offer High Bandwidth Memory,
+    Recent FPGAs like the Xilinx UltraScale+ series offer High Bandwidth Memory (HBM),
     ideal for data intensive applications!
 \end{frame}
 
@@ -174,21 +174,8 @@
 \end{frame}
 
 \begin{frame}[fragile]{Architecture}
-    Boot procedure summary:
-    \begin{enumerate}[<+->]
-        \item Rocket core powers up
-        \item boot-ROM awaits UART connection from host PC
-        \item rocketload sends commands and data to fill memory
-        \item rocketload sends a boot command
-        \item Rocket core jumps to start of memory
-        \item bbl is executed and inits console
-        \item bbl loads the vmlinux ELF and executes Linux
-        \item Linux boots up and user programs can be executed
-    \end{enumerate}
-\end{frame}
+    How does Linux know about the connected hardware?
 
-\begin{frame}[fragile]{Architecture}
-    How does Linux know about the hardware connected?
     \only<2>{
         It uses a device tree from boot-ROM!
         \begin{center}
@@ -265,7 +252,7 @@
 \end{frame}
 
 \begin{frame}[fragile]{Evaluation}
-    The boot procedure over UART is very basic --- unfortunately too basic.
+    The boot procedure over UART is very basic --- waiting 3 minutes is not acceptable.
 
     Booting over UART is very slow which makes Kernel and software debugging an exceptionally time consuming process.
 
@@ -275,7 +262,6 @@
 \section{Summary}
 
 \begin{frame}[fragile]{Summary}
-    Topics covered:
     \begin{itemize}[<+->]
         \item NMC as a method to increase performance for data intensive workloads
         \item components required to create a platform that can host NMC accelerators
@@ -299,6 +285,20 @@
 
 \appendix
 
+\begin{frame}[fragile]{Architecture}
+    Boot procedure summary:
+    \begin{enumerate}[<+->]
+        \item Rocket core powers up
+        \item boot-ROM awaits UART connection from host PC
+        \item rocketload sends commands and data to fill memory
+        \item rocketload sends a boot command
+        \item Rocket core jumps to start of memory
+        \item bbl is executed and inits console
+        \item bbl loads the vmlinux ELF and executes Linux
+        \item Linux boots up and user programs can be executed
+    \end{enumerate}
+\end{frame}
+
 \begin{frame}[fragile]{Linux RISC-V history}
     \begin{figure}
         \centering