diff --git a/TopModule_tb_behav.wcfg b/TopModule_tb_behav.wcfg
new file mode 100644
index 0000000000000000000000000000000000000000..e651d2beabcfa24a366a3b5fc9e056e184741a4e
--- /dev/null
+++ b/TopModule_tb_behav.wcfg
@@ -0,0 +1,95 @@
+<?xml version="1.0" encoding="UTF-8"?>
+<wave_config>
+ <wave_state>
+ </wave_state>
+ <db_ref_list>
+ <db_ref path="TopModule_tb_behav.wdb" id="1">
+ <top_modules>
+ <top_module name="TopModule_tb" />
+ <top_module name="glbl" />
+ </top_modules>
+ </db_ref>
+ </db_ref_list>
+ <zoom_setting>
+ <ZoomStartTime time="0.000 ns"></ZoomStartTime>
+ <ZoomEndTime time="1,932.082 ns"></ZoomEndTime>
+ <Cursor1Time time="1,000.000 ns"></Cursor1Time>
+ </zoom_setting>
+ <column_width_setting>
+ <NameColumnWidth column_width="254"></NameColumnWidth>
+ <ValueColumnWidth column_width="66"></ValueColumnWidth>
+ </column_width_setting>
+ <WVObjectSize size="18" />
+ <wvobject type="logic" fp_name="/TopModule_tb/DUT/clk25">
+ <obj_property name="ElementShortName">clk25</obj_property>
+ <obj_property name="ObjectShortName">clk25</obj_property>
+ </wvobject>
+ <wvobject type="logic" fp_name="/TopModule_tb/btnCpuReset_i">
+ <obj_property name="ElementShortName">btnCpuReset_i</obj_property>
+ <obj_property name="ObjectShortName">btnCpuReset_i</obj_property>
+ </wvobject>
+ <wvobject type="other" fp_name="/TopModule_tb/DUT/hcounter_sig">
+ <obj_property name="ElementShortName">hcounter_sig</obj_property>
+ <obj_property name="ObjectShortName">hcounter_sig</obj_property>
+ </wvobject>
+ <wvobject type="other" fp_name="/TopModule_tb/DUT/vcounter_sig">
+ <obj_property name="ElementShortName">vcounter_sig</obj_property>
+ <obj_property name="ObjectShortName">vcounter_sig</obj_property>
+ </wvobject>
+ <wvobject type="other" fp_name="/TopModule_tb/DUT/fcounter_sig">
+ <obj_property name="ElementShortName">fcounter_sig</obj_property>
+ <obj_property name="ObjectShortName">fcounter_sig</obj_property>
+ </wvobject>
+ <wvobject type="logic" fp_name="/TopModule_tb/DUT/vgaInterface/FStrobe">
+ <obj_property name="ElementShortName">FStrobe</obj_property>
+ <obj_property name="ObjectShortName">FStrobe</obj_property>
+ </wvobject>
+ <wvobject type="logic" fp_name="/TopModule_tb/DUT/Hsync">
+ <obj_property name="ElementShortName">Hsync</obj_property>
+ <obj_property name="ObjectShortName">Hsync</obj_property>
+ </wvobject>
+ <wvobject type="logic" fp_name="/TopModule_tb/DUT/Vsync">
+ <obj_property name="ElementShortName">Vsync</obj_property>
+ <obj_property name="ObjectShortName">Vsync</obj_property>
+ </wvobject>
+ <wvobject type="array" fp_name="/TopModule_tb/vgaRed_i">
+ <obj_property name="ElementShortName">vgaRed_i[3:0]</obj_property>
+ <obj_property name="ObjectShortName">vgaRed_i[3:0]</obj_property>
+ </wvobject>
+ <wvobject type="array" fp_name="/TopModule_tb/vgaBlue_i">
+ <obj_property name="ElementShortName">vgaBlue_i[3:0]</obj_property>
+ <obj_property name="ObjectShortName">vgaBlue_i[3:0]</obj_property>
+ </wvobject>
+ <wvobject type="array" fp_name="/TopModule_tb/vgaGreen_i">
+ <obj_property name="ElementShortName">vgaGreen_i[3:0]</obj_property>
+ <obj_property name="ObjectShortName">vgaGreen_i[3:0]</obj_property>
+ </wvobject>
+ <wvobject type="logic" fp_name="/TopModule_tb/btnU_i">
+ <obj_property name="ElementShortName">btnU_i</obj_property>
+ <obj_property name="ObjectShortName">btnU_i</obj_property>
+ </wvobject>
+ <wvobject type="other" fp_name="/TopModule_tb/DUT/runnerObject/pos_object_y_target">
+ <obj_property name="ElementShortName">pos_object_y_target</obj_property>
+ <obj_property name="ObjectShortName">pos_object_y_target</obj_property>
+ </wvobject>
+ <wvobject type="other" fp_name="/TopModule_tb/DUT/runnerObject/pos_object_y_actual">
+ <obj_property name="ElementShortName">pos_object_y_actual</obj_property>
+ <obj_property name="ObjectShortName">pos_object_y_actual</obj_property>
+ </wvobject>
+ <wvobject type="other" fp_name="/TopModule_tb/DUT/runnerObject/fcount_edge">
+ <obj_property name="ElementShortName">fcount_edge</obj_property>
+ <obj_property name="ObjectShortName">fcount_edge</obj_property>
+ </wvobject>
+ <wvobject type="logic" fp_name="/TopModule_tb/DUT/runnerObject/runner_status">
+ <obj_property name="ElementShortName">runner_status</obj_property>
+ <obj_property name="ObjectShortName">runner_status</obj_property>
+ </wvobject>
+ <wvobject type="logic" fp_name="/TopModule_tb/DUT/runnerObject/runner_not_landed">
+ <obj_property name="ElementShortName">runner_not_landed</obj_property>
+ <obj_property name="ObjectShortName">runner_not_landed</obj_property>
+ </wvobject>
+ <wvobject type="logic" fp_name="/TopModule_tb/DUT/runnerObject/runner_jumped">
+ <obj_property name="ElementShortName">runner_jumped</obj_property>
+ <obj_property name="ObjectShortName">runner_jumped</obj_property>
+ </wvobject>
+</wave_config>
diff --git a/game.cache/ip/2022.2/1/8/186611fea06d2870/186611fea06d2870.xci b/game.cache/ip/2022.2/1/8/186611fea06d2870/186611fea06d2870.xci
new file mode 100644
index 0000000000000000000000000000000000000000..65d1c6749275e710e4ed8b36dc9a7f492b146feb
--- /dev/null
+++ b/game.cache/ip/2022.2/1/8/186611fea06d2870/186611fea06d2870.xci
@@ -0,0 +1,295 @@
+<?xml version="1.0" encoding="UTF-8"?>
+<spirit:design xmlns:xilinx="http://www.xilinx.com" xmlns:spirit="http://www.spiritconsortium.org/XMLSchema/SPIRIT/1685-2009" xmlns:xsi="http://www.w3.org/2001/XMLSchema-instance">
+ <spirit:vendor>xilinx.com</spirit:vendor>
+ <spirit:library>ipcache</spirit:library>
+ <spirit:name>186611fea06d2870</spirit:name>
+ <spirit:version>0</spirit:version>
+ <spirit:componentInstances>
+ <spirit:componentInstance>
+ <spirit:instanceName>clk_wiz_0</spirit:instanceName>
+ <spirit:componentRef spirit:vendor="xilinx.com" spirit:library="ip" spirit:name="clk_wiz" spirit:version="6.0"/>
+ <spirit:configurableElementValues>
+ <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.CLOCK_CLK_IN1.FREQ_HZ">100000000</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.CLOCK_CLK_OUT1.FREQ_HZ">100000000</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.AUTO_PRIMITIVE">MMCM</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.AXI_DRP">false</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.CALC_DONE">empty</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.CDDCDONE_PORT">cddcdone</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.CDDCREQ_PORT">cddcreq</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.CLKFB_IN_N_PORT">clkfb_in_n</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.CLKFB_IN_PORT">clkfb_in</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.CLKFB_IN_P_PORT">clkfb_in_p</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.CLKFB_IN_SIGNALING">SINGLE</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.CLKFB_OUT_N_PORT">clkfb_out_n</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.CLKFB_OUT_PORT">clkfb_out</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.CLKFB_OUT_P_PORT">clkfb_out_p</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.CLKFB_STOPPED_PORT">clkfb_stopped</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.CLKIN1_JITTER_PS">100.0</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.CLKIN1_UI_JITTER">0.010</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.CLKIN2_JITTER_PS">100.0</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.CLKIN2_UI_JITTER">0.010</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.CLKOUT1_DRIVES">BUFG</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.CLKOUT1_JITTER">181.828</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.CLKOUT1_MATCHED_ROUTING">false</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.CLKOUT1_PHASE_ERROR">104.359</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.CLKOUT1_REQUESTED_DUTY_CYCLE">50.000</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.CLKOUT1_REQUESTED_OUT_FREQ">25</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.CLKOUT1_REQUESTED_PHASE">0.000</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.CLKOUT1_SEQUENCE_NUMBER">1</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.CLKOUT1_USED">true</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.CLKOUT2_DRIVES">BUFG</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.CLKOUT2_JITTER">0.0</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.CLKOUT2_MATCHED_ROUTING">false</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.CLKOUT2_PHASE_ERROR">0.0</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.CLKOUT2_REQUESTED_DUTY_CYCLE">50.000</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.CLKOUT2_REQUESTED_OUT_FREQ">100.000</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.CLKOUT2_REQUESTED_PHASE">0.000</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.CLKOUT2_SEQUENCE_NUMBER">1</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.CLKOUT2_USED">false</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.CLKOUT3_DRIVES">BUFG</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.CLKOUT3_JITTER">0.0</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.CLKOUT3_MATCHED_ROUTING">false</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.CLKOUT3_PHASE_ERROR">0.0</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.CLKOUT3_REQUESTED_DUTY_CYCLE">50.000</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.CLKOUT3_REQUESTED_OUT_FREQ">100.000</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.CLKOUT3_REQUESTED_PHASE">0.000</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.CLKOUT3_SEQUENCE_NUMBER">1</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.CLKOUT3_USED">false</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.CLKOUT4_DRIVES">BUFG</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.CLKOUT4_JITTER">0.0</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.CLKOUT4_MATCHED_ROUTING">false</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.CLKOUT4_PHASE_ERROR">0.0</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.CLKOUT4_REQUESTED_DUTY_CYCLE">50.000</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.CLKOUT4_REQUESTED_OUT_FREQ">100.000</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.CLKOUT4_REQUESTED_PHASE">0.000</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.CLKOUT4_SEQUENCE_NUMBER">1</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.CLKOUT4_USED">false</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.CLKOUT5_DRIVES">BUFG</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.CLKOUT5_JITTER">0.0</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.CLKOUT5_MATCHED_ROUTING">false</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.CLKOUT5_PHASE_ERROR">0.0</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.CLKOUT5_REQUESTED_DUTY_CYCLE">50.000</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.CLKOUT5_REQUESTED_OUT_FREQ">100.000</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.CLKOUT5_REQUESTED_PHASE">0.000</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.CLKOUT5_SEQUENCE_NUMBER">1</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.CLKOUT5_USED">false</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.CLKOUT6_DRIVES">BUFG</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.CLKOUT6_JITTER">0.0</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.CLKOUT6_MATCHED_ROUTING">false</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.CLKOUT6_PHASE_ERROR">0.0</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.CLKOUT6_REQUESTED_DUTY_CYCLE">50.000</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.CLKOUT6_REQUESTED_OUT_FREQ">100.000</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.CLKOUT6_REQUESTED_PHASE">0.000</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.CLKOUT6_SEQUENCE_NUMBER">1</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.CLKOUT6_USED">false</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.CLKOUT7_DRIVES">BUFG</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.CLKOUT7_JITTER">0.0</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.CLKOUT7_MATCHED_ROUTING">false</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.CLKOUT7_PHASE_ERROR">0.0</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.CLKOUT7_REQUESTED_DUTY_CYCLE">50.000</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.CLKOUT7_REQUESTED_OUT_FREQ">100.000</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.CLKOUT7_REQUESTED_PHASE">0.000</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.CLKOUT7_SEQUENCE_NUMBER">1</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.CLKOUT7_USED">false</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.CLKOUTPHY_REQUESTED_FREQ">600.000</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.CLK_IN1_BOARD_INTERFACE">Custom</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.CLK_IN2_BOARD_INTERFACE">Custom</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.CLK_IN_SEL_PORT">clk_in_sel</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.CLK_OUT1_PORT">clk_out1</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.CLK_OUT1_USE_FINE_PS_GUI">false</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.CLK_OUT2_PORT">clk_out2</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.CLK_OUT2_USE_FINE_PS_GUI">false</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.CLK_OUT3_PORT">clk_out3</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.CLK_OUT3_USE_FINE_PS_GUI">false</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.CLK_OUT4_PORT">clk_out4</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.CLK_OUT4_USE_FINE_PS_GUI">false</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.CLK_OUT5_PORT">clk_out5</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.CLK_OUT5_USE_FINE_PS_GUI">false</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.CLK_OUT6_PORT">clk_out6</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.CLK_OUT6_USE_FINE_PS_GUI">false</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.CLK_OUT7_PORT">clk_out7</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.CLK_OUT7_USE_FINE_PS_GUI">false</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.CLK_VALID_PORT">CLK_VALID</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.CLOCK_MGR_TYPE">auto</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Component_Name">clk_wiz_0</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.DADDR_PORT">daddr</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.DCLK_PORT">dclk</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.DEN_PORT">den</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.DIFF_CLK_IN1_BOARD_INTERFACE">Custom</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.DIFF_CLK_IN2_BOARD_INTERFACE">Custom</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.DIN_PORT">din</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.DOUT_PORT">dout</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.DRDY_PORT">drdy</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.DWE_PORT">dwe</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.ENABLE_CDDC">false</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.ENABLE_CLKOUTPHY">false</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.ENABLE_CLOCK_MONITOR">false</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.ENABLE_USER_CLOCK0">false</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.ENABLE_USER_CLOCK1">false</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.ENABLE_USER_CLOCK2">false</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.ENABLE_USER_CLOCK3">false</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Enable_PLL0">false</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Enable_PLL1">false</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.FEEDBACK_SOURCE">FDBK_AUTO</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.INPUT_CLK_STOPPED_PORT">input_clk_stopped</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.INPUT_MODE">frequency</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.INTERFACE_SELECTION">Enable_AXI</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.IN_FREQ_UNITS">Units_MHz</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.IN_JITTER_UNITS">Units_UI</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.JITTER_OPTIONS">UI</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.JITTER_SEL">No_Jitter</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.LOCKED_PORT">locked</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.MMCM_BANDWIDTH">OPTIMIZED</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.MMCM_CLKFBOUT_MULT_F">9.125</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.MMCM_CLKFBOUT_PHASE">0.000</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.MMCM_CLKFBOUT_USE_FINE_PS">false</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.MMCM_CLKIN1_PERIOD">10.000</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.MMCM_CLKIN2_PERIOD">10.000</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.MMCM_CLKOUT0_DIVIDE_F">36.500</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.MMCM_CLKOUT0_DUTY_CYCLE">0.500</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.MMCM_CLKOUT0_PHASE">0.000</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.MMCM_CLKOUT0_USE_FINE_PS">false</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.MMCM_CLKOUT1_DIVIDE">1</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.MMCM_CLKOUT1_DUTY_CYCLE">0.500</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.MMCM_CLKOUT1_PHASE">0.000</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.MMCM_CLKOUT1_USE_FINE_PS">false</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.MMCM_CLKOUT2_DIVIDE">1</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.MMCM_CLKOUT2_DUTY_CYCLE">0.500</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.MMCM_CLKOUT2_PHASE">0.000</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.MMCM_CLKOUT2_USE_FINE_PS">false</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.MMCM_CLKOUT3_DIVIDE">1</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.MMCM_CLKOUT3_DUTY_CYCLE">0.500</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.MMCM_CLKOUT3_PHASE">0.000</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.MMCM_CLKOUT3_USE_FINE_PS">false</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.MMCM_CLKOUT4_CASCADE">false</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.MMCM_CLKOUT4_DIVIDE">1</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.MMCM_CLKOUT4_DUTY_CYCLE">0.500</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.MMCM_CLKOUT4_PHASE">0.000</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.MMCM_CLKOUT4_USE_FINE_PS">false</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.MMCM_CLKOUT5_DIVIDE">1</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.MMCM_CLKOUT5_DUTY_CYCLE">0.500</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.MMCM_CLKOUT5_PHASE">0.000</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.MMCM_CLKOUT5_USE_FINE_PS">false</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.MMCM_CLKOUT6_DIVIDE">1</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.MMCM_CLKOUT6_DUTY_CYCLE">0.500</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.MMCM_CLKOUT6_PHASE">0.000</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.MMCM_CLKOUT6_USE_FINE_PS">false</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.MMCM_CLOCK_HOLD">false</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.MMCM_COMPENSATION">ZHOLD</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.MMCM_DIVCLK_DIVIDE">1</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.MMCM_NOTES">None</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.MMCM_REF_JITTER1">0.010</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.MMCM_REF_JITTER2">0.010</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.MMCM_STARTUP_WAIT">false</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.NUM_OUT_CLKS">1</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.OPTIMIZE_CLOCKING_STRUCTURE_EN">false</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.OVERRIDE_MMCM">false</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.OVERRIDE_PLL">false</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.PHASESHIFT_MODE">WAVEFORM</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.PHASE_DUTY_CONFIG">false</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.PLATFORM">UNKNOWN</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.PLL_BANDWIDTH">OPTIMIZED</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.PLL_CLKFBOUT_MULT">4</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.PLL_CLKFBOUT_PHASE">0.000</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.PLL_CLKIN_PERIOD">10.000</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.PLL_CLKOUT0_DIVIDE">1</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.PLL_CLKOUT0_DUTY_CYCLE">0.500</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.PLL_CLKOUT0_PHASE">0.000</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.PLL_CLKOUT1_DIVIDE">1</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.PLL_CLKOUT1_DUTY_CYCLE">0.500</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.PLL_CLKOUT1_PHASE">0.000</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.PLL_CLKOUT2_DIVIDE">1</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.PLL_CLKOUT2_DUTY_CYCLE">0.500</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.PLL_CLKOUT2_PHASE">0.000</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.PLL_CLKOUT3_DIVIDE">1</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.PLL_CLKOUT3_DUTY_CYCLE">0.500</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.PLL_CLKOUT3_PHASE">0.000</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.PLL_CLKOUT4_DIVIDE">1</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.PLL_CLKOUT4_DUTY_CYCLE">0.500</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.PLL_CLKOUT4_PHASE">0.000</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.PLL_CLKOUT5_DIVIDE">1</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.PLL_CLKOUT5_DUTY_CYCLE">0.500</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.PLL_CLKOUT5_PHASE">0.000</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.PLL_CLK_FEEDBACK">CLKFBOUT</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.PLL_COMPENSATION">SYSTEM_SYNCHRONOUS</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.PLL_DIVCLK_DIVIDE">1</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.PLL_NOTES">None</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.PLL_REF_JITTER">0.010</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.POWER_DOWN_PORT">power_down</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.PRECISION">1</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.PRIMARY_PORT">clk_in1</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.PRIMITIVE">MMCM</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.PRIMTYPE_SEL">mmcm_adv</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.PRIM_IN_FREQ">100.000</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.PRIM_IN_JITTER">0.010</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.PRIM_IN_TIMEPERIOD">10.000</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.PRIM_SOURCE">Single_ended_clock_capable_pin</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.PSCLK_PORT">psclk</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.PSDONE_PORT">psdone</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.PSEN_PORT">psen</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.PSINCDEC_PORT">psincdec</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.REF_CLK_FREQ">100.0</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.RELATIVE_INCLK">REL_PRIMARY</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.RESET_BOARD_INTERFACE">Custom</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.RESET_PORT">resetn</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.RESET_TYPE">ACTIVE_LOW</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.SECONDARY_IN_FREQ">100.000</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.SECONDARY_IN_JITTER">0.010</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.SECONDARY_IN_TIMEPERIOD">10.000</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.SECONDARY_PORT">clk_in2</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.SECONDARY_SOURCE">Single_ended_clock_capable_pin</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.SS_MODE">CENTER_HIGH</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.SS_MOD_FREQ">250</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.SS_MOD_TIME">0.004</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.STATUS_PORT">STATUS</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.SUMMARY_STRINGS">empty</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.USER_CLK_FREQ0">100.0</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.USER_CLK_FREQ1">100.0</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.USER_CLK_FREQ2">100.0</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.USER_CLK_FREQ3">100.0</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.USE_BOARD_FLOW">false</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.USE_CLKFB_STOPPED">false</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.USE_CLK_VALID">false</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.USE_CLOCK_SEQUENCING">false</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.USE_DYN_PHASE_SHIFT">false</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.USE_DYN_RECONFIG">false</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.USE_FREEZE">false</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.USE_FREQ_SYNTH">true</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.USE_INCLK_STOPPED">false</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.USE_INCLK_SWITCHOVER">false</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.USE_LOCKED">false</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.USE_MAX_I_JITTER">false</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.USE_MIN_O_JITTER">false</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.USE_MIN_POWER">false</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.USE_PHASE_ALIGNMENT">true</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.USE_POWER_DOWN">false</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.USE_RESET">true</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.USE_SAFE_CLOCK_STARTUP">false</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.USE_SPREAD_SPECTRUM">false</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.USE_STATUS">false</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PROJECT_PARAM.ARCHITECTURE">artix7</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PROJECT_PARAM.DEVICE">xc7a100t</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PROJECT_PARAM.PACKAGE">csg324</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PROJECT_PARAM.PREFHDL">VHDL</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PROJECT_PARAM.SILICON_REVISION"/>
+ <spirit:configurableElementValue spirit:referenceId="PROJECT_PARAM.SPEEDGRADE">-1</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="PROJECT_PARAM.STATIC_POWER"/>
+ <spirit:configurableElementValue spirit:referenceId="PROJECT_PARAM.TEMPERATURE_GRADE"/>
+ <spirit:configurableElementValue spirit:referenceId="RUNTIME_PARAM.IPCACHEELABORATESCRC">4e5828b5</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="RUNTIME_PARAM.IPCACHEID">186611fea06d2870</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="RUNTIME_PARAM.IPCACHESPECIALDATA">clk_wiz_0</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="RUNTIME_PARAM.IPCACHESYNTHCL">$Change: 3669142 $</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="RUNTIME_PARAM.IPCACHESYNTHCRC">984cb417</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="RUNTIME_PARAM.IPCACHESYNTHRUNTIME">30</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="RUNTIME_PARAM.IPCONTEXT">IP_Unknown</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="RUNTIME_PARAM.IPREVISION">11</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="RUNTIME_PARAM.MANAGED">TRUE</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="RUNTIME_PARAM.OUTPUTDIR">.</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="RUNTIME_PARAM.SELECTEDSIMMODEL"/>
+ <spirit:configurableElementValue spirit:referenceId="RUNTIME_PARAM.SHAREDDIR">.</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="RUNTIME_PARAM.SWVERSION">2022.2</spirit:configurableElementValue>
+ <spirit:configurableElementValue spirit:referenceId="RUNTIME_PARAM.SYNTHESISFLOW">GLOBAL</spirit:configurableElementValue>
+ </spirit:configurableElementValues>
+ </spirit:componentInstance>
+ </spirit:componentInstances>
+</spirit:design>
diff --git a/game.cache/ip/2022.2/1/8/186611fea06d2870/clk_wiz_0.dcp b/game.cache/ip/2022.2/1/8/186611fea06d2870/clk_wiz_0.dcp
new file mode 100644
index 0000000000000000000000000000000000000000..bbccf5e41df65c4ba3e30721deac00481e21ad11
Binary files /dev/null and b/game.cache/ip/2022.2/1/8/186611fea06d2870/clk_wiz_0.dcp differ
diff --git a/game.cache/ip/2022.2/1/8/186611fea06d2870/clk_wiz_0_sim_netlist.v b/game.cache/ip/2022.2/1/8/186611fea06d2870/clk_wiz_0_sim_netlist.v
new file mode 100755
index 0000000000000000000000000000000000000000..59f0cff5873002cf02335178b4ac59e326ab8970
--- /dev/null
+++ b/game.cache/ip/2022.2/1/8/186611fea06d2870/clk_wiz_0_sim_netlist.v
@@ -0,0 +1,258 @@
+// Copyright 1986-2022 Xilinx, Inc. All Rights Reserved.
+// --------------------------------------------------------------------------------
+// Tool Version: Vivado v.2022.2 (lin64) Build 3671981 Fri Oct 14 04:59:54 MDT 2022
+// Date : Mon Feb 27 10:46:52 2023
+// Host : LikeUE06 running 64-bit Linux Mint 20.3
+// Command : write_verilog -force -mode funcsim -rename_top decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix -prefix
+// decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_ clk_wiz_0_sim_netlist.v
+// Design : clk_wiz_0
+// Purpose : This verilog netlist is a functional simulation representation of the design and should not be modified
+// or synthesized. This netlist cannot be used for SDF annotated simulation.
+// Device : xc7a100tcsg324-1
+// --------------------------------------------------------------------------------
+`timescale 1 ps / 1 ps
+
+(* NotValidForBitStream *)
+module decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix
+ (clk_out1,
+ resetn,
+ clk_in1);
+ output clk_out1;
+ input resetn;
+ input clk_in1;
+
+ (* IBUF_LOW_PWR *) wire clk_in1;
+ wire clk_out1;
+ wire resetn;
+
+ decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_clk_wiz_0_clk_wiz inst
+ (.clk_in1(clk_in1),
+ .clk_out1(clk_out1),
+ .resetn(resetn));
+endmodule
+
+module decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_clk_wiz_0_clk_wiz
+ (clk_out1,
+ resetn,
+ clk_in1);
+ output clk_out1;
+ input resetn;
+ input clk_in1;
+
+ wire clk_in1;
+ wire clk_in1_clk_wiz_0;
+ wire clk_out1;
+ wire clk_out1_clk_wiz_0;
+ wire clkfbout_buf_clk_wiz_0;
+ wire clkfbout_clk_wiz_0;
+ wire reset_high;
+ wire resetn;
+ wire NLW_mmcm_adv_inst_CLKFBOUTB_UNCONNECTED;
+ wire NLW_mmcm_adv_inst_CLKFBSTOPPED_UNCONNECTED;
+ wire NLW_mmcm_adv_inst_CLKINSTOPPED_UNCONNECTED;
+ wire NLW_mmcm_adv_inst_CLKOUT0B_UNCONNECTED;
+ wire NLW_mmcm_adv_inst_CLKOUT1_UNCONNECTED;
+ wire NLW_mmcm_adv_inst_CLKOUT1B_UNCONNECTED;
+ wire NLW_mmcm_adv_inst_CLKOUT2_UNCONNECTED;
+ wire NLW_mmcm_adv_inst_CLKOUT2B_UNCONNECTED;
+ wire NLW_mmcm_adv_inst_CLKOUT3_UNCONNECTED;
+ wire NLW_mmcm_adv_inst_CLKOUT3B_UNCONNECTED;
+ wire NLW_mmcm_adv_inst_CLKOUT4_UNCONNECTED;
+ wire NLW_mmcm_adv_inst_CLKOUT5_UNCONNECTED;
+ wire NLW_mmcm_adv_inst_CLKOUT6_UNCONNECTED;
+ wire NLW_mmcm_adv_inst_DRDY_UNCONNECTED;
+ wire NLW_mmcm_adv_inst_LOCKED_UNCONNECTED;
+ wire NLW_mmcm_adv_inst_PSDONE_UNCONNECTED;
+ wire [15:0]NLW_mmcm_adv_inst_DO_UNCONNECTED;
+
+ (* BOX_TYPE = "PRIMITIVE" *)
+ BUFG clkf_buf
+ (.I(clkfbout_clk_wiz_0),
+ .O(clkfbout_buf_clk_wiz_0));
+ (* BOX_TYPE = "PRIMITIVE" *)
+ (* CAPACITANCE = "DONT_CARE" *)
+ (* IBUF_DELAY_VALUE = "0" *)
+ (* IFD_DELAY_VALUE = "AUTO" *)
+ IBUF #(
+ .CCIO_EN("TRUE"),
+ .IOSTANDARD("DEFAULT"))
+ clkin1_ibufg
+ (.I(clk_in1),
+ .O(clk_in1_clk_wiz_0));
+ (* BOX_TYPE = "PRIMITIVE" *)
+ BUFG clkout1_buf
+ (.I(clk_out1_clk_wiz_0),
+ .O(clk_out1));
+ (* BOX_TYPE = "PRIMITIVE" *)
+ MMCME2_ADV #(
+ .BANDWIDTH("OPTIMIZED"),
+ .CLKFBOUT_MULT_F(9.125000),
+ .CLKFBOUT_PHASE(0.000000),
+ .CLKFBOUT_USE_FINE_PS("FALSE"),
+ .CLKIN1_PERIOD(10.000000),
+ .CLKIN2_PERIOD(0.000000),
+ .CLKOUT0_DIVIDE_F(36.500000),
+ .CLKOUT0_DUTY_CYCLE(0.500000),
+ .CLKOUT0_PHASE(0.000000),
+ .CLKOUT0_USE_FINE_PS("FALSE"),
+ .CLKOUT1_DIVIDE(1),
+ .CLKOUT1_DUTY_CYCLE(0.500000),
+ .CLKOUT1_PHASE(0.000000),
+ .CLKOUT1_USE_FINE_PS("FALSE"),
+ .CLKOUT2_DIVIDE(1),
+ .CLKOUT2_DUTY_CYCLE(0.500000),
+ .CLKOUT2_PHASE(0.000000),
+ .CLKOUT2_USE_FINE_PS("FALSE"),
+ .CLKOUT3_DIVIDE(1),
+ .CLKOUT3_DUTY_CYCLE(0.500000),
+ .CLKOUT3_PHASE(0.000000),
+ .CLKOUT3_USE_FINE_PS("FALSE"),
+ .CLKOUT4_CASCADE("FALSE"),
+ .CLKOUT4_DIVIDE(1),
+ .CLKOUT4_DUTY_CYCLE(0.500000),
+ .CLKOUT4_PHASE(0.000000),
+ .CLKOUT4_USE_FINE_PS("FALSE"),
+ .CLKOUT5_DIVIDE(1),
+ .CLKOUT5_DUTY_CYCLE(0.500000),
+ .CLKOUT5_PHASE(0.000000),
+ .CLKOUT5_USE_FINE_PS("FALSE"),
+ .CLKOUT6_DIVIDE(1),
+ .CLKOUT6_DUTY_CYCLE(0.500000),
+ .CLKOUT6_PHASE(0.000000),
+ .CLKOUT6_USE_FINE_PS("FALSE"),
+ .COMPENSATION("ZHOLD"),
+ .DIVCLK_DIVIDE(1),
+ .IS_CLKINSEL_INVERTED(1'b0),
+ .IS_PSEN_INVERTED(1'b0),
+ .IS_PSINCDEC_INVERTED(1'b0),
+ .IS_PWRDWN_INVERTED(1'b0),
+ .IS_RST_INVERTED(1'b0),
+ .REF_JITTER1(0.010000),
+ .REF_JITTER2(0.010000),
+ .SS_EN("FALSE"),
+ .SS_MODE("CENTER_HIGH"),
+ .SS_MOD_PERIOD(10000),
+ .STARTUP_WAIT("FALSE"))
+ mmcm_adv_inst
+ (.CLKFBIN(clkfbout_buf_clk_wiz_0),
+ .CLKFBOUT(clkfbout_clk_wiz_0),
+ .CLKFBOUTB(NLW_mmcm_adv_inst_CLKFBOUTB_UNCONNECTED),
+ .CLKFBSTOPPED(NLW_mmcm_adv_inst_CLKFBSTOPPED_UNCONNECTED),
+ .CLKIN1(clk_in1_clk_wiz_0),
+ .CLKIN2(1'b0),
+ .CLKINSEL(1'b1),
+ .CLKINSTOPPED(NLW_mmcm_adv_inst_CLKINSTOPPED_UNCONNECTED),
+ .CLKOUT0(clk_out1_clk_wiz_0),
+ .CLKOUT0B(NLW_mmcm_adv_inst_CLKOUT0B_UNCONNECTED),
+ .CLKOUT1(NLW_mmcm_adv_inst_CLKOUT1_UNCONNECTED),
+ .CLKOUT1B(NLW_mmcm_adv_inst_CLKOUT1B_UNCONNECTED),
+ .CLKOUT2(NLW_mmcm_adv_inst_CLKOUT2_UNCONNECTED),
+ .CLKOUT2B(NLW_mmcm_adv_inst_CLKOUT2B_UNCONNECTED),
+ .CLKOUT3(NLW_mmcm_adv_inst_CLKOUT3_UNCONNECTED),
+ .CLKOUT3B(NLW_mmcm_adv_inst_CLKOUT3B_UNCONNECTED),
+ .CLKOUT4(NLW_mmcm_adv_inst_CLKOUT4_UNCONNECTED),
+ .CLKOUT5(NLW_mmcm_adv_inst_CLKOUT5_UNCONNECTED),
+ .CLKOUT6(NLW_mmcm_adv_inst_CLKOUT6_UNCONNECTED),
+ .DADDR({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
+ .DCLK(1'b0),
+ .DEN(1'b0),
+ .DI({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
+ .DO(NLW_mmcm_adv_inst_DO_UNCONNECTED[15:0]),
+ .DRDY(NLW_mmcm_adv_inst_DRDY_UNCONNECTED),
+ .DWE(1'b0),
+ .LOCKED(NLW_mmcm_adv_inst_LOCKED_UNCONNECTED),
+ .PSCLK(1'b0),
+ .PSDONE(NLW_mmcm_adv_inst_PSDONE_UNCONNECTED),
+ .PSEN(1'b0),
+ .PSINCDEC(1'b0),
+ .PWRDWN(1'b0),
+ .RST(reset_high));
+ LUT1 #(
+ .INIT(2'h1))
+ mmcm_adv_inst_i_1
+ (.I0(resetn),
+ .O(reset_high));
+endmodule
+`ifndef GLBL
+`define GLBL
+`timescale 1 ps / 1 ps
+
+module glbl ();
+
+ parameter ROC_WIDTH = 100000;
+ parameter TOC_WIDTH = 0;
+ parameter GRES_WIDTH = 10000;
+ parameter GRES_START = 10000;
+
+//-------- STARTUP Globals --------------
+ wire GSR;
+ wire GTS;
+ wire GWE;
+ wire PRLD;
+ wire GRESTORE;
+ tri1 p_up_tmp;
+ tri (weak1, strong0) PLL_LOCKG = p_up_tmp;
+
+ wire PROGB_GLBL;
+ wire CCLKO_GLBL;
+ wire FCSBO_GLBL;
+ wire [3:0] DO_GLBL;
+ wire [3:0] DI_GLBL;
+
+ reg GSR_int;
+ reg GTS_int;
+ reg PRLD_int;
+ reg GRESTORE_int;
+
+//-------- JTAG Globals --------------
+ wire JTAG_TDO_GLBL;
+ wire JTAG_TCK_GLBL;
+ wire JTAG_TDI_GLBL;
+ wire JTAG_TMS_GLBL;
+ wire JTAG_TRST_GLBL;
+
+ reg JTAG_CAPTURE_GLBL;
+ reg JTAG_RESET_GLBL;
+ reg JTAG_SHIFT_GLBL;
+ reg JTAG_UPDATE_GLBL;
+ reg JTAG_RUNTEST_GLBL;
+
+ reg JTAG_SEL1_GLBL = 0;
+ reg JTAG_SEL2_GLBL = 0 ;
+ reg JTAG_SEL3_GLBL = 0;
+ reg JTAG_SEL4_GLBL = 0;
+
+ reg JTAG_USER_TDO1_GLBL = 1'bz;
+ reg JTAG_USER_TDO2_GLBL = 1'bz;
+ reg JTAG_USER_TDO3_GLBL = 1'bz;
+ reg JTAG_USER_TDO4_GLBL = 1'bz;
+
+ assign (strong1, weak0) GSR = GSR_int;
+ assign (strong1, weak0) GTS = GTS_int;
+ assign (weak1, weak0) PRLD = PRLD_int;
+ assign (strong1, weak0) GRESTORE = GRESTORE_int;
+
+ initial begin
+ GSR_int = 1'b1;
+ PRLD_int = 1'b1;
+ #(ROC_WIDTH)
+ GSR_int = 1'b0;
+ PRLD_int = 1'b0;
+ end
+
+ initial begin
+ GTS_int = 1'b1;
+ #(TOC_WIDTH)
+ GTS_int = 1'b0;
+ end
+
+ initial begin
+ GRESTORE_int = 1'b0;
+ #(GRES_START);
+ GRESTORE_int = 1'b1;
+ #(GRES_WIDTH);
+ GRESTORE_int = 1'b0;
+ end
+
+endmodule
+`endif
diff --git a/game.cache/ip/2022.2/1/8/186611fea06d2870/clk_wiz_0_sim_netlist.vhdl b/game.cache/ip/2022.2/1/8/186611fea06d2870/clk_wiz_0_sim_netlist.vhdl
new file mode 100755
index 0000000000000000000000000000000000000000..f25af002e3c3ad7e04243cd403bda30140ffaec5
--- /dev/null
+++ b/game.cache/ip/2022.2/1/8/186611fea06d2870/clk_wiz_0_sim_netlist.vhdl
@@ -0,0 +1,196 @@
+-- Copyright 1986-2022 Xilinx, Inc. All Rights Reserved.
+-- --------------------------------------------------------------------------------
+-- Tool Version: Vivado v.2022.2 (lin64) Build 3671981 Fri Oct 14 04:59:54 MDT 2022
+-- Date : Mon Feb 27 10:46:52 2023
+-- Host : LikeUE06 running 64-bit Linux Mint 20.3
+-- Command : write_vhdl -force -mode funcsim -rename_top decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix -prefix
+-- decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_ clk_wiz_0_sim_netlist.vhdl
+-- Design : clk_wiz_0
+-- Purpose : This VHDL netlist is a functional simulation representation of the design and should not be modified or
+-- synthesized. This netlist cannot be used for SDF annotated simulation.
+-- Device : xc7a100tcsg324-1
+-- --------------------------------------------------------------------------------
+library IEEE;
+use IEEE.STD_LOGIC_1164.ALL;
+library UNISIM;
+use UNISIM.VCOMPONENTS.ALL;
+entity decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_clk_wiz_0_clk_wiz is
+ port (
+ clk_out1 : out STD_LOGIC;
+ resetn : in STD_LOGIC;
+ clk_in1 : in STD_LOGIC
+ );
+end decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_clk_wiz_0_clk_wiz;
+
+architecture STRUCTURE of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_clk_wiz_0_clk_wiz is
+ signal clk_in1_clk_wiz_0 : STD_LOGIC;
+ signal clk_out1_clk_wiz_0 : STD_LOGIC;
+ signal clkfbout_buf_clk_wiz_0 : STD_LOGIC;
+ signal clkfbout_clk_wiz_0 : STD_LOGIC;
+ signal reset_high : STD_LOGIC;
+ signal NLW_mmcm_adv_inst_CLKFBOUTB_UNCONNECTED : STD_LOGIC;
+ signal NLW_mmcm_adv_inst_CLKFBSTOPPED_UNCONNECTED : STD_LOGIC;
+ signal NLW_mmcm_adv_inst_CLKINSTOPPED_UNCONNECTED : STD_LOGIC;
+ signal NLW_mmcm_adv_inst_CLKOUT0B_UNCONNECTED : STD_LOGIC;
+ signal NLW_mmcm_adv_inst_CLKOUT1_UNCONNECTED : STD_LOGIC;
+ signal NLW_mmcm_adv_inst_CLKOUT1B_UNCONNECTED : STD_LOGIC;
+ signal NLW_mmcm_adv_inst_CLKOUT2_UNCONNECTED : STD_LOGIC;
+ signal NLW_mmcm_adv_inst_CLKOUT2B_UNCONNECTED : STD_LOGIC;
+ signal NLW_mmcm_adv_inst_CLKOUT3_UNCONNECTED : STD_LOGIC;
+ signal NLW_mmcm_adv_inst_CLKOUT3B_UNCONNECTED : STD_LOGIC;
+ signal NLW_mmcm_adv_inst_CLKOUT4_UNCONNECTED : STD_LOGIC;
+ signal NLW_mmcm_adv_inst_CLKOUT5_UNCONNECTED : STD_LOGIC;
+ signal NLW_mmcm_adv_inst_CLKOUT6_UNCONNECTED : STD_LOGIC;
+ signal NLW_mmcm_adv_inst_DRDY_UNCONNECTED : STD_LOGIC;
+ signal NLW_mmcm_adv_inst_LOCKED_UNCONNECTED : STD_LOGIC;
+ signal NLW_mmcm_adv_inst_PSDONE_UNCONNECTED : STD_LOGIC;
+ signal NLW_mmcm_adv_inst_DO_UNCONNECTED : STD_LOGIC_VECTOR ( 15 downto 0 );
+ attribute BOX_TYPE : string;
+ attribute BOX_TYPE of clkf_buf : label is "PRIMITIVE";
+ attribute BOX_TYPE of clkin1_ibufg : label is "PRIMITIVE";
+ attribute CAPACITANCE : string;
+ attribute CAPACITANCE of clkin1_ibufg : label is "DONT_CARE";
+ attribute IBUF_DELAY_VALUE : string;
+ attribute IBUF_DELAY_VALUE of clkin1_ibufg : label is "0";
+ attribute IFD_DELAY_VALUE : string;
+ attribute IFD_DELAY_VALUE of clkin1_ibufg : label is "AUTO";
+ attribute BOX_TYPE of clkout1_buf : label is "PRIMITIVE";
+ attribute BOX_TYPE of mmcm_adv_inst : label is "PRIMITIVE";
+begin
+clkf_buf: unisim.vcomponents.BUFG
+ port map (
+ I => clkfbout_clk_wiz_0,
+ O => clkfbout_buf_clk_wiz_0
+ );
+clkin1_ibufg: unisim.vcomponents.IBUF
+ generic map(
+ CCIO_EN => "TRUE",
+ IOSTANDARD => "DEFAULT"
+ )
+ port map (
+ I => clk_in1,
+ O => clk_in1_clk_wiz_0
+ );
+clkout1_buf: unisim.vcomponents.BUFG
+ port map (
+ I => clk_out1_clk_wiz_0,
+ O => clk_out1
+ );
+mmcm_adv_inst: unisim.vcomponents.MMCME2_ADV
+ generic map(
+ BANDWIDTH => "OPTIMIZED",
+ CLKFBOUT_MULT_F => 9.125000,
+ CLKFBOUT_PHASE => 0.000000,
+ CLKFBOUT_USE_FINE_PS => false,
+ CLKIN1_PERIOD => 10.000000,
+ CLKIN2_PERIOD => 0.000000,
+ CLKOUT0_DIVIDE_F => 36.500000,
+ CLKOUT0_DUTY_CYCLE => 0.500000,
+ CLKOUT0_PHASE => 0.000000,
+ CLKOUT0_USE_FINE_PS => false,
+ CLKOUT1_DIVIDE => 1,
+ CLKOUT1_DUTY_CYCLE => 0.500000,
+ CLKOUT1_PHASE => 0.000000,
+ CLKOUT1_USE_FINE_PS => false,
+ CLKOUT2_DIVIDE => 1,
+ CLKOUT2_DUTY_CYCLE => 0.500000,
+ CLKOUT2_PHASE => 0.000000,
+ CLKOUT2_USE_FINE_PS => false,
+ CLKOUT3_DIVIDE => 1,
+ CLKOUT3_DUTY_CYCLE => 0.500000,
+ CLKOUT3_PHASE => 0.000000,
+ CLKOUT3_USE_FINE_PS => false,
+ CLKOUT4_CASCADE => false,
+ CLKOUT4_DIVIDE => 1,
+ CLKOUT4_DUTY_CYCLE => 0.500000,
+ CLKOUT4_PHASE => 0.000000,
+ CLKOUT4_USE_FINE_PS => false,
+ CLKOUT5_DIVIDE => 1,
+ CLKOUT5_DUTY_CYCLE => 0.500000,
+ CLKOUT5_PHASE => 0.000000,
+ CLKOUT5_USE_FINE_PS => false,
+ CLKOUT6_DIVIDE => 1,
+ CLKOUT6_DUTY_CYCLE => 0.500000,
+ CLKOUT6_PHASE => 0.000000,
+ CLKOUT6_USE_FINE_PS => false,
+ COMPENSATION => "ZHOLD",
+ DIVCLK_DIVIDE => 1,
+ IS_CLKINSEL_INVERTED => '0',
+ IS_PSEN_INVERTED => '0',
+ IS_PSINCDEC_INVERTED => '0',
+ IS_PWRDWN_INVERTED => '0',
+ IS_RST_INVERTED => '0',
+ REF_JITTER1 => 0.010000,
+ REF_JITTER2 => 0.010000,
+ SS_EN => "FALSE",
+ SS_MODE => "CENTER_HIGH",
+ SS_MOD_PERIOD => 10000,
+ STARTUP_WAIT => false
+ )
+ port map (
+ CLKFBIN => clkfbout_buf_clk_wiz_0,
+ CLKFBOUT => clkfbout_clk_wiz_0,
+ CLKFBOUTB => NLW_mmcm_adv_inst_CLKFBOUTB_UNCONNECTED,
+ CLKFBSTOPPED => NLW_mmcm_adv_inst_CLKFBSTOPPED_UNCONNECTED,
+ CLKIN1 => clk_in1_clk_wiz_0,
+ CLKIN2 => '0',
+ CLKINSEL => '1',
+ CLKINSTOPPED => NLW_mmcm_adv_inst_CLKINSTOPPED_UNCONNECTED,
+ CLKOUT0 => clk_out1_clk_wiz_0,
+ CLKOUT0B => NLW_mmcm_adv_inst_CLKOUT0B_UNCONNECTED,
+ CLKOUT1 => NLW_mmcm_adv_inst_CLKOUT1_UNCONNECTED,
+ CLKOUT1B => NLW_mmcm_adv_inst_CLKOUT1B_UNCONNECTED,
+ CLKOUT2 => NLW_mmcm_adv_inst_CLKOUT2_UNCONNECTED,
+ CLKOUT2B => NLW_mmcm_adv_inst_CLKOUT2B_UNCONNECTED,
+ CLKOUT3 => NLW_mmcm_adv_inst_CLKOUT3_UNCONNECTED,
+ CLKOUT3B => NLW_mmcm_adv_inst_CLKOUT3B_UNCONNECTED,
+ CLKOUT4 => NLW_mmcm_adv_inst_CLKOUT4_UNCONNECTED,
+ CLKOUT5 => NLW_mmcm_adv_inst_CLKOUT5_UNCONNECTED,
+ CLKOUT6 => NLW_mmcm_adv_inst_CLKOUT6_UNCONNECTED,
+ DADDR(6 downto 0) => B"0000000",
+ DCLK => '0',
+ DEN => '0',
+ DI(15 downto 0) => B"0000000000000000",
+ DO(15 downto 0) => NLW_mmcm_adv_inst_DO_UNCONNECTED(15 downto 0),
+ DRDY => NLW_mmcm_adv_inst_DRDY_UNCONNECTED,
+ DWE => '0',
+ LOCKED => NLW_mmcm_adv_inst_LOCKED_UNCONNECTED,
+ PSCLK => '0',
+ PSDONE => NLW_mmcm_adv_inst_PSDONE_UNCONNECTED,
+ PSEN => '0',
+ PSINCDEC => '0',
+ PWRDWN => '0',
+ RST => reset_high
+ );
+mmcm_adv_inst_i_1: unisim.vcomponents.LUT1
+ generic map(
+ INIT => X"1"
+ )
+ port map (
+ I0 => resetn,
+ O => reset_high
+ );
+end STRUCTURE;
+library IEEE;
+use IEEE.STD_LOGIC_1164.ALL;
+library UNISIM;
+use UNISIM.VCOMPONENTS.ALL;
+entity decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix is
+ port (
+ clk_out1 : out STD_LOGIC;
+ resetn : in STD_LOGIC;
+ clk_in1 : in STD_LOGIC
+ );
+ attribute NotValidForBitStream : boolean;
+ attribute NotValidForBitStream of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix : entity is true;
+end decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix;
+
+architecture STRUCTURE of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix is
+begin
+inst: entity work.decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_clk_wiz_0_clk_wiz
+ port map (
+ clk_in1 => clk_in1,
+ clk_out1 => clk_out1,
+ resetn => resetn
+ );
+end STRUCTURE;
diff --git a/game.cache/ip/2022.2/1/8/186611fea06d2870/clk_wiz_0_stub.v b/game.cache/ip/2022.2/1/8/186611fea06d2870/clk_wiz_0_stub.v
new file mode 100755
index 0000000000000000000000000000000000000000..74698fd901afb581e1bd85d6a0be0a8380822c91
--- /dev/null
+++ b/game.cache/ip/2022.2/1/8/186611fea06d2870/clk_wiz_0_stub.v
@@ -0,0 +1,21 @@
+// Copyright 1986-2022 Xilinx, Inc. All Rights Reserved.
+// --------------------------------------------------------------------------------
+// Tool Version: Vivado v.2022.2 (lin64) Build 3671981 Fri Oct 14 04:59:54 MDT 2022
+// Date : Mon Feb 27 10:46:51 2023
+// Host : LikeUE06 running 64-bit Linux Mint 20.3
+// Command : write_verilog -force -mode synth_stub -rename_top decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix -prefix
+// decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_ clk_wiz_0_stub.v
+// Design : clk_wiz_0
+// Purpose : Stub declaration of top-level module interface
+// Device : xc7a100tcsg324-1
+// --------------------------------------------------------------------------------
+
+// This empty module with port declaration file causes synthesis tools to infer a black box for IP.
+// The synthesis directives are for Synopsys Synplify support to prevent IO buffer insertion.
+// Please paste the declaration into a Verilog source file or add the file as an additional source.
+module decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix(clk_out1, resetn, clk_in1)
+/* synthesis syn_black_box black_box_pad_pin="clk_out1,resetn,clk_in1" */;
+ output clk_out1;
+ input resetn;
+ input clk_in1;
+endmodule
diff --git a/game.cache/ip/2022.2/1/8/186611fea06d2870/clk_wiz_0_stub.vhdl b/game.cache/ip/2022.2/1/8/186611fea06d2870/clk_wiz_0_stub.vhdl
new file mode 100755
index 0000000000000000000000000000000000000000..0354892c999aa725e573dcbdc18924327b178697
--- /dev/null
+++ b/game.cache/ip/2022.2/1/8/186611fea06d2870/clk_wiz_0_stub.vhdl
@@ -0,0 +1,30 @@
+-- Copyright 1986-2022 Xilinx, Inc. All Rights Reserved.
+-- --------------------------------------------------------------------------------
+-- Tool Version: Vivado v.2022.2 (lin64) Build 3671981 Fri Oct 14 04:59:54 MDT 2022
+-- Date : Mon Feb 27 10:46:51 2023
+-- Host : LikeUE06 running 64-bit Linux Mint 20.3
+-- Command : write_vhdl -force -mode synth_stub -rename_top decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix -prefix
+-- decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_ clk_wiz_0_stub.vhdl
+-- Design : clk_wiz_0
+-- Purpose : Stub declaration of top-level module interface
+-- Device : xc7a100tcsg324-1
+-- --------------------------------------------------------------------------------
+library IEEE;
+use IEEE.STD_LOGIC_1164.ALL;
+
+entity decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix is
+ Port (
+ clk_out1 : out STD_LOGIC;
+ resetn : in STD_LOGIC;
+ clk_in1 : in STD_LOGIC
+ );
+
+end decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix;
+
+architecture stub of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix is
+attribute syn_black_box : boolean;
+attribute black_box_pad_pin : string;
+attribute syn_black_box of stub : architecture is true;
+attribute black_box_pad_pin of stub : architecture is "clk_out1,resetn,clk_in1";
+begin
+end;
diff --git a/game.cache/sim/ssm.db b/game.cache/sim/ssm.db
new file mode 100644
index 0000000000000000000000000000000000000000..f642a5141fd151e15137ed5f80f7c576fa005d60
--- /dev/null
+++ b/game.cache/sim/ssm.db
@@ -0,0 +1,12 @@
+################################################################################
+# DONOT REMOVE THIS FILE
+# Unified simulation database file for selected simulation model for IP
+#
+# File: ssm.db (Mon Feb 27 12:45:36 2023)
+#
+# This file is generated by the unified simulation automation and contains the
+# selected simulation model information for the IP/BD instances.
+# DONOT REMOVE THIS FILE
+################################################################################
+clk_wiz_0,rtl
+clk_wiz_1,rtl
diff --git a/game.cache/wt/project.wpc b/game.cache/wt/project.wpc
new file mode 100644
index 0000000000000000000000000000000000000000..30d3330fd06ee45c9c4838b5a3767b6cba4e65d6
--- /dev/null
+++ b/game.cache/wt/project.wpc
@@ -0,0 +1,3 @@
+version:1
+6d6f64655f636f756e7465727c4755494d6f6465:4
+eof:
diff --git a/game.cache/wt/synthesis.wdf b/game.cache/wt/synthesis.wdf
new file mode 100644
index 0000000000000000000000000000000000000000..689475f48df2c65f30dc156bb6660ade05670caa
--- /dev/null
+++ b/game.cache/wt/synthesis.wdf
@@ -0,0 +1,47 @@
+version:1
+73796e746865736973:73796e7468657369735c636f6d6d616e645f6c696e655f6f7074696f6e73:2d70617274:78633761313030746373673332342d31:00:00
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diff --git a/game.cache/wt/synthesis_details.wdf b/game.cache/wt/synthesis_details.wdf
new file mode 100644
index 0000000000000000000000000000000000000000..78f8d66e566c72c9b7f2063ebfcca519992e3006
--- /dev/null
+++ b/game.cache/wt/synthesis_details.wdf
@@ -0,0 +1,3 @@
+version:1
+73796e746865736973:73796e7468657369735c7573616765:686c735f6970:30:00:00
+eof:2511430288
diff --git a/game.cache/wt/webtalk_pa.xml b/game.cache/wt/webtalk_pa.xml
new file mode 100644
index 0000000000000000000000000000000000000000..f02c8dd453bfa47623dd160809b3b822c4d154f8
--- /dev/null
+++ b/game.cache/wt/webtalk_pa.xml
@@ -0,0 +1,21 @@
+<?xml version="1.0" encoding="UTF-8" ?>
+<document>
+<!--The data in this file is primarily intended for consumption by Xilinx tools.
+The structure and the elements are likely to change over the next few releases.
+This means code written to parse this file will need to be revisited each subsequent release.-->
+<application name="pa" timeStamp="Tue Feb 28 17:00:53 2023">
+<section name="Project Information" visible="false">
+<property name="ProjectID" value="62c9dceeeae7423dacdbf7c86449ea63" type="ProjectID"/>
+<property name="ProjectIteration" value="56" type="ProjectIteration"/>
+</section>
+<section name="PlanAhead Usage" visible="true">
+<item name="Project Data">
+<property name="SrcSetCount" value="1" type="SrcSetCount"/>
+<property name="ConstraintSetCount" value="1" type="ConstraintSetCount"/>
+<property name="DesignMode" value="RTL" type="DesignMode"/>
+<property name="SynthesisStrategy" value="Vivado Synthesis Defaults" type="SynthesisStrategy"/>
+<property name="ImplStrategy" value="Vivado Implementation Defaults" type="ImplStrategy"/>
+</item>
+</section>
+</application>
+</document>
diff --git a/game.cache/wt/xsim.wdf b/game.cache/wt/xsim.wdf
new file mode 100644
index 0000000000000000000000000000000000000000..50afb2c7aebfafa7cc5fa823be2031ae4ebbf3af
--- /dev/null
+++ b/game.cache/wt/xsim.wdf
@@ -0,0 +1,4 @@
+version:1
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+eof:241934075
diff --git a/game.gen/sources_1/ip/clk_wiz_0/clk_wiz_0.dcp b/game.gen/sources_1/ip/clk_wiz_0/clk_wiz_0.dcp
new file mode 100644
index 0000000000000000000000000000000000000000..08b3e248e4bbd9eb3a5701ea43e6671ccdbfd720
Binary files /dev/null and b/game.gen/sources_1/ip/clk_wiz_0/clk_wiz_0.dcp differ
diff --git a/game.gen/sources_1/ip/clk_wiz_0/clk_wiz_0.v b/game.gen/sources_1/ip/clk_wiz_0/clk_wiz_0.v
new file mode 100644
index 0000000000000000000000000000000000000000..21ba75f16c1e98c0aa918fc7c7080e462070a5b3
--- /dev/null
+++ b/game.gen/sources_1/ip/clk_wiz_0/clk_wiz_0.v
@@ -0,0 +1,90 @@
+
+// file: clk_wiz_0.v
+//
+// (c) Copyright 2008 - 2013 Xilinx, Inc. All rights reserved.
+//
+// This file contains confidential and proprietary information
+// of Xilinx, Inc. and is protected under U.S. and
+// international copyright and other intellectual property
+// laws.
+//
+// DISCLAIMER
+// This disclaimer is not a license and does not grant any
+// rights to the materials distributed herewith. Except as
+// otherwise provided in a valid license issued to you by
+// Xilinx, and to the maximum extent permitted by applicable
+// law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
+// WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
+// AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
+// BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
+// INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
+// (2) Xilinx shall not be liable (whether in contract or tort,
+// including negligence, or under any other theory of
+// liability) for any loss or damage of any kind or nature
+// related to, arising under or in connection with these
+// materials, including for any direct, or any indirect,
+// special, incidental, or consequential loss or damage
+// (including loss of data, profits, goodwill, or any type of
+// loss or damage suffered as a result of any action brought
+// by a third party) even if such damage or loss was
+// reasonably foreseeable or Xilinx had been advised of the
+// possibility of the same.
+//
+// CRITICAL APPLICATIONS
+// Xilinx products are not designed or intended to be fail-
+// safe, or for use in any application requiring fail-safe
+// performance, such as life-support or safety devices or
+// systems, Class III medical devices, nuclear facilities,
+// applications related to the deployment of airbags, or any
+// other applications that could lead to death, personal
+// injury, or severe property or environmental damage
+// (individually and collectively, "Critical
+// Applications"). Customer assumes the sole risk and
+// liability of any use of Xilinx products in Critical
+// Applications, subject only to applicable laws and
+// regulations governing limitations on product liability.
+//
+// THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
+// PART OF THIS FILE AT ALL TIMES.
+//
+//----------------------------------------------------------------------------
+// User entered comments
+//----------------------------------------------------------------------------
+// None
+//
+//----------------------------------------------------------------------------
+// Output Output Phase Duty Cycle Pk-to-Pk Phase
+// Clock Freq (MHz) (degrees) (%) Jitter (ps) Error (ps)
+//----------------------------------------------------------------------------
+// clk_out1__25.00000______0.000______50.0______181.828____104.359
+//
+//----------------------------------------------------------------------------
+// Input Clock Freq (MHz) Input Jitter (UI)
+//----------------------------------------------------------------------------
+// __primary_________100.000____________0.010
+
+`timescale 1ps/1ps
+
+(* CORE_GENERATION_INFO = "clk_wiz_0,clk_wiz_v6_0_11_0_0,{component_name=clk_wiz_0,use_phase_alignment=true,use_min_o_jitter=false,use_max_i_jitter=false,use_dyn_phase_shift=false,use_inclk_switchover=false,use_dyn_reconfig=false,enable_axi=0,feedback_source=FDBK_AUTO,PRIMITIVE=MMCM,num_out_clk=1,clkin1_period=10.000,clkin2_period=10.000,use_power_down=false,use_reset=true,use_locked=false,use_inclk_stopped=false,feedback_type=SINGLE,CLOCK_MGR_TYPE=NA,manual_override=false}" *)
+
+module clk_wiz_0
+ (
+ // Clock out ports
+ output clk_out1,
+ // Status and control signals
+ input resetn,
+ // Clock in ports
+ input clk_in1
+ );
+
+ clk_wiz_0_clk_wiz inst
+ (
+ // Clock out ports
+ .clk_out1(clk_out1),
+ // Status and control signals
+ .resetn(resetn),
+ // Clock in ports
+ .clk_in1(clk_in1)
+ );
+
+endmodule
diff --git a/game.gen/sources_1/ip/clk_wiz_0/clk_wiz_0.vho b/game.gen/sources_1/ip/clk_wiz_0/clk_wiz_0.vho
new file mode 100644
index 0000000000000000000000000000000000000000..0fa97dbfe9fd121047d190f4c2b038836ac332a6
--- /dev/null
+++ b/game.gen/sources_1/ip/clk_wiz_0/clk_wiz_0.vho
@@ -0,0 +1,92 @@
+
+--
+-- (c) Copyright 2008 - 2013 Xilinx, Inc. All rights reserved.
+--
+-- This file contains confidential and proprietary information
+-- of Xilinx, Inc. and is protected under U.S. and
+-- international copyright and other intellectual property
+-- laws.
+--
+-- DISCLAIMER
+-- This disclaimer is not a license and does not grant any
+-- rights to the materials distributed herewith. Except as
+-- otherwise provided in a valid license issued to you by
+-- Xilinx, and to the maximum extent permitted by applicable
+-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
+-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
+-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
+-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
+-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
+-- (2) Xilinx shall not be liable (whether in contract or tort,
+-- including negligence, or under any other theory of
+-- liability) for any loss or damage of any kind or nature
+-- related to, arising under or in connection with these
+-- materials, including for any direct, or any indirect,
+-- special, incidental, or consequential loss or damage
+-- (including loss of data, profits, goodwill, or any type of
+-- loss or damage suffered as a result of any action brought
+-- by a third party) even if such damage or loss was
+-- reasonably foreseeable or Xilinx had been advised of the
+-- possibility of the same.
+--
+-- CRITICAL APPLICATIONS
+-- Xilinx products are not designed or intended to be fail-
+-- safe, or for use in any application requiring fail-safe
+-- performance, such as life-support or safety devices or
+-- systems, Class III medical devices, nuclear facilities,
+-- applications related to the deployment of airbags, or any
+-- other applications that could lead to death, personal
+-- injury, or severe property or environmental damage
+-- (individually and collectively, "Critical
+-- Applications"). Customer assumes the sole risk and
+-- liability of any use of Xilinx products in Critical
+-- Applications, subject only to applicable laws and
+-- regulations governing limitations on product liability.
+--
+-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
+-- PART OF THIS FILE AT ALL TIMES.
+--
+------------------------------------------------------------------------------
+-- User entered comments
+------------------------------------------------------------------------------
+-- None
+--
+------------------------------------------------------------------------------
+-- Output Output Phase Duty Cycle Pk-to-Pk Phase
+-- Clock Freq (MHz) (degrees) (%) Jitter (ps) Error (ps)
+------------------------------------------------------------------------------
+-- clk_out1__25.00000______0.000______50.0______181.828____104.359
+--
+------------------------------------------------------------------------------
+-- Input Clock Freq (MHz) Input Jitter (UI)
+------------------------------------------------------------------------------
+-- __primary_________100.000____________0.010
+
+
+-- The following code must appear in the VHDL architecture header:
+------------- Begin Cut here for COMPONENT Declaration ------ COMP_TAG
+component clk_wiz_0
+port
+ (-- Clock in ports
+ -- Clock out ports
+ clk_out1 : out std_logic;
+ -- Status and control signals
+ resetn : in std_logic;
+ clk_in1 : in std_logic
+ );
+end component;
+
+-- COMP_TAG_END ------ End COMPONENT Declaration ------------
+-- The following code must appear in the VHDL architecture
+-- body. Substitute your own instance name and net names.
+------------- Begin Cut here for INSTANTIATION Template ----- INST_TAG
+your_instance_name : clk_wiz_0
+ port map (
+ -- Clock out ports
+ clk_out1 => clk_out1,
+ -- Status and control signals
+ resetn => resetn,
+ -- Clock in ports
+ clk_in1 => clk_in1
+ );
+-- INST_TAG_END ------ End INSTANTIATION Template ------------
diff --git a/game.gen/sources_1/ip/clk_wiz_0/clk_wiz_0.xdc b/game.gen/sources_1/ip/clk_wiz_0/clk_wiz_0.xdc
new file mode 100644
index 0000000000000000000000000000000000000000..d426798667f913e3986bf9585fc808bf02d0c05a
--- /dev/null
+++ b/game.gen/sources_1/ip/clk_wiz_0/clk_wiz_0.xdc
@@ -0,0 +1,60 @@
+
+# file: clk_wiz_0.xdc
+#
+# (c) Copyright 2008 - 2013 Xilinx, Inc. All rights reserved.
+#
+# This file contains confidential and proprietary information
+# of Xilinx, Inc. and is protected under U.S. and
+# international copyright and other intellectual property
+# laws.
+#
+# DISCLAIMER
+# This disclaimer is not a license and does not grant any
+# rights to the materials distributed herewith. Except as
+# otherwise provided in a valid license issued to you by
+# Xilinx, and to the maximum extent permitted by applicable
+# law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
+# WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
+# AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
+# BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
+# INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
+# (2) Xilinx shall not be liable (whether in contract or tort,
+# including negligence, or under any other theory of
+# liability) for any loss or damage of any kind or nature
+# related to, arising under or in connection with these
+# materials, including for any direct, or any indirect,
+# special, incidental, or consequential loss or damage
+# (including loss of data, profits, goodwill, or any type of
+# loss or damage suffered as a result of any action brought
+# by a third party) even if such damage or loss was
+# reasonably foreseeable or Xilinx had been advised of the
+# possibility of the same.
+#
+# CRITICAL APPLICATIONS
+# Xilinx products are not designed or intended to be fail-
+# safe, or for use in any application requiring fail-safe
+# performance, such as life-support or safety devices or
+# systems, Class III medical devices, nuclear facilities,
+# applications related to the deployment of airbags, or any
+# other applications that could lead to death, personal
+# injury, or severe property or environmental damage
+# (individually and collectively, "Critical
+# Applications"). Customer assumes the sole risk and
+# liability of any use of Xilinx products in Critical
+# Applications, subject only to applicable laws and
+# regulations governing limitations on product liability.
+#
+# THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
+# PART OF THIS FILE AT ALL TIMES.
+#
+
+# Input clock periods. These duplicate the values entered for the
+# input clocks. You can use these to time your system. If required
+# commented constraints can be used in the top level xdc
+#----------------------------------------------------------------
+# Connect to input port when clock capable pin is selected for input
+create_clock -period 10.000 [get_ports clk_in1]
+set_input_jitter [get_clocks -of_objects [get_ports clk_in1]] 0.100
+
+
+set_property PHASESHIFT_MODE WAVEFORM [get_cells -hierarchical *adv*]
diff --git a/game.gen/sources_1/ip/clk_wiz_0/clk_wiz_0.xml b/game.gen/sources_1/ip/clk_wiz_0/clk_wiz_0.xml
new file mode 100644
index 0000000000000000000000000000000000000000..0711c53875f66f25863e8cf8c71a806114e447bf
--- /dev/null
+++ b/game.gen/sources_1/ip/clk_wiz_0/clk_wiz_0.xml
@@ -0,0 +1,4999 @@
+<?xml version="1.0" encoding="UTF-8"?>
+<spirit:component xmlns:xilinx="http://www.xilinx.com" xmlns:spirit="http://www.spiritconsortium.org/XMLSchema/SPIRIT/1685-2009" xmlns:xsi="http://www.w3.org/2001/XMLSchema-instance">
+ <spirit:vendor>xilinx.com</spirit:vendor>
+ <spirit:library>customized_ip</spirit:library>
+ <spirit:name>clk_wiz_0</spirit:name>
+ <spirit:version>1.0</spirit:version>
+ <spirit:busInterfaces>
+ <spirit:busInterface>
+ <spirit:name>s_axi_lite</spirit:name>
+ <spirit:displayName>S_AXI_LITE</spirit:displayName>
+ <spirit:busType spirit:vendor="xilinx.com" spirit:library="interface" spirit:name="aximm" spirit:version="1.0"/>
+ <spirit:abstractionType spirit:vendor="xilinx.com" spirit:library="interface" spirit:name="aximm_rtl" spirit:version="1.0"/>
+ <spirit:slave/>
+ <spirit:portMaps>
+ <spirit:portMap>
+ <spirit:logicalPort>
+ <spirit:name>ARADDR</spirit:name>
+ </spirit:logicalPort>
+ <spirit:physicalPort>
+ <spirit:name>s_axi_araddr</spirit:name>
+ </spirit:physicalPort>
+ </spirit:portMap>
+ <spirit:portMap>
+ <spirit:logicalPort>
+ <spirit:name>ARREADY</spirit:name>
+ </spirit:logicalPort>
+ <spirit:physicalPort>
+ <spirit:name>s_axi_arready</spirit:name>
+ </spirit:physicalPort>
+ </spirit:portMap>
+ <spirit:portMap>
+ <spirit:logicalPort>
+ <spirit:name>ARVALID</spirit:name>
+ </spirit:logicalPort>
+ <spirit:physicalPort>
+ <spirit:name>s_axi_arvalid</spirit:name>
+ </spirit:physicalPort>
+ </spirit:portMap>
+ <spirit:portMap>
+ <spirit:logicalPort>
+ <spirit:name>AWADDR</spirit:name>
+ </spirit:logicalPort>
+ <spirit:physicalPort>
+ <spirit:name>s_axi_awaddr</spirit:name>
+ </spirit:physicalPort>
+ </spirit:portMap>
+ <spirit:portMap>
+ <spirit:logicalPort>
+ <spirit:name>AWREADY</spirit:name>
+ </spirit:logicalPort>
+ <spirit:physicalPort>
+ <spirit:name>s_axi_awready</spirit:name>
+ </spirit:physicalPort>
+ </spirit:portMap>
+ <spirit:portMap>
+ <spirit:logicalPort>
+ <spirit:name>AWVALID</spirit:name>
+ </spirit:logicalPort>
+ <spirit:physicalPort>
+ <spirit:name>s_axi_awvalid</spirit:name>
+ </spirit:physicalPort>
+ </spirit:portMap>
+ <spirit:portMap>
+ <spirit:logicalPort>
+ <spirit:name>BREADY</spirit:name>
+ </spirit:logicalPort>
+ <spirit:physicalPort>
+ <spirit:name>s_axi_bready</spirit:name>
+ </spirit:physicalPort>
+ </spirit:portMap>
+ <spirit:portMap>
+ <spirit:logicalPort>
+ <spirit:name>BRESP</spirit:name>
+ </spirit:logicalPort>
+ <spirit:physicalPort>
+ <spirit:name>s_axi_bresp</spirit:name>
+ </spirit:physicalPort>
+ </spirit:portMap>
+ <spirit:portMap>
+ <spirit:logicalPort>
+ <spirit:name>BVALID</spirit:name>
+ </spirit:logicalPort>
+ <spirit:physicalPort>
+ <spirit:name>s_axi_bvalid</spirit:name>
+ </spirit:physicalPort>
+ </spirit:portMap>
+ <spirit:portMap>
+ <spirit:logicalPort>
+ <spirit:name>RDATA</spirit:name>
+ </spirit:logicalPort>
+ <spirit:physicalPort>
+ <spirit:name>s_axi_rdata</spirit:name>
+ </spirit:physicalPort>
+ </spirit:portMap>
+ <spirit:portMap>
+ <spirit:logicalPort>
+ <spirit:name>RREADY</spirit:name>
+ </spirit:logicalPort>
+ <spirit:physicalPort>
+ <spirit:name>s_axi_rready</spirit:name>
+ </spirit:physicalPort>
+ </spirit:portMap>
+ <spirit:portMap>
+ <spirit:logicalPort>
+ <spirit:name>RRESP</spirit:name>
+ </spirit:logicalPort>
+ <spirit:physicalPort>
+ <spirit:name>s_axi_rresp</spirit:name>
+ </spirit:physicalPort>
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+ <spirit:name>RVALID</spirit:name>
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+ <spirit:name>s_axi_rvalid</spirit:name>
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+ <spirit:logicalPort>
+ <spirit:name>WDATA</spirit:name>
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+ <spirit:physicalPort>
+ <spirit:name>s_axi_wdata</spirit:name>
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+ <spirit:portMap>
+ <spirit:logicalPort>
+ <spirit:name>WREADY</spirit:name>
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+ <spirit:physicalPort>
+ <spirit:name>s_axi_wready</spirit:name>
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+ <spirit:logicalPort>
+ <spirit:name>WSTRB</spirit:name>
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+ <spirit:physicalPort>
+ <spirit:name>s_axi_wstrb</spirit:name>
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+ <spirit:portMap>
+ <spirit:logicalPort>
+ <spirit:name>WVALID</spirit:name>
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+ <spirit:physicalPort>
+ <spirit:name>s_axi_wvalid</spirit:name>
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+ <spirit:parameter>
+ <spirit:name>PROTOCOL</spirit:name>
+ <spirit:value spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.S_AXI_LITE.PROTOCOL">AXI4LITE</spirit:value>
+ <spirit:vendorExtensions>
+ <xilinx:parameterInfo>
+ <xilinx:parameterUsage>none</xilinx:parameterUsage>
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+ <spirit:name>FREQ_HZ</spirit:name>
+ <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.S_AXI_LITE.FREQ_HZ">100000000</spirit:value>
+ <spirit:vendorExtensions>
+ <xilinx:parameterInfo>
+ <xilinx:parameterUsage>none</xilinx:parameterUsage>
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+ <spirit:parameter>
+ <spirit:name>ID_WIDTH</spirit:name>
+ <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.S_AXI_LITE.ID_WIDTH">0</spirit:value>
+ <spirit:vendorExtensions>
+ <xilinx:parameterInfo>
+ <xilinx:parameterUsage>none</xilinx:parameterUsage>
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+ <spirit:parameter>
+ <spirit:name>ADDR_WIDTH</spirit:name>
+ <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.S_AXI_LITE.ADDR_WIDTH">1</spirit:value>
+ <spirit:vendorExtensions>
+ <xilinx:parameterInfo>
+ <xilinx:parameterUsage>none</xilinx:parameterUsage>
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+ <spirit:name>AWUSER_WIDTH</spirit:name>
+ <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.S_AXI_LITE.AWUSER_WIDTH">0</spirit:value>
+ <spirit:vendorExtensions>
+ <xilinx:parameterInfo>
+ <xilinx:parameterUsage>none</xilinx:parameterUsage>
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+ <spirit:parameter>
+ <spirit:name>ARUSER_WIDTH</spirit:name>
+ <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.S_AXI_LITE.ARUSER_WIDTH">0</spirit:value>
+ <spirit:vendorExtensions>
+ <xilinx:parameterInfo>
+ <xilinx:parameterUsage>none</xilinx:parameterUsage>
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+ <spirit:name>WUSER_WIDTH</spirit:name>
+ <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.S_AXI_LITE.WUSER_WIDTH">0</spirit:value>
+ <spirit:vendorExtensions>
+ <xilinx:parameterInfo>
+ <xilinx:parameterUsage>none</xilinx:parameterUsage>
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+ <spirit:parameter>
+ <spirit:name>RUSER_WIDTH</spirit:name>
+ <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.S_AXI_LITE.RUSER_WIDTH">0</spirit:value>
+ <spirit:vendorExtensions>
+ <xilinx:parameterInfo>
+ <xilinx:parameterUsage>none</xilinx:parameterUsage>
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+ </spirit:vendorExtensions>
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+ <spirit:parameter>
+ <spirit:name>BUSER_WIDTH</spirit:name>
+ <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.S_AXI_LITE.BUSER_WIDTH">0</spirit:value>
+ <spirit:vendorExtensions>
+ <xilinx:parameterInfo>
+ <xilinx:parameterUsage>none</xilinx:parameterUsage>
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+ </spirit:vendorExtensions>
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+ <spirit:parameter>
+ <spirit:name>READ_WRITE_MODE</spirit:name>
+ <spirit:value spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.S_AXI_LITE.READ_WRITE_MODE">READ_WRITE</spirit:value>
+ <spirit:vendorExtensions>
+ <xilinx:parameterInfo>
+ <xilinx:parameterUsage>none</xilinx:parameterUsage>
+ </xilinx:parameterInfo>
+ </spirit:vendorExtensions>
+ </spirit:parameter>
+ <spirit:parameter>
+ <spirit:name>HAS_BURST</spirit:name>
+ <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.S_AXI_LITE.HAS_BURST">0</spirit:value>
+ <spirit:vendorExtensions>
+ <xilinx:parameterInfo>
+ <xilinx:parameterUsage>none</xilinx:parameterUsage>
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+ </spirit:vendorExtensions>
+ </spirit:parameter>
+ <spirit:parameter>
+ <spirit:name>HAS_LOCK</spirit:name>
+ <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.S_AXI_LITE.HAS_LOCK">0</spirit:value>
+ <spirit:vendorExtensions>
+ <xilinx:parameterInfo>
+ <xilinx:parameterUsage>none</xilinx:parameterUsage>
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+ </spirit:vendorExtensions>
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+ <spirit:parameter>
+ <spirit:name>HAS_PROT</spirit:name>
+ <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.S_AXI_LITE.HAS_PROT">0</spirit:value>
+ <spirit:vendorExtensions>
+ <xilinx:parameterInfo>
+ <xilinx:parameterUsage>none</xilinx:parameterUsage>
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+ </spirit:vendorExtensions>
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+ <spirit:parameter>
+ <spirit:name>HAS_CACHE</spirit:name>
+ <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.S_AXI_LITE.HAS_CACHE">0</spirit:value>
+ <spirit:vendorExtensions>
+ <xilinx:parameterInfo>
+ <xilinx:parameterUsage>none</xilinx:parameterUsage>
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+ </spirit:vendorExtensions>
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+ <spirit:parameter>
+ <spirit:name>HAS_QOS</spirit:name>
+ <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.S_AXI_LITE.HAS_QOS">0</spirit:value>
+ <spirit:vendorExtensions>
+ <xilinx:parameterInfo>
+ <xilinx:parameterUsage>none</xilinx:parameterUsage>
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+ </spirit:vendorExtensions>
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+ <spirit:parameter>
+ <spirit:name>HAS_REGION</spirit:name>
+ <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.S_AXI_LITE.HAS_REGION">0</spirit:value>
+ <spirit:vendorExtensions>
+ <xilinx:parameterInfo>
+ <xilinx:parameterUsage>none</xilinx:parameterUsage>
+ </xilinx:parameterInfo>
+ </spirit:vendorExtensions>
+ </spirit:parameter>
+ <spirit:parameter>
+ <spirit:name>HAS_WSTRB</spirit:name>
+ <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.S_AXI_LITE.HAS_WSTRB">0</spirit:value>
+ <spirit:vendorExtensions>
+ <xilinx:parameterInfo>
+ <xilinx:parameterUsage>none</xilinx:parameterUsage>
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+ </spirit:vendorExtensions>
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+ <spirit:parameter>
+ <spirit:name>HAS_BRESP</spirit:name>
+ <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.S_AXI_LITE.HAS_BRESP">0</spirit:value>
+ <spirit:vendorExtensions>
+ <xilinx:parameterInfo>
+ <xilinx:parameterUsage>none</xilinx:parameterUsage>
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+ </spirit:vendorExtensions>
+ </spirit:parameter>
+ <spirit:parameter>
+ <spirit:name>HAS_RRESP</spirit:name>
+ <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.S_AXI_LITE.HAS_RRESP">0</spirit:value>
+ <spirit:vendorExtensions>
+ <xilinx:parameterInfo>
+ <xilinx:parameterUsage>none</xilinx:parameterUsage>
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+ </spirit:vendorExtensions>
+ </spirit:parameter>
+ <spirit:parameter>
+ <spirit:name>SUPPORTS_NARROW_BURST</spirit:name>
+ <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.S_AXI_LITE.SUPPORTS_NARROW_BURST">0</spirit:value>
+ <spirit:vendorExtensions>
+ <xilinx:parameterInfo>
+ <xilinx:parameterUsage>none</xilinx:parameterUsage>
+ </xilinx:parameterInfo>
+ </spirit:vendorExtensions>
+ </spirit:parameter>
+ <spirit:parameter>
+ <spirit:name>NUM_READ_OUTSTANDING</spirit:name>
+ <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.S_AXI_LITE.NUM_READ_OUTSTANDING">1</spirit:value>
+ <spirit:vendorExtensions>
+ <xilinx:parameterInfo>
+ <xilinx:parameterUsage>none</xilinx:parameterUsage>
+ </xilinx:parameterInfo>
+ </spirit:vendorExtensions>
+ </spirit:parameter>
+ <spirit:parameter>
+ <spirit:name>NUM_WRITE_OUTSTANDING</spirit:name>
+ <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.S_AXI_LITE.NUM_WRITE_OUTSTANDING">1</spirit:value>
+ <spirit:vendorExtensions>
+ <xilinx:parameterInfo>
+ <xilinx:parameterUsage>none</xilinx:parameterUsage>
+ </xilinx:parameterInfo>
+ </spirit:vendorExtensions>
+ </spirit:parameter>
+ <spirit:parameter>
+ <spirit:name>MAX_BURST_LENGTH</spirit:name>
+ <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.S_AXI_LITE.MAX_BURST_LENGTH">1</spirit:value>
+ <spirit:vendorExtensions>
+ <xilinx:parameterInfo>
+ <xilinx:parameterUsage>none</xilinx:parameterUsage>
+ </xilinx:parameterInfo>
+ </spirit:vendorExtensions>
+ </spirit:parameter>
+ <spirit:parameter>
+ <spirit:name>PHASE</spirit:name>
+ <spirit:value spirit:format="float" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.S_AXI_LITE.PHASE">0.0</spirit:value>
+ <spirit:vendorExtensions>
+ <xilinx:parameterInfo>
+ <xilinx:parameterUsage>none</xilinx:parameterUsage>
+ </xilinx:parameterInfo>
+ </spirit:vendorExtensions>
+ </spirit:parameter>
+ <spirit:parameter>
+ <spirit:name>CLK_DOMAIN</spirit:name>
+ <spirit:value spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.S_AXI_LITE.CLK_DOMAIN"/>
+ <spirit:vendorExtensions>
+ <xilinx:parameterInfo>
+ <xilinx:parameterUsage>none</xilinx:parameterUsage>
+ </xilinx:parameterInfo>
+ </spirit:vendorExtensions>
+ </spirit:parameter>
+ <spirit:parameter>
+ <spirit:name>NUM_READ_THREADS</spirit:name>
+ <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.S_AXI_LITE.NUM_READ_THREADS">1</spirit:value>
+ <spirit:vendorExtensions>
+ <xilinx:parameterInfo>
+ <xilinx:parameterUsage>none</xilinx:parameterUsage>
+ </xilinx:parameterInfo>
+ </spirit:vendorExtensions>
+ </spirit:parameter>
+ <spirit:parameter>
+ <spirit:name>NUM_WRITE_THREADS</spirit:name>
+ <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.S_AXI_LITE.NUM_WRITE_THREADS">1</spirit:value>
+ <spirit:vendorExtensions>
+ <xilinx:parameterInfo>
+ <xilinx:parameterUsage>none</xilinx:parameterUsage>
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+ </spirit:vendorExtensions>
+ </spirit:parameter>
+ <spirit:parameter>
+ <spirit:name>RUSER_BITS_PER_BYTE</spirit:name>
+ <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.S_AXI_LITE.RUSER_BITS_PER_BYTE">0</spirit:value>
+ <spirit:vendorExtensions>
+ <xilinx:parameterInfo>
+ <xilinx:parameterUsage>none</xilinx:parameterUsage>
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+ </spirit:vendorExtensions>
+ </spirit:parameter>
+ <spirit:parameter>
+ <spirit:name>WUSER_BITS_PER_BYTE</spirit:name>
+ <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.S_AXI_LITE.WUSER_BITS_PER_BYTE">0</spirit:value>
+ <spirit:vendorExtensions>
+ <xilinx:parameterInfo>
+ <xilinx:parameterUsage>none</xilinx:parameterUsage>
+ </xilinx:parameterInfo>
+ </spirit:vendorExtensions>
+ </spirit:parameter>
+ <spirit:parameter>
+ <spirit:name>INSERT_VIP</spirit:name>
+ <spirit:value spirit:format="long" spirit:resolve="user" spirit:id="BUSIFPARAM_VALUE.S_AXI_LITE.INSERT_VIP">0</spirit:value>
+ <spirit:vendorExtensions>
+ <xilinx:parameterInfo>
+ <xilinx:parameterUsage>simulation.rtl</xilinx:parameterUsage>
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+ </spirit:vendorExtensions>
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+ </spirit:parameters>
+ <spirit:vendorExtensions>
+ <xilinx:busInterfaceInfo>
+ <xilinx:enablement>
+ <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="BUSIF_ENABLEMENT.s_axi_lite" xilinx:dependency="spirit:decode(id('MODELPARAM_VALUE.C_INTERFACE_SELECTION'))">false</xilinx:isEnabled>
+ </xilinx:enablement>
+ </xilinx:busInterfaceInfo>
+ </spirit:vendorExtensions>
+ </spirit:busInterface>
+ <spirit:busInterface>
+ <spirit:name>s_axi_aclk</spirit:name>
+ <spirit:displayName>s_axi_aclk</spirit:displayName>
+ <spirit:busType spirit:vendor="xilinx.com" spirit:library="signal" spirit:name="clock" spirit:version="1.0"/>
+ <spirit:abstractionType spirit:vendor="xilinx.com" spirit:library="signal" spirit:name="clock_rtl" spirit:version="1.0"/>
+ <spirit:slave/>
+ <spirit:portMaps>
+ <spirit:portMap>
+ <spirit:logicalPort>
+ <spirit:name>CLK</spirit:name>
+ </spirit:logicalPort>
+ <spirit:physicalPort>
+ <spirit:name>s_axi_aclk</spirit:name>
+ </spirit:physicalPort>
+ </spirit:portMap>
+ </spirit:portMaps>
+ <spirit:parameters>
+ <spirit:parameter>
+ <spirit:name>ASSOCIATED_BUSIF</spirit:name>
+ <spirit:value spirit:id="BUSIFPARAM_VALUE.S_AXI_ACLK.ASSOCIATED_BUSIF">s_axi_lite</spirit:value>
+ </spirit:parameter>
+ <spirit:parameter>
+ <spirit:name>ASSOCIATED_RESET</spirit:name>
+ <spirit:value spirit:id="BUSIFPARAM_VALUE.S_AXI_ACLK.ASSOCIATED_RESET">s_axi_aresetn</spirit:value>
+ </spirit:parameter>
+ <spirit:parameter>
+ <spirit:name>FREQ_HZ</spirit:name>
+ <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.S_AXI_ACLK.FREQ_HZ">100000000</spirit:value>
+ <spirit:vendorExtensions>
+ <xilinx:parameterInfo>
+ <xilinx:parameterUsage>none</xilinx:parameterUsage>
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+ </spirit:vendorExtensions>
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+ <spirit:parameter>
+ <spirit:name>FREQ_TOLERANCE_HZ</spirit:name>
+ <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.S_AXI_ACLK.FREQ_TOLERANCE_HZ">0</spirit:value>
+ <spirit:vendorExtensions>
+ <xilinx:parameterInfo>
+ <xilinx:parameterUsage>none</xilinx:parameterUsage>
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+ </spirit:vendorExtensions>
+ </spirit:parameter>
+ <spirit:parameter>
+ <spirit:name>PHASE</spirit:name>
+ <spirit:value spirit:format="float" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.S_AXI_ACLK.PHASE">0.0</spirit:value>
+ <spirit:vendorExtensions>
+ <xilinx:parameterInfo>
+ <xilinx:parameterUsage>none</xilinx:parameterUsage>
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+ </spirit:vendorExtensions>
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+ <spirit:parameter>
+ <spirit:name>CLK_DOMAIN</spirit:name>
+ <spirit:value spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.S_AXI_ACLK.CLK_DOMAIN"/>
+ <spirit:vendorExtensions>
+ <xilinx:parameterInfo>
+ <xilinx:parameterUsage>none</xilinx:parameterUsage>
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+ </spirit:vendorExtensions>
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+ <spirit:parameter>
+ <spirit:name>ASSOCIATED_PORT</spirit:name>
+ <spirit:value spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.S_AXI_ACLK.ASSOCIATED_PORT"/>
+ <spirit:vendorExtensions>
+ <xilinx:parameterInfo>
+ <xilinx:parameterUsage>none</xilinx:parameterUsage>
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+ <spirit:parameter>
+ <spirit:name>INSERT_VIP</spirit:name>
+ <spirit:value spirit:format="long" spirit:resolve="user" spirit:id="BUSIFPARAM_VALUE.S_AXI_ACLK.INSERT_VIP">0</spirit:value>
+ <spirit:vendorExtensions>
+ <xilinx:parameterInfo>
+ <xilinx:parameterUsage>simulation.rtl</xilinx:parameterUsage>
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+ <spirit:vendorExtensions>
+ <xilinx:busInterfaceInfo>
+ <xilinx:enablement>
+ <xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="BUSIF_ENABLEMENT.s_axi_aclk" xilinx:dependency="spirit:decode(id('MODELPARAM_VALUE.C_INTERFACE_SELECTION'))">false</xilinx:isEnabled>
+ </xilinx:enablement>
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+ </spirit:vendorExtensions>
+ </spirit:busInterface>
+ <spirit:busInterface>
+ <spirit:name>ref_clk</spirit:name>
+ <spirit:displayName>ref_clk</spirit:displayName>
+ <spirit:busType spirit:vendor="xilinx.com" spirit:library="signal" spirit:name="clock" spirit:version="1.0"/>
+ <spirit:abstractionType spirit:vendor="xilinx.com" spirit:library="signal" spirit:name="clock_rtl" spirit:version="1.0"/>
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+ <spirit:portMaps>
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+ <spirit:logicalPort>
+ <spirit:name>CLK</spirit:name>
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+ <spirit:physicalPort>
+ <spirit:name>ref_clk</spirit:name>
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+ <spirit:name>FREQ_HZ</spirit:name>
+ <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.REF_CLK.FREQ_HZ">100000000</spirit:value>
+ <spirit:vendorExtensions>
+ <xilinx:parameterInfo>
+ <xilinx:parameterUsage>none</xilinx:parameterUsage>
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+ </spirit:vendorExtensions>
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+ <spirit:parameter>
+ <spirit:name>FREQ_TOLERANCE_HZ</spirit:name>
+ <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.REF_CLK.FREQ_TOLERANCE_HZ">0</spirit:value>
+ <spirit:vendorExtensions>
+ <xilinx:parameterInfo>
+ <xilinx:parameterUsage>none</xilinx:parameterUsage>
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+ <spirit:parameter>
+ <spirit:name>PHASE</spirit:name>
+ <spirit:value spirit:format="float" spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.REF_CLK.PHASE">0.0</spirit:value>
+ <spirit:vendorExtensions>
+ <xilinx:parameterInfo>
+ <xilinx:parameterUsage>none</xilinx:parameterUsage>
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+ </spirit:vendorExtensions>
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+ <spirit:parameter>
+ <spirit:name>CLK_DOMAIN</spirit:name>
+ <spirit:value spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.REF_CLK.CLK_DOMAIN"/>
+ <spirit:vendorExtensions>
+ <xilinx:parameterInfo>
+ <xilinx:parameterUsage>none</xilinx:parameterUsage>
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+ <spirit:parameter>
+ <spirit:name>ASSOCIATED_BUSIF</spirit:name>
+ <spirit:value spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.REF_CLK.ASSOCIATED_BUSIF"/>
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+ <xilinx:parameterInfo>
+ <xilinx:parameterUsage>none</xilinx:parameterUsage>
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+ <spirit:parameter>
+ <spirit:name>ASSOCIATED_PORT</spirit:name>
+ <spirit:value spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.REF_CLK.ASSOCIATED_PORT"/>
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+ <xilinx:parameterUsage>none</xilinx:parameterUsage>
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+ <spirit:parameter>
+ <spirit:name>ASSOCIATED_RESET</spirit:name>
+ <spirit:value spirit:resolve="generated" spirit:id="BUSIFPARAM_VALUE.REF_CLK.ASSOCIATED_RESET"/>
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+ <xilinx:parameterUsage>none</xilinx:parameterUsage>
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+ <spirit:parameter>
+ <spirit:name>INSERT_VIP</spirit:name>
+ <spirit:value spirit:format="long" spirit:resolve="user" spirit:id="BUSIFPARAM_VALUE.REF_CLK.INSERT_VIP">0</spirit:value>
+ <spirit:vendorExtensions>
+ <xilinx:parameterInfo>
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+ <xilinx:busInterfaceInfo>
+ <xilinx:enablement>
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+ </spirit:vendorExtensions>
+ </spirit:busInterface>
+ <spirit:busInterface>
+ <spirit:name>s_axi_resetn</spirit:name>
+ <spirit:displayName>S_AXI_RESETN</spirit:displayName>
+ <spirit:busType spirit:vendor="xilinx.com" spirit:library="signal" spirit:name="reset" spirit:version="1.0"/>
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+ <spirit:logicalPort>
+ <spirit:name>RST</spirit:name>
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+ <spirit:name>C_USE_CLKOUT2_BAR</spirit:name>
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+ <spirit:name>C_USE_CLKOUT4_BAR</spirit:name>
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+ <spirit:name>c_component_name</spirit:name>
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+ <spirit:modelParameter spirit:dataType="STRING">
+ <spirit:name>C_PLATFORM</spirit:name>
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+ <spirit:modelParameter spirit:dataType="INTEGER">
+ <spirit:name>C_USE_FREQ_SYNTH</spirit:name>
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+ <spirit:modelParameter spirit:dataType="INTEGER">
+ <spirit:name>C_USE_PHASE_ALIGNMENT</spirit:name>
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+ <spirit:name>C_SECONDARY_IN_JITTER</spirit:name>
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+ <spirit:name>C_JITTER_SEL</spirit:name>
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+ <spirit:modelParameter spirit:dataType="INTEGER">
+ <spirit:name>C_USE_MIN_POWER</spirit:name>
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+ <spirit:name>C_USE_DYN_PHASE_SHIFT</spirit:name>
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+ <spirit:modelParameter spirit:dataType="INTEGER">
+ <spirit:name>C_OPTIMIZE_CLOCKING_STRUCTURE_EN</spirit:name>
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+ <spirit:name>C_USE_INCLK_SWITCHOVER</spirit:name>
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+ <spirit:modelParameter spirit:dataType="INTEGER">
+ <spirit:name>C_USE_SPREAD_SPECTRUM</spirit:name>
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+ <spirit:name>C_USE_FAST_SIMULATION</spirit:name>
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+ <spirit:name>C_PRIMTYPE_SEL</spirit:name>
+ <spirit:value spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C_PRIMTYPE_SEL" spirit:order="218">AUTO</spirit:value>
+ </spirit:modelParameter>
+ <spirit:modelParameter spirit:dataType="INTEGER">
+ <spirit:name>C_USE_CLK_VALID</spirit:name>
+ <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C_USE_CLK_VALID" spirit:order="219">0</spirit:value>
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+ <spirit:modelParameter spirit:dataType="STRING">
+ <spirit:name>C_PRIM_IN_FREQ</spirit:name>
+ <spirit:value spirit:format="float" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C_PRIM_IN_FREQ" spirit:order="220">100.000</spirit:value>
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+ <spirit:modelParameter spirit:dataType="STRING">
+ <spirit:name>C_PRIM_IN_TIMEPERIOD</spirit:name>
+ <spirit:value spirit:format="float" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C_PRIM_IN_TIMEPERIOD" spirit:order="220.001">10.000</spirit:value>
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+ <spirit:name>C_IN_FREQ_UNITS</spirit:name>
+ <spirit:value spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C_IN_FREQ_UNITS" spirit:order="221">Units_MHz</spirit:value>
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+ <spirit:name>C_SECONDARY_IN_FREQ</spirit:name>
+ <spirit:value spirit:format="float" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C_SECONDARY_IN_FREQ" spirit:order="222">100.000</spirit:value>
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+ <spirit:name>C_SECONDARY_IN_TIMEPERIOD</spirit:name>
+ <spirit:value spirit:format="float" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C_SECONDARY_IN_TIMEPERIOD" spirit:order="222.001">10.000</spirit:value>
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+ <spirit:name>C_FEEDBACK_SOURCE</spirit:name>
+ <spirit:value spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C_FEEDBACK_SOURCE" spirit:order="223">FDBK_AUTO</spirit:value>
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+ <spirit:value spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C_PRIM_SOURCE" spirit:order="224">Single_ended_clock_capable_pin</spirit:value>
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+ <spirit:modelParameter spirit:dataType="STRING">
+ <spirit:name>C_PHASESHIFT_MODE</spirit:name>
+ <spirit:value spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C_PHASESHIFT_MODE" spirit:order="2240">WAVEFORM</spirit:value>
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+ <spirit:modelParameter spirit:dataType="STRING">
+ <spirit:name>C_CLKFB_IN_SIGNALING</spirit:name>
+ <spirit:value spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C_CLKFB_IN_SIGNALING" spirit:order="226">SINGLE</spirit:value>
+ </spirit:modelParameter>
+ <spirit:modelParameter spirit:dataType="INTEGER">
+ <spirit:name>C_USE_RESET</spirit:name>
+ <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C_USE_RESET" spirit:order="227">1</spirit:value>
+ </spirit:modelParameter>
+ <spirit:modelParameter spirit:dataType="INTEGER">
+ <spirit:name>C_RESET_LOW</spirit:name>
+ <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C_RESET_LOW" spirit:order="408">1</spirit:value>
+ </spirit:modelParameter>
+ <spirit:modelParameter spirit:dataType="INTEGER">
+ <spirit:name>C_USE_LOCKED</spirit:name>
+ <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C_USE_LOCKED" spirit:order="228">0</spirit:value>
+ </spirit:modelParameter>
+ <spirit:modelParameter spirit:dataType="INTEGER">
+ <spirit:name>C_USE_INCLK_STOPPED</spirit:name>
+ <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C_USE_INCLK_STOPPED" spirit:order="229">0</spirit:value>
+ </spirit:modelParameter>
+ <spirit:modelParameter spirit:dataType="INTEGER">
+ <spirit:name>C_USE_CLKFB_STOPPED</spirit:name>
+ <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C_USE_CLKFB_STOPPED" spirit:order="230">0</spirit:value>
+ </spirit:modelParameter>
+ <spirit:modelParameter spirit:dataType="INTEGER">
+ <spirit:name>C_USE_POWER_DOWN</spirit:name>
+ <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C_USE_POWER_DOWN" spirit:order="231">0</spirit:value>
+ </spirit:modelParameter>
+ <spirit:modelParameter spirit:dataType="INTEGER">
+ <spirit:name>C_USE_STATUS</spirit:name>
+ <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C_USE_STATUS" spirit:order="232">0</spirit:value>
+ </spirit:modelParameter>
+ <spirit:modelParameter spirit:dataType="INTEGER">
+ <spirit:name>C_USE_FREEZE</spirit:name>
+ <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C_USE_FREEZE" spirit:order="233">0</spirit:value>
+ </spirit:modelParameter>
+ <spirit:modelParameter spirit:dataType="INTEGER">
+ <spirit:name>C_NUM_OUT_CLKS</spirit:name>
+ <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C_NUM_OUT_CLKS" spirit:order="234">1</spirit:value>
+ </spirit:modelParameter>
+ <spirit:modelParameter spirit:dataType="STRING">
+ <spirit:name>C_CLKOUT1_DRIVES</spirit:name>
+ <spirit:value spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C_CLKOUT1_DRIVES" spirit:order="235">BUFG</spirit:value>
+ </spirit:modelParameter>
+ <spirit:modelParameter spirit:dataType="STRING">
+ <spirit:name>C_CLKOUT2_DRIVES</spirit:name>
+ <spirit:value spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C_CLKOUT2_DRIVES" spirit:order="236">BUFG</spirit:value>
+ </spirit:modelParameter>
+ <spirit:modelParameter spirit:dataType="STRING">
+ <spirit:name>C_CLKOUT3_DRIVES</spirit:name>
+ <spirit:value spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C_CLKOUT3_DRIVES" spirit:order="237">BUFG</spirit:value>
+ </spirit:modelParameter>
+ <spirit:modelParameter spirit:dataType="STRING">
+ <spirit:name>C_CLKOUT4_DRIVES</spirit:name>
+ <spirit:value spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C_CLKOUT4_DRIVES" spirit:order="238">BUFG</spirit:value>
+ </spirit:modelParameter>
+ <spirit:modelParameter spirit:dataType="STRING">
+ <spirit:name>C_CLKOUT5_DRIVES</spirit:name>
+ <spirit:value spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C_CLKOUT5_DRIVES" spirit:order="239">BUFG</spirit:value>
+ </spirit:modelParameter>
+ <spirit:modelParameter spirit:dataType="STRING">
+ <spirit:name>C_CLKOUT6_DRIVES</spirit:name>
+ <spirit:value spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C_CLKOUT6_DRIVES" spirit:order="240">BUFG</spirit:value>
+ </spirit:modelParameter>
+ <spirit:modelParameter spirit:dataType="STRING">
+ <spirit:name>C_CLKOUT7_DRIVES</spirit:name>
+ <spirit:value spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C_CLKOUT7_DRIVES" spirit:order="241">BUFG</spirit:value>
+ </spirit:modelParameter>
+ <spirit:modelParameter spirit:dataType="STRING">
+ <spirit:name>C_INCLK_SUM_ROW0</spirit:name>
+ <spirit:value spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C_INCLK_SUM_ROW0" spirit:order="242">Input Clock Freq (MHz) Input Jitter (UI)</spirit:value>
+ </spirit:modelParameter>
+ <spirit:modelParameter spirit:dataType="STRING">
+ <spirit:name>C_INCLK_SUM_ROW1</spirit:name>
+ <spirit:value spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C_INCLK_SUM_ROW1" spirit:order="243">__primary_________100.000____________0.010</spirit:value>
+ </spirit:modelParameter>
+ <spirit:modelParameter spirit:dataType="STRING">
+ <spirit:name>C_INCLK_SUM_ROW2</spirit:name>
+ <spirit:value spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C_INCLK_SUM_ROW2" spirit:order="244">no_secondary_input_clock </spirit:value>
+ </spirit:modelParameter>
+ <spirit:modelParameter spirit:dataType="STRING">
+ <spirit:name>C_OUTCLK_SUM_ROW0A</spirit:name>
+ <spirit:displayName>C Outclk Sum Row0a</spirit:displayName>
+ <spirit:value spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C_OUTCLK_SUM_ROW0A" spirit:order="245"> Output Output Phase Duty Cycle Pk-to-Pk Phase</spirit:value>
+ </spirit:modelParameter>
+ <spirit:modelParameter spirit:dataType="STRING">
+ <spirit:name>C_OUTCLK_SUM_ROW0B</spirit:name>
+ <spirit:value spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C_OUTCLK_SUM_ROW0B" spirit:order="246"> Clock Freq (MHz) (degrees) (%) Jitter (ps) Error (ps)</spirit:value>
+ </spirit:modelParameter>
+ <spirit:modelParameter spirit:dataType="STRING">
+ <spirit:name>C_OUTCLK_SUM_ROW1</spirit:name>
+ <spirit:value spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C_OUTCLK_SUM_ROW1" spirit:order="247">clk_out1__25.00000______0.000______50.0______181.828____104.359</spirit:value>
+ </spirit:modelParameter>
+ <spirit:modelParameter spirit:dataType="STRING">
+ <spirit:name>C_OUTCLK_SUM_ROW2</spirit:name>
+ <spirit:value spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C_OUTCLK_SUM_ROW2" spirit:order="248">no_CLK_OUT2_output</spirit:value>
+ </spirit:modelParameter>
+ <spirit:modelParameter spirit:dataType="STRING">
+ <spirit:name>C_OUTCLK_SUM_ROW3</spirit:name>
+ <spirit:value spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C_OUTCLK_SUM_ROW3" spirit:order="249">no_CLK_OUT3_output</spirit:value>
+ </spirit:modelParameter>
+ <spirit:modelParameter spirit:dataType="STRING">
+ <spirit:name>C_OUTCLK_SUM_ROW4</spirit:name>
+ <spirit:value spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C_OUTCLK_SUM_ROW4" spirit:order="250">no_CLK_OUT4_output</spirit:value>
+ </spirit:modelParameter>
+ <spirit:modelParameter spirit:dataType="STRING">
+ <spirit:name>C_OUTCLK_SUM_ROW5</spirit:name>
+ <spirit:value spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C_OUTCLK_SUM_ROW5" spirit:order="251">no_CLK_OUT5_output</spirit:value>
+ </spirit:modelParameter>
+ <spirit:modelParameter spirit:dataType="STRING">
+ <spirit:name>C_OUTCLK_SUM_ROW6</spirit:name>
+ <spirit:value spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C_OUTCLK_SUM_ROW6" spirit:order="252">no_CLK_OUT6_output</spirit:value>
+ </spirit:modelParameter>
+ <spirit:modelParameter spirit:dataType="STRING">
+ <spirit:name>C_OUTCLK_SUM_ROW7</spirit:name>
+ <spirit:value spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C_OUTCLK_SUM_ROW7" spirit:order="253">no_CLK_OUT7_output</spirit:value>
+ </spirit:modelParameter>
+ <spirit:modelParameter spirit:dataType="STRING">
+ <spirit:name>C_CLKOUT1_REQUESTED_OUT_FREQ</spirit:name>
+ <spirit:value spirit:format="float" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C_CLKOUT1_REQUESTED_OUT_FREQ" spirit:order="254">25</spirit:value>
+ </spirit:modelParameter>
+ <spirit:modelParameter spirit:dataType="STRING">
+ <spirit:name>C_CLKOUT2_REQUESTED_OUT_FREQ</spirit:name>
+ <spirit:value spirit:format="float" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C_CLKOUT2_REQUESTED_OUT_FREQ" spirit:order="255">100.000</spirit:value>
+ </spirit:modelParameter>
+ <spirit:modelParameter spirit:dataType="STRING">
+ <spirit:name>C_CLKOUT3_REQUESTED_OUT_FREQ</spirit:name>
+ <spirit:value spirit:format="float" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C_CLKOUT3_REQUESTED_OUT_FREQ" spirit:order="256">100.000</spirit:value>
+ </spirit:modelParameter>
+ <spirit:modelParameter spirit:dataType="STRING">
+ <spirit:name>C_CLKOUT4_REQUESTED_OUT_FREQ</spirit:name>
+ <spirit:value spirit:format="float" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C_CLKOUT4_REQUESTED_OUT_FREQ" spirit:order="257">100.000</spirit:value>
+ </spirit:modelParameter>
+ <spirit:modelParameter spirit:dataType="STRING">
+ <spirit:name>C_CLKOUT5_REQUESTED_OUT_FREQ</spirit:name>
+ <spirit:value spirit:format="float" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C_CLKOUT5_REQUESTED_OUT_FREQ" spirit:order="258">100.000</spirit:value>
+ </spirit:modelParameter>
+ <spirit:modelParameter spirit:dataType="STRING">
+ <spirit:name>C_CLKOUT6_REQUESTED_OUT_FREQ</spirit:name>
+ <spirit:value spirit:format="float" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C_CLKOUT6_REQUESTED_OUT_FREQ" spirit:order="259">100.000</spirit:value>
+ </spirit:modelParameter>
+ <spirit:modelParameter spirit:dataType="STRING">
+ <spirit:name>C_CLKOUT7_REQUESTED_OUT_FREQ</spirit:name>
+ <spirit:value spirit:format="float" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C_CLKOUT7_REQUESTED_OUT_FREQ" spirit:order="260">100.000</spirit:value>
+ </spirit:modelParameter>
+ <spirit:modelParameter spirit:dataType="STRING">
+ <spirit:name>C_CLKOUT1_REQUESTED_PHASE</spirit:name>
+ <spirit:value spirit:format="float" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C_CLKOUT1_REQUESTED_PHASE" spirit:order="261">0.000</spirit:value>
+ </spirit:modelParameter>
+ <spirit:modelParameter spirit:dataType="STRING">
+ <spirit:name>C_CLKOUT2_REQUESTED_PHASE</spirit:name>
+ <spirit:value spirit:format="float" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C_CLKOUT2_REQUESTED_PHASE" spirit:order="262">0.000</spirit:value>
+ </spirit:modelParameter>
+ <spirit:modelParameter spirit:dataType="STRING">
+ <spirit:name>C_CLKOUT3_REQUESTED_PHASE</spirit:name>
+ <spirit:value spirit:format="float" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C_CLKOUT3_REQUESTED_PHASE" spirit:order="263">0.000</spirit:value>
+ </spirit:modelParameter>
+ <spirit:modelParameter spirit:dataType="STRING">
+ <spirit:name>C_CLKOUT4_REQUESTED_PHASE</spirit:name>
+ <spirit:value spirit:format="float" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C_CLKOUT4_REQUESTED_PHASE" spirit:order="264">0.000</spirit:value>
+ </spirit:modelParameter>
+ <spirit:modelParameter spirit:dataType="STRING">
+ <spirit:name>C_CLKOUT5_REQUESTED_PHASE</spirit:name>
+ <spirit:value spirit:format="float" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C_CLKOUT5_REQUESTED_PHASE" spirit:order="265">0.000</spirit:value>
+ </spirit:modelParameter>
+ <spirit:modelParameter spirit:dataType="STRING">
+ <spirit:name>C_CLKOUT6_REQUESTED_PHASE</spirit:name>
+ <spirit:value spirit:format="float" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C_CLKOUT6_REQUESTED_PHASE" spirit:order="266">0.000</spirit:value>
+ </spirit:modelParameter>
+ <spirit:modelParameter spirit:dataType="STRING">
+ <spirit:name>C_CLKOUT7_REQUESTED_PHASE</spirit:name>
+ <spirit:value spirit:format="float" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C_CLKOUT7_REQUESTED_PHASE" spirit:order="267">0.000</spirit:value>
+ </spirit:modelParameter>
+ <spirit:modelParameter spirit:dataType="STRING">
+ <spirit:name>C_CLKOUT1_REQUESTED_DUTY_CYCLE</spirit:name>
+ <spirit:value spirit:format="float" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C_CLKOUT1_REQUESTED_DUTY_CYCLE" spirit:order="268">50.000</spirit:value>
+ </spirit:modelParameter>
+ <spirit:modelParameter spirit:dataType="STRING">
+ <spirit:name>C_CLKOUT2_REQUESTED_DUTY_CYCLE</spirit:name>
+ <spirit:value spirit:format="float" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C_CLKOUT2_REQUESTED_DUTY_CYCLE" spirit:order="269">50.000</spirit:value>
+ </spirit:modelParameter>
+ <spirit:modelParameter spirit:dataType="STRING">
+ <spirit:name>C_CLKOUT3_REQUESTED_DUTY_CYCLE</spirit:name>
+ <spirit:value spirit:format="float" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C_CLKOUT3_REQUESTED_DUTY_CYCLE" spirit:order="270">50.000</spirit:value>
+ </spirit:modelParameter>
+ <spirit:modelParameter spirit:dataType="STRING">
+ <spirit:name>C_CLKOUT4_REQUESTED_DUTY_CYCLE</spirit:name>
+ <spirit:value spirit:format="float" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C_CLKOUT4_REQUESTED_DUTY_CYCLE" spirit:order="271">50.000</spirit:value>
+ </spirit:modelParameter>
+ <spirit:modelParameter spirit:dataType="STRING">
+ <spirit:name>C_CLKOUT5_REQUESTED_DUTY_CYCLE</spirit:name>
+ <spirit:value spirit:format="float" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C_CLKOUT5_REQUESTED_DUTY_CYCLE" spirit:order="272">50.000</spirit:value>
+ </spirit:modelParameter>
+ <spirit:modelParameter spirit:dataType="STRING">
+ <spirit:name>C_CLKOUT6_REQUESTED_DUTY_CYCLE</spirit:name>
+ <spirit:value spirit:format="float" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C_CLKOUT6_REQUESTED_DUTY_CYCLE" spirit:order="273">50.000</spirit:value>
+ </spirit:modelParameter>
+ <spirit:modelParameter spirit:dataType="STRING">
+ <spirit:name>C_CLKOUT7_REQUESTED_DUTY_CYCLE</spirit:name>
+ <spirit:value spirit:format="float" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C_CLKOUT7_REQUESTED_DUTY_CYCLE" spirit:order="274">50.000</spirit:value>
+ </spirit:modelParameter>
+ <spirit:modelParameter spirit:dataType="STRING">
+ <spirit:name>C_CLKOUT1_OUT_FREQ</spirit:name>
+ <spirit:value spirit:format="float" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C_CLKOUT1_OUT_FREQ" spirit:order="275">25.00000</spirit:value>
+ </spirit:modelParameter>
+ <spirit:modelParameter spirit:dataType="STRING">
+ <spirit:name>C_CLKOUT2_OUT_FREQ</spirit:name>
+ <spirit:value spirit:format="float" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C_CLKOUT2_OUT_FREQ" spirit:order="276">100.000</spirit:value>
+ </spirit:modelParameter>
+ <spirit:modelParameter spirit:dataType="STRING">
+ <spirit:name>C_CLKOUT3_OUT_FREQ</spirit:name>
+ <spirit:value spirit:format="float" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C_CLKOUT3_OUT_FREQ" spirit:order="277">100.000</spirit:value>
+ </spirit:modelParameter>
+ <spirit:modelParameter spirit:dataType="STRING">
+ <spirit:name>C_CLKOUT4_OUT_FREQ</spirit:name>
+ <spirit:value spirit:format="float" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C_CLKOUT4_OUT_FREQ" spirit:order="278">100.000</spirit:value>
+ </spirit:modelParameter>
+ <spirit:modelParameter spirit:dataType="STRING">
+ <spirit:name>C_CLKOUT5_OUT_FREQ</spirit:name>
+ <spirit:value spirit:format="float" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C_CLKOUT5_OUT_FREQ" spirit:order="279">100.000</spirit:value>
+ </spirit:modelParameter>
+ <spirit:modelParameter spirit:dataType="STRING">
+ <spirit:name>C_CLKOUT6_OUT_FREQ</spirit:name>
+ <spirit:value spirit:format="float" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C_CLKOUT6_OUT_FREQ" spirit:order="280">100.000</spirit:value>
+ </spirit:modelParameter>
+ <spirit:modelParameter spirit:dataType="STRING">
+ <spirit:name>C_CLKOUT7_OUT_FREQ</spirit:name>
+ <spirit:value spirit:format="float" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C_CLKOUT7_OUT_FREQ" spirit:order="281">100.000</spirit:value>
+ </spirit:modelParameter>
+ <spirit:modelParameter spirit:dataType="STRING">
+ <spirit:name>C_CLKOUT1_PHASE</spirit:name>
+ <spirit:value spirit:format="float" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C_CLKOUT1_PHASE" spirit:order="282">0.000</spirit:value>
+ </spirit:modelParameter>
+ <spirit:modelParameter spirit:dataType="STRING">
+ <spirit:name>C_CLKOUT2_PHASE</spirit:name>
+ <spirit:value spirit:format="float" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C_CLKOUT2_PHASE" spirit:order="283">0.000</spirit:value>
+ </spirit:modelParameter>
+ <spirit:modelParameter spirit:dataType="STRING">
+ <spirit:name>C_CLKOUT3_PHASE</spirit:name>
+ <spirit:value spirit:format="float" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C_CLKOUT3_PHASE" spirit:order="284">0.000</spirit:value>
+ </spirit:modelParameter>
+ <spirit:modelParameter spirit:dataType="STRING">
+ <spirit:name>C_CLKOUT4_PHASE</spirit:name>
+ <spirit:value spirit:format="float" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C_CLKOUT4_PHASE" spirit:order="285">0.000</spirit:value>
+ </spirit:modelParameter>
+ <spirit:modelParameter spirit:dataType="STRING">
+ <spirit:name>C_CLKOUT5_PHASE</spirit:name>
+ <spirit:value spirit:format="float" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C_CLKOUT5_PHASE" spirit:order="286">0.000</spirit:value>
+ </spirit:modelParameter>
+ <spirit:modelParameter spirit:dataType="STRING">
+ <spirit:name>C_CLKOUT6_PHASE</spirit:name>
+ <spirit:value spirit:format="float" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C_CLKOUT6_PHASE" spirit:order="287">0.000</spirit:value>
+ </spirit:modelParameter>
+ <spirit:modelParameter spirit:dataType="STRING">
+ <spirit:name>C_CLKOUT7_PHASE</spirit:name>
+ <spirit:value spirit:format="float" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C_CLKOUT7_PHASE" spirit:order="288">0.000</spirit:value>
+ </spirit:modelParameter>
+ <spirit:modelParameter spirit:dataType="STRING">
+ <spirit:name>C_CLKOUT1_DUTY_CYCLE</spirit:name>
+ <spirit:value spirit:format="float" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C_CLKOUT1_DUTY_CYCLE" spirit:order="289">50.0</spirit:value>
+ </spirit:modelParameter>
+ <spirit:modelParameter spirit:dataType="STRING">
+ <spirit:name>C_CLKOUT2_DUTY_CYCLE</spirit:name>
+ <spirit:value spirit:format="float" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C_CLKOUT2_DUTY_CYCLE" spirit:order="290">50.000</spirit:value>
+ </spirit:modelParameter>
+ <spirit:modelParameter spirit:dataType="STRING">
+ <spirit:name>C_CLKOUT3_DUTY_CYCLE</spirit:name>
+ <spirit:value spirit:format="float" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C_CLKOUT3_DUTY_CYCLE" spirit:order="291">50.000</spirit:value>
+ </spirit:modelParameter>
+ <spirit:modelParameter spirit:dataType="STRING">
+ <spirit:name>C_CLKOUT4_DUTY_CYCLE</spirit:name>
+ <spirit:value spirit:format="float" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C_CLKOUT4_DUTY_CYCLE" spirit:order="292">50.000</spirit:value>
+ </spirit:modelParameter>
+ <spirit:modelParameter spirit:dataType="STRING">
+ <spirit:name>C_CLKOUT5_DUTY_CYCLE</spirit:name>
+ <spirit:value spirit:format="float" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C_CLKOUT5_DUTY_CYCLE" spirit:order="293">50.000</spirit:value>
+ </spirit:modelParameter>
+ <spirit:modelParameter spirit:dataType="STRING">
+ <spirit:name>C_CLKOUT6_DUTY_CYCLE</spirit:name>
+ <spirit:value spirit:format="float" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C_CLKOUT6_DUTY_CYCLE" spirit:order="294">50.000</spirit:value>
+ </spirit:modelParameter>
+ <spirit:modelParameter spirit:dataType="STRING">
+ <spirit:name>C_CLKOUT7_DUTY_CYCLE</spirit:name>
+ <spirit:value spirit:format="float" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C_CLKOUT7_DUTY_CYCLE" spirit:order="295">50.000</spirit:value>
+ </spirit:modelParameter>
+ <spirit:modelParameter spirit:dataType="INTEGER">
+ <spirit:name>C_USE_SAFE_CLOCK_STARTUP</spirit:name>
+ <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C_USE_SAFE_CLOCK_STARTUP" spirit:order="500">0</spirit:value>
+ </spirit:modelParameter>
+ <spirit:modelParameter spirit:dataType="INTEGER">
+ <spirit:name>C_USE_CLOCK_SEQUENCING</spirit:name>
+ <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C_USE_CLOCK_SEQUENCING" spirit:order="501">0</spirit:value>
+ </spirit:modelParameter>
+ <spirit:modelParameter spirit:dataType="INTEGER">
+ <spirit:name>C_CLKOUT1_SEQUENCE_NUMBER</spirit:name>
+ <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C_CLKOUT1_SEQUENCE_NUMBER" spirit:order="502">1</spirit:value>
+ </spirit:modelParameter>
+ <spirit:modelParameter spirit:dataType="INTEGER">
+ <spirit:name>C_CLKOUT2_SEQUENCE_NUMBER</spirit:name>
+ <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C_CLKOUT2_SEQUENCE_NUMBER" spirit:order="503">1</spirit:value>
+ </spirit:modelParameter>
+ <spirit:modelParameter spirit:dataType="INTEGER">
+ <spirit:name>C_CLKOUT3_SEQUENCE_NUMBER</spirit:name>
+ <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C_CLKOUT3_SEQUENCE_NUMBER" spirit:order="504">1</spirit:value>
+ </spirit:modelParameter>
+ <spirit:modelParameter spirit:dataType="INTEGER">
+ <spirit:name>C_CLKOUT4_SEQUENCE_NUMBER</spirit:name>
+ <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C_CLKOUT4_SEQUENCE_NUMBER" spirit:order="505">1</spirit:value>
+ </spirit:modelParameter>
+ <spirit:modelParameter spirit:dataType="INTEGER">
+ <spirit:name>C_CLKOUT5_SEQUENCE_NUMBER</spirit:name>
+ <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C_CLKOUT5_SEQUENCE_NUMBER" spirit:order="506">1</spirit:value>
+ </spirit:modelParameter>
+ <spirit:modelParameter spirit:dataType="INTEGER">
+ <spirit:name>C_CLKOUT6_SEQUENCE_NUMBER</spirit:name>
+ <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C_CLKOUT6_SEQUENCE_NUMBER" spirit:order="507">1</spirit:value>
+ </spirit:modelParameter>
+ <spirit:modelParameter spirit:dataType="INTEGER">
+ <spirit:name>C_CLKOUT7_SEQUENCE_NUMBER</spirit:name>
+ <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C_CLKOUT7_SEQUENCE_NUMBER" spirit:order="508">1</spirit:value>
+ </spirit:modelParameter>
+ <spirit:modelParameter spirit:dataType="STRING">
+ <spirit:name>C_MMCM_NOTES</spirit:name>
+ <spirit:value spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C_MMCM_NOTES" spirit:order="296">None</spirit:value>
+ </spirit:modelParameter>
+ <spirit:modelParameter spirit:dataType="STRING">
+ <spirit:name>C_MMCM_BANDWIDTH</spirit:name>
+ <spirit:value spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C_MMCM_BANDWIDTH" spirit:order="297">OPTIMIZED</spirit:value>
+ </spirit:modelParameter>
+ <spirit:modelParameter spirit:dataType="STRING">
+ <spirit:name>C_MMCM_CLKFBOUT_MULT_F</spirit:name>
+ <spirit:value spirit:format="float" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C_MMCM_CLKFBOUT_MULT_F" spirit:order="298">9.125</spirit:value>
+ </spirit:modelParameter>
+ <spirit:modelParameter spirit:dataType="STRING">
+ <spirit:name>C_MMCM_CLKIN1_PERIOD</spirit:name>
+ <spirit:value spirit:format="float" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C_MMCM_CLKIN1_PERIOD" spirit:order="299">10.000</spirit:value>
+ </spirit:modelParameter>
+ <spirit:modelParameter spirit:dataType="STRING">
+ <spirit:name>C_MMCM_CLKIN2_PERIOD</spirit:name>
+ <spirit:value spirit:format="float" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C_MMCM_CLKIN2_PERIOD" spirit:order="300">10.000</spirit:value>
+ </spirit:modelParameter>
+ <spirit:modelParameter spirit:dataType="STRING">
+ <spirit:name>C_MMCM_CLKOUT4_CASCADE</spirit:name>
+ <spirit:value spirit:format="bool" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C_MMCM_CLKOUT4_CASCADE" spirit:order="301">FALSE</spirit:value>
+ </spirit:modelParameter>
+ <spirit:modelParameter spirit:dataType="STRING">
+ <spirit:name>C_MMCM_CLOCK_HOLD</spirit:name>
+ <spirit:value spirit:format="bool" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C_MMCM_CLOCK_HOLD" spirit:order="302">FALSE</spirit:value>
+ </spirit:modelParameter>
+ <spirit:modelParameter spirit:dataType="STRING">
+ <spirit:name>C_MMCM_COMPENSATION</spirit:name>
+ <spirit:value spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C_MMCM_COMPENSATION" spirit:order="303">ZHOLD</spirit:value>
+ </spirit:modelParameter>
+ <spirit:modelParameter spirit:dataType="INTEGER">
+ <spirit:name>C_MMCM_DIVCLK_DIVIDE</spirit:name>
+ <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C_MMCM_DIVCLK_DIVIDE" spirit:order="304">1</spirit:value>
+ </spirit:modelParameter>
+ <spirit:modelParameter spirit:dataType="STRING">
+ <spirit:name>C_MMCM_REF_JITTER1</spirit:name>
+ <spirit:value spirit:format="float" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C_MMCM_REF_JITTER1" spirit:order="305">0.010</spirit:value>
+ </spirit:modelParameter>
+ <spirit:modelParameter spirit:dataType="STRING">
+ <spirit:name>C_MMCM_REF_JITTER2</spirit:name>
+ <spirit:value spirit:format="float" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C_MMCM_REF_JITTER2" spirit:order="306">0.010</spirit:value>
+ </spirit:modelParameter>
+ <spirit:modelParameter spirit:dataType="STRING">
+ <spirit:name>C_MMCM_STARTUP_WAIT</spirit:name>
+ <spirit:value spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C_MMCM_STARTUP_WAIT" spirit:order="307">FALSE</spirit:value>
+ </spirit:modelParameter>
+ <spirit:modelParameter spirit:dataType="STRING">
+ <spirit:name>C_MMCM_CLKOUT0_DIVIDE_F</spirit:name>
+ <spirit:value spirit:format="float" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C_MMCM_CLKOUT0_DIVIDE_F" spirit:order="308">36.500</spirit:value>
+ </spirit:modelParameter>
+ <spirit:modelParameter spirit:dataType="STRING">
+ <spirit:name>C_MMCM_CLKOUT1_DIVIDE</spirit:name>
+ <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C_MMCM_CLKOUT1_DIVIDE" spirit:order="309">1</spirit:value>
+ </spirit:modelParameter>
+ <spirit:modelParameter spirit:dataType="STRING">
+ <spirit:name>C_MMCM_CLKOUT2_DIVIDE</spirit:name>
+ <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C_MMCM_CLKOUT2_DIVIDE" spirit:order="310">1</spirit:value>
+ </spirit:modelParameter>
+ <spirit:modelParameter spirit:dataType="STRING">
+ <spirit:name>C_MMCM_CLKOUT3_DIVIDE</spirit:name>
+ <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C_MMCM_CLKOUT3_DIVIDE" spirit:order="311">1</spirit:value>
+ </spirit:modelParameter>
+ <spirit:modelParameter spirit:dataType="STRING">
+ <spirit:name>C_MMCM_CLKOUT4_DIVIDE</spirit:name>
+ <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C_MMCM_CLKOUT4_DIVIDE" spirit:order="312">1</spirit:value>
+ </spirit:modelParameter>
+ <spirit:modelParameter spirit:dataType="STRING">
+ <spirit:name>C_MMCM_CLKOUT5_DIVIDE</spirit:name>
+ <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C_MMCM_CLKOUT5_DIVIDE" spirit:order="313">1</spirit:value>
+ </spirit:modelParameter>
+ <spirit:modelParameter spirit:dataType="STRING">
+ <spirit:name>C_MMCM_CLKOUT6_DIVIDE</spirit:name>
+ <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C_MMCM_CLKOUT6_DIVIDE" spirit:order="314">1</spirit:value>
+ </spirit:modelParameter>
+ <spirit:modelParameter spirit:dataType="STRING">
+ <spirit:name>C_MMCM_CLKOUT0_DUTY_CYCLE</spirit:name>
+ <spirit:value spirit:format="float" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C_MMCM_CLKOUT0_DUTY_CYCLE" spirit:order="315">0.500</spirit:value>
+ </spirit:modelParameter>
+ <spirit:modelParameter spirit:dataType="STRING">
+ <spirit:name>C_MMCM_CLKOUT1_DUTY_CYCLE</spirit:name>
+ <spirit:value spirit:format="float" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C_MMCM_CLKOUT1_DUTY_CYCLE" spirit:order="316">0.500</spirit:value>
+ </spirit:modelParameter>
+ <spirit:modelParameter spirit:dataType="STRING">
+ <spirit:name>C_MMCM_CLKOUT2_DUTY_CYCLE</spirit:name>
+ <spirit:value spirit:format="float" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C_MMCM_CLKOUT2_DUTY_CYCLE" spirit:order="317">0.500</spirit:value>
+ </spirit:modelParameter>
+ <spirit:modelParameter spirit:dataType="STRING">
+ <spirit:name>C_MMCM_CLKOUT3_DUTY_CYCLE</spirit:name>
+ <spirit:value spirit:format="float" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C_MMCM_CLKOUT3_DUTY_CYCLE" spirit:order="318">0.500</spirit:value>
+ </spirit:modelParameter>
+ <spirit:modelParameter spirit:dataType="STRING">
+ <spirit:name>C_MMCM_CLKOUT4_DUTY_CYCLE</spirit:name>
+ <spirit:value spirit:format="float" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C_MMCM_CLKOUT4_DUTY_CYCLE" spirit:order="319">0.500</spirit:value>
+ </spirit:modelParameter>
+ <spirit:modelParameter spirit:dataType="STRING">
+ <spirit:name>C_MMCM_CLKOUT5_DUTY_CYCLE</spirit:name>
+ <spirit:value spirit:format="float" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C_MMCM_CLKOUT5_DUTY_CYCLE" spirit:order="320">0.500</spirit:value>
+ </spirit:modelParameter>
+ <spirit:modelParameter spirit:dataType="STRING">
+ <spirit:name>C_MMCM_CLKOUT6_DUTY_CYCLE</spirit:name>
+ <spirit:value spirit:format="float" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C_MMCM_CLKOUT6_DUTY_CYCLE" spirit:order="321">0.500</spirit:value>
+ </spirit:modelParameter>
+ <spirit:modelParameter spirit:dataType="STRING">
+ <spirit:name>C_MMCM_CLKFBOUT_PHASE</spirit:name>
+ <spirit:value spirit:format="float" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C_MMCM_CLKFBOUT_PHASE" spirit:order="322">0.000</spirit:value>
+ </spirit:modelParameter>
+ <spirit:modelParameter spirit:dataType="STRING">
+ <spirit:name>C_MMCM_CLKOUT0_PHASE</spirit:name>
+ <spirit:value spirit:format="float" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C_MMCM_CLKOUT0_PHASE" spirit:order="323">0.000</spirit:value>
+ </spirit:modelParameter>
+ <spirit:modelParameter spirit:dataType="STRING">
+ <spirit:name>C_MMCM_CLKOUT1_PHASE</spirit:name>
+ <spirit:value spirit:format="float" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C_MMCM_CLKOUT1_PHASE" spirit:order="324">0.000</spirit:value>
+ </spirit:modelParameter>
+ <spirit:modelParameter spirit:dataType="STRING">
+ <spirit:name>C_MMCM_CLKOUT2_PHASE</spirit:name>
+ <spirit:value spirit:format="float" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C_MMCM_CLKOUT2_PHASE" spirit:order="325">0.000</spirit:value>
+ </spirit:modelParameter>
+ <spirit:modelParameter spirit:dataType="STRING">
+ <spirit:name>C_MMCM_CLKOUT3_PHASE</spirit:name>
+ <spirit:value spirit:format="float" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C_MMCM_CLKOUT3_PHASE" spirit:order="326">0.000</spirit:value>
+ </spirit:modelParameter>
+ <spirit:modelParameter spirit:dataType="STRING">
+ <spirit:name>C_MMCM_CLKOUT4_PHASE</spirit:name>
+ <spirit:value spirit:format="float" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C_MMCM_CLKOUT4_PHASE" spirit:order="327">0.000</spirit:value>
+ </spirit:modelParameter>
+ <spirit:modelParameter spirit:dataType="STRING">
+ <spirit:name>C_MMCM_CLKOUT5_PHASE</spirit:name>
+ <spirit:value spirit:format="float" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C_MMCM_CLKOUT5_PHASE" spirit:order="328">0.000</spirit:value>
+ </spirit:modelParameter>
+ <spirit:modelParameter spirit:dataType="STRING">
+ <spirit:name>C_MMCM_CLKOUT6_PHASE</spirit:name>
+ <spirit:value spirit:format="float" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C_MMCM_CLKOUT6_PHASE" spirit:order="329">0.000</spirit:value>
+ </spirit:modelParameter>
+ <spirit:modelParameter spirit:dataType="STRING">
+ <spirit:name>C_MMCM_CLKFBOUT_USE_FINE_PS</spirit:name>
+ <spirit:value spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C_MMCM_CLKFBOUT_USE_FINE_PS" spirit:order="330">FALSE</spirit:value>
+ </spirit:modelParameter>
+ <spirit:modelParameter spirit:dataType="STRING">
+ <spirit:name>C_MMCM_CLKOUT0_USE_FINE_PS</spirit:name>
+ <spirit:value spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C_MMCM_CLKOUT0_USE_FINE_PS" spirit:order="331">FALSE</spirit:value>
+ </spirit:modelParameter>
+ <spirit:modelParameter spirit:dataType="STRING">
+ <spirit:name>C_MMCM_CLKOUT1_USE_FINE_PS</spirit:name>
+ <spirit:value spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C_MMCM_CLKOUT1_USE_FINE_PS" spirit:order="332">FALSE</spirit:value>
+ </spirit:modelParameter>
+ <spirit:modelParameter spirit:dataType="STRING">
+ <spirit:name>C_MMCM_CLKOUT2_USE_FINE_PS</spirit:name>
+ <spirit:value spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C_MMCM_CLKOUT2_USE_FINE_PS" spirit:order="333">FALSE</spirit:value>
+ </spirit:modelParameter>
+ <spirit:modelParameter spirit:dataType="STRING">
+ <spirit:name>C_MMCM_CLKOUT3_USE_FINE_PS</spirit:name>
+ <spirit:value spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C_MMCM_CLKOUT3_USE_FINE_PS" spirit:order="334">FALSE</spirit:value>
+ </spirit:modelParameter>
+ <spirit:modelParameter spirit:dataType="STRING">
+ <spirit:name>C_MMCM_CLKOUT4_USE_FINE_PS</spirit:name>
+ <spirit:value spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C_MMCM_CLKOUT4_USE_FINE_PS" spirit:order="335">FALSE</spirit:value>
+ </spirit:modelParameter>
+ <spirit:modelParameter spirit:dataType="STRING">
+ <spirit:name>C_MMCM_CLKOUT5_USE_FINE_PS</spirit:name>
+ <spirit:value spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C_MMCM_CLKOUT5_USE_FINE_PS" spirit:order="336">FALSE</spirit:value>
+ </spirit:modelParameter>
+ <spirit:modelParameter spirit:dataType="STRING">
+ <spirit:name>C_MMCM_CLKOUT6_USE_FINE_PS</spirit:name>
+ <spirit:value spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C_MMCM_CLKOUT6_USE_FINE_PS" spirit:order="337">FALSE</spirit:value>
+ </spirit:modelParameter>
+ <spirit:modelParameter spirit:dataType="STRING">
+ <spirit:name>C_PLL_NOTES</spirit:name>
+ <spirit:value spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C_PLL_NOTES" spirit:order="338">No notes</spirit:value>
+ </spirit:modelParameter>
+ <spirit:modelParameter spirit:dataType="STRING">
+ <spirit:name>C_PLL_BANDWIDTH</spirit:name>
+ <spirit:value spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C_PLL_BANDWIDTH" spirit:order="339">OPTIMIZED</spirit:value>
+ </spirit:modelParameter>
+ <spirit:modelParameter spirit:dataType="STRING">
+ <spirit:name>C_PLL_CLK_FEEDBACK</spirit:name>
+ <spirit:value spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C_PLL_CLK_FEEDBACK" spirit:order="340">CLKFBOUT</spirit:value>
+ </spirit:modelParameter>
+ <spirit:modelParameter spirit:dataType="INTEGER">
+ <spirit:name>C_PLL_CLKFBOUT_MULT</spirit:name>
+ <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C_PLL_CLKFBOUT_MULT" spirit:order="341">1</spirit:value>
+ </spirit:modelParameter>
+ <spirit:modelParameter spirit:dataType="STRING">
+ <spirit:name>C_PLL_CLKIN_PERIOD</spirit:name>
+ <spirit:value spirit:format="float" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C_PLL_CLKIN_PERIOD" spirit:order="342">1.000</spirit:value>
+ </spirit:modelParameter>
+ <spirit:modelParameter spirit:dataType="STRING">
+ <spirit:name>C_PLL_COMPENSATION</spirit:name>
+ <spirit:value spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C_PLL_COMPENSATION" spirit:order="343">SYSTEM_SYNCHRONOUS</spirit:value>
+ </spirit:modelParameter>
+ <spirit:modelParameter spirit:dataType="INTEGER">
+ <spirit:name>C_PLL_DIVCLK_DIVIDE</spirit:name>
+ <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C_PLL_DIVCLK_DIVIDE" spirit:order="344">1</spirit:value>
+ </spirit:modelParameter>
+ <spirit:modelParameter spirit:dataType="STRING">
+ <spirit:name>C_PLL_REF_JITTER</spirit:name>
+ <spirit:value spirit:format="float" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C_PLL_REF_JITTER" spirit:order="345">0.010</spirit:value>
+ </spirit:modelParameter>
+ <spirit:modelParameter spirit:dataType="INTEGER">
+ <spirit:name>C_PLL_CLKOUT0_DIVIDE</spirit:name>
+ <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C_PLL_CLKOUT0_DIVIDE" spirit:order="346">1</spirit:value>
+ </spirit:modelParameter>
+ <spirit:modelParameter spirit:dataType="INTEGER">
+ <spirit:name>C_PLL_CLKOUT1_DIVIDE</spirit:name>
+ <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C_PLL_CLKOUT1_DIVIDE" spirit:order="347">1</spirit:value>
+ </spirit:modelParameter>
+ <spirit:modelParameter spirit:dataType="INTEGER">
+ <spirit:name>C_PLL_CLKOUT2_DIVIDE</spirit:name>
+ <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C_PLL_CLKOUT2_DIVIDE" spirit:order="348">1</spirit:value>
+ </spirit:modelParameter>
+ <spirit:modelParameter spirit:dataType="INTEGER">
+ <spirit:name>C_PLL_CLKOUT3_DIVIDE</spirit:name>
+ <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C_PLL_CLKOUT3_DIVIDE" spirit:order="349">1</spirit:value>
+ </spirit:modelParameter>
+ <spirit:modelParameter spirit:dataType="INTEGER">
+ <spirit:name>C_PLL_CLKOUT4_DIVIDE</spirit:name>
+ <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C_PLL_CLKOUT4_DIVIDE" spirit:order="350">1</spirit:value>
+ </spirit:modelParameter>
+ <spirit:modelParameter spirit:dataType="INTEGER">
+ <spirit:name>C_PLL_CLKOUT5_DIVIDE</spirit:name>
+ <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C_PLL_CLKOUT5_DIVIDE" spirit:order="351">1</spirit:value>
+ </spirit:modelParameter>
+ <spirit:modelParameter spirit:dataType="STRING">
+ <spirit:name>C_PLL_CLKOUT0_DUTY_CYCLE</spirit:name>
+ <spirit:value spirit:format="float" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C_PLL_CLKOUT0_DUTY_CYCLE" spirit:order="352">0.500</spirit:value>
+ </spirit:modelParameter>
+ <spirit:modelParameter spirit:dataType="STRING">
+ <spirit:name>C_PLL_CLKOUT1_DUTY_CYCLE</spirit:name>
+ <spirit:value spirit:format="float" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C_PLL_CLKOUT1_DUTY_CYCLE" spirit:order="353">0.500</spirit:value>
+ </spirit:modelParameter>
+ <spirit:modelParameter spirit:dataType="STRING">
+ <spirit:name>C_PLL_CLKOUT2_DUTY_CYCLE</spirit:name>
+ <spirit:value spirit:format="float" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C_PLL_CLKOUT2_DUTY_CYCLE" spirit:order="354">0.500</spirit:value>
+ </spirit:modelParameter>
+ <spirit:modelParameter spirit:dataType="STRING">
+ <spirit:name>C_PLL_CLKOUT3_DUTY_CYCLE</spirit:name>
+ <spirit:value spirit:format="float" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C_PLL_CLKOUT3_DUTY_CYCLE" spirit:order="355">0.500</spirit:value>
+ </spirit:modelParameter>
+ <spirit:modelParameter spirit:dataType="STRING">
+ <spirit:name>C_PLL_CLKOUT4_DUTY_CYCLE</spirit:name>
+ <spirit:value spirit:format="float" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C_PLL_CLKOUT4_DUTY_CYCLE" spirit:order="356">0.500</spirit:value>
+ </spirit:modelParameter>
+ <spirit:modelParameter spirit:dataType="STRING">
+ <spirit:name>C_PLL_CLKOUT5_DUTY_CYCLE</spirit:name>
+ <spirit:value spirit:format="float" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C_PLL_CLKOUT5_DUTY_CYCLE" spirit:order="357">0.500</spirit:value>
+ </spirit:modelParameter>
+ <spirit:modelParameter spirit:dataType="STRING">
+ <spirit:name>C_PLL_CLKFBOUT_PHASE</spirit:name>
+ <spirit:value spirit:format="float" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C_PLL_CLKFBOUT_PHASE" spirit:order="358">0.000</spirit:value>
+ </spirit:modelParameter>
+ <spirit:modelParameter spirit:dataType="STRING">
+ <spirit:name>C_PLL_CLKOUT0_PHASE</spirit:name>
+ <spirit:value spirit:format="float" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C_PLL_CLKOUT0_PHASE" spirit:order="359">0.000</spirit:value>
+ </spirit:modelParameter>
+ <spirit:modelParameter spirit:dataType="STRING">
+ <spirit:name>C_PLL_CLKOUT1_PHASE</spirit:name>
+ <spirit:value spirit:format="float" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C_PLL_CLKOUT1_PHASE" spirit:order="360">0.000</spirit:value>
+ </spirit:modelParameter>
+ <spirit:modelParameter spirit:dataType="STRING">
+ <spirit:name>C_PLL_CLKOUT2_PHASE</spirit:name>
+ <spirit:value spirit:format="float" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C_PLL_CLKOUT2_PHASE" spirit:order="361">0.000</spirit:value>
+ </spirit:modelParameter>
+ <spirit:modelParameter spirit:dataType="STRING">
+ <spirit:name>C_PLL_CLKOUT3_PHASE</spirit:name>
+ <spirit:value spirit:format="float" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C_PLL_CLKOUT3_PHASE" spirit:order="362">0.000</spirit:value>
+ </spirit:modelParameter>
+ <spirit:modelParameter spirit:dataType="STRING">
+ <spirit:name>C_PLL_CLKOUT4_PHASE</spirit:name>
+ <spirit:value spirit:format="float" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C_PLL_CLKOUT4_PHASE" spirit:order="363">0.000</spirit:value>
+ </spirit:modelParameter>
+ <spirit:modelParameter spirit:dataType="STRING">
+ <spirit:name>C_PLL_CLKOUT5_PHASE</spirit:name>
+ <spirit:value spirit:format="float" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C_PLL_CLKOUT5_PHASE" spirit:order="364">0.000</spirit:value>
+ </spirit:modelParameter>
+ <spirit:modelParameter spirit:dataType="STRING">
+ <spirit:name>C_CLOCK_MGR_TYPE</spirit:name>
+ <spirit:value spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C_CLOCK_MGR_TYPE" spirit:order="365">NA</spirit:value>
+ </spirit:modelParameter>
+ <spirit:modelParameter spirit:dataType="INTEGER">
+ <spirit:name>C_OVERRIDE_MMCM</spirit:name>
+ <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C_OVERRIDE_MMCM" spirit:order="366">0</spirit:value>
+ </spirit:modelParameter>
+ <spirit:modelParameter spirit:dataType="INTEGER">
+ <spirit:name>C_OVERRIDE_PLL</spirit:name>
+ <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C_OVERRIDE_PLL" spirit:order="367">0</spirit:value>
+ </spirit:modelParameter>
+ <spirit:modelParameter spirit:dataType="STRING">
+ <spirit:name>C_PRIMARY_PORT</spirit:name>
+ <spirit:value spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C_PRIMARY_PORT" spirit:order="368">clk_in1</spirit:value>
+ </spirit:modelParameter>
+ <spirit:modelParameter spirit:dataType="STRING">
+ <spirit:name>C_SECONDARY_PORT</spirit:name>
+ <spirit:value spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C_SECONDARY_PORT" spirit:order="369">clk_in2</spirit:value>
+ </spirit:modelParameter>
+ <spirit:modelParameter spirit:dataType="STRING">
+ <spirit:name>C_CLK_OUT1_PORT</spirit:name>
+ <spirit:value spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C_CLK_OUT1_PORT" spirit:order="370">clk_out1</spirit:value>
+ </spirit:modelParameter>
+ <spirit:modelParameter spirit:dataType="STRING">
+ <spirit:name>C_CLK_OUT2_PORT</spirit:name>
+ <spirit:value spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C_CLK_OUT2_PORT" spirit:order="371">clk_out2</spirit:value>
+ </spirit:modelParameter>
+ <spirit:modelParameter spirit:dataType="STRING">
+ <spirit:name>C_CLK_OUT3_PORT</spirit:name>
+ <spirit:value spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C_CLK_OUT3_PORT" spirit:order="372">clk_out3</spirit:value>
+ </spirit:modelParameter>
+ <spirit:modelParameter spirit:dataType="STRING">
+ <spirit:name>C_CLK_OUT4_PORT</spirit:name>
+ <spirit:value spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C_CLK_OUT4_PORT" spirit:order="373">clk_out4</spirit:value>
+ </spirit:modelParameter>
+ <spirit:modelParameter spirit:dataType="STRING">
+ <spirit:name>C_CLK_OUT5_PORT</spirit:name>
+ <spirit:value spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C_CLK_OUT5_PORT" spirit:order="374">clk_out5</spirit:value>
+ </spirit:modelParameter>
+ <spirit:modelParameter spirit:dataType="STRING">
+ <spirit:name>C_CLK_OUT6_PORT</spirit:name>
+ <spirit:value spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C_CLK_OUT6_PORT" spirit:order="375">clk_out6</spirit:value>
+ </spirit:modelParameter>
+ <spirit:modelParameter spirit:dataType="STRING">
+ <spirit:name>C_CLK_OUT7_PORT</spirit:name>
+ <spirit:value spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C_CLK_OUT7_PORT" spirit:order="376">clk_out7</spirit:value>
+ </spirit:modelParameter>
+ <spirit:modelParameter spirit:dataType="STRING">
+ <spirit:name>C_RESET_PORT</spirit:name>
+ <spirit:value spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C_RESET_PORT" spirit:order="377">resetn</spirit:value>
+ </spirit:modelParameter>
+ <spirit:modelParameter spirit:dataType="STRING">
+ <spirit:name>C_LOCKED_PORT</spirit:name>
+ <spirit:value spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C_LOCKED_PORT" spirit:order="378">locked</spirit:value>
+ </spirit:modelParameter>
+ <spirit:modelParameter spirit:dataType="STRING">
+ <spirit:name>C_CLKFB_IN_PORT</spirit:name>
+ <spirit:value spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C_CLKFB_IN_PORT" spirit:order="379">clkfb_in</spirit:value>
+ </spirit:modelParameter>
+ <spirit:modelParameter spirit:dataType="STRING">
+ <spirit:name>C_CLKFB_IN_P_PORT</spirit:name>
+ <spirit:value spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C_CLKFB_IN_P_PORT" spirit:order="380">clkfb_in_p</spirit:value>
+ </spirit:modelParameter>
+ <spirit:modelParameter spirit:dataType="STRING">
+ <spirit:name>C_CLKFB_IN_N_PORT</spirit:name>
+ <spirit:value spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C_CLKFB_IN_N_PORT" spirit:order="381">clkfb_in_n</spirit:value>
+ </spirit:modelParameter>
+ <spirit:modelParameter spirit:dataType="STRING">
+ <spirit:name>C_CLKFB_OUT_PORT</spirit:name>
+ <spirit:value spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C_CLKFB_OUT_PORT" spirit:order="382">clkfb_out</spirit:value>
+ </spirit:modelParameter>
+ <spirit:modelParameter spirit:dataType="STRING">
+ <spirit:name>C_CLKFB_OUT_P_PORT</spirit:name>
+ <spirit:value spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C_CLKFB_OUT_P_PORT" spirit:order="383">clkfb_out_p</spirit:value>
+ </spirit:modelParameter>
+ <spirit:modelParameter spirit:dataType="STRING">
+ <spirit:name>C_CLKFB_OUT_N_PORT</spirit:name>
+ <spirit:value spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C_CLKFB_OUT_N_PORT" spirit:order="384">clkfb_out_n</spirit:value>
+ </spirit:modelParameter>
+ <spirit:modelParameter spirit:dataType="STRING">
+ <spirit:name>C_POWER_DOWN_PORT</spirit:name>
+ <spirit:value spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C_POWER_DOWN_PORT" spirit:order="385">power_down</spirit:value>
+ </spirit:modelParameter>
+ <spirit:modelParameter spirit:dataType="STRING">
+ <spirit:name>C_DADDR_PORT</spirit:name>
+ <spirit:value spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C_DADDR_PORT" spirit:order="386">daddr</spirit:value>
+ </spirit:modelParameter>
+ <spirit:modelParameter spirit:dataType="STRING">
+ <spirit:name>C_DCLK_PORT</spirit:name>
+ <spirit:value spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C_DCLK_PORT" spirit:order="387">dclk</spirit:value>
+ </spirit:modelParameter>
+ <spirit:modelParameter spirit:dataType="STRING">
+ <spirit:name>C_DRDY_PORT</spirit:name>
+ <spirit:value spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C_DRDY_PORT" spirit:order="388">drdy</spirit:value>
+ </spirit:modelParameter>
+ <spirit:modelParameter spirit:dataType="STRING">
+ <spirit:name>C_DWE_PORT</spirit:name>
+ <spirit:value spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C_DWE_PORT" spirit:order="389">dwe</spirit:value>
+ </spirit:modelParameter>
+ <spirit:modelParameter spirit:dataType="STRING">
+ <spirit:name>C_DIN_PORT</spirit:name>
+ <spirit:value spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C_DIN_PORT" spirit:order="390">din</spirit:value>
+ </spirit:modelParameter>
+ <spirit:modelParameter spirit:dataType="STRING">
+ <spirit:name>C_DOUT_PORT</spirit:name>
+ <spirit:value spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C_DOUT_PORT" spirit:order="391">dout</spirit:value>
+ </spirit:modelParameter>
+ <spirit:modelParameter spirit:dataType="STRING">
+ <spirit:name>C_DEN_PORT</spirit:name>
+ <spirit:value spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C_DEN_PORT" spirit:order="392">den</spirit:value>
+ </spirit:modelParameter>
+ <spirit:modelParameter spirit:dataType="STRING">
+ <spirit:name>C_PSCLK_PORT</spirit:name>
+ <spirit:value spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C_PSCLK_PORT" spirit:order="393">psclk</spirit:value>
+ </spirit:modelParameter>
+ <spirit:modelParameter spirit:dataType="STRING">
+ <spirit:name>C_PSEN_PORT</spirit:name>
+ <spirit:value spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C_PSEN_PORT" spirit:order="394">psen</spirit:value>
+ </spirit:modelParameter>
+ <spirit:modelParameter spirit:dataType="STRING">
+ <spirit:name>C_PSINCDEC_PORT</spirit:name>
+ <spirit:value spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C_PSINCDEC_PORT" spirit:order="395">psincdec</spirit:value>
+ </spirit:modelParameter>
+ <spirit:modelParameter spirit:dataType="STRING">
+ <spirit:name>C_PSDONE_PORT</spirit:name>
+ <spirit:value spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C_PSDONE_PORT" spirit:order="396">psdone</spirit:value>
+ </spirit:modelParameter>
+ <spirit:modelParameter spirit:dataType="STRING">
+ <spirit:name>C_CLK_VALID_PORT</spirit:name>
+ <spirit:value spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C_CLK_VALID_PORT" spirit:order="397">CLK_VALID</spirit:value>
+ </spirit:modelParameter>
+ <spirit:modelParameter spirit:dataType="STRING">
+ <spirit:name>C_STATUS_PORT</spirit:name>
+ <spirit:value spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C_STATUS_PORT" spirit:order="398">STATUS</spirit:value>
+ </spirit:modelParameter>
+ <spirit:modelParameter spirit:dataType="STRING">
+ <spirit:name>C_CLK_IN_SEL_PORT</spirit:name>
+ <spirit:value spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C_CLK_IN_SEL_PORT" spirit:order="399">clk_in_sel</spirit:value>
+ </spirit:modelParameter>
+ <spirit:modelParameter spirit:dataType="STRING">
+ <spirit:name>C_INPUT_CLK_STOPPED_PORT</spirit:name>
+ <spirit:value spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C_INPUT_CLK_STOPPED_PORT" spirit:order="400">input_clk_stopped</spirit:value>
+ </spirit:modelParameter>
+ <spirit:modelParameter spirit:dataType="STRING">
+ <spirit:name>C_CLKFB_STOPPED_PORT</spirit:name>
+ <spirit:value spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C_CLKFB_STOPPED_PORT" spirit:order="401">clkfb_stopped</spirit:value>
+ </spirit:modelParameter>
+ <spirit:modelParameter spirit:dataType="STRING">
+ <spirit:name>C_CLKIN1_JITTER_PS</spirit:name>
+ <spirit:value spirit:format="float" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C_CLKIN1_JITTER_PS" spirit:order="402">100.0</spirit:value>
+ </spirit:modelParameter>
+ <spirit:modelParameter spirit:dataType="STRING">
+ <spirit:name>C_CLKIN2_JITTER_PS</spirit:name>
+ <spirit:value spirit:format="float" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C_CLKIN2_JITTER_PS" spirit:order="403">100.0</spirit:value>
+ </spirit:modelParameter>
+ <spirit:modelParameter spirit:dataType="STRING">
+ <spirit:name>C_PRIMITIVE</spirit:name>
+ <spirit:value spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C_PRIMITIVE" spirit:order="404">MMCM</spirit:value>
+ </spirit:modelParameter>
+ <spirit:modelParameter spirit:dataType="STRING">
+ <spirit:name>C_SS_MODE</spirit:name>
+ <spirit:value spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C_SS_MODE" spirit:order="405">CENTER_HIGH</spirit:value>
+ </spirit:modelParameter>
+ <spirit:modelParameter spirit:dataType="INTEGER">
+ <spirit:name>C_SS_MOD_PERIOD</spirit:name>
+ <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C_SS_MOD_PERIOD" spirit:order="406">4000</spirit:value>
+ </spirit:modelParameter>
+ <spirit:modelParameter spirit:dataType="STRING">
+ <spirit:name>C_SS_MOD_TIME</spirit:name>
+ <spirit:value spirit:format="float" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C_SS_MOD_TIME" spirit:order="406.001">0.004</spirit:value>
+ </spirit:modelParameter>
+ <spirit:modelParameter spirit:dataType="INTEGER">
+ <spirit:name>C_HAS_CDDC</spirit:name>
+ <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C_HAS_CDDC" spirit:order="407">0</spirit:value>
+ </spirit:modelParameter>
+ <spirit:modelParameter spirit:dataType="STRING">
+ <spirit:name>C_CDDCDONE_PORT</spirit:name>
+ <spirit:value spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C_CDDCDONE_PORT" spirit:order="408">cddcdone</spirit:value>
+ </spirit:modelParameter>
+ <spirit:modelParameter spirit:dataType="STRING">
+ <spirit:name>C_CDDCREQ_PORT</spirit:name>
+ <spirit:value spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C_CDDCREQ_PORT" spirit:order="409">cddcreq</spirit:value>
+ </spirit:modelParameter>
+ <spirit:modelParameter spirit:dataType="STRING">
+ <spirit:name>C_CLKOUTPHY_MODE</spirit:name>
+ <spirit:value spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C_CLKOUTPHY_MODE" spirit:order="410">VCO</spirit:value>
+ </spirit:modelParameter>
+ <spirit:modelParameter spirit:dataType="INTEGER">
+ <spirit:name>C_ENABLE_CLKOUTPHY</spirit:name>
+ <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C_ENABLE_CLKOUTPHY" spirit:order="411">0</spirit:value>
+ </spirit:modelParameter>
+ <spirit:modelParameter spirit:dataType="INTEGER">
+ <spirit:name>C_INTERFACE_SELECTION</spirit:name>
+ <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C_INTERFACE_SELECTION" spirit:order="412">0</spirit:value>
+ </spirit:modelParameter>
+ <spirit:modelParameter spirit:dataType="INTEGER">
+ <spirit:name>C_S_AXI_ADDR_WIDTH</spirit:name>
+ <spirit:displayName>C S Axi Addr Width</spirit:displayName>
+ <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C_S_AXI_ADDR_WIDTH" spirit:order="215" spirit:minimum="2" spirit:maximum="32" spirit:rangeType="long">11</spirit:value>
+ </spirit:modelParameter>
+ <spirit:modelParameter spirit:dataType="INTEGER">
+ <spirit:name>C_S_AXI_DATA_WIDTH</spirit:name>
+ <spirit:displayName>C S Axi Data Width</spirit:displayName>
+ <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C_S_AXI_DATA_WIDTH" spirit:order="216" spirit:minimum="32" spirit:maximum="128" spirit:rangeType="long">32</spirit:value>
+ </spirit:modelParameter>
+ <spirit:modelParameter spirit:dataType="STRING">
+ <spirit:name>C_POWER_REG</spirit:name>
+ <spirit:value spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C_POWER_REG" spirit:order="409">0000</spirit:value>
+ </spirit:modelParameter>
+ <spirit:modelParameter spirit:dataType="STRING">
+ <spirit:name>C_CLKOUT0_1</spirit:name>
+ <spirit:value spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C_CLKOUT0_1" spirit:order="410">0000</spirit:value>
+ </spirit:modelParameter>
+ <spirit:modelParameter spirit:dataType="STRING">
+ <spirit:name>C_CLKOUT0_2</spirit:name>
+ <spirit:value spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C_CLKOUT0_2" spirit:order="411">0000</spirit:value>
+ </spirit:modelParameter>
+ <spirit:modelParameter spirit:dataType="STRING">
+ <spirit:name>C_CLKOUT1_1</spirit:name>
+ <spirit:value spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C_CLKOUT1_1" spirit:order="410">0000</spirit:value>
+ </spirit:modelParameter>
+ <spirit:modelParameter spirit:dataType="STRING">
+ <spirit:name>C_CLKOUT1_2</spirit:name>
+ <spirit:value spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C_CLKOUT1_2" spirit:order="410">0000</spirit:value>
+ </spirit:modelParameter>
+ <spirit:modelParameter spirit:dataType="STRING">
+ <spirit:name>C_CLKOUT2_1</spirit:name>
+ <spirit:value spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C_CLKOUT2_1" spirit:order="411">0000</spirit:value>
+ </spirit:modelParameter>
+ <spirit:modelParameter spirit:dataType="STRING">
+ <spirit:name>C_CLKOUT2_2</spirit:name>
+ <spirit:value spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C_CLKOUT2_2" spirit:order="411">0000</spirit:value>
+ </spirit:modelParameter>
+ <spirit:modelParameter spirit:dataType="STRING">
+ <spirit:name>C_CLKOUT3_1</spirit:name>
+ <spirit:value spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C_CLKOUT3_1" spirit:order="410">0000</spirit:value>
+ </spirit:modelParameter>
+ <spirit:modelParameter spirit:dataType="STRING">
+ <spirit:name>C_CLKOUT3_2</spirit:name>
+ <spirit:value spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C_CLKOUT3_2" spirit:order="411">0000</spirit:value>
+ </spirit:modelParameter>
+ <spirit:modelParameter spirit:dataType="STRING">
+ <spirit:name>C_CLKOUT4_1</spirit:name>
+ <spirit:value spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C_CLKOUT4_1" spirit:order="410">0000</spirit:value>
+ </spirit:modelParameter>
+ <spirit:modelParameter spirit:dataType="STRING">
+ <spirit:name>C_CLKOUT4_2</spirit:name>
+ <spirit:value spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C_CLKOUT4_2" spirit:order="411">0000</spirit:value>
+ </spirit:modelParameter>
+ <spirit:modelParameter spirit:dataType="STRING">
+ <spirit:name>C_CLKOUT5_1</spirit:name>
+ <spirit:value spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C_CLKOUT5_1" spirit:order="410">0000</spirit:value>
+ </spirit:modelParameter>
+ <spirit:modelParameter spirit:dataType="STRING">
+ <spirit:name>C_CLKOUT5_2</spirit:name>
+ <spirit:value spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C_CLKOUT5_2" spirit:order="411">0000</spirit:value>
+ </spirit:modelParameter>
+ <spirit:modelParameter spirit:dataType="STRING">
+ <spirit:name>C_CLKOUT6_1</spirit:name>
+ <spirit:value spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C_CLKOUT6_1" spirit:order="410">0000</spirit:value>
+ </spirit:modelParameter>
+ <spirit:modelParameter spirit:dataType="STRING">
+ <spirit:name>C_CLKOUT6_2</spirit:name>
+ <spirit:value spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C_CLKOUT6_2" spirit:order="411">0000</spirit:value>
+ </spirit:modelParameter>
+ <spirit:modelParameter spirit:dataType="STRING">
+ <spirit:name>C_CLKFBOUT_1</spirit:name>
+ <spirit:value spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C_CLKFBOUT_1" spirit:order="410">0000</spirit:value>
+ </spirit:modelParameter>
+ <spirit:modelParameter spirit:dataType="STRING">
+ <spirit:name>C_CLKFBOUT_2</spirit:name>
+ <spirit:value spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C_CLKFBOUT_2" spirit:order="411">0000</spirit:value>
+ </spirit:modelParameter>
+ <spirit:modelParameter spirit:dataType="STRING">
+ <spirit:name>C_DIVCLK</spirit:name>
+ <spirit:value spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C_DIVCLK" spirit:order="411">0000</spirit:value>
+ </spirit:modelParameter>
+ <spirit:modelParameter spirit:dataType="STRING">
+ <spirit:name>C_LOCK_1</spirit:name>
+ <spirit:value spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C_LOCK_1" spirit:order="411">0000</spirit:value>
+ </spirit:modelParameter>
+ <spirit:modelParameter spirit:dataType="STRING">
+ <spirit:name>C_LOCK_2</spirit:name>
+ <spirit:value spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C_LOCK_2" spirit:order="411">0000</spirit:value>
+ </spirit:modelParameter>
+ <spirit:modelParameter spirit:dataType="STRING">
+ <spirit:name>C_LOCK_3</spirit:name>
+ <spirit:value spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C_LOCK_3" spirit:order="411">0000</spirit:value>
+ </spirit:modelParameter>
+ <spirit:modelParameter spirit:dataType="STRING">
+ <spirit:name>C_FILTER_1</spirit:name>
+ <spirit:value spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C_FILTER_1" spirit:order="411">0000</spirit:value>
+ </spirit:modelParameter>
+ <spirit:modelParameter spirit:dataType="STRING">
+ <spirit:name>C_FILTER_2</spirit:name>
+ <spirit:value spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C_FILTER_2" spirit:order="411">0000</spirit:value>
+ </spirit:modelParameter>
+ <spirit:modelParameter spirit:dataType="STRING">
+ <spirit:name>C_DIVIDE1_AUTO</spirit:name>
+ <spirit:value spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C_DIVIDE1_AUTO" spirit:order="411">1</spirit:value>
+ </spirit:modelParameter>
+ <spirit:modelParameter spirit:dataType="STRING">
+ <spirit:name>C_DIVIDE2_AUTO</spirit:name>
+ <spirit:value spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C_DIVIDE2_AUTO" spirit:order="411">0.0273972602739726</spirit:value>
+ </spirit:modelParameter>
+ <spirit:modelParameter spirit:dataType="STRING">
+ <spirit:name>C_DIVIDE3_AUTO</spirit:name>
+ <spirit:value spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C_DIVIDE3_AUTO" spirit:order="411">0.0273972602739726</spirit:value>
+ </spirit:modelParameter>
+ <spirit:modelParameter spirit:dataType="STRING">
+ <spirit:name>C_DIVIDE4_AUTO</spirit:name>
+ <spirit:value spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C_DIVIDE4_AUTO" spirit:order="411">0.0273972602739726</spirit:value>
+ </spirit:modelParameter>
+ <spirit:modelParameter spirit:dataType="STRING">
+ <spirit:name>C_DIVIDE5_AUTO</spirit:name>
+ <spirit:value spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C_DIVIDE5_AUTO" spirit:order="411">0.0273972602739726</spirit:value>
+ </spirit:modelParameter>
+ <spirit:modelParameter spirit:dataType="STRING">
+ <spirit:name>C_DIVIDE6_AUTO</spirit:name>
+ <spirit:value spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C_DIVIDE6_AUTO" spirit:order="411">0.0273972602739726</spirit:value>
+ </spirit:modelParameter>
+ <spirit:modelParameter spirit:dataType="STRING">
+ <spirit:name>C_DIVIDE7_AUTO</spirit:name>
+ <spirit:value spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C_DIVIDE7_AUTO" spirit:order="411">0.0273972602739726</spirit:value>
+ </spirit:modelParameter>
+ <spirit:modelParameter spirit:dataType="STRING">
+ <spirit:name>C_PLLBUFGCEDIV</spirit:name>
+ <spirit:value spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C_PLLBUFGCEDIV" spirit:order="411">false</spirit:value>
+ </spirit:modelParameter>
+ <spirit:modelParameter spirit:dataType="STRING">
+ <spirit:name>C_MMCMBUFGCEDIV</spirit:name>
+ <spirit:value spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C_MMCMBUFGCEDIV" spirit:order="411">false</spirit:value>
+ </spirit:modelParameter>
+ <spirit:modelParameter spirit:dataType="STRING">
+ <spirit:name>C_PLLBUFGCEDIV1</spirit:name>
+ <spirit:value spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C_PLLBUFGCEDIV1" spirit:order="411">false</spirit:value>
+ </spirit:modelParameter>
+ <spirit:modelParameter spirit:dataType="STRING">
+ <spirit:name>C_PLLBUFGCEDIV2</spirit:name>
+ <spirit:value spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C_PLLBUFGCEDIV2" spirit:order="411">false</spirit:value>
+ </spirit:modelParameter>
+ <spirit:modelParameter spirit:dataType="STRING">
+ <spirit:name>C_PLLBUFGCEDIV3</spirit:name>
+ <spirit:value spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C_PLLBUFGCEDIV3" spirit:order="411">false</spirit:value>
+ </spirit:modelParameter>
+ <spirit:modelParameter spirit:dataType="STRING">
+ <spirit:name>C_PLLBUFGCEDIV4</spirit:name>
+ <spirit:value spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C_PLLBUFGCEDIV4" spirit:order="411">false</spirit:value>
+ </spirit:modelParameter>
+ <spirit:modelParameter spirit:dataType="STRING">
+ <spirit:name>C_MMCMBUFGCEDIV1</spirit:name>
+ <spirit:value spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C_MMCMBUFGCEDIV1" spirit:order="411">false</spirit:value>
+ </spirit:modelParameter>
+ <spirit:modelParameter spirit:dataType="STRING">
+ <spirit:name>C_MMCMBUFGCEDIV2</spirit:name>
+ <spirit:value spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C_MMCMBUFGCEDIV2" spirit:order="411">false</spirit:value>
+ </spirit:modelParameter>
+ <spirit:modelParameter spirit:dataType="STRING">
+ <spirit:name>C_MMCMBUFGCEDIV3</spirit:name>
+ <spirit:value spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C_MMCMBUFGCEDIV3" spirit:order="411">false</spirit:value>
+ </spirit:modelParameter>
+ <spirit:modelParameter spirit:dataType="STRING">
+ <spirit:name>C_MMCMBUFGCEDIV4</spirit:name>
+ <spirit:value spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C_MMCMBUFGCEDIV4" spirit:order="411">false</spirit:value>
+ </spirit:modelParameter>
+ <spirit:modelParameter spirit:dataType="STRING">
+ <spirit:name>C_MMCMBUFGCEDIV5</spirit:name>
+ <spirit:value spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C_MMCMBUFGCEDIV5" spirit:order="411">false</spirit:value>
+ </spirit:modelParameter>
+ <spirit:modelParameter spirit:dataType="STRING">
+ <spirit:name>C_MMCMBUFGCEDIV6</spirit:name>
+ <spirit:value spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C_MMCMBUFGCEDIV6" spirit:order="411">false</spirit:value>
+ </spirit:modelParameter>
+ <spirit:modelParameter spirit:dataType="STRING">
+ <spirit:name>C_MMCMBUFGCEDIV7</spirit:name>
+ <spirit:value spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C_MMCMBUFGCEDIV7" spirit:order="411">false</spirit:value>
+ </spirit:modelParameter>
+ <spirit:modelParameter spirit:dataType="STRING">
+ <spirit:name>C_CLKOUT1_MATCHED_ROUTING</spirit:name>
+ <spirit:value spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C_CLKOUT1_MATCHED_ROUTING" spirit:order="411">false</spirit:value>
+ </spirit:modelParameter>
+ <spirit:modelParameter spirit:dataType="STRING">
+ <spirit:name>C_CLKOUT2_MATCHED_ROUTING</spirit:name>
+ <spirit:value spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C_CLKOUT2_MATCHED_ROUTING" spirit:order="411">false</spirit:value>
+ </spirit:modelParameter>
+ <spirit:modelParameter spirit:dataType="STRING">
+ <spirit:name>C_CLKOUT3_MATCHED_ROUTING</spirit:name>
+ <spirit:value spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C_CLKOUT3_MATCHED_ROUTING" spirit:order="411">false</spirit:value>
+ </spirit:modelParameter>
+ <spirit:modelParameter spirit:dataType="STRING">
+ <spirit:name>C_CLKOUT4_MATCHED_ROUTING</spirit:name>
+ <spirit:value spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C_CLKOUT4_MATCHED_ROUTING" spirit:order="411">false</spirit:value>
+ </spirit:modelParameter>
+ <spirit:modelParameter spirit:dataType="STRING">
+ <spirit:name>C_CLKOUT5_MATCHED_ROUTING</spirit:name>
+ <spirit:value spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C_CLKOUT5_MATCHED_ROUTING" spirit:order="411">false</spirit:value>
+ </spirit:modelParameter>
+ <spirit:modelParameter spirit:dataType="STRING">
+ <spirit:name>C_CLKOUT6_MATCHED_ROUTING</spirit:name>
+ <spirit:value spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C_CLKOUT6_MATCHED_ROUTING" spirit:order="411">false</spirit:value>
+ </spirit:modelParameter>
+ <spirit:modelParameter spirit:dataType="STRING">
+ <spirit:name>C_CLKOUT7_MATCHED_ROUTING</spirit:name>
+ <spirit:value spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C_CLKOUT7_MATCHED_ROUTING" spirit:order="411">false</spirit:value>
+ </spirit:modelParameter>
+ <spirit:modelParameter spirit:dataType="STRING">
+ <spirit:name>C_CLKOUT0_ACTUAL_FREQ</spirit:name>
+ <spirit:value spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C_CLKOUT0_ACTUAL_FREQ" spirit:order="711">25.00000</spirit:value>
+ </spirit:modelParameter>
+ <spirit:modelParameter spirit:dataType="STRING">
+ <spirit:name>C_CLKOUT1_ACTUAL_FREQ</spirit:name>
+ <spirit:value spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C_CLKOUT1_ACTUAL_FREQ" spirit:order="712">100.000</spirit:value>
+ </spirit:modelParameter>
+ <spirit:modelParameter spirit:dataType="STRING">
+ <spirit:name>C_CLKOUT2_ACTUAL_FREQ</spirit:name>
+ <spirit:value spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C_CLKOUT2_ACTUAL_FREQ" spirit:order="713">100.000</spirit:value>
+ </spirit:modelParameter>
+ <spirit:modelParameter spirit:dataType="STRING">
+ <spirit:name>C_CLKOUT3_ACTUAL_FREQ</spirit:name>
+ <spirit:value spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C_CLKOUT3_ACTUAL_FREQ" spirit:order="714">100.000</spirit:value>
+ </spirit:modelParameter>
+ <spirit:modelParameter spirit:dataType="STRING">
+ <spirit:name>C_CLKOUT4_ACTUAL_FREQ</spirit:name>
+ <spirit:value spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C_CLKOUT4_ACTUAL_FREQ" spirit:order="715">100.000</spirit:value>
+ </spirit:modelParameter>
+ <spirit:modelParameter spirit:dataType="STRING">
+ <spirit:name>C_CLKOUT5_ACTUAL_FREQ</spirit:name>
+ <spirit:value spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C_CLKOUT5_ACTUAL_FREQ" spirit:order="716">100.000</spirit:value>
+ </spirit:modelParameter>
+ <spirit:modelParameter spirit:dataType="STRING">
+ <spirit:name>C_CLKOUT6_ACTUAL_FREQ</spirit:name>
+ <spirit:value spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C_CLKOUT6_ACTUAL_FREQ" spirit:order="717">100.000</spirit:value>
+ </spirit:modelParameter>
+ <spirit:modelParameter spirit:dataType="REAL">
+ <spirit:name>C_M_MAX</spirit:name>
+ <spirit:value spirit:format="float" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C_M_MAX" spirit:order="403">64.000</spirit:value>
+ </spirit:modelParameter>
+ <spirit:modelParameter spirit:dataType="REAL">
+ <spirit:name>C_M_MIN</spirit:name>
+ <spirit:value spirit:format="float" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C_M_MIN" spirit:order="403">2.000</spirit:value>
+ </spirit:modelParameter>
+ <spirit:modelParameter spirit:dataType="REAL">
+ <spirit:name>C_D_MAX</spirit:name>
+ <spirit:value spirit:format="float" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C_D_MAX" spirit:order="403">80.000</spirit:value>
+ </spirit:modelParameter>
+ <spirit:modelParameter spirit:dataType="REAL">
+ <spirit:name>C_D_MIN</spirit:name>
+ <spirit:value spirit:format="float" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C_D_MIN" spirit:order="403">1.000</spirit:value>
+ </spirit:modelParameter>
+ <spirit:modelParameter spirit:dataType="REAL">
+ <spirit:name>C_O_MAX</spirit:name>
+ <spirit:value spirit:format="float" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C_O_MAX" spirit:order="403">128.000</spirit:value>
+ </spirit:modelParameter>
+ <spirit:modelParameter spirit:dataType="REAL">
+ <spirit:name>C_O_MIN</spirit:name>
+ <spirit:value spirit:format="float" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C_O_MIN" spirit:order="403">1.000</spirit:value>
+ </spirit:modelParameter>
+ <spirit:modelParameter spirit:dataType="REAL">
+ <spirit:name>C_VCO_MIN</spirit:name>
+ <spirit:value spirit:format="float" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C_VCO_MIN" spirit:order="403">600.000</spirit:value>
+ </spirit:modelParameter>
+ <spirit:modelParameter spirit:dataType="REAL">
+ <spirit:name>C_VCO_MAX</spirit:name>
+ <spirit:value spirit:format="float" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C_VCO_MAX" spirit:order="403">1200.000</spirit:value>
+ </spirit:modelParameter>
+ </spirit:modelParameters>
+ </spirit:model>
+ <spirit:choices>
+ <spirit:choice>
+ <spirit:name>choice_list_1d3de01d</spirit:name>
+ <spirit:enumeration>WAVEFORM</spirit:enumeration>
+ <spirit:enumeration>LATENCY</spirit:enumeration>
+ </spirit:choice>
+ <spirit:choice>
+ <spirit:name>choice_list_876bfc32</spirit:name>
+ <spirit:enumeration>UI</spirit:enumeration>
+ <spirit:enumeration>PS</spirit:enumeration>
+ </spirit:choice>
+ <spirit:choice>
+ <spirit:name>choice_list_a9bdfce0</spirit:name>
+ <spirit:enumeration>LOW</spirit:enumeration>
+ <spirit:enumeration>HIGH</spirit:enumeration>
+ <spirit:enumeration>OPTIMIZED</spirit:enumeration>
+ </spirit:choice>
+ <spirit:choice>
+ <spirit:name>choice_list_ac75ef1e</spirit:name>
+ <spirit:enumeration>Custom</spirit:enumeration>
+ </spirit:choice>
+ <spirit:choice>
+ <spirit:name>choice_list_b9d38208</spirit:name>
+ <spirit:enumeration>CLKFBOUT</spirit:enumeration>
+ <spirit:enumeration>CLKOUT0</spirit:enumeration>
+ </spirit:choice>
+ <spirit:choice>
+ <spirit:name>choice_list_e099fe6c</spirit:name>
+ <spirit:enumeration>MMCM</spirit:enumeration>
+ <spirit:enumeration>PLL</spirit:enumeration>
+ </spirit:choice>
+ <spirit:choice>
+ <spirit:name>choice_pairs_035ca1c3</spirit:name>
+ <spirit:enumeration spirit:text="SYSTEM SYNCHRONOUS">SYSTEM_SYNCHRONOUS</spirit:enumeration>
+ <spirit:enumeration spirit:text="SOURCE SYNCHRONOUS">SOURCE_SYNCHRONOUS</spirit:enumeration>
+ <spirit:enumeration spirit:text="INTERNAL">INTERNAL</spirit:enumeration>
+ <spirit:enumeration spirit:text="EXTERNAL">EXTERNAL</spirit:enumeration>
+ </spirit:choice>
+ <spirit:choice>
+ <spirit:name>choice_pairs_0920eb1b</spirit:name>
+ <spirit:enumeration spirit:text="Custom">Custom</spirit:enumeration>
+ <spirit:enumeration spirit:text="sys diff clock">sys_diff_clock</spirit:enumeration>
+ </spirit:choice>
+ <spirit:choice>
+ <spirit:name>choice_pairs_11d71346</spirit:name>
+ <spirit:enumeration spirit:text="Single ended clock capable pin">Single_ended_clock_capable_pin</spirit:enumeration>
+ <spirit:enumeration spirit:text="Differential clock capable pin">Differential_clock_capable_pin</spirit:enumeration>
+ <spirit:enumeration spirit:text="Global buffer">Global_buffer</spirit:enumeration>
+ <spirit:enumeration spirit:text="No buffer">No_buffer</spirit:enumeration>
+ </spirit:choice>
+ <spirit:choice>
+ <spirit:name>choice_pairs_15c806d5</spirit:name>
+ <spirit:enumeration spirit:text="Automatic Control On-Chip">FDBK_AUTO</spirit:enumeration>
+ <spirit:enumeration spirit:text="Automatic Control Off-Chip">FDBK_AUTO_OFFCHIP</spirit:enumeration>
+ <spirit:enumeration spirit:text="User-Controlled On-Chip">FDBK_ONCHIP</spirit:enumeration>
+ <spirit:enumeration spirit:text="User-Controlled Off-Chip">FDBK_OFFCHIP</spirit:enumeration>
+ </spirit:choice>
+ <spirit:choice>
+ <spirit:name>choice_pairs_340369e0</spirit:name>
+ <spirit:enumeration spirit:text="Custom">Custom</spirit:enumeration>
+ <spirit:enumeration spirit:text="sys clock">sys_clock</spirit:enumeration>
+ <spirit:enumeration spirit:text="sys diff clock">sys_diff_clock</spirit:enumeration>
+ </spirit:choice>
+ <spirit:choice>
+ <spirit:name>choice_pairs_3c2d3ec7</spirit:name>
+ <spirit:enumeration spirit:text="Single-ended">SINGLE</spirit:enumeration>
+ <spirit:enumeration spirit:text="Differential">DIFF</spirit:enumeration>
+ </spirit:choice>
+ <spirit:choice>
+ <spirit:name>choice_pairs_502d9f23</spirit:name>
+ <spirit:enumeration spirit:text="ZHOLD">ZHOLD</spirit:enumeration>
+ <spirit:enumeration spirit:text="EXTERNAL">EXTERNAL</spirit:enumeration>
+ <spirit:enumeration spirit:text="INTERNAL">INTERNAL</spirit:enumeration>
+ <spirit:enumeration spirit:text="BUF IN">BUF_IN</spirit:enumeration>
+ </spirit:choice>
+ <spirit:choice>
+ <spirit:name>choice_pairs_66e4c81f</spirit:name>
+ <spirit:enumeration spirit:text="BUFG">BUFG</spirit:enumeration>
+ <spirit:enumeration spirit:text="BUFH">BUFH</spirit:enumeration>
+ <spirit:enumeration spirit:text="BUFGCE">BUFGCE</spirit:enumeration>
+ <spirit:enumeration spirit:text="BUFHCE">BUFHCE</spirit:enumeration>
+ <spirit:enumeration spirit:text="No buffer">No_buffer</spirit:enumeration>
+ </spirit:choice>
+ <spirit:choice>
+ <spirit:name>choice_pairs_77d3d587</spirit:name>
+ <spirit:enumeration spirit:text="MMCM">MMCM</spirit:enumeration>
+ <spirit:enumeration spirit:text="PLL">PLL</spirit:enumeration>
+ <spirit:enumeration spirit:text="BUFGCE DIV">BUFGCE_DIV</spirit:enumeration>
+ </spirit:choice>
+ <spirit:choice>
+ <spirit:name>choice_pairs_8b28f1f7</spirit:name>
+ <spirit:enumeration spirit:text="AXI4Lite">Enable_AXI</spirit:enumeration>
+ <spirit:enumeration spirit:text="DRP">Enable_DRP</spirit:enumeration>
+ </spirit:choice>
+ <spirit:choice>
+ <spirit:name>choice_pairs_8eea9b32</spirit:name>
+ <spirit:enumeration spirit:text="Units MHz">Units_MHz</spirit:enumeration>
+ <spirit:enumeration spirit:text="Units ns">Units_ns</spirit:enumeration>
+ </spirit:choice>
+ <spirit:choice>
+ <spirit:name>choice_pairs_a4fbc00c</spirit:name>
+ <spirit:enumeration spirit:text="Active High">ACTIVE_HIGH</spirit:enumeration>
+ <spirit:enumeration spirit:text="Active Low">ACTIVE_LOW</spirit:enumeration>
+ </spirit:choice>
+ <spirit:choice>
+ <spirit:name>choice_pairs_a8642b4c</spirit:name>
+ <spirit:enumeration spirit:text="Balanced">No_Jitter</spirit:enumeration>
+ <spirit:enumeration spirit:text="Minimize Output Jitter">Min_O_Jitter</spirit:enumeration>
+ <spirit:enumeration spirit:text="Maximize Input Jitter filtering">Max_I_Jitter</spirit:enumeration>
+ </spirit:choice>
+ <spirit:choice>
+ <spirit:name>choice_pairs_c5ef7212</spirit:name>
+ <spirit:enumeration spirit:text="Units UI">Units_UI</spirit:enumeration>
+ <spirit:enumeration spirit:text="Units ps">Units_ps</spirit:enumeration>
+ </spirit:choice>
+ <spirit:choice>
+ <spirit:name>choice_pairs_e1c87518</spirit:name>
+ <spirit:enumeration spirit:text="Primary Clock">REL_PRIMARY</spirit:enumeration>
+ <spirit:enumeration spirit:text="Secondary Clock">REL_SECONDARY</spirit:enumeration>
+ </spirit:choice>
+ <spirit:choice>
+ <spirit:name>choice_pairs_f4e10086</spirit:name>
+ <spirit:enumeration spirit:text="CENTER HIGH">CENTER_HIGH</spirit:enumeration>
+ <spirit:enumeration spirit:text="CENTER LOW">CENTER_LOW</spirit:enumeration>
+ <spirit:enumeration spirit:text="DOWN HIGH">DOWN_HIGH</spirit:enumeration>
+ <spirit:enumeration spirit:text="DOWN LOW">DOWN_LOW</spirit:enumeration>
+ </spirit:choice>
+ <spirit:choice>
+ <spirit:name>choice_pairs_f669c2f5</spirit:name>
+ <spirit:enumeration spirit:text="Frequency">frequency</spirit:enumeration>
+ <spirit:enumeration spirit:text="Time">Time</spirit:enumeration>
+ </spirit:choice>
+ </spirit:choices>
+ <spirit:fileSets>
+ <spirit:fileSet>
+ <spirit:name>xilinx_vhdlinstantiationtemplate_view_fileset</spirit:name>
+ <spirit:file>
+ <spirit:name>clk_wiz_0.vho</spirit:name>
+ <spirit:userFileType>vhdlTemplate</spirit:userFileType>
+ </spirit:file>
+ </spirit:fileSet>
+ <spirit:fileSet>
+ <spirit:name>xilinx_anylanguagesynthesis_view_fileset</spirit:name>
+ <spirit:file>
+ <spirit:name>clk_wiz_0.xdc</spirit:name>
+ <spirit:userFileType>xdc</spirit:userFileType>
+ <spirit:define>
+ <spirit:name>processing_order</spirit:name>
+ <spirit:value>early</spirit:value>
+ </spirit:define>
+ </spirit:file>
+ <spirit:file>
+ <spirit:name>clk_wiz_0_ooc.xdc</spirit:name>
+ <spirit:userFileType>xdc</spirit:userFileType>
+ <spirit:userFileType>USED_IN_implementation</spirit:userFileType>
+ <spirit:userFileType>USED_IN_out_of_context</spirit:userFileType>
+ <spirit:userFileType>USED_IN_synthesis</spirit:userFileType>
+ </spirit:file>
+ <spirit:file>
+ <spirit:name>mmcm_pll_drp_func_7s_mmcm.vh</spirit:name>
+ <spirit:fileType>verilogSource</spirit:fileType>
+ <spirit:isIncludeFile>true</spirit:isIncludeFile>
+ <spirit:logicalName>clk_wiz_v6_0_11</spirit:logicalName>
+ </spirit:file>
+ <spirit:file>
+ <spirit:name>mmcm_pll_drp_func_7s_pll.vh</spirit:name>
+ <spirit:fileType>verilogSource</spirit:fileType>
+ <spirit:isIncludeFile>true</spirit:isIncludeFile>
+ <spirit:logicalName>clk_wiz_v6_0_11</spirit:logicalName>
+ </spirit:file>
+ <spirit:file>
+ <spirit:name>mmcm_pll_drp_func_us_mmcm.vh</spirit:name>
+ <spirit:fileType>verilogSource</spirit:fileType>
+ <spirit:isIncludeFile>true</spirit:isIncludeFile>
+ <spirit:logicalName>clk_wiz_v6_0_11</spirit:logicalName>
+ </spirit:file>
+ <spirit:file>
+ <spirit:name>mmcm_pll_drp_func_us_pll.vh</spirit:name>
+ <spirit:fileType>verilogSource</spirit:fileType>
+ <spirit:isIncludeFile>true</spirit:isIncludeFile>
+ <spirit:logicalName>clk_wiz_v6_0_11</spirit:logicalName>
+ </spirit:file>
+ <spirit:file>
+ <spirit:name>mmcm_pll_drp_func_us_plus_pll.vh</spirit:name>
+ <spirit:fileType>verilogSource</spirit:fileType>
+ <spirit:isIncludeFile>true</spirit:isIncludeFile>
+ <spirit:logicalName>clk_wiz_v6_0_11</spirit:logicalName>
+ </spirit:file>
+ <spirit:file>
+ <spirit:name>mmcm_pll_drp_func_us_plus_mmcm.vh</spirit:name>
+ <spirit:fileType>verilogSource</spirit:fileType>
+ <spirit:isIncludeFile>true</spirit:isIncludeFile>
+ <spirit:logicalName>clk_wiz_v6_0_11</spirit:logicalName>
+ </spirit:file>
+ <spirit:file>
+ <spirit:name>clk_wiz_0_clk_wiz.v</spirit:name>
+ <spirit:fileType>verilogSource</spirit:fileType>
+ </spirit:file>
+ </spirit:fileSet>
+ <spirit:fileSet>
+ <spirit:name>xilinx_anylanguagesynthesiswrapper_view_fileset</spirit:name>
+ <spirit:file>
+ <spirit:name>clk_wiz_0.v</spirit:name>
+ <spirit:fileType>verilogSource</spirit:fileType>
+ </spirit:file>
+ </spirit:fileSet>
+ <spirit:fileSet>
+ <spirit:name>xilinx_anylanguagebehavioralsimulation_view_fileset</spirit:name>
+ <spirit:file>
+ <spirit:name>mmcm_pll_drp_func_7s_mmcm.vh</spirit:name>
+ <spirit:fileType>verilogSource</spirit:fileType>
+ <spirit:userFileType>USED_IN_ipstatic</spirit:userFileType>
+ <spirit:isIncludeFile>true</spirit:isIncludeFile>
+ <spirit:logicalName>clk_wiz_v6_0_11</spirit:logicalName>
+ </spirit:file>
+ <spirit:file>
+ <spirit:name>mmcm_pll_drp_func_7s_pll.vh</spirit:name>
+ <spirit:fileType>verilogSource</spirit:fileType>
+ <spirit:userFileType>USED_IN_ipstatic</spirit:userFileType>
+ <spirit:isIncludeFile>true</spirit:isIncludeFile>
+ <spirit:logicalName>clk_wiz_v6_0_11</spirit:logicalName>
+ </spirit:file>
+ <spirit:file>
+ <spirit:name>mmcm_pll_drp_func_us_mmcm.vh</spirit:name>
+ <spirit:fileType>verilogSource</spirit:fileType>
+ <spirit:userFileType>USED_IN_ipstatic</spirit:userFileType>
+ <spirit:isIncludeFile>true</spirit:isIncludeFile>
+ <spirit:logicalName>clk_wiz_v6_0_11</spirit:logicalName>
+ </spirit:file>
+ <spirit:file>
+ <spirit:name>mmcm_pll_drp_func_us_pll.vh</spirit:name>
+ <spirit:fileType>verilogSource</spirit:fileType>
+ <spirit:userFileType>USED_IN_ipstatic</spirit:userFileType>
+ <spirit:isIncludeFile>true</spirit:isIncludeFile>
+ <spirit:logicalName>clk_wiz_v6_0_11</spirit:logicalName>
+ </spirit:file>
+ <spirit:file>
+ <spirit:name>mmcm_pll_drp_func_us_plus_pll.vh</spirit:name>
+ <spirit:fileType>verilogSource</spirit:fileType>
+ <spirit:userFileType>USED_IN_ipstatic</spirit:userFileType>
+ <spirit:isIncludeFile>true</spirit:isIncludeFile>
+ <spirit:logicalName>clk_wiz_v6_0_11</spirit:logicalName>
+ </spirit:file>
+ <spirit:file>
+ <spirit:name>mmcm_pll_drp_func_us_plus_mmcm.vh</spirit:name>
+ <spirit:fileType>verilogSource</spirit:fileType>
+ <spirit:userFileType>USED_IN_ipstatic</spirit:userFileType>
+ <spirit:isIncludeFile>true</spirit:isIncludeFile>
+ <spirit:logicalName>clk_wiz_v6_0_11</spirit:logicalName>
+ </spirit:file>
+ <spirit:file>
+ <spirit:name>clk_wiz_0_clk_wiz.v</spirit:name>
+ <spirit:fileType>verilogSource</spirit:fileType>
+ </spirit:file>
+ </spirit:fileSet>
+ <spirit:fileSet>
+ <spirit:name>xilinx_anylanguagesimulationwrapper_view_fileset</spirit:name>
+ <spirit:file>
+ <spirit:name>clk_wiz_0.v</spirit:name>
+ <spirit:fileType>verilogSource</spirit:fileType>
+ </spirit:file>
+ </spirit:fileSet>
+ <spirit:fileSet>
+ <spirit:name>xilinx_implementation_view_fileset</spirit:name>
+ <spirit:file>
+ <spirit:name>clk_wiz_0_board.xdc</spirit:name>
+ <spirit:userFileType>xdc</spirit:userFileType>
+ <spirit:userFileType>USED_IN_board</spirit:userFileType>
+ <spirit:userFileType>USED_IN_implementation</spirit:userFileType>
+ <spirit:userFileType>USED_IN_synthesis</spirit:userFileType>
+ </spirit:file>
+ </spirit:fileSet>
+ <spirit:fileSet>
+ <spirit:name>xilinx_versioninformation_view_fileset</spirit:name>
+ <spirit:file>
+ <spirit:name>doc/clk_wiz_v6_0_changelog.txt</spirit:name>
+ <spirit:userFileType>text</spirit:userFileType>
+ </spirit:file>
+ </spirit:fileSet>
+ <spirit:fileSet>
+ <spirit:name>xilinx_externalfiles_view_fileset</spirit:name>
+ <spirit:file>
+ <spirit:name>clk_wiz_0.dcp</spirit:name>
+ <spirit:userFileType>dcp</spirit:userFileType>
+ <spirit:userFileType>USED_IN_implementation</spirit:userFileType>
+ <spirit:userFileType>USED_IN_synthesis</spirit:userFileType>
+ <spirit:logicalName>xil_defaultlib</spirit:logicalName>
+ </spirit:file>
+ <spirit:file>
+ <spirit:name>clk_wiz_0_stub.v</spirit:name>
+ <spirit:fileType>verilogSource</spirit:fileType>
+ <spirit:userFileType>USED_IN_synth_blackbox_stub</spirit:userFileType>
+ <spirit:logicalName>xil_defaultlib</spirit:logicalName>
+ </spirit:file>
+ <spirit:file>
+ <spirit:name>clk_wiz_0_stub.vhdl</spirit:name>
+ <spirit:fileType>vhdlSource</spirit:fileType>
+ <spirit:userFileType>USED_IN_synth_blackbox_stub</spirit:userFileType>
+ <spirit:logicalName>xil_defaultlib</spirit:logicalName>
+ </spirit:file>
+ <spirit:file>
+ <spirit:name>clk_wiz_0_sim_netlist.v</spirit:name>
+ <spirit:fileType>verilogSource</spirit:fileType>
+ <spirit:userFileType>USED_IN_simulation</spirit:userFileType>
+ <spirit:userFileType>USED_IN_single_language</spirit:userFileType>
+ <spirit:logicalName>xil_defaultlib</spirit:logicalName>
+ </spirit:file>
+ <spirit:file>
+ <spirit:name>clk_wiz_0_sim_netlist.vhdl</spirit:name>
+ <spirit:fileType>vhdlSource</spirit:fileType>
+ <spirit:userFileType>USED_IN_simulation</spirit:userFileType>
+ <spirit:userFileType>USED_IN_single_language</spirit:userFileType>
+ <spirit:logicalName>xil_defaultlib</spirit:logicalName>
+ </spirit:file>
+ </spirit:fileSet>
+ </spirit:fileSets>
+ <spirit:description>The Clocking Wizard creates an HDL file (Verilog or VHDL) that contains a clocking circuit customized to the user's clocking requirements.</spirit:description>
+ <spirit:parameters>
+ <spirit:parameter>
+ <spirit:name>Component_Name</spirit:name>
+ <spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.Component_Name" spirit:order="1">clk_wiz_0</spirit:value>
+ </spirit:parameter>
+ <spirit:parameter>
+ <spirit:name>USER_CLK_FREQ0</spirit:name>
+ <spirit:displayName>User Frequency(MHz)</spirit:displayName>
+ <spirit:value spirit:format="float" spirit:resolve="user" spirit:id="PARAM_VALUE.USER_CLK_FREQ0" spirit:order="15200" spirit:minimum="1" spirit:maximum="300">100.0</spirit:value>
+ </spirit:parameter>
+ <spirit:parameter>
+ <spirit:name>USER_CLK_FREQ1</spirit:name>
+ <spirit:displayName>User Frequency(MHz)</spirit:displayName>
+ <spirit:value spirit:format="float" spirit:resolve="user" spirit:id="PARAM_VALUE.USER_CLK_FREQ1" spirit:order="15200" spirit:minimum="1" spirit:maximum="300">100.0</spirit:value>
+ </spirit:parameter>
+ <spirit:parameter>
+ <spirit:name>USER_CLK_FREQ2</spirit:name>
+ <spirit:displayName>User Frequency(MHz)</spirit:displayName>
+ <spirit:value spirit:format="float" spirit:resolve="user" spirit:id="PARAM_VALUE.USER_CLK_FREQ2" spirit:order="15200" spirit:minimum="1" spirit:maximum="300">100.0</spirit:value>
+ </spirit:parameter>
+ <spirit:parameter>
+ <spirit:name>USER_CLK_FREQ3</spirit:name>
+ <spirit:displayName>User Frequency(MHz)</spirit:displayName>
+ <spirit:value spirit:format="float" spirit:resolve="user" spirit:id="PARAM_VALUE.USER_CLK_FREQ3" spirit:order="15200" spirit:minimum="1" spirit:maximum="300">100.0</spirit:value>
+ </spirit:parameter>
+ <spirit:parameter>
+ <spirit:name>ENABLE_CLOCK_MONITOR</spirit:name>
+ <spirit:displayName>Enable Clock Monitoring</spirit:displayName>
+ <spirit:value spirit:format="bool" spirit:resolve="user" spirit:id="PARAM_VALUE.ENABLE_CLOCK_MONITOR" spirit:order="10.1">false</spirit:value>
+ </spirit:parameter>
+ <spirit:parameter>
+ <spirit:name>OPTIMIZE_CLOCKING_STRUCTURE_EN</spirit:name>
+ <spirit:displayName>Optimize Clocking Structure</spirit:displayName>
+ <spirit:value spirit:format="bool" spirit:resolve="user" spirit:id="PARAM_VALUE.OPTIMIZE_CLOCKING_STRUCTURE_EN" spirit:order="10.1">false</spirit:value>
+ </spirit:parameter>
+ <spirit:parameter>
+ <spirit:name>ENABLE_USER_CLOCK0</spirit:name>
+ <spirit:displayName>User Clock</spirit:displayName>
+ <spirit:value spirit:format="bool" spirit:resolve="user" spirit:id="PARAM_VALUE.ENABLE_USER_CLOCK0" spirit:order="1090">false</spirit:value>
+ </spirit:parameter>
+ <spirit:parameter>
+ <spirit:name>ENABLE_USER_CLOCK1</spirit:name>
+ <spirit:displayName>User Clock</spirit:displayName>
+ <spirit:value spirit:format="bool" spirit:resolve="user" spirit:id="PARAM_VALUE.ENABLE_USER_CLOCK1" spirit:order="1090">false</spirit:value>
+ </spirit:parameter>
+ <spirit:parameter>
+ <spirit:name>ENABLE_USER_CLOCK2</spirit:name>
+ <spirit:displayName>User Clock</spirit:displayName>
+ <spirit:value spirit:format="bool" spirit:resolve="user" spirit:id="PARAM_VALUE.ENABLE_USER_CLOCK2" spirit:order="1090">false</spirit:value>
+ </spirit:parameter>
+ <spirit:parameter>
+ <spirit:name>ENABLE_USER_CLOCK3</spirit:name>
+ <spirit:displayName>User Clock</spirit:displayName>
+ <spirit:value spirit:format="bool" spirit:resolve="user" spirit:id="PARAM_VALUE.ENABLE_USER_CLOCK3" spirit:order="1090">false</spirit:value>
+ </spirit:parameter>
+ <spirit:parameter>
+ <spirit:name>Enable_PLL0</spirit:name>
+ <spirit:displayName>User Clock</spirit:displayName>
+ <spirit:value spirit:format="bool" spirit:resolve="user" spirit:id="PARAM_VALUE.Enable_PLL0" spirit:order="1090">false</spirit:value>
+ </spirit:parameter>
+ <spirit:parameter>
+ <spirit:name>Enable_PLL1</spirit:name>
+ <spirit:displayName>User Clock</spirit:displayName>
+ <spirit:value spirit:format="bool" spirit:resolve="user" spirit:id="PARAM_VALUE.Enable_PLL1" spirit:order="1090">false</spirit:value>
+ </spirit:parameter>
+ <spirit:parameter>
+ <spirit:name>REF_CLK_FREQ</spirit:name>
+ <spirit:displayName>Reference Frequency(MHz)</spirit:displayName>
+ <spirit:value spirit:format="float" spirit:resolve="user" spirit:id="PARAM_VALUE.REF_CLK_FREQ" spirit:order="15300" spirit:minimum="1" spirit:maximum="300">100.0</spirit:value>
+ </spirit:parameter>
+ <spirit:parameter>
+ <spirit:name>PRECISION</spirit:name>
+ <spirit:displayName>Tolerance(MHz)</spirit:displayName>
+ <spirit:value spirit:format="float" spirit:resolve="user" spirit:id="PARAM_VALUE.PRECISION" spirit:order="15400" spirit:minimum="1" spirit:maximum="100">1</spirit:value>
+ </spirit:parameter>
+ <spirit:parameter>
+ <spirit:name>PRIMITIVE</spirit:name>
+ <spirit:displayName>Primitive</spirit:displayName>
+ <spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.PRIMITIVE" spirit:choiceRef="choice_list_e099fe6c" spirit:order="2">MMCM</spirit:value>
+ </spirit:parameter>
+ <spirit:parameter>
+ <spirit:name>PRIMTYPE_SEL</spirit:name>
+ <spirit:displayName>Primtype Sel</spirit:displayName>
+ <spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.PRIMTYPE_SEL" spirit:order="3">mmcm_adv</spirit:value>
+ </spirit:parameter>
+ <spirit:parameter>
+ <spirit:name>CLOCK_MGR_TYPE</spirit:name>
+ <spirit:displayName>Clock Mgr Type</spirit:displayName>
+ <spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.CLOCK_MGR_TYPE" spirit:order="410">auto</spirit:value>
+ </spirit:parameter>
+ <spirit:parameter>
+ <spirit:name>USE_FREQ_SYNTH</spirit:name>
+ <spirit:value spirit:format="bool" spirit:resolve="user" spirit:id="PARAM_VALUE.USE_FREQ_SYNTH" spirit:order="6" spirit:configGroups="0 NoDisplay">true</spirit:value>
+ </spirit:parameter>
+ <spirit:parameter>
+ <spirit:name>USE_SPREAD_SPECTRUM</spirit:name>
+ <spirit:value spirit:format="bool" spirit:resolve="user" spirit:id="PARAM_VALUE.USE_SPREAD_SPECTRUM" spirit:order="7" spirit:configGroups="0 NoDisplay">false</spirit:value>
+ </spirit:parameter>
+ <spirit:parameter>
+ <spirit:name>USE_PHASE_ALIGNMENT</spirit:name>
+ <spirit:value spirit:format="bool" spirit:resolve="user" spirit:id="PARAM_VALUE.USE_PHASE_ALIGNMENT" spirit:order="8" spirit:configGroups="0 NoDisplay">true</spirit:value>
+ </spirit:parameter>
+ <spirit:parameter>
+ <spirit:name>USE_MIN_POWER</spirit:name>
+ <spirit:value spirit:format="bool" spirit:resolve="user" spirit:id="PARAM_VALUE.USE_MIN_POWER" spirit:order="9" spirit:configGroups="0 NoDisplay">false</spirit:value>
+ </spirit:parameter>
+ <spirit:parameter>
+ <spirit:name>USE_DYN_PHASE_SHIFT</spirit:name>
+ <spirit:value spirit:format="bool" spirit:resolve="user" spirit:id="PARAM_VALUE.USE_DYN_PHASE_SHIFT" spirit:order="10" spirit:configGroups="0 NoDisplay">false</spirit:value>
+ </spirit:parameter>
+ <spirit:parameter>
+ <spirit:name>USE_DYN_RECONFIG</spirit:name>
+ <spirit:value spirit:format="bool" spirit:resolve="user" spirit:id="PARAM_VALUE.USE_DYN_RECONFIG" spirit:order="11" spirit:configGroups="0 NoDisplay">false</spirit:value>
+ </spirit:parameter>
+ <spirit:parameter>
+ <spirit:name>JITTER_SEL</spirit:name>
+ <spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.JITTER_SEL" spirit:choiceRef="choice_pairs_a8642b4c" spirit:order="13" spirit:configGroups="0 NoDisplay">No_Jitter</spirit:value>
+ </spirit:parameter>
+ <spirit:parameter>
+ <spirit:name>PRIM_IN_FREQ</spirit:name>
+ <spirit:value spirit:format="float" spirit:resolve="user" spirit:id="PARAM_VALUE.PRIM_IN_FREQ" spirit:order="14.401" spirit:configGroups="0 NoDisplay">100.000</spirit:value>
+ </spirit:parameter>
+ <spirit:parameter>
+ <spirit:name>PRIM_IN_TIMEPERIOD</spirit:name>
+ <spirit:value spirit:format="float" spirit:resolve="user" spirit:id="PARAM_VALUE.PRIM_IN_TIMEPERIOD" spirit:order="14.9" spirit:configGroups="0 NoDisplay">10.000</spirit:value>
+ </spirit:parameter>
+ <spirit:parameter>
+ <spirit:name>IN_FREQ_UNITS</spirit:name>
+ <spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.IN_FREQ_UNITS" spirit:choiceRef="choice_pairs_8eea9b32" spirit:order="15" spirit:configGroups="0 NoDisplay">Units_MHz</spirit:value>
+ </spirit:parameter>
+ <spirit:parameter>
+ <spirit:name>PHASESHIFT_MODE</spirit:name>
+ <spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.PHASESHIFT_MODE" spirit:choiceRef="choice_list_1d3de01d" spirit:order="116" spirit:configGroups="0 NoDisplay">WAVEFORM</spirit:value>
+ </spirit:parameter>
+ <spirit:parameter>
+ <spirit:name>IN_JITTER_UNITS</spirit:name>
+ <spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.IN_JITTER_UNITS" spirit:choiceRef="choice_pairs_c5ef7212" spirit:order="16" spirit:configGroups="0 NoDisplay">Units_UI</spirit:value>
+ </spirit:parameter>
+ <spirit:parameter>
+ <spirit:name>RELATIVE_INCLK</spirit:name>
+ <spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.RELATIVE_INCLK" spirit:choiceRef="choice_pairs_e1c87518" spirit:order="17" spirit:configGroups="0 NoDisplay">REL_PRIMARY</spirit:value>
+ </spirit:parameter>
+ <spirit:parameter>
+ <spirit:name>USE_INCLK_SWITCHOVER</spirit:name>
+ <spirit:value spirit:format="bool" spirit:resolve="user" spirit:id="PARAM_VALUE.USE_INCLK_SWITCHOVER" spirit:order="13.9" spirit:configGroups="0 NoDisplay">false</spirit:value>
+ </spirit:parameter>
+ <spirit:parameter>
+ <spirit:name>SECONDARY_IN_FREQ</spirit:name>
+ <spirit:value spirit:format="float" spirit:resolve="user" spirit:id="PARAM_VALUE.SECONDARY_IN_FREQ" spirit:order="21.3" spirit:configGroups="0 NoDisplay">100.000</spirit:value>
+ </spirit:parameter>
+ <spirit:parameter>
+ <spirit:name>SECONDARY_IN_TIMEPERIOD</spirit:name>
+ <spirit:value spirit:format="float" spirit:resolve="user" spirit:id="PARAM_VALUE.SECONDARY_IN_TIMEPERIOD" spirit:order="21.299" spirit:configGroups="0 NoDisplay">10.000</spirit:value>
+ </spirit:parameter>
+ <spirit:parameter>
+ <spirit:name>SECONDARY_PORT</spirit:name>
+ <spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.SECONDARY_PORT" spirit:order="20" spirit:configGroups="0 NoDisplay">clk_in2</spirit:value>
+ </spirit:parameter>
+ <spirit:parameter>
+ <spirit:name>SECONDARY_SOURCE</spirit:name>
+ <spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.SECONDARY_SOURCE" spirit:choiceRef="choice_pairs_11d71346" spirit:order="21" spirit:configGroups="0 NoDisplay">Single_ended_clock_capable_pin</spirit:value>
+ </spirit:parameter>
+ <spirit:parameter>
+ <spirit:name>JITTER_OPTIONS</spirit:name>
+ <spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.JITTER_OPTIONS" spirit:choiceRef="choice_list_876bfc32" spirit:order="22" spirit:configGroups="0 NoDisplay">UI</spirit:value>
+ </spirit:parameter>
+ <spirit:parameter>
+ <spirit:name>CLKIN1_UI_JITTER</spirit:name>
+ <spirit:value spirit:format="float" spirit:resolve="user" spirit:id="PARAM_VALUE.CLKIN1_UI_JITTER" spirit:order="23" spirit:configGroups="0 NoDisplay">0.010</spirit:value>
+ </spirit:parameter>
+ <spirit:parameter>
+ <spirit:name>CLKIN2_UI_JITTER</spirit:name>
+ <spirit:value spirit:format="float" spirit:resolve="user" spirit:id="PARAM_VALUE.CLKIN2_UI_JITTER" spirit:order="24" spirit:configGroups="0 NoDisplay">0.010</spirit:value>
+ </spirit:parameter>
+ <spirit:parameter>
+ <spirit:name>PRIM_IN_JITTER</spirit:name>
+ <spirit:value spirit:format="float" spirit:resolve="user" spirit:id="PARAM_VALUE.PRIM_IN_JITTER" spirit:order="25" spirit:configGroups="0 NoDisplay">0.010</spirit:value>
+ </spirit:parameter>
+ <spirit:parameter>
+ <spirit:name>SECONDARY_IN_JITTER</spirit:name>
+ <spirit:value spirit:format="float" spirit:resolve="user" spirit:id="PARAM_VALUE.SECONDARY_IN_JITTER" spirit:order="26" spirit:configGroups="0 NoDisplay">0.010</spirit:value>
+ </spirit:parameter>
+ <spirit:parameter>
+ <spirit:name>CLKIN1_JITTER_PS</spirit:name>
+ <spirit:value spirit:format="float" spirit:resolve="user" spirit:id="PARAM_VALUE.CLKIN1_JITTER_PS" spirit:order="27" spirit:configGroups="0 NoDisplay">100.0</spirit:value>
+ </spirit:parameter>
+ <spirit:parameter>
+ <spirit:name>CLKIN2_JITTER_PS</spirit:name>
+ <spirit:value spirit:format="float" spirit:resolve="user" spirit:id="PARAM_VALUE.CLKIN2_JITTER_PS" spirit:order="28" spirit:configGroups="0 NoDisplay">100.0</spirit:value>
+ </spirit:parameter>
+ <spirit:parameter>
+ <spirit:name>CLKOUT1_USED</spirit:name>
+ <spirit:value spirit:format="bool" spirit:resolve="user" spirit:id="PARAM_VALUE.CLKOUT1_USED" spirit:order="4" spirit:configGroups="0 NoDisplay">true</spirit:value>
+ </spirit:parameter>
+ <spirit:parameter>
+ <spirit:name>CLKOUT2_USED</spirit:name>
+ <spirit:value spirit:format="bool" spirit:resolve="user" spirit:id="PARAM_VALUE.CLKOUT2_USED" spirit:order="29" spirit:configGroups="0 NoDisplay">false</spirit:value>
+ </spirit:parameter>
+ <spirit:parameter>
+ <spirit:name>CLKOUT3_USED</spirit:name>
+ <spirit:value spirit:format="bool" spirit:resolve="user" spirit:id="PARAM_VALUE.CLKOUT3_USED" spirit:order="30" spirit:configGroups="0 NoDisplay">false</spirit:value>
+ </spirit:parameter>
+ <spirit:parameter>
+ <spirit:name>CLKOUT4_USED</spirit:name>
+ <spirit:value spirit:format="bool" spirit:resolve="user" spirit:id="PARAM_VALUE.CLKOUT4_USED" spirit:order="31" spirit:configGroups="0 NoDisplay">false</spirit:value>
+ </spirit:parameter>
+ <spirit:parameter>
+ <spirit:name>CLKOUT5_USED</spirit:name>
+ <spirit:value spirit:format="bool" spirit:resolve="user" spirit:id="PARAM_VALUE.CLKOUT5_USED" spirit:order="32" spirit:configGroups="0 NoDisplay">false</spirit:value>
+ </spirit:parameter>
+ <spirit:parameter>
+ <spirit:name>CLKOUT6_USED</spirit:name>
+ <spirit:value spirit:format="bool" spirit:resolve="user" spirit:id="PARAM_VALUE.CLKOUT6_USED" spirit:order="33" spirit:configGroups="0 NoDisplay">false</spirit:value>
+ </spirit:parameter>
+ <spirit:parameter>
+ <spirit:name>CLKOUT7_USED</spirit:name>
+ <spirit:value spirit:format="bool" spirit:resolve="user" spirit:id="PARAM_VALUE.CLKOUT7_USED" spirit:order="34" spirit:configGroups="0 NoDisplay">false</spirit:value>
+ </spirit:parameter>
+ <spirit:parameter>
+ <spirit:name>NUM_OUT_CLKS</spirit:name>
+ <spirit:value spirit:format="long" spirit:resolve="user" spirit:id="PARAM_VALUE.NUM_OUT_CLKS" spirit:order="407" spirit:configGroups="0 NoDisplay" spirit:minimum="1" spirit:maximum="7" spirit:rangeType="long">1</spirit:value>
+ </spirit:parameter>
+ <spirit:parameter>
+ <spirit:name>CLK_OUT1_USE_FINE_PS_GUI</spirit:name>
+ <spirit:value spirit:format="bool" spirit:resolve="user" spirit:id="PARAM_VALUE.CLK_OUT1_USE_FINE_PS_GUI" spirit:order="36" spirit:configGroups="0 NoDisplay">false</spirit:value>
+ </spirit:parameter>
+ <spirit:parameter>
+ <spirit:name>CLK_OUT2_USE_FINE_PS_GUI</spirit:name>
+ <spirit:value spirit:format="bool" spirit:resolve="user" spirit:id="PARAM_VALUE.CLK_OUT2_USE_FINE_PS_GUI" spirit:order="37" spirit:configGroups="0 NoDisplay">false</spirit:value>
+ </spirit:parameter>
+ <spirit:parameter>
+ <spirit:name>CLK_OUT3_USE_FINE_PS_GUI</spirit:name>
+ <spirit:value spirit:format="bool" spirit:resolve="user" spirit:id="PARAM_VALUE.CLK_OUT3_USE_FINE_PS_GUI" spirit:order="38" spirit:configGroups="0 NoDisplay">false</spirit:value>
+ </spirit:parameter>
+ <spirit:parameter>
+ <spirit:name>CLK_OUT4_USE_FINE_PS_GUI</spirit:name>
+ <spirit:value spirit:format="bool" spirit:resolve="user" spirit:id="PARAM_VALUE.CLK_OUT4_USE_FINE_PS_GUI" spirit:order="39" spirit:configGroups="0 NoDisplay">false</spirit:value>
+ </spirit:parameter>
+ <spirit:parameter>
+ <spirit:name>CLK_OUT5_USE_FINE_PS_GUI</spirit:name>
+ <spirit:value spirit:format="bool" spirit:resolve="user" spirit:id="PARAM_VALUE.CLK_OUT5_USE_FINE_PS_GUI" spirit:order="40" spirit:configGroups="0 NoDisplay">false</spirit:value>
+ </spirit:parameter>
+ <spirit:parameter>
+ <spirit:name>CLK_OUT6_USE_FINE_PS_GUI</spirit:name>
+ <spirit:value spirit:format="bool" spirit:resolve="user" spirit:id="PARAM_VALUE.CLK_OUT6_USE_FINE_PS_GUI" spirit:order="41" spirit:configGroups="0 NoDisplay">false</spirit:value>
+ </spirit:parameter>
+ <spirit:parameter>
+ <spirit:name>CLK_OUT7_USE_FINE_PS_GUI</spirit:name>
+ <spirit:value spirit:format="bool" spirit:resolve="user" spirit:id="PARAM_VALUE.CLK_OUT7_USE_FINE_PS_GUI" spirit:order="42" spirit:configGroups="0 NoDisplay">false</spirit:value>
+ </spirit:parameter>
+ <spirit:parameter>
+ <spirit:name>PRIMARY_PORT</spirit:name>
+ <spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.PRIMARY_PORT" spirit:order="43" spirit:configGroups="0 NoDisplay">clk_in1</spirit:value>
+ </spirit:parameter>
+ <spirit:parameter>
+ <spirit:name>CLK_OUT1_PORT</spirit:name>
+ <spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.CLK_OUT1_PORT" spirit:order="44" spirit:configGroups="0 NoDisplay">clk_out1</spirit:value>
+ </spirit:parameter>
+ <spirit:parameter>
+ <spirit:name>CLK_OUT2_PORT</spirit:name>
+ <spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.CLK_OUT2_PORT" spirit:order="45" spirit:configGroups="0 NoDisplay">clk_out2</spirit:value>
+ </spirit:parameter>
+ <spirit:parameter>
+ <spirit:name>CLK_OUT3_PORT</spirit:name>
+ <spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.CLK_OUT3_PORT" spirit:order="46" spirit:configGroups="0 NoDisplay">clk_out3</spirit:value>
+ </spirit:parameter>
+ <spirit:parameter>
+ <spirit:name>CLK_OUT4_PORT</spirit:name>
+ <spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.CLK_OUT4_PORT" spirit:order="47" spirit:configGroups="0 NoDisplay">clk_out4</spirit:value>
+ </spirit:parameter>
+ <spirit:parameter>
+ <spirit:name>CLK_OUT5_PORT</spirit:name>
+ <spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.CLK_OUT5_PORT" spirit:order="48" spirit:configGroups="0 NoDisplay">clk_out5</spirit:value>
+ </spirit:parameter>
+ <spirit:parameter>
+ <spirit:name>CLK_OUT6_PORT</spirit:name>
+ <spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.CLK_OUT6_PORT" spirit:order="49" spirit:configGroups="0 NoDisplay">clk_out6</spirit:value>
+ </spirit:parameter>
+ <spirit:parameter>
+ <spirit:name>CLK_OUT7_PORT</spirit:name>
+ <spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.CLK_OUT7_PORT" spirit:order="50" spirit:configGroups="0 NoDisplay">clk_out7</spirit:value>
+ </spirit:parameter>
+ <spirit:parameter>
+ <spirit:name>DADDR_PORT</spirit:name>
+ <spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.DADDR_PORT" spirit:order="51" spirit:configGroups="0 NoDisplay">daddr</spirit:value>
+ </spirit:parameter>
+ <spirit:parameter>
+ <spirit:name>DCLK_PORT</spirit:name>
+ <spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.DCLK_PORT" spirit:order="52" spirit:configGroups="0 NoDisplay">dclk</spirit:value>
+ </spirit:parameter>
+ <spirit:parameter>
+ <spirit:name>DRDY_PORT</spirit:name>
+ <spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.DRDY_PORT" spirit:order="53" spirit:configGroups="0 NoDisplay">drdy</spirit:value>
+ </spirit:parameter>
+ <spirit:parameter>
+ <spirit:name>DWE_PORT</spirit:name>
+ <spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.DWE_PORT" spirit:order="54" spirit:configGroups="0 NoDisplay">dwe</spirit:value>
+ </spirit:parameter>
+ <spirit:parameter>
+ <spirit:name>DIN_PORT</spirit:name>
+ <spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.DIN_PORT" spirit:order="55" spirit:configGroups="0 NoDisplay">din</spirit:value>
+ </spirit:parameter>
+ <spirit:parameter>
+ <spirit:name>DOUT_PORT</spirit:name>
+ <spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.DOUT_PORT" spirit:order="56" spirit:configGroups="0 NoDisplay">dout</spirit:value>
+ </spirit:parameter>
+ <spirit:parameter>
+ <spirit:name>DEN_PORT</spirit:name>
+ <spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.DEN_PORT" spirit:order="57" spirit:configGroups="0 NoDisplay">den</spirit:value>
+ </spirit:parameter>
+ <spirit:parameter>
+ <spirit:name>PSCLK_PORT</spirit:name>
+ <spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.PSCLK_PORT" spirit:order="58" spirit:configGroups="0 NoDisplay">psclk</spirit:value>
+ </spirit:parameter>
+ <spirit:parameter>
+ <spirit:name>PSEN_PORT</spirit:name>
+ <spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.PSEN_PORT" spirit:order="59" spirit:configGroups="0 NoDisplay">psen</spirit:value>
+ </spirit:parameter>
+ <spirit:parameter>
+ <spirit:name>PSINCDEC_PORT</spirit:name>
+ <spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.PSINCDEC_PORT" spirit:order="60" spirit:configGroups="0 NoDisplay">psincdec</spirit:value>
+ </spirit:parameter>
+ <spirit:parameter>
+ <spirit:name>PSDONE_PORT</spirit:name>
+ <spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.PSDONE_PORT" spirit:order="61" spirit:configGroups="0 NoDisplay">psdone</spirit:value>
+ </spirit:parameter>
+ <spirit:parameter>
+ <spirit:name>CLKOUT1_REQUESTED_OUT_FREQ</spirit:name>
+ <spirit:value spirit:format="float" spirit:resolve="user" spirit:id="PARAM_VALUE.CLKOUT1_REQUESTED_OUT_FREQ" spirit:order="62" spirit:configGroups="0 NoDisplay">25</spirit:value>
+ </spirit:parameter>
+ <spirit:parameter>
+ <spirit:name>CLKOUT1_REQUESTED_PHASE</spirit:name>
+ <spirit:value spirit:format="float" spirit:resolve="user" spirit:id="PARAM_VALUE.CLKOUT1_REQUESTED_PHASE" spirit:order="63" spirit:configGroups="0 NoDisplay">0.000</spirit:value>
+ </spirit:parameter>
+ <spirit:parameter>
+ <spirit:name>CLKOUT1_REQUESTED_DUTY_CYCLE</spirit:name>
+ <spirit:value spirit:format="float" spirit:resolve="user" spirit:id="PARAM_VALUE.CLKOUT1_REQUESTED_DUTY_CYCLE" spirit:order="64" spirit:configGroups="0 NoDisplay">50.000</spirit:value>
+ </spirit:parameter>
+ <spirit:parameter>
+ <spirit:name>CLKOUT2_REQUESTED_OUT_FREQ</spirit:name>
+ <spirit:value spirit:format="float" spirit:resolve="user" spirit:id="PARAM_VALUE.CLKOUT2_REQUESTED_OUT_FREQ" spirit:order="65" spirit:configGroups="0 NoDisplay">100.000</spirit:value>
+ </spirit:parameter>
+ <spirit:parameter>
+ <spirit:name>CLKOUT2_REQUESTED_PHASE</spirit:name>
+ <spirit:value spirit:format="float" spirit:resolve="user" spirit:id="PARAM_VALUE.CLKOUT2_REQUESTED_PHASE" spirit:order="66" spirit:configGroups="0 NoDisplay">0.000</spirit:value>
+ </spirit:parameter>
+ <spirit:parameter>
+ <spirit:name>CLKOUT2_REQUESTED_DUTY_CYCLE</spirit:name>
+ <spirit:value spirit:format="float" spirit:resolve="user" spirit:id="PARAM_VALUE.CLKOUT2_REQUESTED_DUTY_CYCLE" spirit:order="67" spirit:configGroups="0 NoDisplay">50.000</spirit:value>
+ </spirit:parameter>
+ <spirit:parameter>
+ <spirit:name>CLKOUT3_REQUESTED_OUT_FREQ</spirit:name>
+ <spirit:value spirit:format="float" spirit:resolve="user" spirit:id="PARAM_VALUE.CLKOUT3_REQUESTED_OUT_FREQ" spirit:order="68" spirit:configGroups="0 NoDisplay">100.000</spirit:value>
+ </spirit:parameter>
+ <spirit:parameter>
+ <spirit:name>CLKOUT3_REQUESTED_PHASE</spirit:name>
+ <spirit:value spirit:format="float" spirit:resolve="user" spirit:id="PARAM_VALUE.CLKOUT3_REQUESTED_PHASE" spirit:order="69" spirit:configGroups="0 NoDisplay">0.000</spirit:value>
+ </spirit:parameter>
+ <spirit:parameter>
+ <spirit:name>CLKOUT3_REQUESTED_DUTY_CYCLE</spirit:name>
+ <spirit:value spirit:format="float" spirit:resolve="user" spirit:id="PARAM_VALUE.CLKOUT3_REQUESTED_DUTY_CYCLE" spirit:order="70" spirit:configGroups="0 NoDisplay">50.000</spirit:value>
+ </spirit:parameter>
+ <spirit:parameter>
+ <spirit:name>CLKOUT4_REQUESTED_OUT_FREQ</spirit:name>
+ <spirit:value spirit:format="float" spirit:resolve="user" spirit:id="PARAM_VALUE.CLKOUT4_REQUESTED_OUT_FREQ" spirit:order="71" spirit:configGroups="0 NoDisplay">100.000</spirit:value>
+ </spirit:parameter>
+ <spirit:parameter>
+ <spirit:name>CLKOUT4_REQUESTED_PHASE</spirit:name>
+ <spirit:value spirit:format="float" spirit:resolve="user" spirit:id="PARAM_VALUE.CLKOUT4_REQUESTED_PHASE" spirit:order="72" spirit:configGroups="0 NoDisplay">0.000</spirit:value>
+ </spirit:parameter>
+ <spirit:parameter>
+ <spirit:name>CLKOUT4_REQUESTED_DUTY_CYCLE</spirit:name>
+ <spirit:value spirit:format="float" spirit:resolve="user" spirit:id="PARAM_VALUE.CLKOUT4_REQUESTED_DUTY_CYCLE" spirit:order="73" spirit:configGroups="0 NoDisplay">50.000</spirit:value>
+ </spirit:parameter>
+ <spirit:parameter>
+ <spirit:name>CLKOUT5_REQUESTED_OUT_FREQ</spirit:name>
+ <spirit:value spirit:format="float" spirit:resolve="user" spirit:id="PARAM_VALUE.CLKOUT5_REQUESTED_OUT_FREQ" spirit:order="74" spirit:configGroups="0 NoDisplay">100.000</spirit:value>
+ </spirit:parameter>
+ <spirit:parameter>
+ <spirit:name>CLKOUT5_REQUESTED_PHASE</spirit:name>
+ <spirit:value spirit:format="float" spirit:resolve="user" spirit:id="PARAM_VALUE.CLKOUT5_REQUESTED_PHASE" spirit:order="75" spirit:configGroups="0 NoDisplay">0.000</spirit:value>
+ </spirit:parameter>
+ <spirit:parameter>
+ <spirit:name>CLKOUT5_REQUESTED_DUTY_CYCLE</spirit:name>
+ <spirit:value spirit:format="float" spirit:resolve="user" spirit:id="PARAM_VALUE.CLKOUT5_REQUESTED_DUTY_CYCLE" spirit:order="76" spirit:configGroups="0 NoDisplay">50.000</spirit:value>
+ </spirit:parameter>
+ <spirit:parameter>
+ <spirit:name>CLKOUT6_REQUESTED_OUT_FREQ</spirit:name>
+ <spirit:value spirit:format="float" spirit:resolve="user" spirit:id="PARAM_VALUE.CLKOUT6_REQUESTED_OUT_FREQ" spirit:order="77" spirit:configGroups="0 NoDisplay">100.000</spirit:value>
+ </spirit:parameter>
+ <spirit:parameter>
+ <spirit:name>CLKOUT6_REQUESTED_PHASE</spirit:name>
+ <spirit:value spirit:format="float" spirit:resolve="user" spirit:id="PARAM_VALUE.CLKOUT6_REQUESTED_PHASE" spirit:order="78" spirit:configGroups="0 NoDisplay">0.000</spirit:value>
+ </spirit:parameter>
+ <spirit:parameter>
+ <spirit:name>CLKOUT6_REQUESTED_DUTY_CYCLE</spirit:name>
+ <spirit:value spirit:format="float" spirit:resolve="user" spirit:id="PARAM_VALUE.CLKOUT6_REQUESTED_DUTY_CYCLE" spirit:order="79" spirit:configGroups="0 NoDisplay">50.000</spirit:value>
+ </spirit:parameter>
+ <spirit:parameter>
+ <spirit:name>CLKOUT7_REQUESTED_OUT_FREQ</spirit:name>
+ <spirit:value spirit:format="float" spirit:resolve="user" spirit:id="PARAM_VALUE.CLKOUT7_REQUESTED_OUT_FREQ" spirit:order="80" spirit:configGroups="0 NoDisplay">100.000</spirit:value>
+ </spirit:parameter>
+ <spirit:parameter>
+ <spirit:name>CLKOUT7_REQUESTED_PHASE</spirit:name>
+ <spirit:value spirit:format="float" spirit:resolve="user" spirit:id="PARAM_VALUE.CLKOUT7_REQUESTED_PHASE" spirit:order="81" spirit:configGroups="0 NoDisplay">0.000</spirit:value>
+ </spirit:parameter>
+ <spirit:parameter>
+ <spirit:name>CLKOUT7_REQUESTED_DUTY_CYCLE</spirit:name>
+ <spirit:value spirit:format="float" spirit:resolve="user" spirit:id="PARAM_VALUE.CLKOUT7_REQUESTED_DUTY_CYCLE" spirit:order="82" spirit:configGroups="0 NoDisplay">50.000</spirit:value>
+ </spirit:parameter>
+ <spirit:parameter>
+ <spirit:name>USE_MAX_I_JITTER</spirit:name>
+ <spirit:value spirit:format="bool" spirit:resolve="user" spirit:id="PARAM_VALUE.USE_MAX_I_JITTER" spirit:order="83" spirit:configGroups="0 NoDisplay">false</spirit:value>
+ </spirit:parameter>
+ <spirit:parameter>
+ <spirit:name>USE_MIN_O_JITTER</spirit:name>
+ <spirit:value spirit:format="bool" spirit:resolve="user" spirit:id="PARAM_VALUE.USE_MIN_O_JITTER" spirit:order="84" spirit:configGroups="0 NoDisplay">false</spirit:value>
+ </spirit:parameter>
+ <spirit:parameter>
+ <spirit:name>CLKOUT1_MATCHED_ROUTING</spirit:name>
+ <spirit:value spirit:format="bool" spirit:resolve="user" spirit:id="PARAM_VALUE.CLKOUT1_MATCHED_ROUTING" spirit:order="984" spirit:configGroups="0 NoDisplay">false</spirit:value>
+ </spirit:parameter>
+ <spirit:parameter>
+ <spirit:name>CLKOUT2_MATCHED_ROUTING</spirit:name>
+ <spirit:value spirit:format="bool" spirit:resolve="user" spirit:id="PARAM_VALUE.CLKOUT2_MATCHED_ROUTING" spirit:order="985" spirit:configGroups="0 NoDisplay">false</spirit:value>
+ </spirit:parameter>
+ <spirit:parameter>
+ <spirit:name>CLKOUT3_MATCHED_ROUTING</spirit:name>
+ <spirit:value spirit:format="bool" spirit:resolve="user" spirit:id="PARAM_VALUE.CLKOUT3_MATCHED_ROUTING" spirit:order="986" spirit:configGroups="0 NoDisplay">false</spirit:value>
+ </spirit:parameter>
+ <spirit:parameter>
+ <spirit:name>CLKOUT4_MATCHED_ROUTING</spirit:name>
+ <spirit:value spirit:format="bool" spirit:resolve="user" spirit:id="PARAM_VALUE.CLKOUT4_MATCHED_ROUTING" spirit:order="987" spirit:configGroups="0 NoDisplay">false</spirit:value>
+ </spirit:parameter>
+ <spirit:parameter>
+ <spirit:name>CLKOUT5_MATCHED_ROUTING</spirit:name>
+ <spirit:value spirit:format="bool" spirit:resolve="user" spirit:id="PARAM_VALUE.CLKOUT5_MATCHED_ROUTING" spirit:order="988" spirit:configGroups="0 NoDisplay">false</spirit:value>
+ </spirit:parameter>
+ <spirit:parameter>
+ <spirit:name>CLKOUT6_MATCHED_ROUTING</spirit:name>
+ <spirit:value spirit:format="bool" spirit:resolve="user" spirit:id="PARAM_VALUE.CLKOUT6_MATCHED_ROUTING" spirit:order="989" spirit:configGroups="0 NoDisplay">false</spirit:value>
+ </spirit:parameter>
+ <spirit:parameter>
+ <spirit:name>CLKOUT7_MATCHED_ROUTING</spirit:name>
+ <spirit:value spirit:format="bool" spirit:resolve="user" spirit:id="PARAM_VALUE.CLKOUT7_MATCHED_ROUTING" spirit:order="990" spirit:configGroups="0 NoDisplay">false</spirit:value>
+ </spirit:parameter>
+ <spirit:parameter>
+ <spirit:name>PRIM_SOURCE</spirit:name>
+ <spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.PRIM_SOURCE" spirit:choiceRef="choice_pairs_11d71346" spirit:order="14.1" spirit:configGroups="0 NoDisplay">Single_ended_clock_capable_pin</spirit:value>
+ </spirit:parameter>
+ <spirit:parameter>
+ <spirit:name>CLKOUT1_DRIVES</spirit:name>
+ <spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.CLKOUT1_DRIVES" spirit:choiceRef="choice_pairs_66e4c81f" spirit:order="86" spirit:configGroups="0 NoDisplay">BUFG</spirit:value>
+ </spirit:parameter>
+ <spirit:parameter>
+ <spirit:name>CLKOUT2_DRIVES</spirit:name>
+ <spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.CLKOUT2_DRIVES" spirit:choiceRef="choice_pairs_66e4c81f" spirit:order="87" spirit:configGroups="0 NoDisplay">BUFG</spirit:value>
+ </spirit:parameter>
+ <spirit:parameter>
+ <spirit:name>CLKOUT3_DRIVES</spirit:name>
+ <spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.CLKOUT3_DRIVES" spirit:choiceRef="choice_pairs_66e4c81f" spirit:order="88" spirit:configGroups="0 NoDisplay">BUFG</spirit:value>
+ </spirit:parameter>
+ <spirit:parameter>
+ <spirit:name>CLKOUT4_DRIVES</spirit:name>
+ <spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.CLKOUT4_DRIVES" spirit:choiceRef="choice_pairs_66e4c81f" spirit:order="89" spirit:configGroups="0 NoDisplay">BUFG</spirit:value>
+ </spirit:parameter>
+ <spirit:parameter>
+ <spirit:name>CLKOUT5_DRIVES</spirit:name>
+ <spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.CLKOUT5_DRIVES" spirit:choiceRef="choice_pairs_66e4c81f" spirit:order="90" spirit:configGroups="0 NoDisplay">BUFG</spirit:value>
+ </spirit:parameter>
+ <spirit:parameter>
+ <spirit:name>CLKOUT6_DRIVES</spirit:name>
+ <spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.CLKOUT6_DRIVES" spirit:choiceRef="choice_pairs_66e4c81f" spirit:order="91" spirit:configGroups="0 NoDisplay">BUFG</spirit:value>
+ </spirit:parameter>
+ <spirit:parameter>
+ <spirit:name>CLKOUT7_DRIVES</spirit:name>
+ <spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.CLKOUT7_DRIVES" spirit:choiceRef="choice_pairs_66e4c81f" spirit:order="92" spirit:configGroups="0 NoDisplay">BUFG</spirit:value>
+ </spirit:parameter>
+ <spirit:parameter>
+ <spirit:name>FEEDBACK_SOURCE</spirit:name>
+ <spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.FEEDBACK_SOURCE" spirit:choiceRef="choice_pairs_15c806d5" spirit:order="93" spirit:configGroups="0 NoDisplay">FDBK_AUTO</spirit:value>
+ </spirit:parameter>
+ <spirit:parameter>
+ <spirit:name>CLKFB_IN_SIGNALING</spirit:name>
+ <spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.CLKFB_IN_SIGNALING" spirit:choiceRef="choice_pairs_3c2d3ec7" spirit:order="94" spirit:configGroups="0 NoDisplay">SINGLE</spirit:value>
+ </spirit:parameter>
+ <spirit:parameter>
+ <spirit:name>CLKFB_IN_PORT</spirit:name>
+ <spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.CLKFB_IN_PORT" spirit:order="95" spirit:configGroups="0 NoDisplay">clkfb_in</spirit:value>
+ </spirit:parameter>
+ <spirit:parameter>
+ <spirit:name>CLKFB_IN_P_PORT</spirit:name>
+ <spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.CLKFB_IN_P_PORT" spirit:order="96" spirit:configGroups="0 NoDisplay">clkfb_in_p</spirit:value>
+ </spirit:parameter>
+ <spirit:parameter>
+ <spirit:name>CLKFB_IN_N_PORT</spirit:name>
+ <spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.CLKFB_IN_N_PORT" spirit:order="97" spirit:configGroups="0 NoDisplay">clkfb_in_n</spirit:value>
+ </spirit:parameter>
+ <spirit:parameter>
+ <spirit:name>CLKFB_OUT_PORT</spirit:name>
+ <spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.CLKFB_OUT_PORT" spirit:order="98" spirit:configGroups="0 NoDisplay">clkfb_out</spirit:value>
+ </spirit:parameter>
+ <spirit:parameter>
+ <spirit:name>CLKFB_OUT_P_PORT</spirit:name>
+ <spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.CLKFB_OUT_P_PORT" spirit:order="99" spirit:configGroups="0 NoDisplay">clkfb_out_p</spirit:value>
+ </spirit:parameter>
+ <spirit:parameter>
+ <spirit:name>CLKFB_OUT_N_PORT</spirit:name>
+ <spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.CLKFB_OUT_N_PORT" spirit:order="100" spirit:configGroups="0 NoDisplay">clkfb_out_n</spirit:value>
+ </spirit:parameter>
+ <spirit:parameter>
+ <spirit:name>PLATFORM</spirit:name>
+ <spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.PLATFORM" spirit:order="101" spirit:configGroups="0 NoDisplay">UNKNOWN</spirit:value>
+ </spirit:parameter>
+ <spirit:parameter>
+ <spirit:name>SUMMARY_STRINGS</spirit:name>
+ <spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.SUMMARY_STRINGS" spirit:order="102" spirit:configGroups="0 NoDisplay">empty</spirit:value>
+ </spirit:parameter>
+ <spirit:parameter>
+ <spirit:name>USE_LOCKED</spirit:name>
+ <spirit:value spirit:format="bool" spirit:resolve="user" spirit:id="PARAM_VALUE.USE_LOCKED" spirit:order="103" spirit:configGroups="0 NoDisplay">false</spirit:value>
+ </spirit:parameter>
+ <spirit:parameter>
+ <spirit:name>CALC_DONE</spirit:name>
+ <spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.CALC_DONE" spirit:order="104" spirit:configGroups="0 NoDisplay">empty</spirit:value>
+ </spirit:parameter>
+ <spirit:parameter>
+ <spirit:name>USE_RESET</spirit:name>
+ <spirit:value spirit:format="bool" spirit:resolve="user" spirit:id="PARAM_VALUE.USE_RESET" spirit:order="105" spirit:configGroups="0 NoDisplay">true</spirit:value>
+ </spirit:parameter>
+ <spirit:parameter>
+ <spirit:name>USE_POWER_DOWN</spirit:name>
+ <spirit:value spirit:format="bool" spirit:resolve="user" spirit:id="PARAM_VALUE.USE_POWER_DOWN" spirit:order="106" spirit:configGroups="0 NoDisplay">false</spirit:value>
+ </spirit:parameter>
+ <spirit:parameter>
+ <spirit:name>USE_STATUS</spirit:name>
+ <spirit:value spirit:format="bool" spirit:resolve="user" spirit:id="PARAM_VALUE.USE_STATUS" spirit:order="107" spirit:configGroups="0 NoDisplay">false</spirit:value>
+ </spirit:parameter>
+ <spirit:parameter>
+ <spirit:name>USE_FREEZE</spirit:name>
+ <spirit:value spirit:format="bool" spirit:resolve="user" spirit:id="PARAM_VALUE.USE_FREEZE" spirit:order="108" spirit:configGroups="0 NoDisplay">false</spirit:value>
+ </spirit:parameter>
+ <spirit:parameter>
+ <spirit:name>USE_CLK_VALID</spirit:name>
+ <spirit:value spirit:format="bool" spirit:resolve="user" spirit:id="PARAM_VALUE.USE_CLK_VALID" spirit:order="109" spirit:configGroups="0 NoDisplay">false</spirit:value>
+ </spirit:parameter>
+ <spirit:parameter>
+ <spirit:name>USE_INCLK_STOPPED</spirit:name>
+ <spirit:value spirit:format="bool" spirit:resolve="user" spirit:id="PARAM_VALUE.USE_INCLK_STOPPED" spirit:order="110" spirit:configGroups="0 NoDisplay">false</spirit:value>
+ </spirit:parameter>
+ <spirit:parameter>
+ <spirit:name>USE_CLKFB_STOPPED</spirit:name>
+ <spirit:value spirit:format="bool" spirit:resolve="user" spirit:id="PARAM_VALUE.USE_CLKFB_STOPPED" spirit:order="111" spirit:configGroups="0 NoDisplay">false</spirit:value>
+ </spirit:parameter>
+ <spirit:parameter>
+ <spirit:name>RESET_PORT</spirit:name>
+ <spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.RESET_PORT" spirit:order="409" spirit:configGroups="0 NoDisplay">resetn</spirit:value>
+ </spirit:parameter>
+ <spirit:parameter>
+ <spirit:name>LOCKED_PORT</spirit:name>
+ <spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.LOCKED_PORT" spirit:order="113" spirit:configGroups="0 NoDisplay">locked</spirit:value>
+ </spirit:parameter>
+ <spirit:parameter>
+ <spirit:name>POWER_DOWN_PORT</spirit:name>
+ <spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.POWER_DOWN_PORT" spirit:order="114" spirit:configGroups="0 NoDisplay">power_down</spirit:value>
+ </spirit:parameter>
+ <spirit:parameter>
+ <spirit:name>CLK_VALID_PORT</spirit:name>
+ <spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.CLK_VALID_PORT" spirit:order="115" spirit:configGroups="0 NoDisplay">CLK_VALID</spirit:value>
+ </spirit:parameter>
+ <spirit:parameter>
+ <spirit:name>STATUS_PORT</spirit:name>
+ <spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.STATUS_PORT" spirit:order="116" spirit:configGroups="0 NoDisplay">STATUS</spirit:value>
+ </spirit:parameter>
+ <spirit:parameter>
+ <spirit:name>CLK_IN_SEL_PORT</spirit:name>
+ <spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.CLK_IN_SEL_PORT" spirit:order="117" spirit:configGroups="0 NoDisplay">clk_in_sel</spirit:value>
+ </spirit:parameter>
+ <spirit:parameter>
+ <spirit:name>INPUT_CLK_STOPPED_PORT</spirit:name>
+ <spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.INPUT_CLK_STOPPED_PORT" spirit:order="118" spirit:configGroups="0 NoDisplay">input_clk_stopped</spirit:value>
+ </spirit:parameter>
+ <spirit:parameter>
+ <spirit:name>CLKFB_STOPPED_PORT</spirit:name>
+ <spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.CLKFB_STOPPED_PORT" spirit:order="119" spirit:configGroups="0 NoDisplay">clkfb_stopped</spirit:value>
+ </spirit:parameter>
+ <spirit:parameter>
+ <spirit:name>SS_MODE</spirit:name>
+ <spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.SS_MODE" spirit:choiceRef="choice_pairs_f4e10086" spirit:order="120" spirit:configGroups="0 NoDisplay">CENTER_HIGH</spirit:value>
+ </spirit:parameter>
+ <spirit:parameter>
+ <spirit:name>SS_MOD_FREQ</spirit:name>
+ <spirit:value spirit:format="float" spirit:resolve="user" spirit:id="PARAM_VALUE.SS_MOD_FREQ" spirit:order="121" spirit:configGroups="0 NoDisplay">250</spirit:value>
+ </spirit:parameter>
+ <spirit:parameter>
+ <spirit:name>SS_MOD_TIME</spirit:name>
+ <spirit:value spirit:format="float" spirit:resolve="user" spirit:id="PARAM_VALUE.SS_MOD_TIME" spirit:order="121.001" spirit:configGroups="0 NoDisplay">0.004</spirit:value>
+ </spirit:parameter>
+ <spirit:parameter>
+ <spirit:name>OVERRIDE_MMCM</spirit:name>
+ <spirit:value spirit:format="bool" spirit:resolve="user" spirit:id="PARAM_VALUE.OVERRIDE_MMCM" spirit:order="122" spirit:configGroups="0 NoDisplay">false</spirit:value>
+ </spirit:parameter>
+ <spirit:parameter>
+ <spirit:name>MMCM_NOTES</spirit:name>
+ <spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.MMCM_NOTES" spirit:order="123" spirit:configGroups="0 NoDisplay">None</spirit:value>
+ </spirit:parameter>
+ <spirit:parameter>
+ <spirit:name>MMCM_DIVCLK_DIVIDE</spirit:name>
+ <spirit:value spirit:format="long" spirit:resolve="user" spirit:id="PARAM_VALUE.MMCM_DIVCLK_DIVIDE" spirit:order="124" spirit:configGroups="0 NoDisplay">1</spirit:value>
+ </spirit:parameter>
+ <spirit:parameter>
+ <spirit:name>MMCM_BANDWIDTH</spirit:name>
+ <spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.MMCM_BANDWIDTH" spirit:choiceRef="choice_list_a9bdfce0" spirit:order="125" spirit:configGroups="0 NoDisplay">OPTIMIZED</spirit:value>
+ </spirit:parameter>
+ <spirit:parameter>
+ <spirit:name>MMCM_CLKFBOUT_MULT_F</spirit:name>
+ <spirit:value spirit:format="float" spirit:resolve="user" spirit:id="PARAM_VALUE.MMCM_CLKFBOUT_MULT_F" spirit:order="126" spirit:configGroups="0 NoDisplay">9.125</spirit:value>
+ </spirit:parameter>
+ <spirit:parameter>
+ <spirit:name>MMCM_CLKFBOUT_PHASE</spirit:name>
+ <spirit:value spirit:format="float" spirit:resolve="user" spirit:id="PARAM_VALUE.MMCM_CLKFBOUT_PHASE" spirit:order="127" spirit:configGroups="0 NoDisplay">0.000</spirit:value>
+ </spirit:parameter>
+ <spirit:parameter>
+ <spirit:name>MMCM_CLKFBOUT_USE_FINE_PS</spirit:name>
+ <spirit:value spirit:format="bool" spirit:resolve="user" spirit:id="PARAM_VALUE.MMCM_CLKFBOUT_USE_FINE_PS" spirit:order="128" spirit:configGroups="0 NoDisplay">false</spirit:value>
+ </spirit:parameter>
+ <spirit:parameter>
+ <spirit:name>MMCM_CLKIN1_PERIOD</spirit:name>
+ <spirit:value spirit:format="float" spirit:resolve="user" spirit:id="PARAM_VALUE.MMCM_CLKIN1_PERIOD" spirit:order="129" spirit:configGroups="0 NoDisplay">10.000</spirit:value>
+ </spirit:parameter>
+ <spirit:parameter>
+ <spirit:name>MMCM_CLKIN2_PERIOD</spirit:name>
+ <spirit:value spirit:format="float" spirit:resolve="user" spirit:id="PARAM_VALUE.MMCM_CLKIN2_PERIOD" spirit:order="130" spirit:configGroups="0 NoDisplay">10.000</spirit:value>
+ </spirit:parameter>
+ <spirit:parameter>
+ <spirit:name>MMCM_CLKOUT4_CASCADE</spirit:name>
+ <spirit:value spirit:format="bool" spirit:resolve="user" spirit:id="PARAM_VALUE.MMCM_CLKOUT4_CASCADE" spirit:order="131" spirit:configGroups="0 NoDisplay">false</spirit:value>
+ </spirit:parameter>
+ <spirit:parameter>
+ <spirit:name>MMCM_CLOCK_HOLD</spirit:name>
+ <spirit:value spirit:format="bool" spirit:resolve="user" spirit:id="PARAM_VALUE.MMCM_CLOCK_HOLD" spirit:order="132" spirit:configGroups="0 NoDisplay">false</spirit:value>
+ </spirit:parameter>
+ <spirit:parameter>
+ <spirit:name>MMCM_COMPENSATION</spirit:name>
+ <spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.MMCM_COMPENSATION" spirit:choiceRef="choice_pairs_502d9f23" spirit:order="133" spirit:configGroups="0 NoDisplay">ZHOLD</spirit:value>
+ </spirit:parameter>
+ <spirit:parameter>
+ <spirit:name>MMCM_REF_JITTER1</spirit:name>
+ <spirit:value spirit:format="float" spirit:resolve="user" spirit:id="PARAM_VALUE.MMCM_REF_JITTER1" spirit:order="134" spirit:configGroups="0 NoDisplay">0.010</spirit:value>
+ </spirit:parameter>
+ <spirit:parameter>
+ <spirit:name>MMCM_REF_JITTER2</spirit:name>
+ <spirit:value spirit:format="float" spirit:resolve="user" spirit:id="PARAM_VALUE.MMCM_REF_JITTER2" spirit:order="135" spirit:configGroups="0 NoDisplay">0.010</spirit:value>
+ </spirit:parameter>
+ <spirit:parameter>
+ <spirit:name>MMCM_STARTUP_WAIT</spirit:name>
+ <spirit:value spirit:format="bool" spirit:resolve="user" spirit:id="PARAM_VALUE.MMCM_STARTUP_WAIT" spirit:order="136" spirit:configGroups="0 NoDisplay">false</spirit:value>
+ </spirit:parameter>
+ <spirit:parameter>
+ <spirit:name>MMCM_CLKOUT0_DIVIDE_F</spirit:name>
+ <spirit:value spirit:format="float" spirit:resolve="user" spirit:id="PARAM_VALUE.MMCM_CLKOUT0_DIVIDE_F" spirit:order="137" spirit:configGroups="0 NoDisplay">36.500</spirit:value>
+ </spirit:parameter>
+ <spirit:parameter>
+ <spirit:name>MMCM_CLKOUT0_DUTY_CYCLE</spirit:name>
+ <spirit:value spirit:format="float" spirit:resolve="user" spirit:id="PARAM_VALUE.MMCM_CLKOUT0_DUTY_CYCLE" spirit:order="138" spirit:configGroups="0 NoDisplay">0.500</spirit:value>
+ </spirit:parameter>
+ <spirit:parameter>
+ <spirit:name>MMCM_CLKOUT0_PHASE</spirit:name>
+ <spirit:value spirit:format="float" spirit:resolve="user" spirit:id="PARAM_VALUE.MMCM_CLKOUT0_PHASE" spirit:order="139" spirit:configGroups="0 NoDisplay">0.000</spirit:value>
+ </spirit:parameter>
+ <spirit:parameter>
+ <spirit:name>MMCM_CLKOUT0_USE_FINE_PS</spirit:name>
+ <spirit:value spirit:format="bool" spirit:resolve="user" spirit:id="PARAM_VALUE.MMCM_CLKOUT0_USE_FINE_PS" spirit:order="140" spirit:configGroups="0 NoDisplay">false</spirit:value>
+ </spirit:parameter>
+ <spirit:parameter>
+ <spirit:name>MMCM_CLKOUT1_DIVIDE</spirit:name>
+ <spirit:value spirit:format="long" spirit:resolve="user" spirit:id="PARAM_VALUE.MMCM_CLKOUT1_DIVIDE" spirit:order="141" spirit:configGroups="0 NoDisplay">1</spirit:value>
+ </spirit:parameter>
+ <spirit:parameter>
+ <spirit:name>MMCM_CLKOUT1_DUTY_CYCLE</spirit:name>
+ <spirit:value spirit:format="float" spirit:resolve="user" spirit:id="PARAM_VALUE.MMCM_CLKOUT1_DUTY_CYCLE" spirit:order="142" spirit:configGroups="0 NoDisplay">0.500</spirit:value>
+ </spirit:parameter>
+ <spirit:parameter>
+ <spirit:name>MMCM_CLKOUT1_PHASE</spirit:name>
+ <spirit:value spirit:format="float" spirit:resolve="user" spirit:id="PARAM_VALUE.MMCM_CLKOUT1_PHASE" spirit:order="143" spirit:configGroups="0 NoDisplay">0.000</spirit:value>
+ </spirit:parameter>
+ <spirit:parameter>
+ <spirit:name>MMCM_CLKOUT1_USE_FINE_PS</spirit:name>
+ <spirit:value spirit:format="bool" spirit:resolve="user" spirit:id="PARAM_VALUE.MMCM_CLKOUT1_USE_FINE_PS" spirit:order="144" spirit:configGroups="0 NoDisplay">false</spirit:value>
+ </spirit:parameter>
+ <spirit:parameter>
+ <spirit:name>MMCM_CLKOUT2_DIVIDE</spirit:name>
+ <spirit:value spirit:format="long" spirit:resolve="user" spirit:id="PARAM_VALUE.MMCM_CLKOUT2_DIVIDE" spirit:order="145" spirit:configGroups="0 NoDisplay">1</spirit:value>
+ </spirit:parameter>
+ <spirit:parameter>
+ <spirit:name>MMCM_CLKOUT2_DUTY_CYCLE</spirit:name>
+ <spirit:value spirit:format="float" spirit:resolve="user" spirit:id="PARAM_VALUE.MMCM_CLKOUT2_DUTY_CYCLE" spirit:order="146" spirit:configGroups="0 NoDisplay">0.500</spirit:value>
+ </spirit:parameter>
+ <spirit:parameter>
+ <spirit:name>MMCM_CLKOUT2_PHASE</spirit:name>
+ <spirit:value spirit:format="float" spirit:resolve="user" spirit:id="PARAM_VALUE.MMCM_CLKOUT2_PHASE" spirit:order="147" spirit:configGroups="0 NoDisplay">0.000</spirit:value>
+ </spirit:parameter>
+ <spirit:parameter>
+ <spirit:name>MMCM_CLKOUT2_USE_FINE_PS</spirit:name>
+ <spirit:value spirit:format="bool" spirit:resolve="user" spirit:id="PARAM_VALUE.MMCM_CLKOUT2_USE_FINE_PS" spirit:order="148" spirit:configGroups="0 NoDisplay">false</spirit:value>
+ </spirit:parameter>
+ <spirit:parameter>
+ <spirit:name>MMCM_CLKOUT3_DIVIDE</spirit:name>
+ <spirit:value spirit:format="long" spirit:resolve="user" spirit:id="PARAM_VALUE.MMCM_CLKOUT3_DIVIDE" spirit:order="149" spirit:configGroups="0 NoDisplay">1</spirit:value>
+ </spirit:parameter>
+ <spirit:parameter>
+ <spirit:name>MMCM_CLKOUT3_DUTY_CYCLE</spirit:name>
+ <spirit:value spirit:format="float" spirit:resolve="user" spirit:id="PARAM_VALUE.MMCM_CLKOUT3_DUTY_CYCLE" spirit:order="150" spirit:configGroups="0 NoDisplay">0.500</spirit:value>
+ </spirit:parameter>
+ <spirit:parameter>
+ <spirit:name>MMCM_CLKOUT3_PHASE</spirit:name>
+ <spirit:value spirit:format="float" spirit:resolve="user" spirit:id="PARAM_VALUE.MMCM_CLKOUT3_PHASE" spirit:order="151" spirit:configGroups="0 NoDisplay">0.000</spirit:value>
+ </spirit:parameter>
+ <spirit:parameter>
+ <spirit:name>MMCM_CLKOUT3_USE_FINE_PS</spirit:name>
+ <spirit:value spirit:format="bool" spirit:resolve="user" spirit:id="PARAM_VALUE.MMCM_CLKOUT3_USE_FINE_PS" spirit:order="152" spirit:configGroups="0 NoDisplay">false</spirit:value>
+ </spirit:parameter>
+ <spirit:parameter>
+ <spirit:name>MMCM_CLKOUT4_DIVIDE</spirit:name>
+ <spirit:value spirit:format="long" spirit:resolve="user" spirit:id="PARAM_VALUE.MMCM_CLKOUT4_DIVIDE" spirit:order="153" spirit:configGroups="0 NoDisplay">1</spirit:value>
+ </spirit:parameter>
+ <spirit:parameter>
+ <spirit:name>MMCM_CLKOUT4_DUTY_CYCLE</spirit:name>
+ <spirit:value spirit:format="float" spirit:resolve="user" spirit:id="PARAM_VALUE.MMCM_CLKOUT4_DUTY_CYCLE" spirit:order="154" spirit:configGroups="0 NoDisplay">0.500</spirit:value>
+ </spirit:parameter>
+ <spirit:parameter>
+ <spirit:name>MMCM_CLKOUT4_PHASE</spirit:name>
+ <spirit:value spirit:format="float" spirit:resolve="user" spirit:id="PARAM_VALUE.MMCM_CLKOUT4_PHASE" spirit:order="155" spirit:configGroups="0 NoDisplay">0.000</spirit:value>
+ </spirit:parameter>
+ <spirit:parameter>
+ <spirit:name>MMCM_CLKOUT4_USE_FINE_PS</spirit:name>
+ <spirit:value spirit:format="bool" spirit:resolve="user" spirit:id="PARAM_VALUE.MMCM_CLKOUT4_USE_FINE_PS" spirit:order="156" spirit:configGroups="0 NoDisplay">false</spirit:value>
+ </spirit:parameter>
+ <spirit:parameter>
+ <spirit:name>MMCM_CLKOUT5_DIVIDE</spirit:name>
+ <spirit:value spirit:format="long" spirit:resolve="user" spirit:id="PARAM_VALUE.MMCM_CLKOUT5_DIVIDE" spirit:order="157" spirit:configGroups="0 NoDisplay">1</spirit:value>
+ </spirit:parameter>
+ <spirit:parameter>
+ <spirit:name>MMCM_CLKOUT5_DUTY_CYCLE</spirit:name>
+ <spirit:value spirit:format="float" spirit:resolve="user" spirit:id="PARAM_VALUE.MMCM_CLKOUT5_DUTY_CYCLE" spirit:order="158" spirit:configGroups="0 NoDisplay">0.500</spirit:value>
+ </spirit:parameter>
+ <spirit:parameter>
+ <spirit:name>MMCM_CLKOUT5_PHASE</spirit:name>
+ <spirit:value spirit:format="float" spirit:resolve="user" spirit:id="PARAM_VALUE.MMCM_CLKOUT5_PHASE" spirit:order="159" spirit:configGroups="0 NoDisplay">0.000</spirit:value>
+ </spirit:parameter>
+ <spirit:parameter>
+ <spirit:name>MMCM_CLKOUT5_USE_FINE_PS</spirit:name>
+ <spirit:value spirit:format="bool" spirit:resolve="user" spirit:id="PARAM_VALUE.MMCM_CLKOUT5_USE_FINE_PS" spirit:order="160" spirit:configGroups="0 NoDisplay">false</spirit:value>
+ </spirit:parameter>
+ <spirit:parameter>
+ <spirit:name>MMCM_CLKOUT6_DIVIDE</spirit:name>
+ <spirit:value spirit:format="long" spirit:resolve="user" spirit:id="PARAM_VALUE.MMCM_CLKOUT6_DIVIDE" spirit:order="161" spirit:configGroups="0 NoDisplay">1</spirit:value>
+ </spirit:parameter>
+ <spirit:parameter>
+ <spirit:name>MMCM_CLKOUT6_DUTY_CYCLE</spirit:name>
+ <spirit:value spirit:format="float" spirit:resolve="user" spirit:id="PARAM_VALUE.MMCM_CLKOUT6_DUTY_CYCLE" spirit:order="162" spirit:configGroups="0 NoDisplay">0.500</spirit:value>
+ </spirit:parameter>
+ <spirit:parameter>
+ <spirit:name>MMCM_CLKOUT6_PHASE</spirit:name>
+ <spirit:value spirit:format="float" spirit:resolve="user" spirit:id="PARAM_VALUE.MMCM_CLKOUT6_PHASE" spirit:order="163" spirit:configGroups="0 NoDisplay">0.000</spirit:value>
+ </spirit:parameter>
+ <spirit:parameter>
+ <spirit:name>MMCM_CLKOUT6_USE_FINE_PS</spirit:name>
+ <spirit:value spirit:format="bool" spirit:resolve="user" spirit:id="PARAM_VALUE.MMCM_CLKOUT6_USE_FINE_PS" spirit:order="164" spirit:configGroups="0 NoDisplay">false</spirit:value>
+ </spirit:parameter>
+ <spirit:parameter>
+ <spirit:name>OVERRIDE_PLL</spirit:name>
+ <spirit:value spirit:format="bool" spirit:resolve="user" spirit:id="PARAM_VALUE.OVERRIDE_PLL" spirit:order="165" spirit:configGroups="0 NoDisplay">false</spirit:value>
+ </spirit:parameter>
+ <spirit:parameter>
+ <spirit:name>PLL_NOTES</spirit:name>
+ <spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.PLL_NOTES" spirit:order="166" spirit:configGroups="0 NoDisplay">None</spirit:value>
+ </spirit:parameter>
+ <spirit:parameter>
+ <spirit:name>PLL_BANDWIDTH</spirit:name>
+ <spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.PLL_BANDWIDTH" spirit:choiceRef="choice_list_a9bdfce0" spirit:order="167" spirit:configGroups="0 NoDisplay">OPTIMIZED</spirit:value>
+ </spirit:parameter>
+ <spirit:parameter>
+ <spirit:name>PLL_CLKFBOUT_MULT</spirit:name>
+ <spirit:value spirit:format="long" spirit:resolve="user" spirit:id="PARAM_VALUE.PLL_CLKFBOUT_MULT" spirit:order="168" spirit:configGroups="0 NoDisplay" spirit:minimum="1" spirit:maximum="64" spirit:rangeType="long">4</spirit:value>
+ </spirit:parameter>
+ <spirit:parameter>
+ <spirit:name>PLL_CLKFBOUT_PHASE</spirit:name>
+ <spirit:value spirit:format="float" spirit:resolve="user" spirit:id="PARAM_VALUE.PLL_CLKFBOUT_PHASE" spirit:order="169" spirit:configGroups="0 NoDisplay">0.000</spirit:value>
+ </spirit:parameter>
+ <spirit:parameter>
+ <spirit:name>PLL_CLK_FEEDBACK</spirit:name>
+ <spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.PLL_CLK_FEEDBACK" spirit:choiceRef="choice_list_b9d38208" spirit:order="170" spirit:configGroups="0 NoDisplay">CLKFBOUT</spirit:value>
+ </spirit:parameter>
+ <spirit:parameter>
+ <spirit:name>PLL_DIVCLK_DIVIDE</spirit:name>
+ <spirit:value spirit:format="long" spirit:resolve="user" spirit:id="PARAM_VALUE.PLL_DIVCLK_DIVIDE" spirit:order="171" spirit:configGroups="0 NoDisplay" spirit:minimum="1" spirit:maximum="52" spirit:rangeType="long">1</spirit:value>
+ </spirit:parameter>
+ <spirit:parameter>
+ <spirit:name>PLL_CLKIN_PERIOD</spirit:name>
+ <spirit:value spirit:format="float" spirit:resolve="user" spirit:id="PARAM_VALUE.PLL_CLKIN_PERIOD" spirit:order="172" spirit:configGroups="0 NoDisplay">10.000</spirit:value>
+ </spirit:parameter>
+ <spirit:parameter>
+ <spirit:name>PLL_COMPENSATION</spirit:name>
+ <spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.PLL_COMPENSATION" spirit:choiceRef="choice_pairs_035ca1c3" spirit:order="173" spirit:configGroups="0 NoDisplay">SYSTEM_SYNCHRONOUS</spirit:value>
+ </spirit:parameter>
+ <spirit:parameter>
+ <spirit:name>PLL_REF_JITTER</spirit:name>
+ <spirit:value spirit:format="float" spirit:resolve="user" spirit:id="PARAM_VALUE.PLL_REF_JITTER" spirit:order="174" spirit:configGroups="0 NoDisplay">0.010</spirit:value>
+ </spirit:parameter>
+ <spirit:parameter>
+ <spirit:name>PLL_CLKOUT0_DIVIDE</spirit:name>
+ <spirit:value spirit:format="long" spirit:resolve="user" spirit:id="PARAM_VALUE.PLL_CLKOUT0_DIVIDE" spirit:order="175" spirit:configGroups="0 NoDisplay" spirit:minimum="1" spirit:maximum="128" spirit:rangeType="long">1</spirit:value>
+ </spirit:parameter>
+ <spirit:parameter>
+ <spirit:name>PLL_CLKOUT0_DUTY_CYCLE</spirit:name>
+ <spirit:value spirit:format="float" spirit:resolve="user" spirit:id="PARAM_VALUE.PLL_CLKOUT0_DUTY_CYCLE" spirit:order="176" spirit:configGroups="0 NoDisplay">0.500</spirit:value>
+ </spirit:parameter>
+ <spirit:parameter>
+ <spirit:name>PLL_CLKOUT0_PHASE</spirit:name>
+ <spirit:value spirit:format="float" spirit:resolve="user" spirit:id="PARAM_VALUE.PLL_CLKOUT0_PHASE" spirit:order="177" spirit:configGroups="0 NoDisplay">0.000</spirit:value>
+ </spirit:parameter>
+ <spirit:parameter>
+ <spirit:name>PLL_CLKOUT1_DIVIDE</spirit:name>
+ <spirit:value spirit:format="long" spirit:resolve="user" spirit:id="PARAM_VALUE.PLL_CLKOUT1_DIVIDE" spirit:order="178" spirit:configGroups="0 NoDisplay" spirit:minimum="1" spirit:maximum="128" spirit:rangeType="long">1</spirit:value>
+ </spirit:parameter>
+ <spirit:parameter>
+ <spirit:name>PLL_CLKOUT1_DUTY_CYCLE</spirit:name>
+ <spirit:value spirit:format="float" spirit:resolve="user" spirit:id="PARAM_VALUE.PLL_CLKOUT1_DUTY_CYCLE" spirit:order="179" spirit:configGroups="0 NoDisplay">0.500</spirit:value>
+ </spirit:parameter>
+ <spirit:parameter>
+ <spirit:name>PLL_CLKOUT1_PHASE</spirit:name>
+ <spirit:value spirit:format="float" spirit:resolve="user" spirit:id="PARAM_VALUE.PLL_CLKOUT1_PHASE" spirit:order="180" spirit:configGroups="0 NoDisplay">0.000</spirit:value>
+ </spirit:parameter>
+ <spirit:parameter>
+ <spirit:name>PLL_CLKOUT2_DIVIDE</spirit:name>
+ <spirit:value spirit:format="long" spirit:resolve="user" spirit:id="PARAM_VALUE.PLL_CLKOUT2_DIVIDE" spirit:order="181" spirit:configGroups="0 NoDisplay" spirit:minimum="1" spirit:maximum="128" spirit:rangeType="long">1</spirit:value>
+ </spirit:parameter>
+ <spirit:parameter>
+ <spirit:name>PLL_CLKOUT2_DUTY_CYCLE</spirit:name>
+ <spirit:value spirit:format="float" spirit:resolve="user" spirit:id="PARAM_VALUE.PLL_CLKOUT2_DUTY_CYCLE" spirit:order="182" spirit:configGroups="0 NoDisplay">0.500</spirit:value>
+ </spirit:parameter>
+ <spirit:parameter>
+ <spirit:name>PLL_CLKOUT2_PHASE</spirit:name>
+ <spirit:value spirit:format="float" spirit:resolve="user" spirit:id="PARAM_VALUE.PLL_CLKOUT2_PHASE" spirit:order="183" spirit:configGroups="0 NoDisplay">0.000</spirit:value>
+ </spirit:parameter>
+ <spirit:parameter>
+ <spirit:name>PLL_CLKOUT3_DIVIDE</spirit:name>
+ <spirit:value spirit:format="long" spirit:resolve="user" spirit:id="PARAM_VALUE.PLL_CLKOUT3_DIVIDE" spirit:order="184" spirit:configGroups="0 NoDisplay" spirit:minimum="1" spirit:maximum="128" spirit:rangeType="long">1</spirit:value>
+ </spirit:parameter>
+ <spirit:parameter>
+ <spirit:name>PLL_CLKOUT3_DUTY_CYCLE</spirit:name>
+ <spirit:value spirit:format="float" spirit:resolve="user" spirit:id="PARAM_VALUE.PLL_CLKOUT3_DUTY_CYCLE" spirit:order="185" spirit:configGroups="0 NoDisplay">0.500</spirit:value>
+ </spirit:parameter>
+ <spirit:parameter>
+ <spirit:name>PLL_CLKOUT3_PHASE</spirit:name>
+ <spirit:value spirit:format="float" spirit:resolve="user" spirit:id="PARAM_VALUE.PLL_CLKOUT3_PHASE" spirit:order="186" spirit:configGroups="0 NoDisplay">0.000</spirit:value>
+ </spirit:parameter>
+ <spirit:parameter>
+ <spirit:name>PLL_CLKOUT4_DIVIDE</spirit:name>
+ <spirit:value spirit:format="long" spirit:resolve="user" spirit:id="PARAM_VALUE.PLL_CLKOUT4_DIVIDE" spirit:order="187" spirit:configGroups="0 NoDisplay" spirit:minimum="1" spirit:maximum="128" spirit:rangeType="long">1</spirit:value>
+ </spirit:parameter>
+ <spirit:parameter>
+ <spirit:name>PLL_CLKOUT4_DUTY_CYCLE</spirit:name>
+ <spirit:value spirit:format="float" spirit:resolve="user" spirit:id="PARAM_VALUE.PLL_CLKOUT4_DUTY_CYCLE" spirit:order="188" spirit:configGroups="0 NoDisplay">0.500</spirit:value>
+ </spirit:parameter>
+ <spirit:parameter>
+ <spirit:name>PLL_CLKOUT4_PHASE</spirit:name>
+ <spirit:value spirit:format="float" spirit:resolve="user" spirit:id="PARAM_VALUE.PLL_CLKOUT4_PHASE" spirit:order="189" spirit:configGroups="0 NoDisplay">0.000</spirit:value>
+ </spirit:parameter>
+ <spirit:parameter>
+ <spirit:name>PLL_CLKOUT5_DIVIDE</spirit:name>
+ <spirit:value spirit:format="long" spirit:resolve="user" spirit:id="PARAM_VALUE.PLL_CLKOUT5_DIVIDE" spirit:order="190" spirit:configGroups="0 NoDisplay" spirit:minimum="1" spirit:maximum="128" spirit:rangeType="long">1</spirit:value>
+ </spirit:parameter>
+ <spirit:parameter>
+ <spirit:name>PLL_CLKOUT5_DUTY_CYCLE</spirit:name>
+ <spirit:value spirit:format="float" spirit:resolve="user" spirit:id="PARAM_VALUE.PLL_CLKOUT5_DUTY_CYCLE" spirit:order="191" spirit:configGroups="0 NoDisplay">0.500</spirit:value>
+ </spirit:parameter>
+ <spirit:parameter>
+ <spirit:name>PLL_CLKOUT5_PHASE</spirit:name>
+ <spirit:value spirit:format="float" spirit:resolve="user" spirit:id="PARAM_VALUE.PLL_CLKOUT5_PHASE" spirit:order="192" spirit:configGroups="0 NoDisplay">0.000</spirit:value>
+ </spirit:parameter>
+ <spirit:parameter>
+ <spirit:name>RESET_TYPE</spirit:name>
+ <spirit:displayName>Reset Type</spirit:displayName>
+ <spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.RESET_TYPE" spirit:choiceRef="choice_pairs_a4fbc00c" spirit:order="408" spirit:configGroups="0 NoDisplay">ACTIVE_LOW</spirit:value>
+ </spirit:parameter>
+ <spirit:parameter>
+ <spirit:name>USE_SAFE_CLOCK_STARTUP</spirit:name>
+ <spirit:value spirit:format="bool" spirit:resolve="user" spirit:id="PARAM_VALUE.USE_SAFE_CLOCK_STARTUP" spirit:order="85.5" spirit:configGroups="0; NoDisplay">false</spirit:value>
+ </spirit:parameter>
+ <spirit:parameter>
+ <spirit:name>USE_CLOCK_SEQUENCING</spirit:name>
+ <spirit:value spirit:format="bool" spirit:resolve="user" spirit:id="PARAM_VALUE.USE_CLOCK_SEQUENCING" spirit:order="501" spirit:configGroups="0; NoDisplay">false</spirit:value>
+ </spirit:parameter>
+ <spirit:parameter>
+ <spirit:name>CLKOUT1_SEQUENCE_NUMBER</spirit:name>
+ <spirit:value spirit:format="long" spirit:resolve="user" spirit:id="PARAM_VALUE.CLKOUT1_SEQUENCE_NUMBER" spirit:order="502" spirit:configGroups="0; NoDisplay" spirit:minimum="1" spirit:maximum="7" spirit:rangeType="long">1</spirit:value>
+ </spirit:parameter>
+ <spirit:parameter>
+ <spirit:name>CLKOUT2_SEQUENCE_NUMBER</spirit:name>
+ <spirit:value spirit:format="long" spirit:resolve="user" spirit:id="PARAM_VALUE.CLKOUT2_SEQUENCE_NUMBER" spirit:order="503" spirit:configGroups="0; NoDisplay" spirit:minimum="1" spirit:maximum="7" spirit:rangeType="long">1</spirit:value>
+ </spirit:parameter>
+ <spirit:parameter>
+ <spirit:name>CLKOUT3_SEQUENCE_NUMBER</spirit:name>
+ <spirit:value spirit:format="long" spirit:resolve="user" spirit:id="PARAM_VALUE.CLKOUT3_SEQUENCE_NUMBER" spirit:order="504" spirit:configGroups="0; NoDisplay" spirit:minimum="1" spirit:maximum="7" spirit:rangeType="long">1</spirit:value>
+ </spirit:parameter>
+ <spirit:parameter>
+ <spirit:name>CLKOUT4_SEQUENCE_NUMBER</spirit:name>
+ <spirit:value spirit:format="long" spirit:resolve="user" spirit:id="PARAM_VALUE.CLKOUT4_SEQUENCE_NUMBER" spirit:order="505" spirit:configGroups="0; NoDisplay" spirit:minimum="1" spirit:maximum="7" spirit:rangeType="long">1</spirit:value>
+ </spirit:parameter>
+ <spirit:parameter>
+ <spirit:name>CLKOUT5_SEQUENCE_NUMBER</spirit:name>
+ <spirit:value spirit:format="long" spirit:resolve="user" spirit:id="PARAM_VALUE.CLKOUT5_SEQUENCE_NUMBER" spirit:order="506" spirit:configGroups="0; NoDisplay" spirit:minimum="1" spirit:maximum="7" spirit:rangeType="long">1</spirit:value>
+ </spirit:parameter>
+ <spirit:parameter>
+ <spirit:name>CLKOUT6_SEQUENCE_NUMBER</spirit:name>
+ <spirit:value spirit:format="long" spirit:resolve="user" spirit:id="PARAM_VALUE.CLKOUT6_SEQUENCE_NUMBER" spirit:order="507" spirit:configGroups="0; NoDisplay" spirit:minimum="1" spirit:maximum="7" spirit:rangeType="long">1</spirit:value>
+ </spirit:parameter>
+ <spirit:parameter>
+ <spirit:name>CLKOUT7_SEQUENCE_NUMBER</spirit:name>
+ <spirit:value spirit:format="long" spirit:resolve="user" spirit:id="PARAM_VALUE.CLKOUT7_SEQUENCE_NUMBER" spirit:order="508" spirit:configGroups="0; NoDisplay" spirit:minimum="1" spirit:maximum="7" spirit:rangeType="long">1</spirit:value>
+ </spirit:parameter>
+ <spirit:parameter>
+ <spirit:name>USE_BOARD_FLOW</spirit:name>
+ <spirit:displayName>Generate Board based IO Constraints</spirit:displayName>
+ <spirit:value spirit:format="bool" spirit:resolve="user" spirit:id="PARAM_VALUE.USE_BOARD_FLOW" spirit:order="1.1">false</spirit:value>
+ </spirit:parameter>
+ <spirit:parameter>
+ <spirit:name>CLK_IN1_BOARD_INTERFACE</spirit:name>
+ <spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.CLK_IN1_BOARD_INTERFACE" spirit:choiceRef="choice_pairs_340369e0" spirit:order="13.8">Custom</spirit:value>
+ </spirit:parameter>
+ <spirit:parameter>
+ <spirit:name>CLK_IN2_BOARD_INTERFACE</spirit:name>
+ <spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.CLK_IN2_BOARD_INTERFACE" spirit:choiceRef="choice_pairs_340369e0" spirit:order="13.9">Custom</spirit:value>
+ </spirit:parameter>
+ <spirit:parameter>
+ <spirit:name>DIFF_CLK_IN1_BOARD_INTERFACE</spirit:name>
+ <spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.DIFF_CLK_IN1_BOARD_INTERFACE" spirit:choiceRef="choice_pairs_0920eb1b" spirit:order="13.1">Custom</spirit:value>
+ </spirit:parameter>
+ <spirit:parameter>
+ <spirit:name>DIFF_CLK_IN2_BOARD_INTERFACE</spirit:name>
+ <spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.DIFF_CLK_IN2_BOARD_INTERFACE" spirit:choiceRef="choice_pairs_0920eb1b" spirit:order="13.2">Custom</spirit:value>
+ </spirit:parameter>
+ <spirit:parameter>
+ <spirit:name>AUTO_PRIMITIVE</spirit:name>
+ <spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.AUTO_PRIMITIVE" spirit:choiceRef="choice_pairs_77d3d587" spirit:order="13212">MMCM</spirit:value>
+ </spirit:parameter>
+ <spirit:parameter>
+ <spirit:name>RESET_BOARD_INTERFACE</spirit:name>
+ <spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.RESET_BOARD_INTERFACE" spirit:choiceRef="choice_list_ac75ef1e" spirit:order="21.4">Custom</spirit:value>
+ </spirit:parameter>
+ <spirit:parameter>
+ <spirit:name>ENABLE_CDDC</spirit:name>
+ <spirit:value spirit:format="bool" spirit:resolve="user" spirit:id="PARAM_VALUE.ENABLE_CDDC" spirit:order="509">false</spirit:value>
+ </spirit:parameter>
+ <spirit:parameter>
+ <spirit:name>CDDCDONE_PORT</spirit:name>
+ <spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.CDDCDONE_PORT" spirit:order="510" spirit:configGroups="0 NoDisplay">cddcdone</spirit:value>
+ </spirit:parameter>
+ <spirit:parameter>
+ <spirit:name>CDDCREQ_PORT</spirit:name>
+ <spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.CDDCREQ_PORT" spirit:order="511" spirit:configGroups="0 NoDisplay">cddcreq</spirit:value>
+ </spirit:parameter>
+ <spirit:parameter>
+ <spirit:name>ENABLE_CLKOUTPHY</spirit:name>
+ <spirit:value spirit:format="bool" spirit:resolve="user" spirit:id="PARAM_VALUE.ENABLE_CLKOUTPHY" spirit:order="123.1">false</spirit:value>
+ </spirit:parameter>
+ <spirit:parameter>
+ <spirit:name>CLKOUTPHY_REQUESTED_FREQ</spirit:name>
+ <spirit:value spirit:format="float" spirit:resolve="user" spirit:id="PARAM_VALUE.CLKOUTPHY_REQUESTED_FREQ" spirit:order="123.2" spirit:configGroups="0 NoDisplay">600.000</spirit:value>
+ </spirit:parameter>
+ <spirit:parameter>
+ <spirit:name>CLKOUT1_JITTER</spirit:name>
+ <spirit:displayName>Clkout1 Jitter</spirit:displayName>
+ <spirit:value spirit:format="float" spirit:resolve="user" spirit:id="PARAM_VALUE.CLKOUT1_JITTER" spirit:order="1000">181.828</spirit:value>
+ </spirit:parameter>
+ <spirit:parameter>
+ <spirit:name>CLKOUT1_PHASE_ERROR</spirit:name>
+ <spirit:displayName>Clkout1 Phase</spirit:displayName>
+ <spirit:value spirit:format="float" spirit:resolve="user" spirit:id="PARAM_VALUE.CLKOUT1_PHASE_ERROR" spirit:order="1001">104.359</spirit:value>
+ </spirit:parameter>
+ <spirit:parameter>
+ <spirit:name>CLKOUT2_JITTER</spirit:name>
+ <spirit:displayName>Clkout2 Jitter</spirit:displayName>
+ <spirit:value spirit:format="float" spirit:resolve="user" spirit:id="PARAM_VALUE.CLKOUT2_JITTER" spirit:order="1002">0.0</spirit:value>
+ </spirit:parameter>
+ <spirit:parameter>
+ <spirit:name>CLKOUT2_PHASE_ERROR</spirit:name>
+ <spirit:displayName>Clkout2 Phase</spirit:displayName>
+ <spirit:value spirit:format="float" spirit:resolve="user" spirit:id="PARAM_VALUE.CLKOUT2_PHASE_ERROR" spirit:order="1003">0.0</spirit:value>
+ </spirit:parameter>
+ <spirit:parameter>
+ <spirit:name>CLKOUT3_JITTER</spirit:name>
+ <spirit:displayName>Clkout3 Jitter</spirit:displayName>
+ <spirit:value spirit:format="float" spirit:resolve="user" spirit:id="PARAM_VALUE.CLKOUT3_JITTER" spirit:order="1004">0.0</spirit:value>
+ </spirit:parameter>
+ <spirit:parameter>
+ <spirit:name>CLKOUT3_PHASE_ERROR</spirit:name>
+ <spirit:displayName>Clkout3 Phase</spirit:displayName>
+ <spirit:value spirit:format="float" spirit:resolve="user" spirit:id="PARAM_VALUE.CLKOUT3_PHASE_ERROR" spirit:order="1005">0.0</spirit:value>
+ </spirit:parameter>
+ <spirit:parameter>
+ <spirit:name>CLKOUT4_JITTER</spirit:name>
+ <spirit:displayName>Clkout4 Jitter</spirit:displayName>
+ <spirit:value spirit:format="float" spirit:resolve="user" spirit:id="PARAM_VALUE.CLKOUT4_JITTER" spirit:order="1006">0.0</spirit:value>
+ </spirit:parameter>
+ <spirit:parameter>
+ <spirit:name>CLKOUT4_PHASE_ERROR</spirit:name>
+ <spirit:displayName>Clkout4 Phase</spirit:displayName>
+ <spirit:value spirit:format="float" spirit:resolve="user" spirit:id="PARAM_VALUE.CLKOUT4_PHASE_ERROR" spirit:order="1007">0.0</spirit:value>
+ </spirit:parameter>
+ <spirit:parameter>
+ <spirit:name>CLKOUT5_JITTER</spirit:name>
+ <spirit:displayName>Clkout5 Jitter</spirit:displayName>
+ <spirit:value spirit:format="float" spirit:resolve="user" spirit:id="PARAM_VALUE.CLKOUT5_JITTER" spirit:order="1008">0.0</spirit:value>
+ </spirit:parameter>
+ <spirit:parameter>
+ <spirit:name>CLKOUT5_PHASE_ERROR</spirit:name>
+ <spirit:displayName>Clkout5 Phase</spirit:displayName>
+ <spirit:value spirit:format="float" spirit:resolve="user" spirit:id="PARAM_VALUE.CLKOUT5_PHASE_ERROR" spirit:order="1009">0.0</spirit:value>
+ </spirit:parameter>
+ <spirit:parameter>
+ <spirit:name>CLKOUT6_JITTER</spirit:name>
+ <spirit:displayName>Clkout6 Jitter</spirit:displayName>
+ <spirit:value spirit:format="float" spirit:resolve="user" spirit:id="PARAM_VALUE.CLKOUT6_JITTER" spirit:order="1010">0.0</spirit:value>
+ </spirit:parameter>
+ <spirit:parameter>
+ <spirit:name>CLKOUT6_PHASE_ERROR</spirit:name>
+ <spirit:displayName>Clkout6 Phase</spirit:displayName>
+ <spirit:value spirit:format="float" spirit:resolve="user" spirit:id="PARAM_VALUE.CLKOUT6_PHASE_ERROR" spirit:order="1011">0.0</spirit:value>
+ </spirit:parameter>
+ <spirit:parameter>
+ <spirit:name>CLKOUT7_JITTER</spirit:name>
+ <spirit:displayName>Clkout7 Jitter</spirit:displayName>
+ <spirit:value spirit:format="float" spirit:resolve="user" spirit:id="PARAM_VALUE.CLKOUT7_JITTER" spirit:order="1012">0.0</spirit:value>
+ </spirit:parameter>
+ <spirit:parameter>
+ <spirit:name>CLKOUT7_PHASE_ERROR</spirit:name>
+ <spirit:displayName>Clkout7 Phase</spirit:displayName>
+ <spirit:value spirit:format="float" spirit:resolve="user" spirit:id="PARAM_VALUE.CLKOUT7_PHASE_ERROR" spirit:order="1013">0.0</spirit:value>
+ </spirit:parameter>
+ <spirit:parameter>
+ <spirit:name>INPUT_MODE</spirit:name>
+ <spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.INPUT_MODE" spirit:choiceRef="choice_pairs_f669c2f5" spirit:order="7.8">frequency</spirit:value>
+ </spirit:parameter>
+ <spirit:parameter>
+ <spirit:name>INTERFACE_SELECTION</spirit:name>
+ <spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.INTERFACE_SELECTION" spirit:choiceRef="choice_pairs_8b28f1f7" spirit:order="11.1">Enable_AXI</spirit:value>
+ </spirit:parameter>
+ <spirit:parameter>
+ <spirit:name>AXI_DRP</spirit:name>
+ <spirit:displayName>Write DRP registers</spirit:displayName>
+ <spirit:value spirit:format="bool" spirit:resolve="user" spirit:id="PARAM_VALUE.AXI_DRP" spirit:order="11.12">false</spirit:value>
+ </spirit:parameter>
+ <spirit:parameter>
+ <spirit:name>PHASE_DUTY_CONFIG</spirit:name>
+ <spirit:displayName>Phase Duty Cycle Config</spirit:displayName>
+ <spirit:value spirit:format="bool" spirit:resolve="user" spirit:id="PARAM_VALUE.PHASE_DUTY_CONFIG" spirit:order="11.2">false</spirit:value>
+ </spirit:parameter>
+ </spirit:parameters>
+ <spirit:vendorExtensions>
+ <xilinx:coreExtensions>
+ <xilinx:displayName>Clocking Wizard</xilinx:displayName>
+ <xilinx:xpmLibraries>
+ <xilinx:xpmLibrary>XPM_CDC</xilinx:xpmLibrary>
+ </xilinx:xpmLibraries>
+ <xilinx:coreRevision>11</xilinx:coreRevision>
+ <xilinx:configElementInfos>
+ <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.S_AXI_LITE.ADDR_WIDTH" xilinx:valueSource="auto"/>
+ <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.S_AXI_LITE.ARUSER_WIDTH" xilinx:valueSource="constant"/>
+ <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.S_AXI_LITE.AWUSER_WIDTH" xilinx:valueSource="constant"/>
+ <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.S_AXI_LITE.BUSER_WIDTH" xilinx:valueSource="constant"/>
+ <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.S_AXI_LITE.DATA_WIDTH" xilinx:valueSource="auto"/>
+ <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.S_AXI_LITE.HAS_BRESP" xilinx:valueSource="auto"/>
+ <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.S_AXI_LITE.HAS_BURST" xilinx:valueSource="constant"/>
+ <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.S_AXI_LITE.HAS_CACHE" xilinx:valueSource="constant"/>
+ <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.S_AXI_LITE.HAS_LOCK" xilinx:valueSource="constant"/>
+ <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.S_AXI_LITE.HAS_PROT" xilinx:valueSource="constant"/>
+ <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.S_AXI_LITE.HAS_QOS" xilinx:valueSource="constant"/>
+ <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.S_AXI_LITE.HAS_REGION" xilinx:valueSource="constant"/>
+ <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.S_AXI_LITE.HAS_RRESP" xilinx:valueSource="auto"/>
+ <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.S_AXI_LITE.HAS_WSTRB" xilinx:valueSource="auto"/>
+ <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.S_AXI_LITE.ID_WIDTH" xilinx:valueSource="constant"/>
+ <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.S_AXI_LITE.PROTOCOL" xilinx:valueSource="constant"/>
+ <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.S_AXI_LITE.RUSER_WIDTH" xilinx:valueSource="constant"/>
+ <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.S_AXI_LITE.WUSER_WIDTH" xilinx:valueSource="constant"/>
+ <xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.CLKOUT1_JITTER" xilinx:valueSource="user"/>
+ <xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.CLKOUT1_PHASE_ERROR" xilinx:valueSource="user"/>
+ <xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.CLKOUT1_REQUESTED_OUT_FREQ" xilinx:valueSource="user"/>
+ <xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.MMCM_CLKFBOUT_MULT_F" xilinx:valueSource="user"/>
+ <xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.MMCM_CLKOUT0_DIVIDE_F" xilinx:valueSource="user"/>
+ <xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.RESET_PORT" xilinx:valueSource="user"/>
+ <xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.RESET_TYPE" xilinx:valueSource="user"/>
+ <xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.USE_LOCKED" xilinx:valueSource="user"/>
+ </xilinx:configElementInfos>
+ </xilinx:coreExtensions>
+ <xilinx:packagingInfo>
+ <xilinx:xilinxVersion>2022.2</xilinx:xilinxVersion>
+ <xilinx:checksum xilinx:scope="busInterfaces" xilinx:value="0d9e23d5"/>
+ <xilinx:checksum xilinx:scope="fileGroups" xilinx:value="e96d5789"/>
+ <xilinx:checksum xilinx:scope="ports" xilinx:value="4f3d3737"/>
+ <xilinx:checksum xilinx:scope="hdlParameters" xilinx:value="c11c59cd"/>
+ <xilinx:checksum xilinx:scope="parameters" xilinx:value="63dcade9"/>
+ </xilinx:packagingInfo>
+ </spirit:vendorExtensions>
+</spirit:component>
diff --git a/game.gen/sources_1/ip/clk_wiz_0/clk_wiz_0_board.xdc b/game.gen/sources_1/ip/clk_wiz_0/clk_wiz_0_board.xdc
new file mode 100644
index 0000000000000000000000000000000000000000..3422a8eba3c6e7f364935db84ab8bb8ad1af9318
--- /dev/null
+++ b/game.gen/sources_1/ip/clk_wiz_0/clk_wiz_0_board.xdc
@@ -0,0 +1,2 @@
+#--------------------Physical Constraints-----------------
+
diff --git a/game.gen/sources_1/ip/clk_wiz_0/clk_wiz_0_clk_wiz.v b/game.gen/sources_1/ip/clk_wiz_0/clk_wiz_0_clk_wiz.v
new file mode 100644
index 0000000000000000000000000000000000000000..114157afa65dbe96697fe5e2ae7e55e1f470eea8
--- /dev/null
+++ b/game.gen/sources_1/ip/clk_wiz_0/clk_wiz_0_clk_wiz.v
@@ -0,0 +1,202 @@
+
+// file: clk_wiz_0.v
+//
+// (c) Copyright 2008 - 2013 Xilinx, Inc. All rights reserved.
+//
+// This file contains confidential and proprietary information
+// of Xilinx, Inc. and is protected under U.S. and
+// international copyright and other intellectual property
+// laws.
+//
+// DISCLAIMER
+// This disclaimer is not a license and does not grant any
+// rights to the materials distributed herewith. Except as
+// otherwise provided in a valid license issued to you by
+// Xilinx, and to the maximum extent permitted by applicable
+// law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
+// WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
+// AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
+// BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
+// INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
+// (2) Xilinx shall not be liable (whether in contract or tort,
+// including negligence, or under any other theory of
+// liability) for any loss or damage of any kind or nature
+// related to, arising under or in connection with these
+// materials, including for any direct, or any indirect,
+// special, incidental, or consequential loss or damage
+// (including loss of data, profits, goodwill, or any type of
+// loss or damage suffered as a result of any action brought
+// by a third party) even if such damage or loss was
+// reasonably foreseeable or Xilinx had been advised of the
+// possibility of the same.
+//
+// CRITICAL APPLICATIONS
+// Xilinx products are not designed or intended to be fail-
+// safe, or for use in any application requiring fail-safe
+// performance, such as life-support or safety devices or
+// systems, Class III medical devices, nuclear facilities,
+// applications related to the deployment of airbags, or any
+// other applications that could lead to death, personal
+// injury, or severe property or environmental damage
+// (individually and collectively, "Critical
+// Applications"). Customer assumes the sole risk and
+// liability of any use of Xilinx products in Critical
+// Applications, subject only to applicable laws and
+// regulations governing limitations on product liability.
+//
+// THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
+// PART OF THIS FILE AT ALL TIMES.
+//
+//----------------------------------------------------------------------------
+// User entered comments
+//----------------------------------------------------------------------------
+// None
+//
+//----------------------------------------------------------------------------
+// Output Output Phase Duty Cycle Pk-to-Pk Phase
+// Clock Freq (MHz) (degrees) (%) Jitter (ps) Error (ps)
+//----------------------------------------------------------------------------
+// clk_out1__25.00000______0.000______50.0______181.828____104.359
+//
+//----------------------------------------------------------------------------
+// Input Clock Freq (MHz) Input Jitter (UI)
+//----------------------------------------------------------------------------
+// __primary_________100.000____________0.010
+
+`timescale 1ps/1ps
+
+module clk_wiz_0_clk_wiz
+
+ (// Clock in ports
+ // Clock out ports
+ output clk_out1,
+ // Status and control signals
+ input resetn,
+ input clk_in1
+ );
+ // Input buffering
+ //------------------------------------
+wire clk_in1_clk_wiz_0;
+wire clk_in2_clk_wiz_0;
+ IBUF clkin1_ibufg
+ (.O (clk_in1_clk_wiz_0),
+ .I (clk_in1));
+
+
+
+
+ // Clocking PRIMITIVE
+ //------------------------------------
+
+ // Instantiation of the MMCM PRIMITIVE
+ // * Unused inputs are tied off
+ // * Unused outputs are labeled unused
+
+ wire clk_out1_clk_wiz_0;
+ wire clk_out2_clk_wiz_0;
+ wire clk_out3_clk_wiz_0;
+ wire clk_out4_clk_wiz_0;
+ wire clk_out5_clk_wiz_0;
+ wire clk_out6_clk_wiz_0;
+ wire clk_out7_clk_wiz_0;
+
+ wire [15:0] do_unused;
+ wire drdy_unused;
+ wire psdone_unused;
+ wire locked_int;
+ wire clkfbout_clk_wiz_0;
+ wire clkfbout_buf_clk_wiz_0;
+ wire clkfboutb_unused;
+ wire clkout0b_unused;
+ wire clkout1_unused;
+ wire clkout1b_unused;
+ wire clkout2_unused;
+ wire clkout2b_unused;
+ wire clkout3_unused;
+ wire clkout3b_unused;
+ wire clkout4_unused;
+ wire clkout5_unused;
+ wire clkout6_unused;
+ wire clkfbstopped_unused;
+ wire clkinstopped_unused;
+ wire reset_high;
+
+ MMCME2_ADV
+ #(.BANDWIDTH ("OPTIMIZED"),
+ .CLKOUT4_CASCADE ("FALSE"),
+ .COMPENSATION ("ZHOLD"),
+ .STARTUP_WAIT ("FALSE"),
+ .DIVCLK_DIVIDE (1),
+ .CLKFBOUT_MULT_F (9.125),
+ .CLKFBOUT_PHASE (0.000),
+ .CLKFBOUT_USE_FINE_PS ("FALSE"),
+ .CLKOUT0_DIVIDE_F (36.500),
+ .CLKOUT0_PHASE (0.000),
+ .CLKOUT0_DUTY_CYCLE (0.500),
+ .CLKOUT0_USE_FINE_PS ("FALSE"),
+ .CLKIN1_PERIOD (10.000))
+ mmcm_adv_inst
+ // Output clocks
+ (
+ .CLKFBOUT (clkfbout_clk_wiz_0),
+ .CLKFBOUTB (clkfboutb_unused),
+ .CLKOUT0 (clk_out1_clk_wiz_0),
+ .CLKOUT0B (clkout0b_unused),
+ .CLKOUT1 (clkout1_unused),
+ .CLKOUT1B (clkout1b_unused),
+ .CLKOUT2 (clkout2_unused),
+ .CLKOUT2B (clkout2b_unused),
+ .CLKOUT3 (clkout3_unused),
+ .CLKOUT3B (clkout3b_unused),
+ .CLKOUT4 (clkout4_unused),
+ .CLKOUT5 (clkout5_unused),
+ .CLKOUT6 (clkout6_unused),
+ // Input clock control
+ .CLKFBIN (clkfbout_buf_clk_wiz_0),
+ .CLKIN1 (clk_in1_clk_wiz_0),
+ .CLKIN2 (1'b0),
+ // Tied to always select the primary input clock
+ .CLKINSEL (1'b1),
+ // Ports for dynamic reconfiguration
+ .DADDR (7'h0),
+ .DCLK (1'b0),
+ .DEN (1'b0),
+ .DI (16'h0),
+ .DO (do_unused),
+ .DRDY (drdy_unused),
+ .DWE (1'b0),
+ // Ports for dynamic phase shift
+ .PSCLK (1'b0),
+ .PSEN (1'b0),
+ .PSINCDEC (1'b0),
+ .PSDONE (psdone_unused),
+ // Other control and status signals
+ .LOCKED (locked_int),
+ .CLKINSTOPPED (clkinstopped_unused),
+ .CLKFBSTOPPED (clkfbstopped_unused),
+ .PWRDWN (1'b0),
+ .RST (reset_high));
+ assign reset_high = ~resetn;
+
+// Clock Monitor clock assigning
+//--------------------------------------
+ // Output buffering
+ //-----------------------------------
+
+ BUFG clkf_buf
+ (.O (clkfbout_buf_clk_wiz_0),
+ .I (clkfbout_clk_wiz_0));
+
+
+
+
+
+
+ BUFG clkout1_buf
+ (.O (clk_out1),
+ .I (clk_out1_clk_wiz_0));
+
+
+
+
+endmodule
diff --git a/game.gen/sources_1/ip/clk_wiz_0/clk_wiz_0_ooc.xdc b/game.gen/sources_1/ip/clk_wiz_0/clk_wiz_0_ooc.xdc
new file mode 100644
index 0000000000000000000000000000000000000000..9305712f8063f46a6eaf6dbd3546536f2fe269d5
--- /dev/null
+++ b/game.gen/sources_1/ip/clk_wiz_0/clk_wiz_0_ooc.xdc
@@ -0,0 +1,58 @@
+
+# file: clk_wiz_0_ooc.xdc
+#
+# (c) Copyright 2008 - 2013 Xilinx, Inc. All rights reserved.
+#
+# This file contains confidential and proprietary information
+# of Xilinx, Inc. and is protected under U.S. and
+# international copyright and other intellectual property
+# laws.
+#
+# DISCLAIMER
+# This disclaimer is not a license and does not grant any
+# rights to the materials distributed herewith. Except as
+# otherwise provided in a valid license issued to you by
+# Xilinx, and to the maximum extent permitted by applicable
+# law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
+# WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
+# AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
+# BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
+# INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
+# (2) Xilinx shall not be liable (whether in contract or tort,
+# including negligence, or under any other theory of
+# liability) for any loss or damage of any kind or nature
+# related to, arising under or in connection with these
+# materials, including for any direct, or any indirect,
+# special, incidental, or consequential loss or damage
+# (including loss of data, profits, goodwill, or any type of
+# loss or damage suffered as a result of any action brought
+# by a third party) even if such damage or loss was
+# reasonably foreseeable or Xilinx had been advised of the
+# possibility of the same.
+#
+# CRITICAL APPLICATIONS
+# Xilinx products are not designed or intended to be fail-
+# safe, or for use in any application requiring fail-safe
+# performance, such as life-support or safety devices or
+# systems, Class III medical devices, nuclear facilities,
+# applications related to the deployment of airbags, or any
+# other applications that could lead to death, personal
+# injury, or severe property or environmental damage
+# (individually and collectively, "Critical
+# Applications"). Customer assumes the sole risk and
+# liability of any use of Xilinx products in Critical
+# Applications, subject only to applicable laws and
+# regulations governing limitations on product liability.
+#
+# THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
+# PART OF THIS FILE AT ALL TIMES.
+#
+
+#################
+#DEFAULT CLOCK CONSTRAINTS
+
+############################################################
+# Clock Period Constraints #
+############################################################
+#create_clock -period 10.000 [get_ports clk_in1]
+
diff --git a/game.gen/sources_1/ip/clk_wiz_0/clk_wiz_0_sim_netlist.v b/game.gen/sources_1/ip/clk_wiz_0/clk_wiz_0_sim_netlist.v
new file mode 100644
index 0000000000000000000000000000000000000000..568f15f747b5d06de8e810ec2747f2dbeb43934d
--- /dev/null
+++ b/game.gen/sources_1/ip/clk_wiz_0/clk_wiz_0_sim_netlist.v
@@ -0,0 +1,258 @@
+// Copyright 1986-2022 Xilinx, Inc. All Rights Reserved.
+// --------------------------------------------------------------------------------
+// Tool Version: Vivado v.2022.2 (lin64) Build 3671981 Fri Oct 14 04:59:54 MDT 2022
+// Date : Mon Feb 27 10:46:52 2023
+// Host : LikeUE06 running 64-bit Linux Mint 20.3
+// Command : write_verilog -force -mode funcsim
+// /home/prasic/game/game.gen/sources_1/ip/clk_wiz_0/clk_wiz_0_sim_netlist.v
+// Design : clk_wiz_0
+// Purpose : This verilog netlist is a functional simulation representation of the design and should not be modified
+// or synthesized. This netlist cannot be used for SDF annotated simulation.
+// Device : xc7a100tcsg324-1
+// --------------------------------------------------------------------------------
+`timescale 1 ps / 1 ps
+
+(* NotValidForBitStream *)
+module clk_wiz_0
+ (clk_out1,
+ resetn,
+ clk_in1);
+ output clk_out1;
+ input resetn;
+ input clk_in1;
+
+ (* IBUF_LOW_PWR *) wire clk_in1;
+ wire clk_out1;
+ wire resetn;
+
+ clk_wiz_0_clk_wiz inst
+ (.clk_in1(clk_in1),
+ .clk_out1(clk_out1),
+ .resetn(resetn));
+endmodule
+
+module clk_wiz_0_clk_wiz
+ (clk_out1,
+ resetn,
+ clk_in1);
+ output clk_out1;
+ input resetn;
+ input clk_in1;
+
+ wire clk_in1;
+ wire clk_in1_clk_wiz_0;
+ wire clk_out1;
+ wire clk_out1_clk_wiz_0;
+ wire clkfbout_buf_clk_wiz_0;
+ wire clkfbout_clk_wiz_0;
+ wire reset_high;
+ wire resetn;
+ wire NLW_mmcm_adv_inst_CLKFBOUTB_UNCONNECTED;
+ wire NLW_mmcm_adv_inst_CLKFBSTOPPED_UNCONNECTED;
+ wire NLW_mmcm_adv_inst_CLKINSTOPPED_UNCONNECTED;
+ wire NLW_mmcm_adv_inst_CLKOUT0B_UNCONNECTED;
+ wire NLW_mmcm_adv_inst_CLKOUT1_UNCONNECTED;
+ wire NLW_mmcm_adv_inst_CLKOUT1B_UNCONNECTED;
+ wire NLW_mmcm_adv_inst_CLKOUT2_UNCONNECTED;
+ wire NLW_mmcm_adv_inst_CLKOUT2B_UNCONNECTED;
+ wire NLW_mmcm_adv_inst_CLKOUT3_UNCONNECTED;
+ wire NLW_mmcm_adv_inst_CLKOUT3B_UNCONNECTED;
+ wire NLW_mmcm_adv_inst_CLKOUT4_UNCONNECTED;
+ wire NLW_mmcm_adv_inst_CLKOUT5_UNCONNECTED;
+ wire NLW_mmcm_adv_inst_CLKOUT6_UNCONNECTED;
+ wire NLW_mmcm_adv_inst_DRDY_UNCONNECTED;
+ wire NLW_mmcm_adv_inst_LOCKED_UNCONNECTED;
+ wire NLW_mmcm_adv_inst_PSDONE_UNCONNECTED;
+ wire [15:0]NLW_mmcm_adv_inst_DO_UNCONNECTED;
+
+ (* BOX_TYPE = "PRIMITIVE" *)
+ BUFG clkf_buf
+ (.I(clkfbout_clk_wiz_0),
+ .O(clkfbout_buf_clk_wiz_0));
+ (* BOX_TYPE = "PRIMITIVE" *)
+ (* CAPACITANCE = "DONT_CARE" *)
+ (* IBUF_DELAY_VALUE = "0" *)
+ (* IFD_DELAY_VALUE = "AUTO" *)
+ IBUF #(
+ .CCIO_EN("TRUE"),
+ .IOSTANDARD("DEFAULT"))
+ clkin1_ibufg
+ (.I(clk_in1),
+ .O(clk_in1_clk_wiz_0));
+ (* BOX_TYPE = "PRIMITIVE" *)
+ BUFG clkout1_buf
+ (.I(clk_out1_clk_wiz_0),
+ .O(clk_out1));
+ (* BOX_TYPE = "PRIMITIVE" *)
+ MMCME2_ADV #(
+ .BANDWIDTH("OPTIMIZED"),
+ .CLKFBOUT_MULT_F(9.125000),
+ .CLKFBOUT_PHASE(0.000000),
+ .CLKFBOUT_USE_FINE_PS("FALSE"),
+ .CLKIN1_PERIOD(10.000000),
+ .CLKIN2_PERIOD(0.000000),
+ .CLKOUT0_DIVIDE_F(36.500000),
+ .CLKOUT0_DUTY_CYCLE(0.500000),
+ .CLKOUT0_PHASE(0.000000),
+ .CLKOUT0_USE_FINE_PS("FALSE"),
+ .CLKOUT1_DIVIDE(1),
+ .CLKOUT1_DUTY_CYCLE(0.500000),
+ .CLKOUT1_PHASE(0.000000),
+ .CLKOUT1_USE_FINE_PS("FALSE"),
+ .CLKOUT2_DIVIDE(1),
+ .CLKOUT2_DUTY_CYCLE(0.500000),
+ .CLKOUT2_PHASE(0.000000),
+ .CLKOUT2_USE_FINE_PS("FALSE"),
+ .CLKOUT3_DIVIDE(1),
+ .CLKOUT3_DUTY_CYCLE(0.500000),
+ .CLKOUT3_PHASE(0.000000),
+ .CLKOUT3_USE_FINE_PS("FALSE"),
+ .CLKOUT4_CASCADE("FALSE"),
+ .CLKOUT4_DIVIDE(1),
+ .CLKOUT4_DUTY_CYCLE(0.500000),
+ .CLKOUT4_PHASE(0.000000),
+ .CLKOUT4_USE_FINE_PS("FALSE"),
+ .CLKOUT5_DIVIDE(1),
+ .CLKOUT5_DUTY_CYCLE(0.500000),
+ .CLKOUT5_PHASE(0.000000),
+ .CLKOUT5_USE_FINE_PS("FALSE"),
+ .CLKOUT6_DIVIDE(1),
+ .CLKOUT6_DUTY_CYCLE(0.500000),
+ .CLKOUT6_PHASE(0.000000),
+ .CLKOUT6_USE_FINE_PS("FALSE"),
+ .COMPENSATION("ZHOLD"),
+ .DIVCLK_DIVIDE(1),
+ .IS_CLKINSEL_INVERTED(1'b0),
+ .IS_PSEN_INVERTED(1'b0),
+ .IS_PSINCDEC_INVERTED(1'b0),
+ .IS_PWRDWN_INVERTED(1'b0),
+ .IS_RST_INVERTED(1'b0),
+ .REF_JITTER1(0.010000),
+ .REF_JITTER2(0.010000),
+ .SS_EN("FALSE"),
+ .SS_MODE("CENTER_HIGH"),
+ .SS_MOD_PERIOD(10000),
+ .STARTUP_WAIT("FALSE"))
+ mmcm_adv_inst
+ (.CLKFBIN(clkfbout_buf_clk_wiz_0),
+ .CLKFBOUT(clkfbout_clk_wiz_0),
+ .CLKFBOUTB(NLW_mmcm_adv_inst_CLKFBOUTB_UNCONNECTED),
+ .CLKFBSTOPPED(NLW_mmcm_adv_inst_CLKFBSTOPPED_UNCONNECTED),
+ .CLKIN1(clk_in1_clk_wiz_0),
+ .CLKIN2(1'b0),
+ .CLKINSEL(1'b1),
+ .CLKINSTOPPED(NLW_mmcm_adv_inst_CLKINSTOPPED_UNCONNECTED),
+ .CLKOUT0(clk_out1_clk_wiz_0),
+ .CLKOUT0B(NLW_mmcm_adv_inst_CLKOUT0B_UNCONNECTED),
+ .CLKOUT1(NLW_mmcm_adv_inst_CLKOUT1_UNCONNECTED),
+ .CLKOUT1B(NLW_mmcm_adv_inst_CLKOUT1B_UNCONNECTED),
+ .CLKOUT2(NLW_mmcm_adv_inst_CLKOUT2_UNCONNECTED),
+ .CLKOUT2B(NLW_mmcm_adv_inst_CLKOUT2B_UNCONNECTED),
+ .CLKOUT3(NLW_mmcm_adv_inst_CLKOUT3_UNCONNECTED),
+ .CLKOUT3B(NLW_mmcm_adv_inst_CLKOUT3B_UNCONNECTED),
+ .CLKOUT4(NLW_mmcm_adv_inst_CLKOUT4_UNCONNECTED),
+ .CLKOUT5(NLW_mmcm_adv_inst_CLKOUT5_UNCONNECTED),
+ .CLKOUT6(NLW_mmcm_adv_inst_CLKOUT6_UNCONNECTED),
+ .DADDR({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
+ .DCLK(1'b0),
+ .DEN(1'b0),
+ .DI({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
+ .DO(NLW_mmcm_adv_inst_DO_UNCONNECTED[15:0]),
+ .DRDY(NLW_mmcm_adv_inst_DRDY_UNCONNECTED),
+ .DWE(1'b0),
+ .LOCKED(NLW_mmcm_adv_inst_LOCKED_UNCONNECTED),
+ .PSCLK(1'b0),
+ .PSDONE(NLW_mmcm_adv_inst_PSDONE_UNCONNECTED),
+ .PSEN(1'b0),
+ .PSINCDEC(1'b0),
+ .PWRDWN(1'b0),
+ .RST(reset_high));
+ LUT1 #(
+ .INIT(2'h1))
+ mmcm_adv_inst_i_1
+ (.I0(resetn),
+ .O(reset_high));
+endmodule
+`ifndef GLBL
+`define GLBL
+`timescale 1 ps / 1 ps
+
+module glbl ();
+
+ parameter ROC_WIDTH = 100000;
+ parameter TOC_WIDTH = 0;
+ parameter GRES_WIDTH = 10000;
+ parameter GRES_START = 10000;
+
+//-------- STARTUP Globals --------------
+ wire GSR;
+ wire GTS;
+ wire GWE;
+ wire PRLD;
+ wire GRESTORE;
+ tri1 p_up_tmp;
+ tri (weak1, strong0) PLL_LOCKG = p_up_tmp;
+
+ wire PROGB_GLBL;
+ wire CCLKO_GLBL;
+ wire FCSBO_GLBL;
+ wire [3:0] DO_GLBL;
+ wire [3:0] DI_GLBL;
+
+ reg GSR_int;
+ reg GTS_int;
+ reg PRLD_int;
+ reg GRESTORE_int;
+
+//-------- JTAG Globals --------------
+ wire JTAG_TDO_GLBL;
+ wire JTAG_TCK_GLBL;
+ wire JTAG_TDI_GLBL;
+ wire JTAG_TMS_GLBL;
+ wire JTAG_TRST_GLBL;
+
+ reg JTAG_CAPTURE_GLBL;
+ reg JTAG_RESET_GLBL;
+ reg JTAG_SHIFT_GLBL;
+ reg JTAG_UPDATE_GLBL;
+ reg JTAG_RUNTEST_GLBL;
+
+ reg JTAG_SEL1_GLBL = 0;
+ reg JTAG_SEL2_GLBL = 0 ;
+ reg JTAG_SEL3_GLBL = 0;
+ reg JTAG_SEL4_GLBL = 0;
+
+ reg JTAG_USER_TDO1_GLBL = 1'bz;
+ reg JTAG_USER_TDO2_GLBL = 1'bz;
+ reg JTAG_USER_TDO3_GLBL = 1'bz;
+ reg JTAG_USER_TDO4_GLBL = 1'bz;
+
+ assign (strong1, weak0) GSR = GSR_int;
+ assign (strong1, weak0) GTS = GTS_int;
+ assign (weak1, weak0) PRLD = PRLD_int;
+ assign (strong1, weak0) GRESTORE = GRESTORE_int;
+
+ initial begin
+ GSR_int = 1'b1;
+ PRLD_int = 1'b1;
+ #(ROC_WIDTH)
+ GSR_int = 1'b0;
+ PRLD_int = 1'b0;
+ end
+
+ initial begin
+ GTS_int = 1'b1;
+ #(TOC_WIDTH)
+ GTS_int = 1'b0;
+ end
+
+ initial begin
+ GRESTORE_int = 1'b0;
+ #(GRES_START);
+ GRESTORE_int = 1'b1;
+ #(GRES_WIDTH);
+ GRESTORE_int = 1'b0;
+ end
+
+endmodule
+`endif
diff --git a/game.gen/sources_1/ip/clk_wiz_0/clk_wiz_0_sim_netlist.vhdl b/game.gen/sources_1/ip/clk_wiz_0/clk_wiz_0_sim_netlist.vhdl
new file mode 100644
index 0000000000000000000000000000000000000000..11648facf78b9015945d1e2d12d2bd3e93d06fe6
--- /dev/null
+++ b/game.gen/sources_1/ip/clk_wiz_0/clk_wiz_0_sim_netlist.vhdl
@@ -0,0 +1,196 @@
+-- Copyright 1986-2022 Xilinx, Inc. All Rights Reserved.
+-- --------------------------------------------------------------------------------
+-- Tool Version: Vivado v.2022.2 (lin64) Build 3671981 Fri Oct 14 04:59:54 MDT 2022
+-- Date : Mon Feb 27 10:46:52 2023
+-- Host : LikeUE06 running 64-bit Linux Mint 20.3
+-- Command : write_vhdl -force -mode funcsim
+-- /home/prasic/game/game.gen/sources_1/ip/clk_wiz_0/clk_wiz_0_sim_netlist.vhdl
+-- Design : clk_wiz_0
+-- Purpose : This VHDL netlist is a functional simulation representation of the design and should not be modified or
+-- synthesized. This netlist cannot be used for SDF annotated simulation.
+-- Device : xc7a100tcsg324-1
+-- --------------------------------------------------------------------------------
+library IEEE;
+use IEEE.STD_LOGIC_1164.ALL;
+library UNISIM;
+use UNISIM.VCOMPONENTS.ALL;
+entity clk_wiz_0_clk_wiz is
+ port (
+ clk_out1 : out STD_LOGIC;
+ resetn : in STD_LOGIC;
+ clk_in1 : in STD_LOGIC
+ );
+end clk_wiz_0_clk_wiz;
+
+architecture STRUCTURE of clk_wiz_0_clk_wiz is
+ signal clk_in1_clk_wiz_0 : STD_LOGIC;
+ signal clk_out1_clk_wiz_0 : STD_LOGIC;
+ signal clkfbout_buf_clk_wiz_0 : STD_LOGIC;
+ signal clkfbout_clk_wiz_0 : STD_LOGIC;
+ signal reset_high : STD_LOGIC;
+ signal NLW_mmcm_adv_inst_CLKFBOUTB_UNCONNECTED : STD_LOGIC;
+ signal NLW_mmcm_adv_inst_CLKFBSTOPPED_UNCONNECTED : STD_LOGIC;
+ signal NLW_mmcm_adv_inst_CLKINSTOPPED_UNCONNECTED : STD_LOGIC;
+ signal NLW_mmcm_adv_inst_CLKOUT0B_UNCONNECTED : STD_LOGIC;
+ signal NLW_mmcm_adv_inst_CLKOUT1_UNCONNECTED : STD_LOGIC;
+ signal NLW_mmcm_adv_inst_CLKOUT1B_UNCONNECTED : STD_LOGIC;
+ signal NLW_mmcm_adv_inst_CLKOUT2_UNCONNECTED : STD_LOGIC;
+ signal NLW_mmcm_adv_inst_CLKOUT2B_UNCONNECTED : STD_LOGIC;
+ signal NLW_mmcm_adv_inst_CLKOUT3_UNCONNECTED : STD_LOGIC;
+ signal NLW_mmcm_adv_inst_CLKOUT3B_UNCONNECTED : STD_LOGIC;
+ signal NLW_mmcm_adv_inst_CLKOUT4_UNCONNECTED : STD_LOGIC;
+ signal NLW_mmcm_adv_inst_CLKOUT5_UNCONNECTED : STD_LOGIC;
+ signal NLW_mmcm_adv_inst_CLKOUT6_UNCONNECTED : STD_LOGIC;
+ signal NLW_mmcm_adv_inst_DRDY_UNCONNECTED : STD_LOGIC;
+ signal NLW_mmcm_adv_inst_LOCKED_UNCONNECTED : STD_LOGIC;
+ signal NLW_mmcm_adv_inst_PSDONE_UNCONNECTED : STD_LOGIC;
+ signal NLW_mmcm_adv_inst_DO_UNCONNECTED : STD_LOGIC_VECTOR ( 15 downto 0 );
+ attribute BOX_TYPE : string;
+ attribute BOX_TYPE of clkf_buf : label is "PRIMITIVE";
+ attribute BOX_TYPE of clkin1_ibufg : label is "PRIMITIVE";
+ attribute CAPACITANCE : string;
+ attribute CAPACITANCE of clkin1_ibufg : label is "DONT_CARE";
+ attribute IBUF_DELAY_VALUE : string;
+ attribute IBUF_DELAY_VALUE of clkin1_ibufg : label is "0";
+ attribute IFD_DELAY_VALUE : string;
+ attribute IFD_DELAY_VALUE of clkin1_ibufg : label is "AUTO";
+ attribute BOX_TYPE of clkout1_buf : label is "PRIMITIVE";
+ attribute BOX_TYPE of mmcm_adv_inst : label is "PRIMITIVE";
+begin
+clkf_buf: unisim.vcomponents.BUFG
+ port map (
+ I => clkfbout_clk_wiz_0,
+ O => clkfbout_buf_clk_wiz_0
+ );
+clkin1_ibufg: unisim.vcomponents.IBUF
+ generic map(
+ CCIO_EN => "TRUE",
+ IOSTANDARD => "DEFAULT"
+ )
+ port map (
+ I => clk_in1,
+ O => clk_in1_clk_wiz_0
+ );
+clkout1_buf: unisim.vcomponents.BUFG
+ port map (
+ I => clk_out1_clk_wiz_0,
+ O => clk_out1
+ );
+mmcm_adv_inst: unisim.vcomponents.MMCME2_ADV
+ generic map(
+ BANDWIDTH => "OPTIMIZED",
+ CLKFBOUT_MULT_F => 9.125000,
+ CLKFBOUT_PHASE => 0.000000,
+ CLKFBOUT_USE_FINE_PS => false,
+ CLKIN1_PERIOD => 10.000000,
+ CLKIN2_PERIOD => 0.000000,
+ CLKOUT0_DIVIDE_F => 36.500000,
+ CLKOUT0_DUTY_CYCLE => 0.500000,
+ CLKOUT0_PHASE => 0.000000,
+ CLKOUT0_USE_FINE_PS => false,
+ CLKOUT1_DIVIDE => 1,
+ CLKOUT1_DUTY_CYCLE => 0.500000,
+ CLKOUT1_PHASE => 0.000000,
+ CLKOUT1_USE_FINE_PS => false,
+ CLKOUT2_DIVIDE => 1,
+ CLKOUT2_DUTY_CYCLE => 0.500000,
+ CLKOUT2_PHASE => 0.000000,
+ CLKOUT2_USE_FINE_PS => false,
+ CLKOUT3_DIVIDE => 1,
+ CLKOUT3_DUTY_CYCLE => 0.500000,
+ CLKOUT3_PHASE => 0.000000,
+ CLKOUT3_USE_FINE_PS => false,
+ CLKOUT4_CASCADE => false,
+ CLKOUT4_DIVIDE => 1,
+ CLKOUT4_DUTY_CYCLE => 0.500000,
+ CLKOUT4_PHASE => 0.000000,
+ CLKOUT4_USE_FINE_PS => false,
+ CLKOUT5_DIVIDE => 1,
+ CLKOUT5_DUTY_CYCLE => 0.500000,
+ CLKOUT5_PHASE => 0.000000,
+ CLKOUT5_USE_FINE_PS => false,
+ CLKOUT6_DIVIDE => 1,
+ CLKOUT6_DUTY_CYCLE => 0.500000,
+ CLKOUT6_PHASE => 0.000000,
+ CLKOUT6_USE_FINE_PS => false,
+ COMPENSATION => "ZHOLD",
+ DIVCLK_DIVIDE => 1,
+ IS_CLKINSEL_INVERTED => '0',
+ IS_PSEN_INVERTED => '0',
+ IS_PSINCDEC_INVERTED => '0',
+ IS_PWRDWN_INVERTED => '0',
+ IS_RST_INVERTED => '0',
+ REF_JITTER1 => 0.010000,
+ REF_JITTER2 => 0.010000,
+ SS_EN => "FALSE",
+ SS_MODE => "CENTER_HIGH",
+ SS_MOD_PERIOD => 10000,
+ STARTUP_WAIT => false
+ )
+ port map (
+ CLKFBIN => clkfbout_buf_clk_wiz_0,
+ CLKFBOUT => clkfbout_clk_wiz_0,
+ CLKFBOUTB => NLW_mmcm_adv_inst_CLKFBOUTB_UNCONNECTED,
+ CLKFBSTOPPED => NLW_mmcm_adv_inst_CLKFBSTOPPED_UNCONNECTED,
+ CLKIN1 => clk_in1_clk_wiz_0,
+ CLKIN2 => '0',
+ CLKINSEL => '1',
+ CLKINSTOPPED => NLW_mmcm_adv_inst_CLKINSTOPPED_UNCONNECTED,
+ CLKOUT0 => clk_out1_clk_wiz_0,
+ CLKOUT0B => NLW_mmcm_adv_inst_CLKOUT0B_UNCONNECTED,
+ CLKOUT1 => NLW_mmcm_adv_inst_CLKOUT1_UNCONNECTED,
+ CLKOUT1B => NLW_mmcm_adv_inst_CLKOUT1B_UNCONNECTED,
+ CLKOUT2 => NLW_mmcm_adv_inst_CLKOUT2_UNCONNECTED,
+ CLKOUT2B => NLW_mmcm_adv_inst_CLKOUT2B_UNCONNECTED,
+ CLKOUT3 => NLW_mmcm_adv_inst_CLKOUT3_UNCONNECTED,
+ CLKOUT3B => NLW_mmcm_adv_inst_CLKOUT3B_UNCONNECTED,
+ CLKOUT4 => NLW_mmcm_adv_inst_CLKOUT4_UNCONNECTED,
+ CLKOUT5 => NLW_mmcm_adv_inst_CLKOUT5_UNCONNECTED,
+ CLKOUT6 => NLW_mmcm_adv_inst_CLKOUT6_UNCONNECTED,
+ DADDR(6 downto 0) => B"0000000",
+ DCLK => '0',
+ DEN => '0',
+ DI(15 downto 0) => B"0000000000000000",
+ DO(15 downto 0) => NLW_mmcm_adv_inst_DO_UNCONNECTED(15 downto 0),
+ DRDY => NLW_mmcm_adv_inst_DRDY_UNCONNECTED,
+ DWE => '0',
+ LOCKED => NLW_mmcm_adv_inst_LOCKED_UNCONNECTED,
+ PSCLK => '0',
+ PSDONE => NLW_mmcm_adv_inst_PSDONE_UNCONNECTED,
+ PSEN => '0',
+ PSINCDEC => '0',
+ PWRDWN => '0',
+ RST => reset_high
+ );
+mmcm_adv_inst_i_1: unisim.vcomponents.LUT1
+ generic map(
+ INIT => X"1"
+ )
+ port map (
+ I0 => resetn,
+ O => reset_high
+ );
+end STRUCTURE;
+library IEEE;
+use IEEE.STD_LOGIC_1164.ALL;
+library UNISIM;
+use UNISIM.VCOMPONENTS.ALL;
+entity clk_wiz_0 is
+ port (
+ clk_out1 : out STD_LOGIC;
+ resetn : in STD_LOGIC;
+ clk_in1 : in STD_LOGIC
+ );
+ attribute NotValidForBitStream : boolean;
+ attribute NotValidForBitStream of clk_wiz_0 : entity is true;
+end clk_wiz_0;
+
+architecture STRUCTURE of clk_wiz_0 is
+begin
+inst: entity work.clk_wiz_0_clk_wiz
+ port map (
+ clk_in1 => clk_in1,
+ clk_out1 => clk_out1,
+ resetn => resetn
+ );
+end STRUCTURE;
diff --git a/game.gen/sources_1/ip/clk_wiz_0/clk_wiz_0_stub.v b/game.gen/sources_1/ip/clk_wiz_0/clk_wiz_0_stub.v
new file mode 100644
index 0000000000000000000000000000000000000000..f319e5c4cc5cfc97156d66d3d2520afefaa346af
--- /dev/null
+++ b/game.gen/sources_1/ip/clk_wiz_0/clk_wiz_0_stub.v
@@ -0,0 +1,20 @@
+// Copyright 1986-2022 Xilinx, Inc. All Rights Reserved.
+// --------------------------------------------------------------------------------
+// Tool Version: Vivado v.2022.2 (lin64) Build 3671981 Fri Oct 14 04:59:54 MDT 2022
+// Date : Mon Feb 27 10:46:52 2023
+// Host : LikeUE06 running 64-bit Linux Mint 20.3
+// Command : write_verilog -force -mode synth_stub /home/prasic/game/game.gen/sources_1/ip/clk_wiz_0/clk_wiz_0_stub.v
+// Design : clk_wiz_0
+// Purpose : Stub declaration of top-level module interface
+// Device : xc7a100tcsg324-1
+// --------------------------------------------------------------------------------
+
+// This empty module with port declaration file causes synthesis tools to infer a black box for IP.
+// The synthesis directives are for Synopsys Synplify support to prevent IO buffer insertion.
+// Please paste the declaration into a Verilog source file or add the file as an additional source.
+module clk_wiz_0(clk_out1, resetn, clk_in1)
+/* synthesis syn_black_box black_box_pad_pin="clk_out1,resetn,clk_in1" */;
+ output clk_out1;
+ input resetn;
+ input clk_in1;
+endmodule
diff --git a/game.gen/sources_1/ip/clk_wiz_0/clk_wiz_0_stub.vhdl b/game.gen/sources_1/ip/clk_wiz_0/clk_wiz_0_stub.vhdl
new file mode 100644
index 0000000000000000000000000000000000000000..45381d7d9e152ba9fc1ce4f64c4eaf84b3de7783
--- /dev/null
+++ b/game.gen/sources_1/ip/clk_wiz_0/clk_wiz_0_stub.vhdl
@@ -0,0 +1,29 @@
+-- Copyright 1986-2022 Xilinx, Inc. All Rights Reserved.
+-- --------------------------------------------------------------------------------
+-- Tool Version: Vivado v.2022.2 (lin64) Build 3671981 Fri Oct 14 04:59:54 MDT 2022
+-- Date : Mon Feb 27 10:46:52 2023
+-- Host : LikeUE06 running 64-bit Linux Mint 20.3
+-- Command : write_vhdl -force -mode synth_stub /home/prasic/game/game.gen/sources_1/ip/clk_wiz_0/clk_wiz_0_stub.vhdl
+-- Design : clk_wiz_0
+-- Purpose : Stub declaration of top-level module interface
+-- Device : xc7a100tcsg324-1
+-- --------------------------------------------------------------------------------
+library IEEE;
+use IEEE.STD_LOGIC_1164.ALL;
+
+entity clk_wiz_0 is
+ Port (
+ clk_out1 : out STD_LOGIC;
+ resetn : in STD_LOGIC;
+ clk_in1 : in STD_LOGIC
+ );
+
+end clk_wiz_0;
+
+architecture stub of clk_wiz_0 is
+attribute syn_black_box : boolean;
+attribute black_box_pad_pin : string;
+attribute syn_black_box of stub : architecture is true;
+attribute black_box_pad_pin of stub : architecture is "clk_out1,resetn,clk_in1";
+begin
+end;
diff --git a/game.gen/sources_1/ip/clk_wiz_0/doc/clk_wiz_v6_0_changelog.txt b/game.gen/sources_1/ip/clk_wiz_0/doc/clk_wiz_v6_0_changelog.txt
new file mode 100755
index 0000000000000000000000000000000000000000..02aca2c449e08678c0925e1161b470a6259acc15
--- /dev/null
+++ b/game.gen/sources_1/ip/clk_wiz_0/doc/clk_wiz_v6_0_changelog.txt
@@ -0,0 +1,286 @@
+2022.2:
+ * Version 6.0 (Rev. 11)
+ * Bug Fix: CR Fixes
+ * Other: CR Fixes
+
+2022.1.2:
+ * Version 6.0 (Rev. 10)
+ * No changes
+
+2022.1.1:
+ * Version 6.0 (Rev. 10)
+ * No changes
+
+2022.1:
+ * Version 6.0 (Rev. 10)
+ * Bug Fix: CR Fixes
+ * Other: CR Fixes
+
+2021.2.2:
+ * Version 6.0 (Rev. 9)
+ * No changes
+
+2021.2.1:
+ * Version 6.0 (Rev. 9)
+ * No changes
+
+2021.2:
+ * Version 6.0 (Rev. 9)
+ * Bug Fix: CR Fixes
+ * Other: CR Fixes
+
+2021.1.1:
+ * Version 6.0 (Rev. 8)
+ * No changes
+
+2021.1:
+ * Version 6.0 (Rev. 8)
+ * Bug Fix: Internal GUI fixes
+ * Other: CR Fixes
+
+2020.3:
+ * Version 6.0 (Rev. 7)
+ * Bug Fix: Internal GUI fixes
+ * Other: CR Fixes
+
+2020.2.2:
+ * Version 6.0 (Rev. 6)
+ * No changes
+
+2020.2.1:
+ * Version 6.0 (Rev. 6)
+ * No changes
+
+2020.2:
+ * Version 6.0 (Rev. 6)
+ * Bug Fix: Internal GUI fixes
+ * Other: CR Fixes
+
+2020.1.1:
+ * Version 6.0 (Rev. 5)
+ * No changes
+
+2020.1:
+ * Version 6.0 (Rev. 5)
+ * Bug Fix: Internal GUI fixes
+ * Other: CR Fixes
+
+2019.2.2:
+ * Version 6.0 (Rev. 4)
+ * No changes
+
+2019.2.1:
+ * Version 6.0 (Rev. 4)
+ * No changes
+
+2019.2:
+ * Version 6.0 (Rev. 4)
+ * Bug Fix: Internal GUI fixes
+ * Other: CR Fixes
+
+2019.1.3:
+ * Version 6.0 (Rev. 3)
+ * No changes
+
+2019.1.2:
+ * Version 6.0 (Rev. 3)
+ * No changes
+
+2019.1.1:
+ * Version 6.0 (Rev. 3)
+ * No changes
+
+2019.1:
+ * Version 6.0 (Rev. 3)
+ * Bug Fix: Internal GUI fixes
+ * Other: New family support added
+
+2018.3.1:
+ * Version 6.0 (Rev. 2)
+ * No changes
+
+2018.3:
+ * Version 6.0 (Rev. 2)
+ * Bug Fix: Made input source independent for primary and secondary clock
+ * Other: New family support added
+
+2018.2:
+ * Version 6.0 (Rev. 1)
+ * Bug Fix: Removed vco freq check when Primitive is None
+ * Other: New family support added
+
+2018.1:
+ * Version 6.0
+ * Bug Fix: Bug fixes in Dynamic Reconfiguration feature and Write DRP feature
+ * Bug Fix: Bug fixes for connection issue for s_axi_aresetn pin in IPI
+ * Feature Enhancement: The default value of USE_PHASE_ALIGMENT is updated to false for UltraScale and UltraScale+ devices. Phase Alignment feature uses extra clock routes in UltraScale and UltraScale+ designs when MMCMs are used. These routing resources are wasted when user do not understand when phase alignment is really needed. Now, implementation tools can use these extra clock routing resources for high fanout signals.
+ * Feature Enhancement: A column "Max. freq of buffer" is added in the Output Clock table which shows the maximum frequency that the selected output buffer can support
+ * Other: DRCs added for invalid input values in Override mode
+
+2017.4:
+ * Version 5.4 (Rev. 3)
+ * Bug Fix: Internal GUI issues are fixed for COMPENSATION mode as INTERNAL
+ * Bug Fix: Fixed issue in dynamic reconfiguration of fractional values of M in MMCME3, MMCME4
+
+2017.3:
+ * Version 5.4 (Rev. 2)
+ * General: Internal GUI changes. No effect on the customer design. Added support for aspartan7 devices
+
+2017.2:
+ * Version 5.4 (Rev. 1)
+ * General: Internal GUI changes. No effect on the customer design.
+
+2017.1:
+ * Version 5.4
+ * Port Change: Minor version upgrade. CLR pins are added to the pin list when selected buffer is BUFGCEDIV for ultrascale and ultrascale plus devices.
+ * Other: Added support for new zynq ultrascale plus devices.
+
+2016.4:
+ * Version 5.3 (Rev. 3)
+ * Bug Fix: Internal GUI issues are fixed.
+
+2016.3:
+ * Version 5.3 (Rev. 2)
+ * Feature Enhancement: Added new option "Auto" under PRIMITIVE selection for ultrascale and above devices. This option allows the Wizard to instantiate appropriate primitive for the user inputs.
+ * Feature Enhancement: Added Matched Routing Option for better timing solutions.
+ * Feature Enhancement: Options 'Buffer' and 'Buffer_with_CE' are added to the buffer selection list.
+ * Other: Source HDL files are concatenated into a single file to speed up synthesis and simulation. No changes required by the user
+ * Other: Added support for Spartan7 devices.
+
+2016.2:
+ * Version 5.3 (Rev. 1)
+ * Internal register bit update, no effect on customer designs.
+
+2016.1:
+ * Version 5.3
+ * Added Clock Monitor Feature as part of clocking wizard
+ * DRP registers can be directly written through AXI without resource utilization
+ * Changes to HDL library management to support Vivado IP simulation library
+
+2015.4.2:
+ * Version 5.2 (Rev. 1)
+ * No changes
+
+2015.4.1:
+ * Version 5.2 (Rev. 1)
+ * No changes
+
+2015.4:
+ * Version 5.2 (Rev. 1)
+ * Internal device family change, no functional changes
+
+2015.3:
+ * Version 5.2
+ * IP revision number added to HDL module, library, and include file names, to support designs with both locked and upgraded IP instances
+ * Port Renaming tab is hidden in the GUI in IP Integrator as this feature is not supported
+ * Phase alignment feature is removed for ultrascale PLL as primitve has limited capabilities of supporting this feature
+ * When clocking wizard is targetted on a board part, the frequency values that gets propagated to primary and secondary clocks are displayed in floating number format
+ * Example design and simulation files are delivered in verilog only
+
+2015.2.1:
+ * Version 5.1 (Rev. 6)
+ * No changes
+
+2015.2:
+ * Version 5.1 (Rev. 6)
+ * No changes
+
+2015.1:
+ * Version 5.1 (Rev. 6)
+ * Updated mmcm_pll_filter_lookup and mmcm_pll_lock_lookup functions in the header file for 7-Series and UltraScale devices
+ * Supported devices and production status are now determined automatically, to simplify support for future devices
+
+2014.4.1:
+ * Version 5.1 (Rev. 5)
+ * No changes
+
+2014.4:
+ * Version 5.1 (Rev. 5)
+ * Internal device family change, no functional changes
+ * updates related to the source selection based on board interface for zed board
+
+2014.3:
+ * Version 5.1 (Rev. 4)
+ * Option added to enable dynamic phase and duty cycle for resource optimization in AXI4-Lite interface
+
+2014.2:
+ * Version 5.1 (Rev. 3)
+ * Updated for AXI4-Lite interface locked status register address and bit mapping to align with the pg065
+
+2014.1:
+ * Version 5.1 (Rev. 2)
+ * Updated to use inverted output CLKOUTB 0-3 of Clocking Primitive based on requested 180 phase w.r.t. previous clock
+ * Internal device family name change, no functional changes
+
+2013.4:
+ * Version 5.1 (Rev. 1)
+ * Added support for Ultrascale devices
+ * Updated Board Flow GUI to select the clock interfaces
+ * Fixed issue with Stub file parameter error for BUFR output driver
+
+2013.3:
+ * Version 5.1
+ * Added AXI4-Lite interface to dynamically reconfigure MMCM/PLL
+ * Improved safe clock logic to remove glitches on clock outputs for odd multiples of input clock frequencies
+ * Fixed precision issues between displayed and actual frequencies
+ * Added tool tips to GUI
+ * Added Jitter and Phase error values to IP properties
+ * Added support for Cadence IES and Synopsys VCS simulators
+ * Reduced warnings in synthesis and simulation
+ * Enhanced support for IP Integrator
+
+2013.2:
+ * Version 5.0 (Rev. 1)
+ * Fixed issue with clock constraints for multiple instances of clocking wizard
+ * Updated Life-Cycle status of devices
+
+2013.1:
+ * Version 5.0
+ * Lower case ports for Verilog
+ * Added Safe Clock Startup and Clock Sequencing
+
+(c) Copyright 2008 - 2022 Xilinx, Inc. All rights reserved.
+
+This file contains confidential and proprietary information
+of Xilinx, Inc. and is protected under U.S. and
+international copyright and other intellectual property
+laws.
+
+DISCLAIMER
+This disclaimer is not a license and does not grant any
+rights to the materials distributed herewith. Except as
+otherwise provided in a valid license issued to you by
+Xilinx, and to the maximum extent permitted by applicable
+law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
+WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
+AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
+BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
+INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
+(2) Xilinx shall not be liable (whether in contract or tort,
+including negligence, or under any other theory of
+liability) for any loss or damage of any kind or nature
+related to, arising under or in connection with these
+materials, including for any direct, or any indirect,
+special, incidental, or consequential loss or damage
+(including loss of data, profits, goodwill, or any type of
+loss or damage suffered as a result of any action brought
+by a third party) even if such damage or loss was
+reasonably foreseeable or Xilinx had been advised of the
+possibility of the same.
+
+CRITICAL APPLICATIONS
+Xilinx products are not designed or intended to be fail-
+safe, or for use in any application requiring fail-safe
+performance, such as life-support or safety devices or
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+applications related to the deployment of airbags, or any
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+(individually and collectively, "Critical
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+Applications, subject only to applicable laws and
+regulations governing limitations on product liability.
+
+THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
+PART OF THIS FILE AT ALL TIMES.
diff --git a/game.gen/sources_1/ip/clk_wiz_0/mmcm_pll_drp_func_7s_mmcm.vh b/game.gen/sources_1/ip/clk_wiz_0/mmcm_pll_drp_func_7s_mmcm.vh
new file mode 100755
index 0000000000000000000000000000000000000000..481cd2d0f4bcd479fd5192a0d44df3da3a7f1e08
--- /dev/null
+++ b/game.gen/sources_1/ip/clk_wiz_0/mmcm_pll_drp_func_7s_mmcm.vh
@@ -0,0 +1,671 @@
+///////////////////////////////////////////////////////////////////////////////
+//
+// Company: Xilinx
+// Engineer: Jim Tatsukawa, Karl Kurbjun and Carl Ribbing
+// Date: 7/30/2014
+// Design Name: MMCME2 DRP
+// Module Name: mmcme2_drp_func.h
+// Version: 1.04
+// Target Devices: 7 Series || MMCM
+// Tool versions: 2014.3
+// Description: This header provides the functions necessary to
+// calculate the DRP register values for the V6 MMCM.
+//
+// Revision Notes: 3/12 - Updating lookup_low/lookup_high (CR)
+// 4/13 - Fractional divide function in mmcm_frac_count_calc function. CRS610807
+//
+// Disclaimer: XILINX IS PROVIDING THIS DESIGN, CODE, OR
+// INFORMATION "AS IS" SOLELY FOR USE IN DEVELOPING
+// PROGRAMS AND SOLUTIONS FOR XILINX DEVICES. BY
+// PROVIDING THIS DESIGN, CODE, OR INFORMATION AS
+// ONE POSSIBLE IMPLEMENTATION OF THIS FEATURE,
+// APPLICATION OR STANDARD, XILINX IS MAKING NO
+// REPRESENTATION THAT THIS IMPLEMENTATION IS FREE
+// FROM ANY CLAIMS OF INFRINGEMENT, AND YOU ARE
+// RESPONSIBLE FOR OBTAINING ANY RIGHTS YOU MAY
+// REQUIRE FOR YOUR IMPLEMENTATION. XILINX
+// EXPRESSLY DISCLAIMS ANY WARRANTY WHATSOEVER WITH
+// RESPECT TO THE ADEQUACY OF THE IMPLEMENTATION,
+// INCLUDING BUT NOT LIMITED TO ANY WARRANTIES OR
+// REPRESENTATIONS THAT THIS IMPLEMENTATION IS FREE
+// FROM CLAIMS OF INFRINGEMENT, IMPLIED WARRANTIES
+// OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
+// PURPOSE.
+//
+// (c) Copyright 2009-2010 Xilinx, Inc.
+// All rights reserved.
+//
+///////////////////////////////////////////////////////////////////////////////
+
+// These are user functions that should not be modified. Changes to the defines
+// or code within the functions may alter the accuracy of the calculations.
+
+// Define debug to provide extra messages durring elaboration
+//`define DEBUG 1
+
+// FRAC_PRECISION describes the width of the fractional portion of the fixed
+// point numbers. These should not be modified, they are for development
+// only
+`define FRAC_PRECISION 10
+// FIXED_WIDTH describes the total size for fixed point calculations(int+frac).
+// Warning: L.50 and below will not calculate properly with FIXED_WIDTHs
+// greater than 32
+`define FIXED_WIDTH 32
+
+// This function takes a fixed point number and rounds it to the nearest
+// fractional precision bit.
+function [`FIXED_WIDTH:1] round_frac
+ (
+ // Input is (FIXED_WIDTH-FRAC_PRECISION).FRAC_PRECISION fixed point number
+ input [`FIXED_WIDTH:1] decimal,
+
+ // This describes the precision of the fraction, for example a value
+ // of 1 would modify the fractional so that instead of being a .16
+ // fractional, it would be a .1 (rounded to the nearest 0.5 in turn)
+ input [`FIXED_WIDTH:1] precision
+ );
+
+ begin
+
+ `ifdef DEBUG
+ $display("round_frac - decimal: %h, precision: %h", decimal, precision);
+ `endif
+ // If the fractional precision bit is high then round up
+ if( decimal[(`FRAC_PRECISION-precision)] == 1'b1) begin
+ round_frac = decimal + (1'b1 << (`FRAC_PRECISION-precision));
+ end else begin
+ round_frac = decimal;
+ end
+ `ifdef DEBUG
+ $display("round_frac: %h", round_frac);
+ `endif
+ end
+endfunction
+
+// This function calculates high_time, low_time, w_edge, and no_count
+// of a non-fractional counter based on the divide and duty cycle
+//
+// NOTE: high_time and low_time are returned as integers between 0 and 63
+// inclusive. 64 should equal 6'b000000 (in other words it is okay to
+// ignore the overflow)
+function [13:0] mmcm_pll_divider
+ (
+ input [7:0] divide, // Max divide is 128
+ input [31:0] duty_cycle // Duty cycle is multiplied by 100,000
+ );
+
+ reg [`FIXED_WIDTH:1] duty_cycle_fix;
+
+ // High/Low time is initially calculated with a wider integer to prevent a
+ // calculation error when it overflows to 64.
+ reg [6:0] high_time;
+ reg [6:0] low_time;
+ reg w_edge;
+ reg no_count;
+
+ reg [`FIXED_WIDTH:1] temp;
+
+ begin
+ // Duty Cycle must be between 0 and 1,000
+ if(duty_cycle <=0 || duty_cycle >= 100000) begin
+`ifndef SYNTHESIS
+ $display("ERROR: duty_cycle: %d is invalid", duty_cycle);
+ `endif
+ $finish;
+ end
+
+ // Convert to FIXED_WIDTH-FRAC_PRECISION.FRAC_PRECISION fixed point
+ duty_cycle_fix = (duty_cycle << `FRAC_PRECISION) / 100_000;
+
+ `ifdef DEBUG
+ $display("duty_cycle_fix: %h", duty_cycle_fix);
+ `endif
+
+ // If the divide is 1 nothing needs to be set except the no_count bit.
+ // Other values are dummies
+ if(divide == 7'h01) begin
+ high_time = 7'h01;
+ w_edge = 1'b0;
+ low_time = 7'h01;
+ no_count = 1'b1;
+ end else begin
+ temp = round_frac(duty_cycle_fix*divide, 1);
+
+ // comes from above round_frac
+ high_time = temp[`FRAC_PRECISION+7:`FRAC_PRECISION+1];
+ // If the duty cycle * divide rounded is .5 or greater then this bit
+ // is set.
+ w_edge = temp[`FRAC_PRECISION]; // comes from round_frac
+
+ // If the high time comes out to 0, it needs to be set to at least 1
+ // and w_edge set to 0
+ if(high_time == 7'h00) begin
+ high_time = 7'h01;
+ w_edge = 1'b0;
+ end
+
+ if(high_time == divide) begin
+ high_time = divide - 1;
+ w_edge = 1'b1;
+ end
+
+ // Calculate low_time based on the divide setting and set no_count to
+ // 0 as it is only used when divide is 1.
+ low_time = divide - high_time;
+ no_count = 1'b0;
+ end
+
+ // Set the return value.
+ mmcm_pll_divider = {w_edge,no_count,high_time[5:0],low_time[5:0]};
+ end
+endfunction
+
+// This function calculates mx, delay_time, and phase_mux
+// of a non-fractional counter based on the divide and phase
+//
+// NOTE: The only valid value for the MX bits is 2'b00 to ensure the coarse mux
+// is used.
+function [10:0] mmcm_pll_phase
+ (
+ // divide must be an integer (use fractional if not)
+ // assumed that divide already checked to be valid
+ input [7:0] divide, // Max divide is 128
+
+ // Phase is given in degrees (-360,000 to 360,000)
+ input signed [31:0] phase
+ );
+
+ reg [`FIXED_WIDTH:1] phase_in_cycles;
+ reg [`FIXED_WIDTH:1] phase_fixed;
+ reg [1:0] mx;
+ reg [5:0] delay_time;
+ reg [2:0] phase_mux;
+
+ reg [`FIXED_WIDTH:1] temp;
+
+ begin
+`ifdef DEBUG
+ $display("mmcm_pll_phase-divide:%d,phase:%d",
+ divide, phase);
+`endif
+
+ if ((phase < -360000) || (phase > 360000)) begin
+`ifndef SYNTHESIS
+ $display("ERROR: phase of $phase is not between -360000 and 360000");
+ `endif
+ $finish;
+ end
+
+ // If phase is less than 0, convert it to a positive phase shift
+ // Convert to (FIXED_WIDTH-FRAC_PRECISION).FRAC_PRECISION fixed point
+ if(phase < 0) begin
+ phase_fixed = ( (phase + 360000) << `FRAC_PRECISION ) / 1000;
+ end else begin
+ phase_fixed = ( phase << `FRAC_PRECISION ) / 1000;
+ end
+
+ // Put phase in terms of decimal number of vco clock cycles
+ phase_in_cycles = ( phase_fixed * divide ) / 360;
+
+`ifdef DEBUG
+ $display("phase_in_cycles: %h", phase_in_cycles);
+`endif
+
+
+ temp = round_frac(phase_in_cycles, 3);
+
+ // set mx to 2'b00 that the phase mux from the VCO is enabled
+ mx = 2'b00;
+ phase_mux = temp[`FRAC_PRECISION:`FRAC_PRECISION-2];
+ delay_time = temp[`FRAC_PRECISION+6:`FRAC_PRECISION+1];
+
+ `ifdef DEBUG
+ $display("temp: %h", temp);
+ `endif
+
+ // Setup the return value
+ mmcm_pll_phase={mx, phase_mux, delay_time};
+ end
+endfunction
+
+// This function takes the divide value and outputs the necessary lock values
+function [39:0] mmcm_pll_lock_lookup
+ (
+ input [6:0] divide // Max divide is 64
+ );
+
+ reg [2559:0] lookup;
+
+ begin
+ lookup = {
+ // This table is composed of:
+ // LockRefDly_LockFBDly_LockCnt_LockSatHigh_UnlockCnt
+ 40'b00110_00110_1111101000_1111101001_0000000001,
+ 40'b00110_00110_1111101000_1111101001_0000000001,
+ 40'b01000_01000_1111101000_1111101001_0000000001,
+ 40'b01011_01011_1111101000_1111101001_0000000001,
+ 40'b01110_01110_1111101000_1111101001_0000000001,
+ 40'b10001_10001_1111101000_1111101001_0000000001,
+ 40'b10011_10011_1111101000_1111101001_0000000001,
+ 40'b10110_10110_1111101000_1111101001_0000000001,
+ 40'b11001_11001_1111101000_1111101001_0000000001,
+ 40'b11100_11100_1111101000_1111101001_0000000001,
+ 40'b11111_11111_1110000100_1111101001_0000000001,
+ 40'b11111_11111_1100111001_1111101001_0000000001,
+ 40'b11111_11111_1011101110_1111101001_0000000001,
+ 40'b11111_11111_1010111100_1111101001_0000000001,
+ 40'b11111_11111_1010001010_1111101001_0000000001,
+ 40'b11111_11111_1001110001_1111101001_0000000001,
+ 40'b11111_11111_1000111111_1111101001_0000000001,
+ 40'b11111_11111_1000100110_1111101001_0000000001,
+ 40'b11111_11111_1000001101_1111101001_0000000001,
+ 40'b11111_11111_0111110100_1111101001_0000000001,
+ 40'b11111_11111_0111011011_1111101001_0000000001,
+ 40'b11111_11111_0111000010_1111101001_0000000001,
+ 40'b11111_11111_0110101001_1111101001_0000000001,
+ 40'b11111_11111_0110010000_1111101001_0000000001,
+ 40'b11111_11111_0110010000_1111101001_0000000001,
+ 40'b11111_11111_0101110111_1111101001_0000000001,
+ 40'b11111_11111_0101011110_1111101001_0000000001,
+ 40'b11111_11111_0101011110_1111101001_0000000001,
+ 40'b11111_11111_0101000101_1111101001_0000000001,
+ 40'b11111_11111_0101000101_1111101001_0000000001,
+ 40'b11111_11111_0100101100_1111101001_0000000001,
+ 40'b11111_11111_0100101100_1111101001_0000000001,
+ 40'b11111_11111_0100101100_1111101001_0000000001,
+ 40'b11111_11111_0100010011_1111101001_0000000001,
+ 40'b11111_11111_0100010011_1111101001_0000000001,
+ 40'b11111_11111_0100010011_1111101001_0000000001,
+ 40'b11111_11111_0011111010_1111101001_0000000001,
+ 40'b11111_11111_0011111010_1111101001_0000000001,
+ 40'b11111_11111_0011111010_1111101001_0000000001,
+ 40'b11111_11111_0011111010_1111101001_0000000001,
+ 40'b11111_11111_0011111010_1111101001_0000000001,
+ 40'b11111_11111_0011111010_1111101001_0000000001,
+ 40'b11111_11111_0011111010_1111101001_0000000001,
+ 40'b11111_11111_0011111010_1111101001_0000000001,
+ 40'b11111_11111_0011111010_1111101001_0000000001,
+ 40'b11111_11111_0011111010_1111101001_0000000001,
+ 40'b11111_11111_0011111010_1111101001_0000000001,
+ 40'b11111_11111_0011111010_1111101001_0000000001,
+ 40'b11111_11111_0011111010_1111101001_0000000001,
+ 40'b11111_11111_0011111010_1111101001_0000000001,
+ 40'b11111_11111_0011111010_1111101001_0000000001,
+ 40'b11111_11111_0011111010_1111101001_0000000001,
+ 40'b11111_11111_0011111010_1111101001_0000000001,
+ 40'b11111_11111_0011111010_1111101001_0000000001,
+ 40'b11111_11111_0011111010_1111101001_0000000001,
+ 40'b11111_11111_0011111010_1111101001_0000000001,
+ 40'b11111_11111_0011111010_1111101001_0000000001,
+ 40'b11111_11111_0011111010_1111101001_0000000001,
+ 40'b11111_11111_0011111010_1111101001_0000000001,
+ 40'b11111_11111_0011111010_1111101001_0000000001,
+ 40'b11111_11111_0011111010_1111101001_0000000001,
+ 40'b11111_11111_0011111010_1111101001_0000000001,
+ 40'b11111_11111_0011111010_1111101001_0000000001,
+ 40'b11111_11111_0011111010_1111101001_0000000001
+ };
+
+ // Set lookup_entry with the explicit bits from lookup with a part select
+ mmcm_pll_lock_lookup = lookup[ ((64-divide)*40) +: 40];
+ `ifdef DEBUG
+ $display("lock_lookup: %b", mmcm_pll_lock_lookup);
+ `endif
+ end
+endfunction
+
+// This function takes the divide value and the bandwidth setting of the MMCM
+// and outputs the digital filter settings necessary.
+function [9:0] mmcm_pll_filter_lookup
+ (
+ input [6:0] divide, // Max divide is 64
+ input [8*9:0] BANDWIDTH
+ );
+
+ reg [639:0] lookup_low;
+ reg [639:0] lookup_high;
+
+ reg [9:0] lookup_entry;
+
+ begin
+ lookup_low = {
+ // CP_RES_LFHF
+ 10'b0010_1111_00,
+ 10'b0010_1111_00,
+ 10'b0010_1111_00,
+ 10'b0010_1111_00,
+ 10'b0010_0111_00,
+ 10'b0010_1011_00,
+ 10'b0010_1101_00,
+ 10'b0010_0011_00,
+ 10'b0010_0101_00,
+ 10'b0010_0101_00,
+ 10'b0010_1001_00,
+ 10'b0010_1110_00,
+ 10'b0010_1110_00,
+ 10'b0010_1110_00,
+ 10'b0010_1110_00,
+ 10'b0010_0001_00,
+ 10'b0010_0001_00,
+ 10'b0010_0001_00,
+ 10'b0010_0110_00,
+ 10'b0010_0110_00,
+ 10'b0010_0110_00,
+ 10'b0010_0110_00,
+ 10'b0010_0110_00,
+ 10'b0010_0110_00,
+ 10'b0010_0110_00,
+ 10'b0010_1010_00,
+ 10'b0010_1010_00,
+ 10'b0010_1010_00,
+ 10'b0010_1010_00,
+ 10'b0010_1010_00,
+ 10'b0010_1100_00,
+ 10'b0010_1100_00,
+ 10'b0010_1100_00,
+ 10'b0010_1100_00,
+ 10'b0010_1100_00,
+ 10'b0010_1100_00,
+ 10'b0010_1100_00,
+ 10'b0010_1100_00,
+ 10'b0010_1100_00,
+ 10'b0010_1100_00,
+ 10'b0010_1100_00,
+ 10'b0010_1100_00,
+ 10'b0010_1100_00,
+ 10'b0010_1100_00,
+ 10'b0010_1100_00,
+ 10'b0010_1100_00,
+ 10'b0010_1100_00,
+ 10'b0010_0010_00,
+ 10'b0010_0010_00,
+ 10'b0010_0010_00,
+ 10'b0010_0010_00,
+ 10'b0010_0010_00,
+ 10'b0010_0010_00,
+ 10'b0010_0010_00,
+ 10'b0010_0010_00,
+ 10'b0010_0010_00,
+ 10'b0010_0010_00,
+ 10'b0010_0010_00,
+ 10'b0010_0010_00,
+ 10'b0010_0010_00,
+ 10'b0010_0010_00,
+ 10'b0010_0010_00,
+ 10'b0010_0010_00,
+ 10'b0010_0010_00
+ };
+
+ lookup_high = {
+ // CP_RES_LFHF
+ 10'b0010_1111_00,
+ 10'b0100_1111_00,
+ 10'b0101_1011_00,
+ 10'b0111_0111_00,
+ 10'b1101_0111_00,
+ 10'b1110_1011_00,
+ 10'b1110_1101_00,
+ 10'b1111_0011_00,
+ 10'b1110_0101_00,
+ 10'b1111_0101_00,
+ 10'b1111_1001_00,
+ 10'b1101_0001_00,
+ 10'b1111_1001_00,
+ 10'b1111_1001_00,
+ 10'b1111_1001_00,
+ 10'b1111_1001_00,
+ 10'b1111_0101_00,
+ 10'b1111_0101_00,
+ 10'b1100_0001_00,
+ 10'b1100_0001_00,
+ 10'b1100_0001_00,
+ 10'b0101_1100_00,
+ 10'b0101_1100_00,
+ 10'b0101_1100_00,
+ 10'b0101_1100_00,
+ 10'b0011_0100_00,
+ 10'b0011_0100_00,
+ 10'b0011_0100_00,
+ 10'b0011_0100_00,
+ 10'b0011_0100_00,
+ 10'b0011_0100_00,
+ 10'b0011_0100_00,
+ 10'b0011_0100_00,
+ 10'b0011_0100_00,
+ 10'b0011_0100_00,
+ 10'b0011_0100_00,
+ 10'b0011_0100_00,
+ 10'b0011_0100_00,
+ 10'b0011_0100_00,
+ 10'b0011_0100_00,
+ 10'b0011_0100_00,
+ 10'b0010_1000_00,
+ 10'b0010_1000_00,
+ 10'b0010_1000_00,
+ 10'b0010_1000_00,
+ 10'b0010_1000_00,
+ 10'b0111_0001_00,
+ 10'b0111_0001_00,
+ 10'b0100_1100_00,
+ 10'b0100_1100_00,
+ 10'b0100_1100_00,
+ 10'b0100_1100_00,
+ 10'b0110_0001_00,
+ 10'b0110_0001_00,
+ 10'b0101_0110_00,
+ 10'b0101_0110_00,
+ 10'b0101_0110_00,
+ 10'b0010_0100_00,
+ 10'b0010_0100_00,
+ 10'b0010_0100_00,
+ 10'b0010_0100_00,
+ 10'b0100_1010_00,
+ 10'b0011_1100_00,
+ 10'b0011_1100_00
+ };
+
+ // Set lookup_entry with the explicit bits from lookup with a part select
+ if(BANDWIDTH == "LOW") begin
+ // Low Bandwidth
+ mmcm_pll_filter_lookup = lookup_low[ ((64-divide)*10) +: 10];
+ end else begin
+ // High or optimized bandwidth
+ mmcm_pll_filter_lookup = lookup_high[ ((64-divide)*10) +: 10];
+ end
+
+ `ifdef DEBUG
+ $display("filter_lookup: %b", mmcm_pll_filter_lookup);
+ `endif
+ end
+endfunction
+
+// This function takes in the divide, phase, and duty cycle
+// setting to calculate the upper and lower counter registers.
+function [37:0] mmcm_pll_count_calc
+ (
+ input [7:0] divide, // Max divide is 128
+ input signed [31:0] phase,
+ input [31:0] duty_cycle // Multiplied by 100,000
+ );
+
+ reg [13:0] div_calc;
+ reg [16:0] phase_calc;
+
+ begin
+ `ifdef DEBUG
+ $display("mmcm_pll_count_calc- divide:%h, phase:%d, duty_cycle:%d",
+ divide, phase, duty_cycle);
+ `endif
+
+ // w_edge[13], no_count[12], high_time[11:6], low_time[5:0]
+ div_calc = mmcm_pll_divider(divide, duty_cycle);
+ // mx[10:9], pm[8:6], dt[5:0]
+ phase_calc = mmcm_pll_phase(divide, phase);
+
+ // Return value is the upper and lower address of counter
+ // Upper address is:
+ // RESERVED [31:26]
+ // MX [25:24]
+ // EDGE [23]
+ // NOCOUNT [22]
+ // DELAY_TIME [21:16]
+ // Lower Address is:
+ // PHASE_MUX [15:13]
+ // RESERVED [12]
+ // HIGH_TIME [11:6]
+ // LOW_TIME [5:0]
+
+ `ifdef DEBUG
+ $display("div:%d dc:%d phase:%d ht:%d lt:%d ed:%d nc:%d mx:%d dt:%d pm:%d",
+ divide, duty_cycle, phase, div_calc[11:6], div_calc[5:0],
+ div_calc[13], div_calc[12],
+ phase_calc[16:15], phase_calc[5:0], phase_calc[14:12]);
+ `endif
+
+ mmcm_pll_count_calc =
+ {
+ // Upper Address
+ 6'h00, phase_calc[10:9], div_calc[13:12], phase_calc[5:0],
+ // Lower Address
+ phase_calc[8:6], 1'b0, div_calc[11:0]
+ };
+ end
+endfunction
+
+
+// This function takes in the divide, phase, and duty cycle
+// setting to calculate the upper and lower counter registers.
+// for fractional multiply/divide functions.
+//
+//
+function [37:0] mmcm_frac_count_calc
+ (
+ input [7:0] divide, // Max divide is 128
+ input signed [31:0] phase,
+ input [31:0] duty_cycle, // Multiplied by 1,000
+ input [9:0] frac // Multiplied by 1000
+ );
+
+ //Required for fractional divide calculations
+ reg [7:0] lt_frac;
+ reg [7:0] ht_frac;
+
+ reg /*[7:0]*/ wf_fall_frac;
+ reg /*[7:0]*/ wf_rise_frac;
+
+ reg [31:0] a;
+ reg [7:0] pm_rise_frac_filtered ;
+ reg [7:0] pm_fall_frac_filtered ;
+ reg [7:0] clkout0_divide_int;
+ reg [2:0] clkout0_divide_frac;
+ reg [7:0] even_part_high;
+ reg [7:0] even_part_low;
+
+ reg [7:0] odd;
+ reg [7:0] odd_and_frac;
+
+ reg [7:0] pm_fall;
+ reg [7:0] pm_rise;
+ reg [7:0] dt;
+ reg [7:0] dt_int;
+ reg [63:0] dt_calc;
+
+ reg [7:0] pm_rise_frac;
+ reg [7:0] pm_fall_frac;
+
+ reg [31:0] a_per_in_octets;
+ reg [31:0] a_phase_in_cycles;
+
+ parameter precision = 0.125;
+
+ reg [31:0] phase_fixed; // changed to 31:0 from 32:1 jt 5/2/11
+ reg [31: 0] phase_pos;
+ reg [31: 0] phase_vco;
+ reg [31:0] temp;// changed to 31:0 from 32:1 jt 5/2/11
+ reg [13:0] div_calc;
+ reg [16:0] phase_calc;
+
+ begin
+ `ifdef DEBUG
+ $display("mmcm_frac_count_calc- divide:%h, phase:%d, duty_cycle:%d",
+ divide, phase, duty_cycle);
+ `endif
+
+ //convert phase to fixed
+ if ((phase < -360000) || (phase > 360000)) begin
+`ifndef SYNTHESIS
+ $display("ERROR: phase of $phase is not between -360000 and 360000");
+ `endif
+ $finish;
+ end
+
+
+ // Return value is
+ // Transfer data
+ // RESERVED [37:36]
+ // FRAC_TIME [35:33]
+ // FRAC_WF_FALL [32]
+ // Upper address is:
+ // RESERVED [31:26]
+ // MX [25:24]
+ // EDGE [23]
+ // NOCOUNT [22]
+ // DELAY_TIME [21:16]
+ // Lower Address is:
+ // PHASE_MUX [15:13]
+ // RESERVED [12]
+ // HIGH_TIME [11:6]
+ // LOW_TIME [5:0]
+
+
+
+ clkout0_divide_frac = frac / 125;
+ clkout0_divide_int = divide;
+
+ even_part_high = clkout0_divide_int >> 1;//$rtoi(clkout0_divide_int / 2);
+ even_part_low = even_part_high;
+
+ odd = clkout0_divide_int - even_part_high - even_part_low;
+ odd_and_frac = (8*odd) + clkout0_divide_frac;
+
+ lt_frac = even_part_high - (odd_and_frac <= 9);//IF(odd_and_frac>9,even_part_high, even_part_high - 1)
+ ht_frac = even_part_low - (odd_and_frac <= 8);//IF(odd_and_frac>8,even_part_low, even_part_low- 1)
+
+ pm_fall = {odd[6:0],2'b00} + {6'h00, clkout0_divide_frac[2:1]}; // using >> instead of clkout0_divide_frac / 2
+ pm_rise = 0; //0
+
+ wf_fall_frac = ((odd_and_frac >=2) && (odd_and_frac <=9)) || ((clkout0_divide_frac == 1) && (clkout0_divide_int == 2));//CRS610807
+ wf_rise_frac = (odd_and_frac >=1) && (odd_and_frac <=8);//IF(odd_and_frac>=1,IF(odd_and_frac <= 8,1,0),0)
+
+
+
+ //Calculate phase in fractional cycles
+ a_per_in_octets = (8 * divide) + (frac / 125) ;
+ a_phase_in_cycles = (phase+10) * a_per_in_octets / 360000 ;//Adding 1 due to rounding errors
+ pm_rise_frac = (a_phase_in_cycles[7:0] ==8'h00)?8'h00:a_phase_in_cycles[7:0] - {a_phase_in_cycles[7:3],3'b000};
+
+ dt_calc = ((phase+10) * a_per_in_octets / 8 )/360000 ;//TRUNC(phase* divide / 360); //or_simply (a_per_in_octets / 8)
+ dt = dt_calc[7:0];
+
+ pm_rise_frac_filtered = (pm_rise_frac >=8) ? (pm_rise_frac ) - 8: pm_rise_frac ; //((phase_fixed * (divide + frac / 1000)) / 360) - {pm_rise_frac[7:3],3'b000};//$rtoi(clkout0_phase * clkout0_divide / 45);//a;
+
+ dt_int = dt + (& pm_rise_frac[7:4]); //IF(pm_rise_overwriting>7,dt+1,dt)
+ pm_fall_frac = pm_fall + pm_rise_frac;
+ pm_fall_frac_filtered = pm_fall + pm_rise_frac - {pm_fall_frac[7:3], 3'b000};
+
+ div_calc = mmcm_pll_divider(divide, duty_cycle); //Use to determine edge[7], no count[6]
+ phase_calc = mmcm_pll_phase(divide, phase);// returns{mx[1:0], phase_mux[2:0], delay_time[5:0]}
+
+ mmcm_frac_count_calc[37:0] =
+ { 2'b00, pm_fall_frac_filtered[2:0], wf_fall_frac,
+ 1'b0, clkout0_divide_frac[2:0], 1'b1, wf_rise_frac, phase_calc[10:9], div_calc[13:12], dt[5:0],
+ pm_rise_frac_filtered[2], pm_rise_frac_filtered[1], pm_rise_frac_filtered[0], 1'b0, ht_frac[5:0], lt_frac[5:0]
+ } ;
+
+ `ifdef DEBUG
+ $display("-%d.%d p%d>> :DADDR_9_15 frac30to28.frac_en.wf_r_frac.dt:%b%d%d_%b:DADDR_7_13 pm_f_frac_filtered_29to27.wf_f_frac_26:%b%d:DADDR_8_14.pm_r_frac_filt_15to13.ht_frac.lt_frac:%b%b%b:", divide, frac, phase, clkout0_divide_frac, 1, wf_rise_frac, dt, pm_fall_frac_filtered, wf_fall_frac, pm_rise_frac_filtered, ht_frac, lt_frac);
+ `endif
+
+ end
+endfunction
+
diff --git a/game.gen/sources_1/ip/clk_wiz_0/mmcm_pll_drp_func_7s_pll.vh b/game.gen/sources_1/ip/clk_wiz_0/mmcm_pll_drp_func_7s_pll.vh
new file mode 100755
index 0000000000000000000000000000000000000000..d34dbe728f2561b75d3502c80f5c2768979d6fb4
--- /dev/null
+++ b/game.gen/sources_1/ip/clk_wiz_0/mmcm_pll_drp_func_7s_pll.vh
@@ -0,0 +1,531 @@
+///////////////////////////////////////////////////////////////////////////////
+//
+// Company: Xilinx
+// Engineer: Jim Tatsukawa, Karl Kurbjun and Carl Ribbing
+// Date: 7/30/2014
+// Design Name: PLLE2 DRP
+// Module Name: plle2_drp_func.h
+// Version: 2.00
+// Target Devices: 7 Series || PLL
+// Tool versions: 2014.3
+// Description: This header provides the functions necessary to
+// calculate the DRP register values for the V6 PLL.
+// Updated for CR663854.
+//
+// Disclaimer: XILINX IS PROVIDING THIS DESIGN, CODE, OR
+// INFORMATION "AS IS" SOLELY FOR USE IN DEVELOPING
+// PROGRAMS AND SOLUTIONS FOR XILINX DEVICES. BY
+// PROVIDING THIS DESIGN, CODE, OR INFORMATION AS
+// ONE POSSIBLE IMPLEMENTATION OF THIS FEATURE,
+// APPLICATION OR STANDARD, XILINX IS MAKING NO
+// REPRESENTATION THAT THIS IMPLEMENTATION IS FREE
+// FROM ANY CLAIMS OF INFRINGEMENT, AND YOU ARE
+// RESPONSIBLE FOR OBTAINING ANY RIGHTS YOU MAY
+// REQUIRE FOR YOUR IMPLEMENTATION. XILINX
+// EXPRESSLY DISCLAIMS ANY WARRANTY WHATSOEVER WITH
+// RESPECT TO THE ADEQUACY OF THE IMPLEMENTATION,
+// INCLUDING BUT NOT LIMITED TO ANY WARRANTIES OR
+// REPRESENTATIONS THAT THIS IMPLEMENTATION IS FREE
+// FROM CLAIMS OF INFRINGEMENT, IMPLIED WARRANTIES
+// OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
+// PURPOSE.
+//
+// (c) Copyright 2009-2010 Xilinx, Inc.
+// All rights reserved.
+//
+///////////////////////////////////////////////////////////////////////////////
+
+// These are user functions that should not be modified. Changes to the defines
+// or code within the functions may alter the accuracy of the calculations.
+
+// Define debug to provide extra messages durring elaboration
+//`define DEBUG 1
+
+// FRAC_PRECISION describes the width of the fractional portion of the fixed
+// point numbers. These should not be modified, they are for development
+// only
+`define FRAC_PRECISION 10
+// FIXED_WIDTH describes the total size for fixed point calculations(int+frac).
+// Warning: L.50 and below will not calculate properly with FIXED_WIDTHs
+// greater than 32
+`define FIXED_WIDTH 32
+
+// This function takes a fixed point number and rounds it to the nearest
+// fractional precision bit.
+function [`FIXED_WIDTH:1] round_frac
+ (
+ // Input is (FIXED_WIDTH-FRAC_PRECISION).FRAC_PRECISION fixed point number
+ input [`FIXED_WIDTH:1] decimal,
+
+ // This describes the precision of the fraction, for example a value
+ // of 1 would modify the fractional so that instead of being a .16
+ // fractional, it would be a .1 (rounded to the nearest 0.5 in turn)
+ input [`FIXED_WIDTH:1] precision
+ );
+
+ begin
+
+`ifdef DEBUG
+ $display("round_frac - decimal: %h, precision: %h", decimal, precision);
+`endif
+ // If the fractional precision bit is high then round up
+ if( decimal[(`FRAC_PRECISION-precision)] == 1'b1) begin
+ round_frac = decimal + (1'b1 << (`FRAC_PRECISION-precision));
+ end else begin
+ round_frac = decimal;
+ end
+`ifdef DEBUG
+ $display("round_frac: %h", round_frac);
+`endif
+ end
+endfunction
+
+// This function calculates high_time, low_time, w_edge, and no_count
+// of a non-fractional counter based on the divide and duty cycle
+//
+// NOTE: high_time and low_time are returned as integers between 0 and 63
+// inclusive. 64 should equal 6'b000000 (in other words it is okay to
+// ignore the overflow)
+function [13:0] mmcm_pll_divider
+ (
+ input [7:0] divide, // Max divide is 128
+ input [31:0] duty_cycle // Duty cycle is multiplied by 100,000
+ );
+
+ reg [`FIXED_WIDTH:1] duty_cycle_fix;
+
+ // High/Low time is initially calculated with a wider integer to prevent a
+ // calculation error when it overflows to 64.
+ reg [6:0] high_time;
+ reg [6:0] low_time;
+ reg w_edge;
+ reg no_count;
+
+ reg [`FIXED_WIDTH:1] temp;
+
+ begin
+ // Duty Cycle must be between 0 and 1,000
+ if(duty_cycle <=0 || duty_cycle >= 100000) begin
+`ifndef SYNTHESIS
+ $display("ERROR: duty_cycle: %d is invalid", duty_cycle);
+ `endif
+ $finish;
+ end
+
+ // Convert to FIXED_WIDTH-FRAC_PRECISION.FRAC_PRECISION fixed point
+ duty_cycle_fix = (duty_cycle << `FRAC_PRECISION) / 100_000;
+
+`ifdef DEBUG
+ $display("duty_cycle_fix: %h", duty_cycle_fix);
+`endif
+
+ // If the divide is 1 nothing needs to be set except the no_count bit.
+ // Other values are dummies
+ if(divide == 7'h01) begin
+ high_time = 7'h01;
+ w_edge = 1'b0;
+ low_time = 7'h01;
+ no_count = 1'b1;
+ end else begin
+ temp = round_frac(duty_cycle_fix*divide, 1);
+
+ // comes from above round_frac
+ high_time = temp[`FRAC_PRECISION+7:`FRAC_PRECISION+1];
+ // If the duty cycle * divide rounded is .5 or greater then this bit
+ // is set.
+ w_edge = temp[`FRAC_PRECISION]; // comes from round_frac
+
+ // If the high time comes out to 0, it needs to be set to at least 1
+ // and w_edge set to 0
+ if(high_time == 7'h00) begin
+ high_time = 7'h01;
+ w_edge = 1'b0;
+ end
+
+ if(high_time == divide) begin
+ high_time = divide - 1;
+ w_edge = 1'b1;
+ end
+
+ // Calculate low_time based on the divide setting and set no_count to
+ // 0 as it is only used when divide is 1.
+ low_time = divide - high_time;
+ no_count = 1'b0;
+ end
+
+ // Set the return value.
+ mmcm_pll_divider = {w_edge,no_count,high_time[5:0],low_time[5:0]};
+ end
+endfunction
+
+// This function calculates mx, delay_time, and phase_mux
+// of a non-fractional counter based on the divide and phase
+//
+// NOTE: The only valid value for the MX bits is 2'b00 to ensure the coarse mux
+// is used.
+function [10:0] mmcm_pll_phase
+ (
+ // divide must be an integer (use fractional if not)
+ // assumed that divide already checked to be valid
+ input [7:0] divide, // Max divide is 128
+
+ // Phase is given in degrees (-360,000 to 360,000)
+ input signed [31:0] phase
+ );
+
+ reg [`FIXED_WIDTH:1] phase_in_cycles;
+ reg [`FIXED_WIDTH:1] phase_fixed;
+ reg [1:0] mx;
+ reg [5:0] delay_time;
+ reg [2:0] phase_mux;
+
+ reg [`FIXED_WIDTH:1] temp;
+
+ begin
+`ifdef DEBUG
+ $display("mmcm_pll_phase-divide:%d,phase:%d",
+ divide, phase);
+`endif
+
+ if ((phase < -360000) || (phase > 360000)) begin
+`ifndef SYNTHESIS
+ $display("ERROR: phase of $phase is not between -360000 and 360000");
+ `endif
+ $finish;
+ end
+
+ // If phase is less than 0, convert it to a positive phase shift
+ // Convert to (FIXED_WIDTH-FRAC_PRECISION).FRAC_PRECISION fixed point
+ if(phase < 0) begin
+ phase_fixed = ( (phase + 360000) << `FRAC_PRECISION ) / 1000;
+ end else begin
+ phase_fixed = ( phase << `FRAC_PRECISION ) / 1000;
+ end
+
+ // Put phase in terms of decimal number of vco clock cycles
+ phase_in_cycles = ( phase_fixed * divide ) / 360;
+
+`ifdef DEBUG
+ $display("phase_in_cycles: %h", phase_in_cycles);
+`endif
+
+
+ temp = round_frac(phase_in_cycles, 3);
+
+ // set mx to 2'b00 that the phase mux from the VCO is enabled
+ mx = 2'b00;
+ phase_mux = temp[`FRAC_PRECISION:`FRAC_PRECISION-2];
+ delay_time = temp[`FRAC_PRECISION+6:`FRAC_PRECISION+1];
+
+`ifdef DEBUG
+ $display("temp: %h", temp);
+`endif
+
+ // Setup the return value
+ mmcm_pll_phase={mx, phase_mux, delay_time};
+ end
+endfunction
+
+// This function takes the divide value and outputs the necessary lock values
+function [39:0] mmcm_pll_lock_lookup
+ (
+ input [6:0] divide // Max divide is 64
+ );
+
+ reg [2559:0] lookup;
+
+ begin
+ lookup = {
+ // This table is composed of:
+ // LockRefDly_LockFBDly_LockCnt_LockSatHigh_UnlockCnt
+ 40'b00110_00110_1111101000_1111101001_0000000001,
+ 40'b00110_00110_1111101000_1111101001_0000000001,
+ 40'b01000_01000_1111101000_1111101001_0000000001,
+ 40'b01011_01011_1111101000_1111101001_0000000001,
+ 40'b01110_01110_1111101000_1111101001_0000000001,
+ 40'b10001_10001_1111101000_1111101001_0000000001,
+ 40'b10011_10011_1111101000_1111101001_0000000001,
+ 40'b10110_10110_1111101000_1111101001_0000000001,
+ 40'b11001_11001_1111101000_1111101001_0000000001,
+ 40'b11100_11100_1111101000_1111101001_0000000001,
+ 40'b11111_11111_1110000100_1111101001_0000000001,
+ 40'b11111_11111_1100111001_1111101001_0000000001,
+ 40'b11111_11111_1011101110_1111101001_0000000001,
+ 40'b11111_11111_1010111100_1111101001_0000000001,
+ 40'b11111_11111_1010001010_1111101001_0000000001,
+ 40'b11111_11111_1001110001_1111101001_0000000001,
+ 40'b11111_11111_1000111111_1111101001_0000000001,
+ 40'b11111_11111_1000100110_1111101001_0000000001,
+ 40'b11111_11111_1000001101_1111101001_0000000001,
+ 40'b11111_11111_0111110100_1111101001_0000000001,
+ 40'b11111_11111_0111011011_1111101001_0000000001,
+ 40'b11111_11111_0111000010_1111101001_0000000001,
+ 40'b11111_11111_0110101001_1111101001_0000000001,
+ 40'b11111_11111_0110010000_1111101001_0000000001,
+ 40'b11111_11111_0110010000_1111101001_0000000001,
+ 40'b11111_11111_0101110111_1111101001_0000000001,
+ 40'b11111_11111_0101011110_1111101001_0000000001,
+ 40'b11111_11111_0101011110_1111101001_0000000001,
+ 40'b11111_11111_0101000101_1111101001_0000000001,
+ 40'b11111_11111_0101000101_1111101001_0000000001,
+ 40'b11111_11111_0100101100_1111101001_0000000001,
+ 40'b11111_11111_0100101100_1111101001_0000000001,
+ 40'b11111_11111_0100101100_1111101001_0000000001,
+ 40'b11111_11111_0100010011_1111101001_0000000001,
+ 40'b11111_11111_0100010011_1111101001_0000000001,
+ 40'b11111_11111_0100010011_1111101001_0000000001,
+ 40'b11111_11111_0011111010_1111101001_0000000001,
+ 40'b11111_11111_0011111010_1111101001_0000000001,
+ 40'b11111_11111_0011111010_1111101001_0000000001,
+ 40'b11111_11111_0011111010_1111101001_0000000001,
+ 40'b11111_11111_0011111010_1111101001_0000000001,
+ 40'b11111_11111_0011111010_1111101001_0000000001,
+ 40'b11111_11111_0011111010_1111101001_0000000001,
+ 40'b11111_11111_0011111010_1111101001_0000000001,
+ 40'b11111_11111_0011111010_1111101001_0000000001,
+ 40'b11111_11111_0011111010_1111101001_0000000001,
+ 40'b11111_11111_0011111010_1111101001_0000000001,
+ 40'b11111_11111_0011111010_1111101001_0000000001,
+ 40'b11111_11111_0011111010_1111101001_0000000001,
+ 40'b11111_11111_0011111010_1111101001_0000000001,
+ 40'b11111_11111_0011111010_1111101001_0000000001,
+ 40'b11111_11111_0011111010_1111101001_0000000001,
+ 40'b11111_11111_0011111010_1111101001_0000000001,
+ 40'b11111_11111_0011111010_1111101001_0000000001,
+ 40'b11111_11111_0011111010_1111101001_0000000001,
+ 40'b11111_11111_0011111010_1111101001_0000000001,
+ 40'b11111_11111_0011111010_1111101001_0000000001,
+ 40'b11111_11111_0011111010_1111101001_0000000001,
+ 40'b11111_11111_0011111010_1111101001_0000000001,
+ 40'b11111_11111_0011111010_1111101001_0000000001,
+ 40'b11111_11111_0011111010_1111101001_0000000001,
+ 40'b11111_11111_0011111010_1111101001_0000000001,
+ 40'b11111_11111_0011111010_1111101001_0000000001,
+ 40'b11111_11111_0011111010_1111101001_0000000001
+ };
+
+ // Set lookup_entry with the explicit bits from lookup with a part select
+ mmcm_pll_lock_lookup = lookup[ ((64-divide)*40) +: 40];
+ `ifdef DEBUG
+ $display("lock_lookup: %b", mmcm_pll_lock_lookup);
+ `endif
+ end
+endfunction
+
+// This function takes the divide value and the bandwidth setting of the PLL
+// and outputs the digital filter settings necessary.
+function [9:0] mmcm_pll_filter_lookup
+ (
+ input [6:0] divide, // Max divide is 64
+ input [8*9:0] BANDWIDTH
+ );
+
+ reg [639:0] lookup_low;
+ reg [639:0] lookup_high;
+
+ reg [9:0] lookup_entry;
+
+ begin
+ lookup_low = {
+ // CP_RES_LFHF
+ 10'b0010_1111_00,
+ 10'b0010_1111_00,
+ 10'b0010_0111_00,
+ 10'b0010_1101_00,
+ 10'b0010_0101_00,
+ 10'b0010_0101_00,
+ 10'b0010_1001_00,
+ 10'b0010_1110_00,
+ 10'b0010_1110_00,
+ 10'b0010_0001_00,
+ 10'b0010_0001_00,
+ 10'b0010_0110_00,
+ 10'b0010_0110_00,
+ 10'b0010_0110_00,
+ 10'b0010_0110_00,
+ 10'b0010_1010_00,
+ 10'b0010_1010_00,
+ 10'b0010_1010_00,
+ 10'b0010_1010_00,
+ 10'b0010_1100_00,
+ 10'b0010_1100_00,
+ 10'b0010_1100_00,
+ 10'b0010_1100_00,
+ 10'b0010_1100_00,
+ 10'b0010_1100_00,
+ 10'b0010_1100_00,
+ 10'b0010_1100_00,
+ 10'b0010_1100_00,
+ 10'b0010_1100_00,
+ 10'b0010_1100_00,
+ 10'b0010_0010_00,
+ 10'b0010_0010_00,
+ 10'b0010_0010_00,
+ 10'b0010_0010_00,
+ 10'b0010_0010_00,
+ 10'b0010_0010_00,
+ 10'b0010_0010_00,
+ 10'b0010_0010_00,
+ 10'b0010_0010_00,
+ 10'b0010_0010_00,
+ 10'b0011_1100_00,
+ 10'b0011_1100_00,
+ 10'b0011_1100_00,
+ 10'b0011_1100_00,
+ 10'b0011_1100_00,
+ 10'b0011_1100_00,
+ 10'b0011_1100_00,
+ 10'b0010_0100_00,
+ 10'b0010_0100_00,
+ 10'b0010_0100_00,
+ 10'b0010_0100_00,
+ 10'b0010_0100_00,
+ 10'b0010_0100_00,
+ 10'b0010_0100_00,
+ 10'b0010_0100_00,
+ 10'b0010_0100_00,
+ 10'b0010_0100_00,
+ 10'b0010_0100_00,
+ 10'b0010_0100_00,
+ 10'b0010_0100_00,
+ 10'b0010_0100_00,
+ 10'b0010_0100_00,
+ 10'b0010_0100_00,
+ 10'b0010_0100_00
+ };
+
+ lookup_high = {
+ // CP_RES_LFHF
+ 10'b0011_0111_00,
+ 10'b0011_0111_00,
+ 10'b0101_1111_00,
+ 10'b0111_1111_00,
+ 10'b0111_1011_00,
+ 10'b1101_0111_00,
+ 10'b1110_1011_00,
+ 10'b1110_1101_00,
+ 10'b1111_1101_00,
+ 10'b1111_0111_00,
+ 10'b1111_1011_00,
+ 10'b1111_1101_00,
+ 10'b1111_0011_00,
+ 10'b1110_0101_00,
+ 10'b1111_0101_00,
+ 10'b1111_0101_00,
+ 10'b1111_0101_00,
+ 10'b1111_0101_00,
+ 10'b0111_0110_00,
+ 10'b0111_0110_00,
+ 10'b0111_0110_00,
+ 10'b0111_0110_00,
+ 10'b0101_1100_00,
+ 10'b0101_1100_00,
+ 10'b0101_1100_00,
+ 10'b1100_0001_00,
+ 10'b1100_0001_00,
+ 10'b1100_0001_00,
+ 10'b1100_0001_00,
+ 10'b1100_0001_00,
+ 10'b1100_0001_00,
+ 10'b1100_0001_00,
+ 10'b1100_0001_00,
+ 10'b0100_0010_00,
+ 10'b0100_0010_00,
+ 10'b0100_0010_00,
+ 10'b0010_1000_00,
+ 10'b0010_1000_00,
+ 10'b0010_1000_00,
+ 10'b0011_0100_00,
+ 10'b0010_1000_00,
+ 10'b0010_1000_00,
+ 10'b0010_1000_00,
+ 10'b0010_1000_00,
+ 10'b0010_1000_00,
+ 10'b0010_1000_00,
+ 10'b0010_1000_00,
+ 10'b0010_1000_00,
+ 10'b0010_1000_00,
+ 10'b0010_1000_00,
+ 10'b0010_1000_00,
+ 10'b0010_1000_00,
+ 10'b0010_1000_00,
+ 10'b0100_1100_00,
+ 10'b0100_1100_00,
+ 10'b0100_1100_00,
+ 10'b0100_1100_00,
+ 10'b0100_1100_00,
+ 10'b0100_1100_00,
+ 10'b0100_1100_00,
+ 10'b0010_0100_00,
+ 10'b0010_0100_00,
+ 10'b0010_0100_00,
+ 10'b0010_0100_00
+ };
+
+ // Set lookup_entry with the explicit bits from lookup with a part select
+ if(BANDWIDTH == "LOW") begin
+ // Low Bandwidth
+ mmcm_pll_filter_lookup = lookup_low[ ((64-divide)*10) +: 10];
+ end else begin
+ // High or optimized bandwidth
+ mmcm_pll_filter_lookup = lookup_high[ ((64-divide)*10) +: 10];
+ end
+
+ `ifdef DEBUG
+ $display("filter_lookup: %b", mmcm_pll_filter_lookup);
+ `endif
+ end
+endfunction
+
+// This function takes in the divide, phase, and duty cycle
+// setting to calculate the upper and lower counter registers.
+function [37:0] mmcm_pll_count_calc
+ (
+ input [7:0] divide, // Max divide is 128
+ input signed [31:0] phase,
+ input [31:0] duty_cycle // Multiplied by 100,000
+ );
+
+ reg [13:0] div_calc;
+ reg [16:0] phase_calc;
+
+ begin
+ `ifdef DEBUG
+ $display("mmcm_pll_count_calc- divide:%h, phase:%d, duty_cycle:%d",
+ divide, phase, duty_cycle);
+`endif
+
+ // w_edge[13], no_count[12], high_time[11:6], low_time[5:0]
+ div_calc = mmcm_pll_divider(divide, duty_cycle);
+ // mx[10:9], pm[8:6], dt[5:0]
+ phase_calc = mmcm_pll_phase(divide, phase);
+
+ // Return value is the upper and lower address of counter
+ // Upper address is:
+ // RESERVED [31:26]
+ // MX [25:24]
+ // EDGE [23]
+ // NOCOUNT [22]
+ // DELAY_TIME [21:16]
+ // Lower Address is:
+ // PHASE_MUX [15:13]
+ // RESERVED [12]
+ // HIGH_TIME [11:6]
+ // LOW_TIME [5:0]
+
+`ifdef DEBUG
+ $display("div:%d dc:%d phase:%d ht:%d lt:%d ed:%d nc:%d mx:%d dt:%d pm:%d",
+ divide, duty_cycle, phase, div_calc[11:6], div_calc[5:0],
+ div_calc[13], div_calc[12],
+ phase_calc[16:15], phase_calc[5:0], phase_calc[14:12]);
+`endif
+
+ mmcm_pll_count_calc =
+ {
+ // Upper Address
+ 6'h00, phase_calc[10:9], div_calc[13:12], phase_calc[5:0],
+ // Lower Address
+ phase_calc[8:6], 1'b0, div_calc[11:0]
+ };
+ end
+endfunction
diff --git a/game.gen/sources_1/ip/clk_wiz_0/mmcm_pll_drp_func_us_mmcm.vh b/game.gen/sources_1/ip/clk_wiz_0/mmcm_pll_drp_func_us_mmcm.vh
new file mode 100755
index 0000000000000000000000000000000000000000..811d4338c6a31e6d63f2f3723d50fb55197e4acb
--- /dev/null
+++ b/game.gen/sources_1/ip/clk_wiz_0/mmcm_pll_drp_func_us_mmcm.vh
@@ -0,0 +1,671 @@
+///////////////////////////////////////////////////////////////////////////////
+//
+// Company: Xilinx
+// Engineer: Jim Tatsukawa
+// Date: 7/30/2014
+// Design Name: MMCME2 DRP
+// Module Name: mmcme2_drp_func.h
+// Version: 1.04
+// Target Devices: UltraScale Architecture || MMCM
+// Tool versions: 2014.3
+// Description: This header provides the functions necessary to
+// calculate the DRP register values for the V6 MMCM.
+//
+// Revision Notes: 3/22 - Updating lookup_low/lookup_high (CR)
+// 4/13 - Fractional divide function in mmcm_frac_count_calc function. CRS610807
+//
+// Disclaimer: XILINX IS PROVIDING THIS DESIGN, CODE, OR
+// INFORMATION "AS IS" SOLELY FOR USE IN DEVELOPING
+// PROGRAMS AND SOLUTIONS FOR XILINX DEVICES. BY
+// PROVIDING THIS DESIGN, CODE, OR INFORMATION AS
+// ONE POSSIBLE IMPLEMENTATION OF THIS FEATURE,
+// APPLICATION OR STANDARD, XILINX IS MAKING NO
+// REPRESENTATION THAT THIS IMPLEMENTATION IS FREE
+// FROM ANY CLAIMS OF INFRINGEMENT, AND YOU ARE
+// RESPONSIBLE FOR OBTAINING ANY RIGHTS YOU MAY
+// REQUIRE FOR YOUR IMPLEMENTATION. XILINX
+// EXPRESSLY DISCLAIMS ANY WARRANTY WHATSOEVER WITH
+// RESPECT TO THE ADEQUACY OF THE IMPLEMENTATION,
+// INCLUDING BUT NOT LIMITED TO ANY WARRANTIES OR
+// REPRESENTATIONS THAT THIS IMPLEMENTATION IS FREE
+// FROM CLAIMS OF INFRINGEMENT, IMPLIED WARRANTIES
+// OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
+// PURPOSE.
+//
+// (c) Copyright 2009-2010 Xilinx, Inc.
+// All rights reserved.
+//
+///////////////////////////////////////////////////////////////////////////////
+
+// These are user functions that should not be modified. Changes to the defines
+// or code within the functions may alter the accuracy of the calculations.
+
+// Define debug to provide extra messages durring elaboration
+//`define DEBUG 1
+
+// FRAC_PRECISION describes the width of the fractional portion of the fixed
+// point numbers. These should not be modified, they are for development
+// only
+`define FRAC_PRECISION 10
+// FIXED_WIDTH describes the total size for fixed point calculations(int+frac).
+// Warning: L.50 and below will not calculate properly with FIXED_WIDTHs
+// greater than 32
+`define FIXED_WIDTH 32
+
+// This function takes a fixed point number and rounds it to the nearest
+// fractional precision bit.
+function [`FIXED_WIDTH:1] round_frac
+ (
+ // Input is (FIXED_WIDTH-FRAC_PRECISION).FRAC_PRECISION fixed point number
+ input [`FIXED_WIDTH:1] decimal,
+
+ // This describes the precision of the fraction, for example a value
+ // of 1 would modify the fractional so that instead of being a .16
+ // fractional, it would be a .1 (rounded to the nearest 0.5 in turn)
+ input [`FIXED_WIDTH:1] precision
+ );
+
+ begin
+
+ `ifdef DEBUG
+ $display("round_frac - decimal: %h, precision: %h", decimal, precision);
+ `endif
+ // If the fractional precision bit is high then round up
+ if( decimal[(`FRAC_PRECISION-precision)] == 1'b1) begin
+ round_frac = decimal + (1'b1 << (`FRAC_PRECISION-precision));
+ end else begin
+ round_frac = decimal;
+ end
+ `ifdef DEBUG
+ $display("round_frac: %h", round_frac);
+ `endif
+ end
+endfunction
+
+// This function calculates high_time, low_time, w_edge, and no_count
+// of a non-fractional counter based on the divide and duty cycle
+//
+// NOTE: high_time and low_time are returned as integers between 0 and 63
+// inclusive. 64 should equal 6'b000000 (in other words it is okay to
+// ignore the overflow)
+function [13:0] mmcm_pll_divider
+ (
+ input [7:0] divide, // Max divide is 128
+ input [31:0] duty_cycle // Duty cycle is multiplied by 100,000
+ );
+
+ reg [`FIXED_WIDTH:1] duty_cycle_fix;
+
+ // High/Low time is initially calculated with a wider integer to prevent a
+ // calculation error when it overflows to 64.
+ reg [6:0] high_time;
+ reg [6:0] low_time;
+ reg w_edge;
+ reg no_count;
+
+ reg [`FIXED_WIDTH:1] temp;
+
+ begin
+ // Duty Cycle must be between 0 and 1,000
+ if(duty_cycle <=0 || duty_cycle >= 100000) begin
+`ifndef SYNTHESIS
+ $display("ERROR: duty_cycle: %d is invalid", duty_cycle);
+ `endif
+ $finish;
+ end
+
+ // Convert to FIXED_WIDTH-FRAC_PRECISION.FRAC_PRECISION fixed point
+ duty_cycle_fix = (duty_cycle << `FRAC_PRECISION) / 100_000;
+
+ `ifdef DEBUG
+ $display("duty_cycle_fix: %h", duty_cycle_fix);
+ `endif
+
+ // If the divide is 1 nothing needs to be set except the no_count bit.
+ // Other values are dummies
+ if(divide == 7'h01) begin
+ high_time = 7'h01;
+ w_edge = 1'b0;
+ low_time = 7'h01;
+ no_count = 1'b1;
+ end else begin
+ temp = round_frac(duty_cycle_fix*divide, 1);
+
+ // comes from above round_frac
+ high_time = temp[`FRAC_PRECISION+7:`FRAC_PRECISION+1];
+ // If the duty cycle * divide rounded is .5 or greater then this bit
+ // is set.
+ w_edge = temp[`FRAC_PRECISION]; // comes from round_frac
+
+ // If the high time comes out to 0, it needs to be set to at least 1
+ // and w_edge set to 0
+ if(high_time == 7'h00) begin
+ high_time = 7'h01;
+ w_edge = 1'b0;
+ end
+
+ if(high_time == divide) begin
+ high_time = divide - 1;
+ w_edge = 1'b1;
+ end
+
+ // Calculate low_time based on the divide setting and set no_count to
+ // 0 as it is only used when divide is 1.
+ low_time = divide - high_time;
+ no_count = 1'b0;
+ end
+
+ // Set the return value.
+ mmcm_pll_divider = {w_edge,no_count,high_time[5:0],low_time[5:0]};
+ end
+endfunction
+
+// This function calculates mx, delay_time, and phase_mux
+// of a non-fractional counter based on the divide and phase
+//
+// NOTE: The only valid value for the MX bits is 2'b00 to ensure the coarse mux
+// is used.
+function [10:0] mmcm_pll_phase
+ (
+ // divide must be an integer (use fractional if not)
+ // assumed that divide already checked to be valid
+ input [7:0] divide, // Max divide is 128
+
+ // Phase is given in degrees (-360,000 to 360,000)
+ input signed [31:0] phase
+ );
+
+ reg [`FIXED_WIDTH:1] phase_in_cycles;
+ reg [`FIXED_WIDTH:1] phase_fixed;
+ reg [1:0] mx;
+ reg [5:0] delay_time;
+ reg [2:0] phase_mux;
+
+ reg [`FIXED_WIDTH:1] temp;
+
+ begin
+`ifdef DEBUG
+ $display("mmcm_pll_phase-divide:%d,phase:%d",
+ divide, phase);
+`endif
+
+ if ((phase < -360000) || (phase > 360000)) begin
+`ifndef SYNTHESIS
+ $display("ERROR: phase of $phase is not between -360000 and 360000");
+ `endif
+ $finish;
+ end
+
+ // If phase is less than 0, convert it to a positive phase shift
+ // Convert to (FIXED_WIDTH-FRAC_PRECISION).FRAC_PRECISION fixed point
+ if(phase < 0) begin
+ phase_fixed = ( (phase + 360000) << `FRAC_PRECISION ) / 1000;
+ end else begin
+ phase_fixed = ( phase << `FRAC_PRECISION ) / 1000;
+ end
+
+ // Put phase in terms of decimal number of vco clock cycles
+ phase_in_cycles = ( phase_fixed * divide ) / 360;
+
+`ifdef DEBUG
+ $display("phase_in_cycles: %h", phase_in_cycles);
+`endif
+
+
+ temp = round_frac(phase_in_cycles, 3);
+
+ // set mx to 2'b00 that the phase mux from the VCO is enabled
+ mx = 2'b00;
+ phase_mux = temp[`FRAC_PRECISION:`FRAC_PRECISION-2];
+ delay_time = temp[`FRAC_PRECISION+6:`FRAC_PRECISION+1];
+
+ `ifdef DEBUG
+ $display("temp: %h", temp);
+ `endif
+
+ // Setup the return value
+ mmcm_pll_phase={mx, phase_mux, delay_time};
+ end
+endfunction
+
+// This function takes the divide value and outputs the necessary lock values
+function [39:0] mmcm_pll_lock_lookup
+ (
+ input [6:0] divide // Max divide is 64
+ );
+
+ reg [2559:0] lookup;
+
+ begin
+ lookup = {
+ // This table is composed of:
+ // LockRefDly_LockFBDly_LockCnt_LockSatHigh_UnlockCnt
+ 40'b00110_00110_1111101000_1111101001_0000000001,
+ 40'b00110_00110_1111101000_1111101001_0000000001,
+ 40'b01000_01000_1111101000_1111101001_0000000001,
+ 40'b01011_01011_1111101000_1111101001_0000000001,
+ 40'b01110_01110_1111101000_1111101001_0000000001,
+ 40'b10001_10001_1111101000_1111101001_0000000001,
+ 40'b10011_10011_1111101000_1111101001_0000000001,
+ 40'b10110_10110_1111101000_1111101001_0000000001,
+ 40'b11001_11001_1111101000_1111101001_0000000001,
+ 40'b11100_11100_1111101000_1111101001_0000000001,
+ 40'b11111_11111_1110000100_1111101001_0000000001,
+ 40'b11111_11111_1100111001_1111101001_0000000001,
+ 40'b11111_11111_1011101110_1111101001_0000000001,
+ 40'b11111_11111_1010111100_1111101001_0000000001,
+ 40'b11111_11111_1010001010_1111101001_0000000001,
+ 40'b11111_11111_1001110001_1111101001_0000000001,
+ 40'b11111_11111_1000111111_1111101001_0000000001,
+ 40'b11111_11111_1000100110_1111101001_0000000001,
+ 40'b11111_11111_1000001101_1111101001_0000000001,
+ 40'b11111_11111_0111110100_1111101001_0000000001,
+ 40'b11111_11111_0111011011_1111101001_0000000001,
+ 40'b11111_11111_0111000010_1111101001_0000000001,
+ 40'b11111_11111_0110101001_1111101001_0000000001,
+ 40'b11111_11111_0110010000_1111101001_0000000001,
+ 40'b11111_11111_0110010000_1111101001_0000000001,
+ 40'b11111_11111_0101110111_1111101001_0000000001,
+ 40'b11111_11111_0101011110_1111101001_0000000001,
+ 40'b11111_11111_0101011110_1111101001_0000000001,
+ 40'b11111_11111_0101000101_1111101001_0000000001,
+ 40'b11111_11111_0101000101_1111101001_0000000001,
+ 40'b11111_11111_0100101100_1111101001_0000000001,
+ 40'b11111_11111_0100101100_1111101001_0000000001,
+ 40'b11111_11111_0100101100_1111101001_0000000001,
+ 40'b11111_11111_0100010011_1111101001_0000000001,
+ 40'b11111_11111_0100010011_1111101001_0000000001,
+ 40'b11111_11111_0100010011_1111101001_0000000001,
+ 40'b11111_11111_0011111010_1111101001_0000000001,
+ 40'b11111_11111_0011111010_1111101001_0000000001,
+ 40'b11111_11111_0011111010_1111101001_0000000001,
+ 40'b11111_11111_0011111010_1111101001_0000000001,
+ 40'b11111_11111_0011111010_1111101001_0000000001,
+ 40'b11111_11111_0011111010_1111101001_0000000001,
+ 40'b11111_11111_0011111010_1111101001_0000000001,
+ 40'b11111_11111_0011111010_1111101001_0000000001,
+ 40'b11111_11111_0011111010_1111101001_0000000001,
+ 40'b11111_11111_0011111010_1111101001_0000000001,
+ 40'b11111_11111_0011111010_1111101001_0000000001,
+ 40'b11111_11111_0011111010_1111101001_0000000001,
+ 40'b11111_11111_0011111010_1111101001_0000000001,
+ 40'b11111_11111_0011111010_1111101001_0000000001,
+ 40'b11111_11111_0011111010_1111101001_0000000001,
+ 40'b11111_11111_0011111010_1111101001_0000000001,
+ 40'b11111_11111_0011111010_1111101001_0000000001,
+ 40'b11111_11111_0011111010_1111101001_0000000001,
+ 40'b11111_11111_0011111010_1111101001_0000000001,
+ 40'b11111_11111_0011111010_1111101001_0000000001,
+ 40'b11111_11111_0011111010_1111101001_0000000001,
+ 40'b11111_11111_0011111010_1111101001_0000000001,
+ 40'b11111_11111_0011111010_1111101001_0000000001,
+ 40'b11111_11111_0011111010_1111101001_0000000001,
+ 40'b11111_11111_0011111010_1111101001_0000000001,
+ 40'b11111_11111_0011111010_1111101001_0000000001,
+ 40'b11111_11111_0011111010_1111101001_0000000001,
+ 40'b11111_11111_0011111010_1111101001_0000000001
+ };
+
+ // Set lookup_entry with the explicit bits from lookup with a part select
+ mmcm_pll_lock_lookup = lookup[ ((64-divide)*40) +: 40];
+ `ifdef DEBUG
+ $display("lock_lookup: %b", mmcm_pll_lock_lookup);
+ `endif
+ end
+endfunction
+
+// This function takes the divide value and the bandwidth setting of the MMCM
+// and outputs the digital filter settings necessary.
+function [9:0] mmcm_pll_filter_lookup
+ (
+ input [6:0] divide, // Max divide is 64
+ input [8*9:0] BANDWIDTH
+ );
+
+ reg [639:0] lookup_low;
+ reg [639:0] lookup_high;
+
+ reg [9:0] lookup_entry;
+
+ begin
+ lookup_low = {
+ // CP_RES_LFHF
+ 10'b0010_1111_11,
+ 10'b0010_1111_11,
+ 10'b0010_1111_11,
+ 10'b0010_1111_11,
+ 10'b0010_1111_11,
+ 10'b0010_1111_11,
+ 10'b0010_0111_11,
+ 10'b0010_0111_11,
+ 10'b0010_0111_11,
+ 10'b0010_1101_11,
+ 10'b0010_1101_11,
+ 10'b0010_1101_11,
+ 10'b0010_0011_11,
+ 10'b0010_0101_11,
+ 10'b0010_0101_11,
+ 10'b0010_0101_11,
+ 10'b0010_1001_11,
+ 10'b0010_1001_11,
+ 10'b0010_1110_11,
+ 10'b0010_1110_11,
+ 10'b0010_1110_11,
+ 10'b0010_1110_11,
+ 10'b0010_1110_11,
+ 10'b0010_1110_11,
+ 10'b0010_0001_11,
+ 10'b0010_0001_11,
+ 10'b0010_0001_11,
+ 10'b0010_0001_11,
+ 10'b0010_0001_11,
+ 10'b0010_0110_11,
+ 10'b0010_0110_11,
+ 10'b0010_0110_11,
+ 10'b0010_0110_11,
+ 10'b0010_0110_11,
+ 10'b0010_0110_11,
+ 10'b0010_0110_11,
+ 10'b0010_0110_11,
+ 10'b0010_0110_11,
+ 10'b0010_0110_11,
+ 10'b0010_1010_11,
+ 10'b0010_1010_11,
+ 10'b0010_1010_11,
+ 10'b0010_1010_11,
+ 10'b0010_1010_11,
+ 10'b0010_1010_11,
+ 10'b0010_1010_11,
+ 10'b0010_1010_11,
+ 10'b0010_1100_11,
+ 10'b0010_1100_11,
+ 10'b0010_1100_11,
+ 10'b0010_1100_11,
+ 10'b0010_1100_11,
+ 10'b0010_1100_11,
+ 10'b0010_1100_11,
+ 10'b0010_1100_11,
+ 10'b0010_1100_11,
+ 10'b0010_1100_11,
+ 10'b0010_1100_11,
+ 10'b0010_1100_11,
+ 10'b0010_1100_11,
+ 10'b0010_1100_11,
+ 10'b0010_1100_11,
+ 10'b0010_1100_11,
+ 10'b0010_1100_11
+ };
+
+ lookup_high = {
+ // CP_RES_LFHF
+ 10'b0010_1111_11,
+ 10'b0010_1111_11,
+ 10'b0010_1011_11,
+ 10'b0011_1111_11,
+ 10'b0100_1111_11,
+ 10'b0100_1111_11,
+ 10'b0101_1111_11,
+ 10'b0110_1111_11,
+ 10'b0111_1111_11,
+ 10'b0111_1111_11,
+ 10'b1100_1111_11,
+ 10'b1101_1111_11,
+ 10'b1110_1111_11,
+ 10'b1111_1111_11,
+ 10'b1111_1111_11,
+ 10'b1110_0111_11,
+ 10'b1110_1011_11,
+ 10'b1111_0111_11,
+ 10'b1111_1011_11,
+ 10'b1111_1011_11,
+ 10'b1110_1101_11,
+ 10'b1111_1101_11,
+ 10'b1111_1101_11,
+ 10'b1111_0011_11,
+ 10'b1111_0011_11,
+ 10'b1111_0011_11,
+ 10'b1110_0101_11,
+ 10'b1110_0101_11,
+ 10'b1110_0101_11,
+ 10'b1111_0101_11,
+ 10'b1111_0101_11,
+ 10'b1111_0101_11,
+ 10'b1111_1001_11,
+ 10'b1111_1001_11,
+ 10'b1111_1001_11,
+ 10'b1111_1001_11,
+ 10'b1111_1001_11,
+ 10'b1110_1110_11,
+ 10'b1110_1110_11,
+ 10'b1110_1110_11,
+ 10'b1110_1110_11,
+ 10'b1111_1110_11,
+ 10'b1111_1110_11,
+ 10'b1111_1110_11,
+ 10'b1111_1110_11,
+ 10'b1111_1110_11,
+ 10'b1111_1110_11,
+ 10'b1111_1110_11,
+ 10'b1110_0001_11,
+ 10'b1110_0001_11,
+ 10'b1110_0001_11,
+ 10'b1110_0001_11,
+ 10'b1110_0001_11,
+ 10'b1100_0110_11,
+ 10'b1100_0110_11,
+ 10'b1100_0110_11,
+ 10'b1100_0110_11,
+ 10'b1100_0110_11,
+ 10'b1100_0110_11,
+ 10'b1100_0110_11,
+ 10'b1100_1010_11,
+ 10'b1100_1010_11,
+ 10'b1100_1010_11,
+ 10'b1100_1010_11
+ };
+
+ // Set lookup_entry with the explicit bits from lookup with a part select
+ if(BANDWIDTH == "LOW") begin
+ // Low Bandwidth
+ mmcm_pll_filter_lookup = lookup_low[ ((64-divide)*10) +: 10];
+ end else begin
+ // High or optimized bandwidth
+ mmcm_pll_filter_lookup = lookup_high[ ((64-divide)*10) +: 10];
+ end
+
+ `ifdef DEBUG
+ $display("filter_lookup: %b", mmcm_pll_filter_lookup);
+ `endif
+ end
+endfunction
+
+// This function takes in the divide, phase, and duty cycle
+// setting to calculate the upper and lower counter registers.
+function [37:0] mmcm_pll_count_calc
+ (
+ input [7:0] divide, // Max divide is 128
+ input signed [31:0] phase,
+ input [31:0] duty_cycle // Multiplied by 100,000
+ );
+
+ reg [13:0] div_calc;
+ reg [16:0] phase_calc;
+
+ begin
+ `ifdef DEBUG
+ $display("mmcm_pll_count_calc- divide:%h, phase:%d, duty_cycle:%d",
+ divide, phase, duty_cycle);
+ `endif
+
+ // w_edge[13], no_count[12], high_time[11:6], low_time[5:0]
+ div_calc = mmcm_pll_divider(divide, duty_cycle);
+ // mx[10:9], pm[8:6], dt[5:0]
+ phase_calc = mmcm_pll_phase(divide, phase);
+
+ // Return value is the upper and lower address of counter
+ // Upper address is:
+ // RESERVED [31:26]
+ // MX [25:24]
+ // EDGE [23]
+ // NOCOUNT [22]
+ // DELAY_TIME [21:16]
+ // Lower Address is:
+ // PHASE_MUX [15:13]
+ // RESERVED [12]
+ // HIGH_TIME [11:6]
+ // LOW_TIME [5:0]
+
+ `ifdef DEBUG
+ $display("div:%d dc:%d phase:%d ht:%d lt:%d ed:%d nc:%d mx:%d dt:%d pm:%d",
+ divide, duty_cycle, phase, div_calc[11:6], div_calc[5:0],
+ div_calc[13], div_calc[12],
+ phase_calc[16:15], phase_calc[5:0], phase_calc[14:12]);
+ `endif
+
+ mmcm_pll_count_calc =
+ {
+ // Upper Address
+ 6'h00, phase_calc[10:9], div_calc[13:12], phase_calc[5:0],
+ // Lower Address
+ phase_calc[8:6], 1'b0, div_calc[11:0]
+ };
+ end
+endfunction
+
+
+// This function takes in the divide, phase, and duty cycle
+// setting to calculate the upper and lower counter registers.
+// for fractional multiply/divide functions.
+//
+//
+function [37:0] mmcm_frac_count_calc
+ (
+ input [7:0] divide, // Max divide is 128
+ input signed [31:0] phase,
+ input [31:0] duty_cycle, // Multiplied by 1,000
+ input [9:0] frac // Multiplied by 1000
+ );
+
+ //Required for fractional divide calculations
+ reg [7:0] lt_frac;
+ reg [7:0] ht_frac;
+
+ reg /*[7:0]*/ wf_fall_frac;
+ reg /*[7:0]*/ wf_rise_frac;
+
+ reg [31:0] a;
+ reg [7:0] pm_rise_frac_filtered ;
+ reg [7:0] pm_fall_frac_filtered ;
+ reg [7:0] clkout0_divide_int;
+ reg [2:0] clkout0_divide_frac;
+ reg [7:0] even_part_high;
+ reg [7:0] even_part_low;
+
+ reg [7:0] odd;
+ reg [7:0] odd_and_frac;
+
+ reg [7:0] pm_fall;
+ reg [7:0] pm_rise;
+ reg [7:0] dt;
+ reg [7:0] dt_int;
+ reg [63:0] dt_calc;
+
+ reg [7:0] pm_rise_frac;
+ reg [7:0] pm_fall_frac;
+
+ reg [31:0] a_per_in_octets;
+ reg [31:0] a_phase_in_cycles;
+
+ parameter precision = 0.125;
+
+ reg [31:0] phase_fixed; // changed to 31:0 from 32:1 jt 5/2/11
+ reg [31: 0] phase_pos;
+ reg [31: 0] phase_vco;
+ reg [31:0] temp;// changed to 31:0 from 32:1 jt 5/2/11
+ reg [13:0] div_calc;
+ reg [16:0] phase_calc;
+
+ begin
+ `ifdef DEBUG
+ $display("mmcm_frac_count_calc- divide:%h, phase:%d, duty_cycle:%d",
+ divide, phase, duty_cycle);
+ `endif
+
+ //convert phase to fixed
+ if ((phase < -360000) || (phase > 360000)) begin
+`ifndef SYNTHESIS
+ $display("ERROR: phase of $phase is not between -360000 and 360000");
+ `endif
+ $finish;
+ end
+
+
+ // Return value is
+ // Transfer data
+ // RESERVED [37:36]
+ // FRAC_TIME [35:33]
+ // FRAC_WF_FALL [32]
+ // Upper address is:
+ // RESERVED [31:26]
+ // MX [25:24]
+ // EDGE [23]
+ // NOCOUNT [22]
+ // DELAY_TIME [21:16]
+ // Lower Address is:
+ // PHASE_MUX [15:13]
+ // RESERVED [12]
+ // HIGH_TIME [11:6]
+ // LOW_TIME [5:0]
+
+
+
+ clkout0_divide_frac = frac / 125;
+ clkout0_divide_int = divide;
+
+ even_part_high = clkout0_divide_int >> 1;//$rtoi(clkout0_divide_int / 2);
+ even_part_low = even_part_high;
+
+ odd = clkout0_divide_int - even_part_high - even_part_low;
+ odd_and_frac = (8*odd) + clkout0_divide_frac;
+
+ lt_frac = even_part_high - (odd_and_frac <= 9);//IF(odd_and_frac>9,even_part_high, even_part_high - 1)
+ ht_frac = even_part_low - (odd_and_frac <= 8);//IF(odd_and_frac>8,even_part_low, even_part_low- 1)
+
+ pm_fall = {odd[6:0],2'b00} + {6'h00, clkout0_divide_frac[2:1]}; // using >> instead of clkout0_divide_frac / 2
+ pm_rise = 0; //0
+
+ wf_fall_frac = ((odd_and_frac >=2) && (odd_and_frac <=9)) || ((clkout0_divide_frac == 1) && (clkout0_divide_int == 2));//CRS610807
+ wf_rise_frac = (odd_and_frac >=1) && (odd_and_frac <=8);//IF(odd_and_frac>=1,IF(odd_and_frac <= 8,1,0),0)
+
+
+
+ //Calculate phase in fractional cycles
+ a_per_in_octets = (8 * divide) + (frac / 125) ;
+ a_phase_in_cycles = (phase+10) * a_per_in_octets / 360000 ;//Adding 1 due to rounding errors
+ pm_rise_frac = (a_phase_in_cycles[7:0] ==8'h00)?8'h00:a_phase_in_cycles[7:0] - {a_phase_in_cycles[7:3],3'b000};
+
+ dt_calc = ((phase+10) * a_per_in_octets / 8 )/360000 ;//TRUNC(phase* divide / 360); //or_simply (a_per_in_octets / 8)
+ dt = dt_calc[7:0];
+
+ pm_rise_frac_filtered = (pm_rise_frac >=8) ? (pm_rise_frac ) - 8: pm_rise_frac ; //((phase_fixed * (divide + frac / 1000)) / 360) - {pm_rise_frac[7:3],3'b000};//$rtoi(clkout0_phase * clkout0_divide / 45);//a;
+
+ dt_int = dt + (& pm_rise_frac[7:4]); //IF(pm_rise_overwriting>7,dt+1,dt)
+ pm_fall_frac = pm_fall + pm_rise_frac;
+ pm_fall_frac_filtered = pm_fall + pm_rise_frac - {pm_fall_frac[7:3], 3'b000};
+
+ div_calc = mmcm_pll_divider(divide, duty_cycle); //Use to determine edge[7], no count[6]
+ phase_calc = mmcm_pll_phase(divide, phase);// returns{mx[1:0], phase_mux[2:0], delay_time[5:0]}
+
+ mmcm_frac_count_calc[37:0] =
+ { 2'b00, pm_fall_frac_filtered[2:0], wf_fall_frac,
+ 1'b0, clkout0_divide_frac[2:0], 1'b1, wf_rise_frac, phase_calc[10:9], div_calc[13:12], dt[5:0],
+ pm_rise_frac_filtered[2], pm_rise_frac_filtered[1], pm_rise_frac_filtered[0], 1'b0, ht_frac[5:0], lt_frac[5:0]
+ } ;
+
+ `ifdef DEBUG
+ $display("-%d.%d p%d>> :DADDR_9_15 frac30to28.frac_en.wf_r_frac.dt:%b%d%d_%b:DADDR_7_13 pm_f_frac_filtered_29to27.wf_f_frac_26:%b%d:DADDR_8_14.pm_r_frac_filt_15to13.ht_frac.lt_frac:%b%b%b:", divide, frac, phase, clkout0_divide_frac, 1, wf_rise_frac, dt, pm_fall_frac_filtered, wf_fall_frac, pm_rise_frac_filtered, ht_frac, lt_frac);
+ `endif
+
+ end
+endfunction
+
diff --git a/game.gen/sources_1/ip/clk_wiz_0/mmcm_pll_drp_func_us_pll.vh b/game.gen/sources_1/ip/clk_wiz_0/mmcm_pll_drp_func_us_pll.vh
new file mode 100755
index 0000000000000000000000000000000000000000..9439f2359ee141fd7306d4bf77f61ac6c416465f
--- /dev/null
+++ b/game.gen/sources_1/ip/clk_wiz_0/mmcm_pll_drp_func_us_pll.vh
@@ -0,0 +1,530 @@
+///////////////////////////////////////////////////////////////////////////////
+//
+// Company: Xilinx
+// Engineer: Jim Tatsukawa
+// Date: 6/15/2015
+// Design Name: PLLE3 DRP
+// Module Name: plle3_drp_func.h
+// Version: 1.10
+// Target Devices: UltraScale Architecture
+// Tool versions: 2015.1
+// Description: This header provides the functions necessary to
+// calculate the DRP register values for the V6 PLL.
+//
+// Revision Notes: 8/11 - PLLE3 updated for PLLE3 file 4564419
+// Revision Notes: 6/15 - pll_filter_lookup fixed for max M of 19
+// PM_Rise bits have been removed for PLLE3
+//
+// Disclaimer: XILINX IS PROVIDING THIS DESIGN, CODE, OR
+// INFORMATION "AS IS" SOLELY FOR USE IN DEVELOPING
+// PROGRAMS AND SOLUTIONS FOR XILINX DEVICES. BY
+// PROVIDING THIS DESIGN, CODE, OR INFORMATION AS
+// ONE POSSIBLE IMPLEMENTATION OF THIS FEATURE,
+// APPLICATION OR STANDARD, XILINX IS MAKING NO
+// REPRESENTATION THAT THIS IMPLEMENTATION IS FREE
+// FROM ANY CLAIMS OF INFRINGEMENT, AND YOU ARE
+// RESPONSIBLE FOR OBTAINING ANY RIGHTS YOU MAY
+// REQUIRE FOR YOUR IMPLEMENTATION. XILINX
+// EXPRESSLY DISCLAIMS ANY WARRANTY WHATSOEVER WITH
+// RESPECT TO THE ADEQUACY OF THE IMPLEMENTATION,
+// INCLUDING BUT NOT LIMITED TO ANY WARRANTIES OR
+// REPRESENTATIONS THAT THIS IMPLEMENTATION IS FREE
+// FROM CLAIMS OF INFRINGEMENT, IMPLIED WARRANTIES
+// OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
+// PURPOSE.
+//
+// (c) Copyright 2009-2010 Xilinx, Inc.
+// All rights reserved.
+//
+///////////////////////////////////////////////////////////////////////////////
+
+// These are user functions that should not be modified. Changes to the defines
+// or code within the functions may alter the accuracy of the calculations.
+
+// Define debug to provide extra messages durring elaboration
+//`define DEBUG 1
+
+// FRAC_PRECISION describes the width of the fractional portion of the fixed
+// point numbers. These should not be modified, they are for development
+// only
+`define FRAC_PRECISION 10
+// FIXED_WIDTH describes the total size for fixed point calculations(int+frac).
+// Warning: L.50 and below will not calculate properly with FIXED_WIDTHs
+// greater than 32
+`define FIXED_WIDTH 32
+
+// This function takes a fixed point number and rounds it to the nearest
+// fractional precision bit.
+function [`FIXED_WIDTH:1] round_frac
+ (
+ // Input is (FIXED_WIDTH-FRAC_PRECISION).FRAC_PRECISION fixed point number
+ input [`FIXED_WIDTH:1] decimal,
+
+ // This describes the precision of the fraction, for example a value
+ // of 1 would modify the fractional so that instead of being a .16
+ // fractional, it would be a .1 (rounded to the nearest 0.5 in turn)
+ input [`FIXED_WIDTH:1] precision
+ );
+
+ begin
+
+ `ifdef DEBUG
+ $display("round_frac - decimal: %h, precision: %h", decimal, precision);
+ `endif
+ // If the fractional precision bit is high then round up
+ if( decimal[(`FRAC_PRECISION-precision)] == 1'b1) begin
+ round_frac = decimal + (1'b1 << (`FRAC_PRECISION-precision));
+ end else begin
+ round_frac = decimal;
+ end
+ `ifdef DEBUG
+ $display("round_frac: %h", round_frac);
+ `endif
+ end
+endfunction
+
+// This function calculates high_time, low_time, w_edge, and no_count
+// of a non-fractional counter based on the divide and duty cycle
+//
+// NOTE: high_time and low_time are returned as integers between 0 and 63
+// inclusive. 64 should equal 6'b000000 (in other words it is okay to
+// ignore the overflow)
+function [13:0] mmcm_pll_divider
+ (
+ input [7:0] divide, // Max divide is 128
+ input [31:0] duty_cycle // Duty cycle is multiplied by 100,000
+ );
+
+ reg [`FIXED_WIDTH:1] duty_cycle_fix;
+
+ // High/Low time is initially calculated with a wider integer to prevent a
+ // calculation error when it overflows to 64.
+ reg [6:0] high_time;
+ reg [6:0] low_time;
+ reg w_edge;
+ reg no_count;
+
+ reg [`FIXED_WIDTH:1] temp;
+
+ begin
+ // Duty Cycle must be between 0 and 1,000
+ if(duty_cycle <=0 || duty_cycle >= 100000) begin
+`ifndef SYNTHESIS
+ $display("ERROR: duty_cycle: %d is invalid", duty_cycle);
+ `endif
+ $finish;
+ end
+
+ // Convert to FIXED_WIDTH-FRAC_PRECISION.FRAC_PRECISION fixed point
+ duty_cycle_fix = (duty_cycle << `FRAC_PRECISION) / 100_000;
+
+ `ifdef DEBUG
+ $display("duty_cycle_fix: %h", duty_cycle_fix);
+ `endif
+
+ // If the divide is 1 nothing needs to be set except the no_count bit.
+ // Other values are dummies
+ if(divide == 7'h01) begin
+ high_time = 7'h01;
+ w_edge = 1'b0;
+ low_time = 7'h01;
+ no_count = 1'b1;
+ end else begin
+ temp = round_frac(duty_cycle_fix*divide, 1);
+
+ // comes from above round_frac
+ high_time = temp[`FRAC_PRECISION+7:`FRAC_PRECISION+1];
+ // If the duty cycle * divide rounded is .5 or greater then this bit
+ // is set.
+ w_edge = temp[`FRAC_PRECISION]; // comes from round_frac
+
+ // If the high time comes out to 0, it needs to be set to at least 1
+ // and w_edge set to 0
+ if(high_time == 7'h00) begin
+ high_time = 7'h01;
+ w_edge = 1'b0;
+ end
+
+ if(high_time == divide) begin
+ high_time = divide - 1;
+ w_edge = 1'b1;
+ end
+
+ // Calculate low_time based on the divide setting and set no_count to
+ // 0 as it is only used when divide is 1.
+ low_time = divide - high_time;
+ no_count = 1'b0;
+ end
+
+ // Set the return value.
+ mmcm_pll_divider = {w_edge,no_count,high_time[5:0],low_time[5:0]};
+ end
+endfunction
+
+// This function calculates mx, delay_time, and phase_mux
+// of a non-fractional counter based on the divide and phase
+//
+// NOTE: The only valid value for the MX bits is 2'b00 to ensure the coarse mux
+// is used.
+function [10:0] mmcm_pll_phase
+ (
+ // divide must be an integer (use fractional if not)
+ // assumed that divide already checked to be valid
+ input [7:0] divide, // Max divide is 128
+
+ // Phase is given in degrees (-360,000 to 360,000)
+ input signed [31:0] phase
+ );
+
+ reg [`FIXED_WIDTH:1] phase_in_cycles;
+ reg [`FIXED_WIDTH:1] phase_fixed;
+ reg [1:0] mx;
+ reg [5:0] delay_time;
+ reg [2:0] phase_mux;
+
+ reg [`FIXED_WIDTH:1] temp;
+
+ begin
+`ifdef DEBUG
+ $display("mmcm_pll_phase-divide:%d,phase:%d",
+ divide, phase);
+`endif
+
+ if ((phase < -360000) || (phase > 360000)) begin
+`ifndef SYNTHESIS
+ $display("ERROR: phase of $phase is not between -360000 and 360000");
+ `endif
+ $finish;
+ end
+
+ // If phase is less than 0, convert it to a positive phase shift
+ // Convert to (FIXED_WIDTH-FRAC_PRECISION).FRAC_PRECISION fixed point
+ if(phase < 0) begin
+ phase_fixed = ( (phase + 360000) << `FRAC_PRECISION ) / 1000;
+ end else begin
+ phase_fixed = ( phase << `FRAC_PRECISION ) / 1000;
+ end
+
+ // Put phase in terms of decimal number of vco clock cycles
+ phase_in_cycles = ( phase_fixed * divide ) / 360;
+
+`ifdef DEBUG
+ $display("phase_in_cycles: %h", phase_in_cycles);
+`endif
+
+
+ temp = round_frac(phase_in_cycles, 3);
+
+ // set mx to 2'b00 that the phase mux from the VCO is enabled
+ mx = 2'b00;
+ phase_mux = temp[`FRAC_PRECISION:`FRAC_PRECISION-2];
+ delay_time = temp[`FRAC_PRECISION+6:`FRAC_PRECISION+1];
+
+ `ifdef DEBUG
+ $display("temp: %h", temp);
+ `endif
+
+ // Setup the return value
+ mmcm_pll_phase={mx, phase_mux, delay_time};
+ end
+endfunction
+
+// This function takes the divide value and outputs the necessary lock values
+function [39:0] mmcm_pll_lock_lookup
+ (
+ input [6:0] divide // Max divide is 64
+ );
+
+ reg [759:0] lookup;
+
+ begin
+ lookup = {
+ // This table is composed of:
+ // LockRefDly_LockFBDly_LockCnt_LockSatHigh_UnlockCnt
+ 40'b00110_00110_1111101000_1111101001_0000000001, //1
+ 40'b00110_00110_1111101000_1111101001_0000000001, //2
+ 40'b01000_01000_1111101000_1111101001_0000000001, //3
+ 40'b01011_01011_1111101000_1111101001_0000000001, //4
+ 40'b01110_01110_1111101000_1111101001_0000000001, //5
+ 40'b10001_10001_1111101000_1111101001_0000000001, //6
+ 40'b10011_10011_1111101000_1111101001_0000000001, //7
+ 40'b10110_10110_1111101000_1111101001_0000000001, //8
+ 40'b11001_11001_1111101000_1111101001_0000000001, //9
+ 40'b11100_11100_1111101000_1111101001_0000000001, //10
+ 40'b11111_11111_1110000100_1111101001_0000000001, //11
+ 40'b11111_11111_1100111001_1111101001_0000000001, //12
+ 40'b11111_11111_1011101110_1111101001_0000000001, //13
+ 40'b11111_11111_1010111100_1111101001_0000000001, //14
+ 40'b11111_11111_1010001010_1111101001_0000000001, //15
+ 40'b11111_11111_1001110001_1111101001_0000000001, //16
+ 40'b11111_11111_1000111111_1111101001_0000000001, //17
+ 40'b11111_11111_1000100110_1111101001_0000000001, //18
+ 40'b11111_11111_1000001101_1111101001_0000000001 //19
+
+ };
+
+ // Set lookup_entry with the explicit bits from lookup with a part select
+ mmcm_pll_lock_lookup = lookup[ ((19-divide)*40) +: 40];
+ `ifdef DEBUG
+ $display("lock_lookup: %b", mmcm_pll_lock_lookup);
+ `endif
+ end
+endfunction
+
+// This function takes the divide value and the bandwidth setting of the PLL
+// and outputs the digital filter settings necessary. Removing bandwidth setting for PLLE3.
+function [9:0] mmcm_pll_filter_lookup
+ (
+ input [6:0] divide // Max divide is 19
+ );
+
+ reg [639:0] lookup;
+ reg [9:0] lookup_entry;
+
+ begin
+
+ lookup = {
+ // CP_RES_LFHF
+ 10'b0010_1111_01, //1
+ 10'b0010_0011_11, //2
+ 10'b0011_0011_11, //3
+ 10'b0010_0001_11, //4
+ 10'b0010_0110_11, //5
+ 10'b0010_1010_11, //6
+ 10'b0010_1010_11, //7
+ 10'b0011_0110_11, //8
+ 10'b0010_1100_11, //9
+ 10'b0010_1100_11, //10
+ 10'b0010_1100_11, //11
+ 10'b0010_0010_11, //12
+ 10'b0011_1100_11, //13
+ 10'b0011_1100_11, //14
+ 10'b0011_1100_11, //15
+ 10'b0011_1100_11, //16
+ 10'b0011_0010_11, //17
+ 10'b0011_0010_11, //18
+ 10'b0011_0010_11 //19
+ };
+
+ mmcm_pll_filter_lookup = lookup [ ((19-divide)*10) +: 10];
+
+ `ifdef DEBUG
+ $display("filter_lookup: %b", mmcm_pll_filter_lookup);
+ `endif
+ end
+endfunction
+
+// This function set the CLKOUTPHY divide settings to match
+// the desired CLKOUTPHY_MODE setting. To create VCO_X2, then
+// the CLKOUTPHY will be set to 2'b00 since the VCO is internally
+// doubled and 2'b00 will represent divide by 1. Similarly "VCO" // will need to divide the doubled clock VCO clock frequency by // 2 therefore 2'b01 will match a divide by 2.And VCO_HALF will // need to divide the doubled VCO by 4, therefore 2'b10
+function [9:0] mmcm_pll_clkoutphy_calc
+ (
+ input [8*9:0] CLKOUTPHY_MODE
+ );
+
+ if(CLKOUTPHY_MODE == "VCO_X2") begin
+ mmcm_pll_clkoutphy_calc= 2'b00;
+ end else if(CLKOUTPHY_MODE == "VCO") begin
+ mmcm_pll_clkoutphy_calc= 2'b01;
+ end else if(CLKOUTPHY_MODE == "CLKIN") begin
+ mmcm_pll_clkoutphy_calc= 2'b11;
+ end else begin // Assume "VCO_HALF"
+ mmcm_pll_clkoutphy_calc= 2'b10;
+ end
+
+endfunction
+
+
+// This function takes in the divide, phase, and duty cycle
+// setting to calculate the upper and lower counter registers.
+function [37:0] mmcm_pll_count_calc
+ (
+ input [7:0] divide, // Max divide is 128
+ input signed [31:0] phase,
+ input [31:0] duty_cycle // Multiplied by 100,000
+ );
+
+ reg [13:0] div_calc;
+ reg [16:0] phase_calc;
+
+ begin
+ `ifdef DEBUG
+ $display("mmcm_pll_count_calc- divide:%h, phase:%d, duty_cycle:%d",
+ divide, phase, duty_cycle);
+ `endif
+
+ // w_edge[13], no_count[12], high_time[11:6], low_time[5:0]
+ div_calc = mmcm_pll_divider(divide, duty_cycle);
+ // mx[10:9], pm[8:6], dt[5:0]
+ phase_calc = mmcm_pll_phase(divide, phase);
+
+ // Return value is the upper and lower address of counter
+ // Upper address is:
+ // RESERVED [31:26]
+ // MX [25:24]
+ // EDGE [23]
+ // NOCOUNT [22]
+ // DELAY_TIME [21:16]
+ // Lower Address is:
+ // PHASE_MUX [15:13]
+ // RESERVED [12]
+ // HIGH_TIME [11:6]
+ // LOW_TIME [5:0]
+
+ `ifdef DEBUG
+ $display("div:%d dc:%d phase:%d ht:%d lt:%d ed:%d nc:%d mx:%d dt:%d pm:%d",
+ divide, duty_cycle, phase, div_calc[11:6], div_calc[5:0],
+ div_calc[13], div_calc[12],
+ phase_calc[16:15], phase_calc[5:0], 3'b000);//Removed PM_Rise bits
+ `endif
+
+ mmcm_pll_count_calc =
+ {
+ // Upper Address
+ 6'h00, phase_calc[10:9], div_calc[13:12], phase_calc[5:0],
+ // Lower Address
+ phase_calc[8:6], 1'b0, div_calc[11:0]
+ };
+ end
+endfunction
+
+
+// This function takes in the divide, phase, and duty cycle
+// setting to calculate the upper and lower counter registers.
+// for fractional multiply/divide functions.
+//
+//
+function [37:0] mmcm_pll_frac_count_calc
+ (
+ input [7:0] divide, // Max divide is 128
+ input signed [31:0] phase,
+ input [31:0] duty_cycle, // Multiplied by 1,000
+ input [9:0] frac // Multiplied by 1000
+ );
+
+ //Required for fractional divide calculations
+ reg [7:0] lt_frac;
+ reg [7:0] ht_frac;
+
+ reg /*[7:0]*/ wf_fall_frac;
+ reg /*[7:0]*/ wf_rise_frac;
+
+ reg [31:0] a;
+ reg [7:0] pm_rise_frac_filtered ;
+ reg [7:0] pm_fall_frac_filtered ;
+ reg [7:0] clkout0_divide_int;
+ reg [2:0] clkout0_divide_frac;
+ reg [7:0] even_part_high;
+ reg [7:0] even_part_low;
+
+ reg [7:0] odd;
+ reg [7:0] odd_and_frac;
+
+ reg [7:0] pm_fall;
+ reg [7:0] pm_rise;
+ reg [7:0] dt;
+ reg [7:0] dt_int;
+ reg [63:0] dt_calc;
+
+ reg [7:0] pm_rise_frac;
+ reg [7:0] pm_fall_frac;
+
+ reg [31:0] a_per_in_octets;
+ reg [31:0] a_phase_in_cycles;
+
+ parameter precision = 0.125;
+
+ reg [31:0] phase_fixed; // changed to 31:0 from 32:1 jt 5/2/11
+ reg [31: 0] phase_pos;
+ reg [31: 0] phase_vco;
+ reg [31:0] temp;// changed to 31:0 from 32:1 jt 5/2/11
+ reg [13:0] div_calc;
+ reg [16:0] phase_calc;
+
+ begin
+ `ifdef DEBUG
+ $display("mmcm_pll_frac_count_calc- divide:%h, phase:%d, duty_cycle:%d",
+ divide, phase, duty_cycle);
+ `endif
+
+ //convert phase to fixed
+ if ((phase < -360000) || (phase > 360000)) begin
+`ifndef SYNTHESIS
+ $display("ERROR: phase of $phase is not between -360000 and 360000");
+ `endif
+ $finish;
+ end
+
+
+ // Return value is
+ // Transfer data
+ // RESERVED [37:36]
+ // FRAC_TIME [35:33]
+ // FRAC_WF_FALL [32]
+ // Upper address is:
+ // RESERVED [31:26]
+ // MX [25:24]
+ // EDGE [23]
+ // NOCOUNT [22]
+ // DELAY_TIME [21:16]
+ // Lower Address is:
+ // PHASE_MUX [15:13]
+ // RESERVED [12]
+ // HIGH_TIME [11:6]
+ // LOW_TIME [5:0]
+
+
+
+ clkout0_divide_frac = frac / 125;
+ clkout0_divide_int = divide;
+
+ even_part_high = clkout0_divide_int >> 1;//$rtoi(clkout0_divide_int / 2);
+ even_part_low = even_part_high;
+
+ odd = clkout0_divide_int - even_part_high - even_part_low;
+ odd_and_frac = (8*odd) + clkout0_divide_frac;
+
+ lt_frac = even_part_high - (odd_and_frac <= 9);//IF(odd_and_frac>9,even_part_high, even_part_high - 1)
+ ht_frac = even_part_low - (odd_and_frac <= 8);//IF(odd_and_frac>8,even_part_low, even_part_low- 1)
+
+ pm_fall = {odd[6:0],2'b00} + {6'h00, clkout0_divide_frac[2:1]}; // using >> instead of clkout0_divide_frac / 2
+ pm_rise = 0; //0
+
+ wf_fall_frac = (odd_and_frac >=2) && (odd_and_frac <=9);//IF(odd_and_frac>=2,IF(odd_and_frac <= 9,1,0),0)
+ wf_rise_frac = (odd_and_frac >=1) && (odd_and_frac <=8);//IF(odd_and_frac>=1,IF(odd_and_frac <= 8,1,0),0)
+
+
+
+ //Calculate phase in fractional cycles
+ a_per_in_octets = (8 * divide) + (frac / 125) ;
+ a_phase_in_cycles = (phase+10) * a_per_in_octets / 360000 ;//Adding 1 due to rounding errors
+ pm_rise_frac = (a_phase_in_cycles[7:0] ==8'h00)?8'h00:a_phase_in_cycles[7:0] - {a_phase_in_cycles[7:3],3'b000};
+
+ dt_calc = ((phase+10) * a_per_in_octets / 8 )/360000 ;//TRUNC(phase* divide / 360); //or_simply (a_per_in_octets / 8)
+ dt = dt_calc[7:0];
+
+ pm_rise_frac_filtered = (pm_rise_frac >=8) ? (pm_rise_frac ) - 8: pm_rise_frac ; //((phase_fixed * (divide + frac / 1000)) / 360) - {pm_rise_frac[7:3],3'b000};//$rtoi(clkout0_phase * clkout0_divide / 45);//a;
+
+ dt_int = dt + (& pm_rise_frac[7:4]); //IF(pm_rise_overwriting>7,dt+1,dt)
+ pm_fall_frac = pm_fall + pm_rise_frac;
+ pm_fall_frac_filtered = pm_fall + pm_rise_frac - {pm_fall_frac[7:3], 3'b000};
+
+ div_calc = mmcm_pll_divider(divide, duty_cycle); //Use to determine edge[7], no count[6]
+ phase_calc = mmcm_pll_phase(divide, phase);// returns{mx[1:0], phase_mux[2:0], delay_time[5:0]}
+
+ mmcm_pll_frac_count_calc[37:0] =
+ { 2'b00, pm_fall_frac_filtered[2:0], wf_fall_frac,
+ 1'b0, clkout0_divide_frac[2:0], 1'b1, wf_rise_frac, phase_calc[10:9], div_calc[13:12], dt[5:0],
+ 3'b000, 1'b0, ht_frac[5:0], lt_frac[5:0] //Removed PM_Rise bits
+// pm_rise_frac_filtered[2], pm_rise_frac_filtered[1], pm_rise_frac_filtered[0], 1'b0, ht_frac[5:0], lt_frac[5:0]
+ } ;
+
+ `ifdef DEBUG
+ $display("-%d.%d p%d>> :DADDR_9_15 frac30to28.frac_en.wf_r_frac.dt:%b%d%d_%b:DADDR_7_13 pm_f_frac_filtered_29to27.wf_f_frac_26:%b%d:DADDR_8_14.pm_r_frac_filt_15to13.ht_frac.lt_frac:%b%b%b:", divide, frac, phase, clkout0_divide_frac, 1, wf_rise_frac, dt, pm_fall_frac_filtered, wf_fall_frac, 3'b000, ht_frac, lt_frac);
+ `endif
+
+ end
+endfunction
+
+
diff --git a/game.gen/sources_1/ip/clk_wiz_0/mmcm_pll_drp_func_us_plus_mmcm.vh b/game.gen/sources_1/ip/clk_wiz_0/mmcm_pll_drp_func_us_plus_mmcm.vh
new file mode 100755
index 0000000000000000000000000000000000000000..ebf87be0b41af231c503eefb0859dbe93dbe8cd4
--- /dev/null
+++ b/game.gen/sources_1/ip/clk_wiz_0/mmcm_pll_drp_func_us_plus_mmcm.vh
@@ -0,0 +1,861 @@
+///////////////////////////////////////////////////////////////////////////////
+//
+// Company: Xilinx
+// Engineer: Jim Tatsukawa. Updated by Ralf Krueger
+// Date: 7/30/2014
+// Design Name: MMCME4 DRP
+// Module Name: mmcme4_drp_func.h
+// Version: 1.31
+// Target Devices: UltraScale Plus Architecture
+// Tool versions: 2017.1
+// Description: This header provides the functions necessary to
+// calculate the DRP register values for UltraScal+ MMCM.
+//
+// Revision Notes: 3/22 - Updating lookup_low/lookup_high (CR)
+// 4/13 - Fractional divide function in mmcm_frac_count_calc function
+// 2/28/17 - Updated for Ultrascale Plus
+//
+// Disclaimer: XILINX IS PROVIDING THIS DESIGN, CODE, OR
+// INFORMATION "AS IS" SOLELY FOR USE IN DEVELOPING
+// PROGRAMS AND SOLUTIONS FOR XILINX DEVICES. BY
+// PROVIDING THIS DESIGN, CODE, OR INFORMATION AS
+// ONE POSSIBLE IMPLEMENTATION OF THIS FEATURE,
+// APPLICATION OR STANDARD, XILINX IS MAKING NO
+// REPRESENTATION THAT THIS IMPLEMENTATION IS FREE
+// FROM ANY CLAIMS OF INFRINGEMENT, AND YOU ARE
+// RESPONSIBLE FOR OBTAINING ANY RIGHTS YOU MAY
+// REQUIRE FOR YOUR IMPLEMENTATION. XILINX
+// EXPRESSLY DISCLAIMS ANY WARRANTY WHATSOEVER WITH
+// RESPECT TO THE ADEQUACY OF THE IMPLEMENTATION,
+// INCLUDING BUT NOT LIMITED TO ANY WARRANTIES OR
+// REPRESENTATIONS THAT THIS IMPLEMENTATION IS FREE
+// FROM CLAIMS OF INFRINGEMENT, IMPLIED WARRANTIES
+// OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
+// PURPOSE.
+//
+// (c) Copyright 2009-2017 Xilinx, Inc.
+// All rights reserved.
+//
+///////////////////////////////////////////////////////////////////////////////
+
+// These are user functions that should not be modified. Changes to the defines
+// or code within the functions may alter the accuracy of the calculations.
+
+// Define debug to provide extra messages during elaboration
+//`define DEBUG 1
+
+// FRAC_PRECISION describes the width of the fractional portion of the fixed
+// point numbers. These should not be modified, they are for development only
+`define FRAC_PRECISION 10
+// FIXED_WIDTH describes the total size for fixed point calculations(int+frac).
+// Warning: L.50 and below will not calculate properly with FIXED_WIDTHs
+// greater than 32
+`define FIXED_WIDTH 32
+
+// This function takes a fixed point number and rounds it to the nearest
+// fractional precision bit.
+function [`FIXED_WIDTH:1] round_frac
+ (
+ // Input is (FIXED_WIDTH-FRAC_PRECISION).FRAC_PRECISION fixed point number
+ input [`FIXED_WIDTH:1] decimal,
+
+ // This describes the precision of the fraction, for example a value
+ // of 1 would modify the fractional so that instead of being a .16
+ // fractional, it would be a .1 (rounded to the nearest 0.5 in turn)
+ input [`FIXED_WIDTH:1] precision
+ );
+
+ begin
+
+ `ifdef DEBUG
+ $display("round_frac - decimal: %h, precision: %h", decimal, precision);
+ `endif
+ // If the fractional precision bit is high then round up
+ if( decimal[(`FRAC_PRECISION-precision)] == 1'b1) begin
+ round_frac = decimal + (1'b1 << (`FRAC_PRECISION-precision));
+ end else begin
+ round_frac = decimal;
+ end
+ `ifdef DEBUG
+ $display("round_frac: %h", round_frac);
+ `endif
+ end
+endfunction
+
+// This function calculates high_time, low_time, w_edge, and no_count
+// of a non-fractional counter based on the divide and duty cycle
+//
+// NOTE: high_time and low_time are returned as integers between 0 and 63
+// inclusive. 64 should equal 6'b000000 (in other words it is okay to
+// ignore the overflow)
+function [13:0] mmcm_pll_divider
+ (
+ input [7:0] divide, // Max divide is 128
+ input [31:0] duty_cycle // Duty cycle is multiplied by 100,000
+ );
+
+ reg [`FIXED_WIDTH:1] duty_cycle_fix;
+
+ // High/Low time is initially calculated with a wider integer to prevent a
+ // calculation error when it overflows to 64.
+ reg [6:0] high_time;
+ reg [6:0] low_time;
+ reg w_edge;
+ reg no_count;
+
+ reg [`FIXED_WIDTH:1] temp;
+
+ begin
+ // Duty Cycle must be between 0 and 1,000
+ if(duty_cycle <=0 || duty_cycle >= 100000) begin
+`ifndef SYNTHESIS
+ $display("ERROR: duty_cycle: %d is invalid", duty_cycle);
+ `endif
+ $finish;
+ end
+
+ // Convert to FIXED_WIDTH-FRAC_PRECISION.FRAC_PRECISION fixed point
+ duty_cycle_fix = (duty_cycle << `FRAC_PRECISION) / 100_000;
+
+ `ifdef DEBUG
+ $display("duty_cycle_fix: %h", duty_cycle_fix);
+ `endif
+
+ // If the divide is 1 nothing needs to be set except the no_count bit.
+ // Other values are dummies
+ if(divide == 7'h01) begin
+ high_time = 7'h01;
+ w_edge = 1'b0;
+ low_time = 7'h01;
+ no_count = 1'b1;
+ end else begin
+ temp = round_frac(duty_cycle_fix*divide, 1);
+
+ // comes from above round_frac
+ high_time = temp[`FRAC_PRECISION+7:`FRAC_PRECISION+1];
+ // If the duty cycle * divide rounded is .5 or greater then this bit
+ // is set.
+ w_edge = temp[`FRAC_PRECISION]; // comes from round_frac
+
+ // If the high time comes out to 0, it needs to be set to at least 1
+ // and w_edge set to 0
+ if(high_time == 7'h00) begin
+ high_time = 7'h01;
+ w_edge = 1'b0;
+ end
+
+ if(high_time == divide) begin
+ high_time = divide - 1;
+ w_edge = 1'b1;
+ end
+
+ // Calculate low_time based on the divide setting and set no_count to
+ // 0 as it is only used when divide is 1.
+ low_time = divide - high_time;
+ no_count = 1'b0;
+ end
+
+ // Set the return value.
+ mmcm_pll_divider = {w_edge,no_count,high_time[5:0],low_time[5:0]};
+ end
+endfunction
+
+// This function calculates mx, delay_time, and phase_mux
+// of a non-fractional counter based on the divide and phase
+//
+// NOTE: The only valid value for the MX bits is 2'b00 to ensure the coarse mux
+// is used.
+function [10:0] mmcm_pll_phase
+ (
+ // divide must be an integer (use fractional if not)
+ // assumed that divide already checked to be valid
+ input [7:0] divide, // Max divide is 128
+
+ // Phase is given in degrees (-360,000 to 360,000)
+ input signed [31:0] phase
+ );
+
+ reg [`FIXED_WIDTH:1] phase_in_cycles;
+ reg [`FIXED_WIDTH:1] phase_fixed;
+ reg [1:0] mx;
+ reg [5:0] delay_time;
+ reg [2:0] phase_mux;
+
+ reg [`FIXED_WIDTH:1] temp;
+
+ begin
+`ifdef DEBUG
+ $display("mmcm_phase-divide:%d,phase:%d", divide, phase);
+`endif
+
+ if ((phase < -360000) || (phase > 360000)) begin
+`ifndef SYNTHESIS
+ $display("ERROR: phase of $phase is not between -360000 and 360000");
+ `endif
+ $finish;
+ end
+
+ // If phase is less than 0, convert it to a positive phase shift
+ // Convert to (FIXED_WIDTH-FRAC_PRECISION).FRAC_PRECISION fixed point
+ if(phase < 0) begin
+ phase_fixed = ( (phase + 360000) << `FRAC_PRECISION ) / 1000;
+ end else begin
+ phase_fixed = ( phase << `FRAC_PRECISION ) / 1000;
+ end
+
+ // Put phase in terms of decimal number of vco clock cycles
+ phase_in_cycles = ( phase_fixed * divide ) / 360;
+
+`ifdef DEBUG
+ $display("phase_in_cycles: %h", phase_in_cycles);
+`endif
+
+ temp = round_frac(phase_in_cycles, 3);
+
+ // set mx to 2'b00 that the phase mux from the VCO is enabled
+ mx = 2'b00;
+ phase_mux = temp[`FRAC_PRECISION:`FRAC_PRECISION-2];
+ delay_time = temp[`FRAC_PRECISION+6:`FRAC_PRECISION+1];
+
+ `ifdef DEBUG
+ $display("temp: %h", temp);
+ `endif
+
+ // Setup the return value
+ mmcm_pll_phase={mx, phase_mux, delay_time};
+ end
+endfunction
+
+// This function takes the divide value and outputs the necessary lock values
+function [39:0] mmcm_pll_lock_lookup
+ (
+ input [7:0] divide // Max M divide is 128 in UltrascalePlus
+ );
+
+ reg [5119:0] lookup;
+
+ begin
+ lookup = {
+ // This table is composed of:
+ // LockRefDly_LockFBDly_LockCnt_LockSatHigh_UnlockCnt
+ 40'b00110_00110_1111101000_1111101001_0000000001, // M=1 (not allowed)
+ 40'b00110_00110_1111101000_1111101001_0000000001, // M=2
+ 40'b01000_01000_1111101000_1111101001_0000000001, // M=3
+ 40'b01011_01011_1111101000_1111101001_0000000001, // M=4
+ 40'b01110_01110_1111101000_1111101001_0000000001, // M=5
+ 40'b10001_10001_1111101000_1111101001_0000000001, // M=6
+ 40'b10011_10011_1111101000_1111101001_0000000001, // M=7
+ 40'b10110_10110_1111101000_1111101001_0000000001,
+ 40'b11001_11001_1111101000_1111101001_0000000001,
+ 40'b11100_11100_1111101000_1111101001_0000000001,
+ 40'b11111_11111_1110000100_1111101001_0000000001,
+ 40'b11111_11111_1100111001_1111101001_0000000001,
+ 40'b11111_11111_1011101110_1111101001_0000000001,
+ 40'b11111_11111_1010111100_1111101001_0000000001,
+ 40'b11111_11111_1010001010_1111101001_0000000001,
+ 40'b11111_11111_1001110001_1111101001_0000000001,
+ 40'b11111_11111_1000111111_1111101001_0000000001,
+ 40'b11111_11111_1000100110_1111101001_0000000001,
+ 40'b11111_11111_1000001101_1111101001_0000000001,
+ 40'b11111_11111_0111110100_1111101001_0000000001,
+ 40'b11111_11111_0111011011_1111101001_0000000001,
+ 40'b11111_11111_0111000010_1111101001_0000000001,
+ 40'b11111_11111_0110101001_1111101001_0000000001,
+ 40'b11111_11111_0110010000_1111101001_0000000001,
+ 40'b11111_11111_0110010000_1111101001_0000000001,
+ 40'b11111_11111_0101110111_1111101001_0000000001,
+ 40'b11111_11111_0101011110_1111101001_0000000001,
+ 40'b11111_11111_0101011110_1111101001_0000000001,
+ 40'b11111_11111_0101000101_1111101001_0000000001,
+ 40'b11111_11111_0101000101_1111101001_0000000001,
+ 40'b11111_11111_0100101100_1111101001_0000000001,
+ 40'b11111_11111_0100101100_1111101001_0000000001,
+ 40'b11111_11111_0100101100_1111101001_0000000001,
+ 40'b11111_11111_0100010011_1111101001_0000000001,
+ 40'b11111_11111_0100010011_1111101001_0000000001,
+ 40'b11111_11111_0100010011_1111101001_0000000001,
+ 40'b11111_11111_0011111010_1111101001_0000000001,
+ 40'b11111_11111_0011111010_1111101001_0000000001,
+ 40'b11111_11111_0011111010_1111101001_0000000001,
+ 40'b11111_11111_0011111010_1111101001_0000000001,
+ 40'b11111_11111_0011111010_1111101001_0000000001,
+ 40'b11111_11111_0011111010_1111101001_0000000001,
+ 40'b11111_11111_0011111010_1111101001_0000000001,
+ 40'b11111_11111_0011111010_1111101001_0000000001,
+ 40'b11111_11111_0011111010_1111101001_0000000001,
+ 40'b11111_11111_0011111010_1111101001_0000000001,
+ 40'b11111_11111_0011111010_1111101001_0000000001,
+ 40'b11111_11111_0011111010_1111101001_0000000001,
+ 40'b11111_11111_0011111010_1111101001_0000000001,
+ 40'b11111_11111_0011111010_1111101001_0000000001,
+ 40'b11111_11111_0011111010_1111101001_0000000001,
+ 40'b11111_11111_0011111010_1111101001_0000000001,
+ 40'b11111_11111_0011111010_1111101001_0000000001,
+ 40'b11111_11111_0011111010_1111101001_0000000001,
+ 40'b11111_11111_0011111010_1111101001_0000000001,
+ 40'b11111_11111_0011111010_1111101001_0000000001,
+ 40'b11111_11111_0011111010_1111101001_0000000001,
+ 40'b11111_11111_0011111010_1111101001_0000000001,
+ 40'b11111_11111_0011111010_1111101001_0000000001,
+ 40'b11111_11111_0011111010_1111101001_0000000001,
+ 40'b11111_11111_0011111010_1111101001_0000000001,
+ 40'b11111_11111_0011111010_1111101001_0000000001,
+ 40'b11111_11111_0011111010_1111101001_0000000001,
+ 40'b11111_11111_0011111010_1111101001_0000000001,
+ 40'b11111_11111_0011111010_1111101001_0000000001,
+ 40'b11111_11111_0011111010_1111101001_0000000001,
+ 40'b11111_11111_0011111010_1111101001_0000000001,
+ 40'b11111_11111_0011111010_1111101001_0000000001,
+ 40'b11111_11111_0011111010_1111101001_0000000001,
+ 40'b11111_11111_0011111010_1111101001_0000000001,
+ 40'b11111_11111_0011111010_1111101001_0000000001,
+ 40'b11111_11111_0011111010_1111101001_0000000001,
+ 40'b11111_11111_0011111010_1111101001_0000000001,
+ 40'b11111_11111_0011111010_1111101001_0000000001,
+ 40'b11111_11111_0011111010_1111101001_0000000001,
+ 40'b11111_11111_0011111010_1111101001_0000000001,
+ 40'b11111_11111_0011111010_1111101001_0000000001,
+ 40'b11111_11111_0011111010_1111101001_0000000001,
+ 40'b11111_11111_0011111010_1111101001_0000000001,
+ 40'b11111_11111_0011111010_1111101001_0000000001,
+ 40'b11111_11111_0011111010_1111101001_0000000001,
+ 40'b11111_11111_0011111010_1111101001_0000000001,
+ 40'b11111_11111_0011111010_1111101001_0000000001,
+ 40'b11111_11111_0011111010_1111101001_0000000001,
+ 40'b11111_11111_0011111010_1111101001_0000000001,
+ 40'b11111_11111_0011111010_1111101001_0000000001,
+ 40'b11111_11111_0011111010_1111101001_0000000001,
+ 40'b11111_11111_0011111010_1111101001_0000000001,
+ 40'b11111_11111_0011111010_1111101001_0000000001,
+ 40'b11111_11111_0011111010_1111101001_0000000001,
+ 40'b11111_11111_0011111010_1111101001_0000000001,
+ 40'b11111_11111_0011111010_1111101001_0000000001,
+ 40'b11111_11111_0011111010_1111101001_0000000001,
+ 40'b11111_11111_0011111010_1111101001_0000000001,
+ 40'b11111_11111_0011111010_1111101001_0000000001,
+ 40'b11111_11111_0011111010_1111101001_0000000001,
+ 40'b11111_11111_0011111010_1111101001_0000000001,
+ 40'b11111_11111_0011111010_1111101001_0000000001,
+ 40'b11111_11111_0011111010_1111101001_0000000001,
+ 40'b11111_11111_0011111010_1111101001_0000000001,
+ 40'b11111_11111_0011111010_1111101001_0000000001,
+ 40'b11111_11111_0011111010_1111101001_0000000001,
+ 40'b11111_11111_0011111010_1111101001_0000000001,
+ 40'b11111_11111_0011111010_1111101001_0000000001,
+ 40'b11111_11111_0011111010_1111101001_0000000001,
+ 40'b11111_11111_0011111010_1111101001_0000000001,
+ 40'b11111_11111_0011111010_1111101001_0000000001,
+ 40'b11111_11111_0011111010_1111101001_0000000001,
+ 40'b11111_11111_0011111010_1111101001_0000000001,
+ 40'b11111_11111_0011111010_1111101001_0000000001,
+ 40'b11111_11111_0011111010_1111101001_0000000001,
+ 40'b11111_11111_0011111010_1111101001_0000000001,
+ 40'b11111_11111_0011111010_1111101001_0000000001,
+ 40'b11111_11111_0011111010_1111101001_0000000001,
+ 40'b11111_11111_0011111010_1111101001_0000000001,
+ 40'b11111_11111_0011111010_1111101001_0000000001,
+ 40'b11111_11111_0011111010_1111101001_0000000001,
+ 40'b11111_11111_0011111010_1111101001_0000000001,
+ 40'b11111_11111_0011111010_1111101001_0000000001,
+ 40'b11111_11111_0011111010_1111101001_0000000001,
+ 40'b11111_11111_0011111010_1111101001_0000000001,
+ 40'b11111_11111_0011111010_1111101001_0000000001,
+ 40'b11111_11111_0011111010_1111101001_0000000001,
+ 40'b11111_11111_0011111010_1111101001_0000000001,
+ 40'b11111_11111_0011111010_1111101001_0000000001,
+ 40'b11111_11111_0011111010_1111101001_0000000001,
+ 40'b11111_11111_0011111010_1111101001_0000000001, // M=127
+ 40'b11111_11111_0011111010_1111101001_0000000001 // M=128
+ };
+
+ // Set lookup_entry with the explicit bits from lookup with a part select
+ mmcm_pll_lock_lookup = lookup[ ((128-divide)*40) +: 40];
+ `ifdef DEBUG
+ $display("lock_lookup: %b", mmcm_pll_lock_lookup);
+ `endif
+ end
+endfunction
+
+// This function takes the divide value and the bandwidth setting of the MMCM
+// and outputs the digital filter settings necessary.
+function [9:0] mmcm_pll_filter_lookup
+ (
+ input [7:0] divide, // input [7:0] divide // Max M divide is 128 in UltraScalePlus
+ input [8*9:0] BANDWIDTH
+ );
+
+ reg [1279:0] lookup_low;
+ reg [1279:0] lookup_high;
+
+ reg [9:0] lookup_entry;
+
+ begin
+ lookup_low = {
+ // CP_RES_LFHF
+ 10'b0011_1111_11, // M=1 - not legal
+ 10'b0011_1111_11, // M=2
+ 10'b0011_1101_11, // M=3
+ 10'b0011_0101_11, // M=4
+ 10'b0011_1001_11, // M=5
+ 10'b0011_1110_11, // M=6
+ 10'b0011_1110_11, // M=7
+ 10'b0011_0001_11,
+ 10'b0011_0110_11,
+ 10'b0011_0110_11,
+ 10'b0011_0110_11,
+ 10'b0011_1010_11,
+ 10'b0011_1010_11,
+ 10'b0011_1010_11,
+ 10'b0100_0110_11,
+ 10'b0011_1100_11,
+ 10'b1110_0110_11,
+ 10'b1111_0110_11,
+ 10'b1110_1010_11,
+ 10'b1110_1010_11,
+ 10'b1111_1010_11,
+ 10'b1111_1010_11,
+ 10'b1111_1010_11,
+ 10'b1111_1010_11,
+ 10'b1111_1010_11,
+ 10'b1101_1100_11,
+ 10'b1101_1100_11,
+ 10'b1101_1100_11,
+ 10'b1110_1100_11,
+ 10'b1110_1100_11,
+ 10'b1110_1100_11,
+ 10'b1111_1100_11,
+ 10'b1111_1100_11,
+ 10'b1111_1100_11,
+ 10'b1111_1100_11,
+ 10'b1111_1100_11,
+ 10'b1111_1100_11,
+ 10'b1110_0010_11,
+ 10'b1110_0010_11,
+ 10'b1110_0010_11,
+ 10'b1110_0010_11,
+ 10'b1111_0010_11,
+ 10'b1111_0010_11,
+ 10'b1111_0010_11,
+ 10'b1111_0010_11,
+ 10'b1111_0010_11,
+ 10'b1111_0010_11,
+ 10'b1111_0010_11,
+ 10'b1111_0010_11,
+ 10'b1111_0010_11,
+ 10'b1111_0010_11,
+ 10'b1111_0010_11,
+ 10'b1111_0010_11,
+ 10'b1111_0010_11,
+ 10'b1111_0010_11,
+ 10'b1111_0010_11,
+ 10'b1111_0010_11,
+ 10'b1111_0010_11,
+ 10'b1111_0010_11,
+ 10'b1111_0010_11,
+ 10'b1111_0010_11,
+ 10'b1111_0010_11,
+ 10'b1100_0100_11,
+ 10'b1100_0100_11,
+ 10'b1100_0100_11,
+ 10'b1100_0100_11,
+ 10'b1100_0100_11,
+ 10'b1100_0100_11,
+ 10'b1100_0100_11,
+ 10'b1100_0100_11,
+ 10'b1101_0100_11,
+ 10'b1101_0100_11,
+ 10'b1101_0100_11,
+ 10'b1101_0100_11,
+ 10'b1101_0100_11,
+ 10'b1101_0100_11,
+ 10'b1101_0100_11,
+ 10'b1110_0100_11,
+ 10'b1110_0100_11,
+ 10'b1110_0100_11,
+ 10'b1110_0100_11,
+ 10'b1110_0100_11,
+ 10'b1110_0100_11,
+ 10'b1110_0100_11,
+ 10'b1110_0100_11,
+ 10'b1111_0100_11,
+ 10'b1111_0100_11,
+ 10'b1111_0100_11,
+ 10'b1111_0100_11,
+ 10'b1111_0100_11,
+ 10'b1111_0100_11,
+ 10'b1111_0100_11,
+ 10'b1111_0100_11,
+ 10'b1111_0100_11,
+ 10'b1111_0100_11,
+ 10'b1111_0100_11,
+ 10'b1111_0100_11,
+ 10'b1111_0100_11,
+ 10'b1111_0100_11,
+ 10'b1111_0100_11,
+ 10'b1111_0100_11,
+ 10'b1111_0100_11,
+ 10'b1111_0100_11,
+ 10'b1111_0100_11,
+ 10'b1111_0100_11,
+ 10'b1111_0100_11,
+ 10'b1111_0100_11,
+ 10'b1111_0100_11,
+ 10'b1111_0100_11,
+ 10'b1111_0100_11,
+ 10'b1111_0100_11,
+ 10'b1111_0100_11,
+ 10'b1111_0100_11,
+ 10'b1111_0100_11,
+ 10'b1111_0100_11,
+ 10'b1111_0100_11,
+ 10'b1111_0100_11,
+ 10'b1111_0100_11,
+ 10'b1111_0100_11,
+ 10'b1101_1000_11,
+ 10'b1101_1000_11,
+ 10'b1101_1000_11,
+ 10'b1101_1000_11,
+ 10'b1101_1000_11,
+ 10'b1101_1000_11,
+ 10'b1101_1000_11,
+ 10'b1101_1000_11, // M=127
+ 10'b1101_1000_11 // M=128
+};
+
+ lookup_high = {
+ // CP_RES_LFHF
+ 10'b0111_1111_11, // M=1 - not legal
+ 10'b0111_1111_11, // M=2
+ 10'b1110_1111_11, // M=3
+ 10'b1111_1111_11, // M=4
+ 10'b1111_1011_11, // M=5
+ 10'b1111_1101_11, // M=6
+ 10'b1111_0011_11, // M=7
+ 10'b1110_0101_11,
+ 10'b1111_1001_11,
+ 10'b1111_1001_11,
+ 10'b1110_1110_11,
+ 10'b1111_1110_11,
+ 10'b1111_0001_11,
+ 10'b1111_0001_11,
+ 10'b1111_0001_11,
+ 10'b1110_0110_11,
+ 10'b1110_0110_11,
+ 10'b1111_0110_11,
+ 10'b1110_1010_11,
+ 10'b1110_1010_11,
+ 10'b1111_1010_11,
+ 10'b1111_1010_11,
+ 10'b1111_1010_11,
+ 10'b1111_1010_11,
+ 10'b1111_1010_11,
+ 10'b1101_1100_11,
+ 10'b1101_1100_11,
+ 10'b1101_1100_11,
+ 10'b1110_1100_11,
+ 10'b1110_1100_11,
+ 10'b1110_1100_11,
+ 10'b1111_1100_11,
+ 10'b1111_1100_11,
+ 10'b1111_1100_11,
+ 10'b1111_1100_11,
+ 10'b1111_1100_11,
+ 10'b1111_1100_11,
+ 10'b1110_0010_11,
+ 10'b1110_0010_11,
+ 10'b1110_0010_11,
+ 10'b1110_0010_11,
+ 10'b1111_0010_11,
+ 10'b1111_0010_11,
+ 10'b1111_0010_11,
+ 10'b1111_0010_11,
+ 10'b1111_0010_11,
+ 10'b1111_0010_11,
+ 10'b1111_0010_11,
+ 10'b1111_0010_11,
+ 10'b1111_0010_11,
+ 10'b1111_0010_11,
+ 10'b1111_0010_11,
+ 10'b1111_0010_11,
+ 10'b1111_0010_11,
+ 10'b1111_0010_11,
+ 10'b1111_0010_11,
+ 10'b1111_0010_11,
+ 10'b1111_0010_11,
+ 10'b1111_0010_11,
+ 10'b1111_0010_11,
+ 10'b1111_0010_11,
+ 10'b1111_0010_11,
+ 10'b1100_0100_11,
+ 10'b1100_0100_11,
+ 10'b1100_0100_11,
+ 10'b1100_0100_11,
+ 10'b1100_0100_11,
+ 10'b1100_0100_11,
+ 10'b1100_0100_11,
+ 10'b1100_0100_11,
+ 10'b1101_0100_11,
+ 10'b1101_0100_11,
+ 10'b1101_0100_11,
+ 10'b1101_0100_11,
+ 10'b1101_0100_11,
+ 10'b1101_0100_11,
+ 10'b1101_0100_11,
+ 10'b1110_0100_11,
+ 10'b1110_0100_11,
+ 10'b1110_0100_11,
+ 10'b1110_0100_11,
+ 10'b1110_0100_11,
+ 10'b1110_0100_11,
+ 10'b1110_0100_11,
+ 10'b1110_0100_11,
+ 10'b1111_0100_11,
+ 10'b1111_0100_11,
+ 10'b1111_0100_11,
+ 10'b1111_0100_11,
+ 10'b1111_0100_11,
+ 10'b1111_0100_11,
+ 10'b1111_0100_11,
+ 10'b1111_0100_11,
+ 10'b1111_0100_11,
+ 10'b1111_0100_11,
+ 10'b1111_0100_11,
+ 10'b1111_0100_11,
+ 10'b1111_0100_11,
+ 10'b1111_0100_11,
+ 10'b1111_0100_11,
+ 10'b1111_0100_11,
+ 10'b1111_0100_11,
+ 10'b1111_0100_11,
+ 10'b1111_0100_11,
+ 10'b1111_0100_11,
+ 10'b1111_0100_11,
+ 10'b1111_0100_11,
+ 10'b1111_0100_11,
+ 10'b1111_0100_11,
+ 10'b1111_0100_11,
+ 10'b1111_0100_11,
+ 10'b1111_0100_11,
+ 10'b1111_0100_11,
+ 10'b1111_0100_11,
+ 10'b1111_0100_11,
+ 10'b1111_0100_11,
+ 10'b1111_0100_11,
+ 10'b1111_0100_11,
+ 10'b1111_0100_11,
+ 10'b1101_1000_11,
+ 10'b1101_1000_11,
+ 10'b1101_1000_11,
+ 10'b1101_1000_11,
+ 10'b1101_1000_11,
+ 10'b1101_1000_11,
+ 10'b1101_1000_11,
+ 10'b1101_1000_11,
+ 10'b1101_1000_11 // M=128
+};
+
+ // Set lookup_entry with the explicit bits from lookup with a part select
+ if(BANDWIDTH == "LOW") begin
+ // Low Bandwidth
+ mmcm_pll_filter_lookup = lookup_low[ ((128-divide)*10) +: 10];
+ end else begin
+ // High or optimized bandwidth
+ mmcm_pll_filter_lookup = lookup_high[ ((128-divide)*10) +: 10];
+ end
+
+ `ifdef DEBUG
+ $display("filter_lookup: %b", mmcm_pll_filter_lookup);
+ `endif
+ end
+endfunction
+
+// This function takes in the divide, phase, and duty cycle
+// setting to calculate the upper and lower counter registers.
+function [37:0] mmcm_pll_count_calc
+ (
+ input [7:0] divide, // Max divide is 128
+ input signed [31:0] phase,
+ input [31:0] duty_cycle // Multiplied by 100,000
+ );
+
+ reg [13:0] div_calc;
+ reg [16:0] phase_calc;
+
+ begin
+ `ifdef DEBUG
+ $display("mmcm_pll_count_calc- divide:%h, phase:%d, duty_cycle:%d",
+ divide, phase, duty_cycle);
+ `endif
+
+ // w_edge[13], no_count[12], high_time[11:6], low_time[5:0]
+ div_calc = mmcm_pll_divider(divide, duty_cycle);
+ // mx[10:9], pm[8:6], dt[5:0]
+ phase_calc = mmcm_pll_phase(divide, phase);
+
+ // Return value is the upper and lower address of counter
+ // Upper address is:
+ // RESERVED [31:26]
+ // MX [25:24]
+ // EDGE [23]
+ // NOCOUNT [22]
+ // DELAY_TIME [21:16]
+ // Lower Address is:
+ // PHASE_MUX [15:13]
+ // RESERVED [12]
+ // HIGH_TIME [11:6]
+ // LOW_TIME [5:0]
+
+ `ifdef DEBUG
+ $display("div:%d dc:%d phase:%d ht:%d lt:%d ed:%d nc:%d mx:%d dt:%d pm:%d",
+ divide, duty_cycle, phase, div_calc[11:6], div_calc[5:0],
+ div_calc[13], div_calc[12],
+ phase_calc[16:15], phase_calc[5:0], phase_calc[14:12]);
+ `endif
+
+ mmcm_pll_count_calc =
+ {
+ // Upper Address
+ 6'h00, phase_calc[10:9], div_calc[13:12], phase_calc[5:0],
+ // Lower Address
+ phase_calc[8:6], 1'b0, div_calc[11:0]
+ };
+ end
+endfunction
+
+
+// This function takes in the divide, phase, and duty cycle
+// setting to calculate the upper and lower counter registers.
+// for fractional multiply/divide functions.
+//
+//
+function [37:0] mmcm_frac_count_calc
+ (
+ input [7:0] divide, // Max divide is 128
+ input signed [31:0] phase,
+ input [31:0] duty_cycle, // Multiplied by 100,000. Not programmable in fractional
+ input [9:0] frac // Multiplied by 1000
+ );
+
+ //Required for fractional divide calculations
+ reg [7:0] lt_frac;
+ reg [7:0] ht_frac;
+
+ reg /*[7:0]*/ wf_fall_frac;
+ reg /*[7:0]*/ wf_rise_frac;
+
+ reg [31:0] a;
+ reg [7:0] pm_rise_frac_filtered ;
+ reg [7:0] pm_fall_frac_filtered ;
+ reg [7:0] clkout0_divide_int;
+ reg [2:0] clkout0_divide_frac;
+ reg [7:0] even_part_high;
+ reg [7:0] even_part_low;
+
+ reg [7:0] odd;
+ reg [7:0] odd_and_frac;
+
+ reg [7:0] pm_fall;
+ reg [7:0] pm_rise;
+ reg [7:0] dt;
+ reg [7:0] dt_int;
+ reg [63:0] dt_calc;
+
+ reg [7:0] pm_rise_frac;
+ reg [7:0] pm_fall_frac;
+
+ reg [31:0] a_per_in_octets;
+ reg [31:0] a_phase_in_cycles;
+
+ parameter precision = 0.125;
+
+ reg [31:0] phase_fixed; // changed to 31:0 from 32:1 jt 5/2/11
+ reg [31: 0] phase_pos;
+ reg [31: 0] phase_vco;
+ reg [31:0] temp;// changed to 31:0 from 32:1 jt 5/2/11
+ reg [13:0] div_calc;
+ reg [16:0] phase_calc;
+
+ begin
+ `ifdef DEBUG
+ $display("mmcm_frac_count_calc- divide:%h, phase:%d, duty_cycle:%d",
+ divide, phase, duty_cycle);
+ `endif
+
+ //convert phase to fixed
+ if ((phase < -360000) || (phase > 360000)) begin
+`ifndef SYNTHESIS
+ $display("ERROR: phase of $phase is not between -360000 and 360000");
+ `endif
+ $finish;
+ end
+
+
+ // Return value is
+ // Transfer data
+ // RESERVED [37:36]
+ // FRAC_TIME [35:33]
+ // FRAC_WF_FALL [32]
+ // Upper address is:
+ // RESERVED [31:26]
+ // MX [25:24]
+ // EDGE [23]
+ // NOCOUNT [22]
+ // DELAY_TIME [21:16]
+ // Lower Address is:
+ // PHASE_MUX [15:13]
+ // RESERVED [12]
+ // HIGH_TIME [11:6]
+ // LOW_TIME [5:0]
+
+
+
+ clkout0_divide_frac = frac / 125;
+ clkout0_divide_int = divide;
+
+ even_part_high = clkout0_divide_int >> 1;//$rtoi(clkout0_divide_int / 2);
+ even_part_low = even_part_high;
+
+ odd = clkout0_divide_int - even_part_high - even_part_low;
+ odd_and_frac = (8*odd) + clkout0_divide_frac;
+
+ lt_frac = even_part_high - (odd_and_frac <= 9);//IF(odd_and_frac>9,even_part_high, even_part_high - 1)
+ ht_frac = even_part_low - (odd_and_frac <= 8);//IF(odd_and_frac>8,even_part_low, even_part_low- 1)
+
+ pm_fall = {odd[6:0],2'b00} + {6'h00, clkout0_divide_frac[2:1]}; // using >> instead of clkout0_divide_frac / 2
+ pm_rise = 0; //0
+
+ wf_fall_frac = ((odd_and_frac >=2) && (odd_and_frac <=9)) || (clkout0_divide_int == 2 && clkout0_divide_frac == 1); //IF(odd_and_frac>=2,IF(odd_and_frac <= 9,1,0),0)
+ wf_rise_frac = (odd_and_frac >=1) && (odd_and_frac <=8); //IF(odd_and_frac>=1,IF(odd_and_frac <= 8,1,0),0)
+
+
+
+ //Calculate phase in fractional cycles
+ a_per_in_octets = (8 * divide) + (frac / 125) ;
+ a_phase_in_cycles = (phase+10) * a_per_in_octets / 360000 ;//Adding 1 due to rounding errors
+ pm_rise_frac = (a_phase_in_cycles[7:0] ==8'h00)?8'h00:a_phase_in_cycles[7:0] - {a_phase_in_cycles[7:3],3'b000};
+
+ dt_calc = ((phase+10) * a_per_in_octets / 8 )/360000 ;//TRUNC(phase* divide / 360); //or_simply (a_per_in_octets / 8)
+ dt = dt_calc[7:0];
+
+ pm_rise_frac_filtered = (pm_rise_frac >=8) ? (pm_rise_frac ) - 8: pm_rise_frac ; //((phase_fixed * (divide + frac / 1000)) / 360) - {pm_rise_frac[7:3],3'b000};//$rtoi(clkout0_phase * clkout0_divide / 45);//a;
+
+ dt_int = dt + (& pm_rise_frac[7:4]); //IF(pm_rise_overwriting>7,dt+1,dt)
+ pm_fall_frac = pm_fall + pm_rise_frac;
+ pm_fall_frac_filtered = pm_fall + pm_rise_frac - {pm_fall_frac[7:3], 3'b000};
+
+ div_calc = mmcm_pll_divider(divide, duty_cycle); //Use to determine edge[7], no count[6]
+ phase_calc = mmcm_pll_phase(divide, phase);// returns{mx[1:0], phase_mux[2:0], delay_time[5:0]}
+
+ mmcm_frac_count_calc[37:0] =
+ { 2'b00, pm_fall_frac_filtered[2:0], wf_fall_frac,
+ 1'b0, clkout0_divide_frac[2:0], 1'b1, wf_rise_frac, phase_calc[10:9], 2'b00, dt[5:0],
+ pm_rise_frac_filtered[2], pm_rise_frac_filtered[1], pm_rise_frac_filtered[0], 1'b0, ht_frac[5:0], lt_frac[5:0]
+ } ;
+
+ `ifdef DEBUG
+ $display("-%d.%d p%d>> :DADDR_9_15 frac30to28.frac_en.wf_r_frac.dt:%b%d%d_%b:DADDR_7_13 pm_f_frac_filtered_29to27.wf_f_frac_26:%b%d:DADDR_8_14.pm_r_frac_filt_15to13.ht_frac.lt_frac:%b%b%b:", divide, frac, phase, clkout0_divide_frac, 1, wf_rise_frac, dt, pm_fall_frac_filtered, wf_fall_frac, pm_rise_frac_filtered, ht_frac, lt_frac);
+ `endif
+
+ end
+endfunction
+
diff --git a/game.gen/sources_1/ip/clk_wiz_0/mmcm_pll_drp_func_us_plus_pll.vh b/game.gen/sources_1/ip/clk_wiz_0/mmcm_pll_drp_func_us_plus_pll.vh
new file mode 100755
index 0000000000000000000000000000000000000000..1d2dc690993b37ed296d61be5c6c2aaad1de90c1
--- /dev/null
+++ b/game.gen/sources_1/ip/clk_wiz_0/mmcm_pll_drp_func_us_plus_pll.vh
@@ -0,0 +1,536 @@
+///////////////////////////////////////////////////////////////////////////////
+//
+// Company: Xilinx
+// Engineer: Jim Tatsukawa, Ralf Krueger, updated for Ultrascale+
+// Date: 6/15/2015
+// Design Name: PLLE4 DRP
+// Module Name: plle4_drp_func.h
+// Version: 2.0
+// Target Devices: UltraScale+ Architecture
+// Tool versions: 2017.1
+// Description: This header provides the functions necessary to
+// calculate the DRP register values for the V6 PLL.
+//
+// Revision Notes: 8/11 - PLLE3 updated for PLLE3 file 4564419
+// Revision Notes: 6/15 - pll_filter_lookup fixed for max M of 19
+// M_Rise bits have been removed for PLLE3
+// Revision Notes: 2/28/17 - pll_filter_lookup and CPRES updated for
+// Ultrascale+ and for max M of 21
+//
+// Disclaimer: XILINX IS PROVIDING THIS DESIGN, CODE, OR
+// INFORMATION "AS IS" SOLELY FOR USE IN DEVELOPING
+// PROGRAMS AND SOLUTIONS FOR XILINX DEVICES. BY
+// PROVIDING THIS DESIGN, CODE, OR INFORMATION AS
+// ONE POSSIBLE IMPLEMENTATION OF THIS FEATURE,
+// APPLICATION OR STANDARD, XILINX IS MAKING NO
+// REPRESENTATION THAT THIS IMPLEMENTATION IS FREE
+// FROM ANY CLAIMS OF INFRINGEMENT, AND YOU ARE
+// RESPONSIBLE FOR OBTAINING ANY RIGHTS YOU MAY
+// REQUIRE FOR YOUR IMPLEMENTATION. XILINX
+// EXPRESSLY DISCLAIMS ANY WARRANTY WHATSOEVER WITH
+// RESPECT TO THE ADEQUACY OF THE IMPLEMENTATION,
+// INCLUDING BUT NOT LIMITED TO ANY WARRANTIES OR
+// REPRESENTATIONS THAT THIS IMPLEMENTATION IS FREE
+// FROM CLAIMS OF INFRINGEMENT, IMPLIED WARRANTIES
+// OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
+// PURPOSE.
+//
+// (c) Copyright 2009-2017 Xilinx, Inc.
+// All rights reserved.
+//
+///////////////////////////////////////////////////////////////////////////////
+
+// These are user functions that should not be modified. Changes to the defines
+// or code within the functions may alter the accuracy of the calculations.
+
+// Define debug to provide extra messages durring elaboration
+//`define DEBUG 1
+
+// FRAC_PRECISION describes the width of the fractional portion of the fixed
+// point numbers. These should not be modified, they are for development
+// only
+`define FRAC_PRECISION 10
+// FIXED_WIDTH describes the total size for fixed point calculations(int+frac).
+// Warning: L.50 and below will not calculate properly with FIXED_WIDTHs
+// greater than 32
+`define FIXED_WIDTH 32
+
+// This function takes a fixed point number and rounds it to the nearest
+// fractional precision bit.
+function [`FIXED_WIDTH:1] round_frac
+ (
+ // Input is (FIXED_WIDTH-FRAC_PRECISION).FRAC_PRECISION fixed point number
+ input [`FIXED_WIDTH:1] decimal,
+
+ // This describes the precision of the fraction, for example a value
+ // of 1 would modify the fractional so that instead of being a .16
+ // fractional, it would be a .1 (rounded to the nearest 0.5 in turn)
+ input [`FIXED_WIDTH:1] precision
+ );
+
+ begin
+
+ `ifdef DEBUG
+ $display("round_frac - decimal: %h, precision: %h", decimal, precision);
+ `endif
+ // If the fractional precision bit is high then round up
+ if( decimal[(`FRAC_PRECISION-precision)] == 1'b1) begin
+ round_frac = decimal + (1'b1 << (`FRAC_PRECISION-precision));
+ end else begin
+ round_frac = decimal;
+ end
+ `ifdef DEBUG
+ $display("round_frac: %h", round_frac);
+ `endif
+ end
+endfunction
+
+// This function calculates high_time, low_time, w_edge, and no_count
+// of a non-fractional counter based on the divide and duty cycle
+//
+// NOTE: high_time and low_time are returned as integers between 0 and 63
+// inclusive. 64 should equal 6'b000000 (in other words it is okay to
+// ignore the overflow)
+function [13:0] mmcm_pll_divider
+ (
+ input [7:0] divide, // Max divide is 128
+ input [31:0] duty_cycle // Duty cycle is multiplied by 100,000
+ );
+
+ reg [`FIXED_WIDTH:1] duty_cycle_fix;
+
+ // High/Low time is initially calculated with a wider integer to prevent a
+ // calculation error when it overflows to 64.
+ reg [6:0] high_time;
+ reg [6:0] low_time;
+ reg w_edge;
+ reg no_count;
+
+ reg [`FIXED_WIDTH:1] temp;
+
+ begin
+ // Duty Cycle must be between 0 and 1,000
+ if(duty_cycle <=0 || duty_cycle >= 100000) begin
+`ifndef SYNTHESIS
+ $display("ERROR: duty_cycle: %d is invalid", duty_cycle);
+ `endif
+ $finish;
+ end
+
+ // Convert to FIXED_WIDTH-FRAC_PRECISION.FRAC_PRECISION fixed point
+ duty_cycle_fix = (duty_cycle << `FRAC_PRECISION) / 100_000;
+
+ `ifdef DEBUG
+ $display("duty_cycle_fix: %h", duty_cycle_fix);
+ `endif
+
+ // If the divide is 1 nothing needs to be set except the no_count bit.
+ // Other values are dummies
+ if(divide == 7'h01) begin
+ high_time = 7'h01;
+ w_edge = 1'b0;
+ low_time = 7'h01;
+ no_count = 1'b1;
+ end else begin
+ temp = round_frac(duty_cycle_fix*divide, 1);
+
+ // comes from above round_frac
+ high_time = temp[`FRAC_PRECISION+7:`FRAC_PRECISION+1];
+ // If the duty cycle * divide rounded is .5 or greater then this bit
+ // is set.
+ w_edge = temp[`FRAC_PRECISION]; // comes from round_frac
+
+ // If the high time comes out to 0, it needs to be set to at least 1
+ // and w_edge set to 0
+ if(high_time == 7'h00) begin
+ high_time = 7'h01;
+ w_edge = 1'b0;
+ end
+
+ if(high_time == divide) begin
+ high_time = divide - 1;
+ w_edge = 1'b1;
+ end
+
+ // Calculate low_time based on the divide setting and set no_count to
+ // 0 as it is only used when divide is 1.
+ low_time = divide - high_time;
+ no_count = 1'b0;
+ end
+
+ // Set the return value.
+ mmcm_pll_divider = {w_edge,no_count,high_time[5:0],low_time[5:0]};
+ end
+endfunction
+
+// This function calculates mx, delay_time, and phase_mux
+// of a non-fractional counter based on the divide and phase
+//
+// NOTE: The only valid value for the MX bits is 2'b00 to ensure the coarse mux
+// is used.
+function [10:0] mmcm_pll_phase
+ (
+ // divide must be an integer (use fractional if not)
+ // assumed that divide already checked to be valid
+ input [7:0] divide, // Max divide is 128
+
+ // Phase is given in degrees (-360,000 to 360,000)
+ input signed [31:0] phase
+ );
+
+ reg [`FIXED_WIDTH:1] phase_in_cycles;
+ reg [`FIXED_WIDTH:1] phase_fixed;
+ reg [1:0] mx;
+ reg [5:0] delay_time;
+ reg [2:0] phase_mux;
+
+ reg [`FIXED_WIDTH:1] temp;
+
+ begin
+`ifdef DEBUG
+ $display("pll_phase-divide:%d,phase:%d",
+ divide, phase);
+`endif
+
+ if ((phase < -360000) || (phase > 360000)) begin
+`ifndef SYNTHESIS
+ $display("ERROR: phase of $phase is not between -360000 and 360000");
+`endif
+ $finish;
+ end
+
+ // If phase is less than 0, convert it to a positive phase shift
+ // Convert to (FIXED_WIDTH-FRAC_PRECISION).FRAC_PRECISION fixed point
+ if(phase < 0) begin
+ phase_fixed = ( (phase + 360000) << `FRAC_PRECISION ) / 1000;
+ end else begin
+ phase_fixed = ( phase << `FRAC_PRECISION ) / 1000;
+ end
+
+ // Put phase in terms of decimal number of vco clock cycles
+ phase_in_cycles = ( phase_fixed * divide ) / 360;
+
+`ifdef DEBUG
+ $display("phase_in_cycles: %h", phase_in_cycles);
+`endif
+
+
+ temp = round_frac(phase_in_cycles, 3);
+
+ // set mx to 2'b00 that the phase mux from the VCO is enabled
+ mx = 2'b00;
+ phase_mux = temp[`FRAC_PRECISION:`FRAC_PRECISION-2];
+ delay_time = temp[`FRAC_PRECISION+6:`FRAC_PRECISION+1];
+
+ `ifdef DEBUG
+ $display("temp: %h", temp);
+ `endif
+
+ // Setup the return value
+ mmcm_pll_phase={mx, phase_mux, delay_time};
+ end
+endfunction
+
+// This function takes the divide value and outputs the necessary lock values
+function [39:0] mmcm_pll_lock_lookup
+ (
+ input [6:0] divide // Max divide is 21
+ );
+
+ reg [839:0] lookup;
+
+ begin
+ lookup = {
+ // This table is composed of:
+ // LockRefDly_LockFBDly_LockCnt_LockSatHigh_UnlockCnt
+ 40'b00110_00110_1111101000_1111101001_0000000001, //1 illegal in Ultrascale+
+ 40'b00110_00110_1111101000_1111101001_0000000001, //2
+ 40'b01000_01000_1111101000_1111101001_0000000001, //3
+ 40'b01011_01011_1111101000_1111101001_0000000001, //4
+ 40'b01110_01110_1111101000_1111101001_0000000001, //5
+ 40'b10001_10001_1111101000_1111101001_0000000001, //6
+ 40'b10011_10011_1111101000_1111101001_0000000001, //7
+ 40'b10110_10110_1111101000_1111101001_0000000001, //8
+ 40'b11001_11001_1111101000_1111101001_0000000001, //9
+ 40'b11100_11100_1111101000_1111101001_0000000001, //10
+ 40'b11111_11111_1110000100_1111101001_0000000001, //11
+ 40'b11111_11111_1100111001_1111101001_0000000001, //12
+ 40'b11111_11111_1011101110_1111101001_0000000001, //13
+ 40'b11111_11111_1010111100_1111101001_0000000001, //14
+ 40'b11111_11111_1010001010_1111101001_0000000001, //15
+ 40'b11111_11111_1001110001_1111101001_0000000001, //16
+ 40'b11111_11111_1000111111_1111101001_0000000001, //17
+ 40'b11111_11111_1000100110_1111101001_0000000001, //18
+ 40'b11111_11111_1000001101_1111101001_0000000001, //19
+ 40'b11111_11111_0111110100_1111101001_0000000001, //20
+ 40'b11111_11111_0111011011_1111101001_0000000001 //21
+ };
+
+ // Set lookup_entry with the explicit bits from lookup with a part select
+ mmcm_pll_lock_lookup = lookup[ ((21-divide)*40) +: 40];
+ `ifdef DEBUG
+ $display("lock_lookup: %b", pll_lock_lookup);
+ `endif
+ end
+endfunction
+
+// This function takes the divide value and the bandwidth setting of the PLL
+// and outputs the digital filter settings necessary. Removing bandwidth setting for PLLE3.
+function [9:0] mmcm_pll_filter_lookup
+ (
+ input [6:0] divide // Max divide is 21
+ );
+
+ reg [209:0] lookup;
+ reg [9:0] lookup_entry;
+
+ begin
+
+ lookup = {
+ // CP_RES_LFHF
+ 10'b0011_0111_11, //1 not legal in Ultrascale+
+ 10'b0011_0111_11, //2
+ 10'b0011_0011_11, //3
+ 10'b0011_1001_11, //4
+ 10'b0011_0001_11, //5
+ 10'b0100_1110_11, //6
+ 10'b0011_0110_11, //7
+ 10'b0011_1010_11, //8
+ 10'b0111_1001_11, //9
+ 10'b0111_1001_11, //10
+ 10'b0101_0110_11, //11
+ 10'b1100_0101_11, //12
+ 10'b0101_1010_11, //13
+ 10'b0110_0110_11, //14
+ 10'b0110_1010_11, //15
+ 10'b0111_0110_11, //16
+ 10'b1111_0101_11, //17
+ 10'b1100_0110_11, //18
+ 10'b1110_0001_11, //19
+ 10'b1101_0110_11, //20
+ 10'b1111_0001_11 //21
+ };
+
+ mmcm_pll_filter_lookup = lookup [ ((21-divide)*10) +: 10];
+
+ `ifdef DEBUG
+ $display("filter_lookup: %b", pll_filter_lookup);
+ `endif
+ end
+endfunction
+
+// This function set the CLKOUTPHY divide settings to match
+// the desired CLKOUTPHY_MODE setting. To create VCO_X2, then
+// the CLKOUTPHY will be set to 2'b00 since the VCO is internally
+// doubled and 2'b00 will represent divide by 1. Similarly "VCO"
+// will need to divide the doubled clock VCO clock frequency by
+// 2 therefore 2'b01 will match a divide by 2.And VCO_HALF will
+// need to divide the doubled VCO by 4, therefore 2'b10
+function [9:0] mmcm_pll_clkoutphy_calc
+ (
+ input [8*9:0] CLKOUTPHY_MODE
+ );
+
+ if(CLKOUTPHY_MODE == "VCO_X2") begin
+ mmcm_pll_clkoutphy_calc= 2'b00;
+ end else if(CLKOUTPHY_MODE == "VCO") begin
+ mmcm_pll_clkoutphy_calc= 2'b01;
+ end else if(CLKOUTPHY_MODE == "CLKIN") begin
+ mmcm_pll_clkoutphy_calc= 2'b11;
+ end else begin // Assume "VCO_HALF"
+ mmcm_pll_clkoutphy_calc= 2'b10;
+ end
+
+endfunction
+
+
+// This function takes in the divide, phase, and duty cycle
+// setting to calculate the upper and lower counter registers.
+function [37:0] mmcm_pll_count_calc
+ (
+ input [7:0] divide, // Max divide is 128
+ input signed [31:0] phase,
+ input [31:0] duty_cycle // Multiplied by 100,000
+ );
+
+ reg [13:0] div_calc;
+ reg [16:0] phase_calc;
+
+ begin
+ `ifdef DEBUG
+ $display("pll_count_calc- divide:%h, phase:%d, duty_cycle:%d",
+ divide, phase, duty_cycle);
+ `endif
+
+ // w_edge[13], no_count[12], high_time[11:6], low_time[5:0]
+ div_calc = mmcm_pll_divider(divide, duty_cycle);
+ // mx[10:9], pm[8:6], dt[5:0]
+ phase_calc = mmcm_pll_phase(divide, phase);
+
+ // Return value is the upper and lower address of counter
+ // Upper address is:
+ // RESERVED [31:26]
+ // MX [25:24]
+ // EDGE [23]
+ // NOCOUNT [22]
+ // DELAY_TIME [21:16]
+ // Lower Address is:
+ // PHASE_MUX [15:13]
+ // RESERVED [12]
+ // HIGH_TIME [11:6]
+ // LOW_TIME [5:0]
+
+ `ifdef DEBUG
+ $display("div:%d dc:%d phase:%d ht:%d lt:%d ed:%d nc:%d mx:%d dt:%d pm:%d",
+ divide, duty_cycle, phase, div_calc[11:6], div_calc[5:0],
+ div_calc[13], div_calc[12],
+ phase_calc[16:15], phase_calc[5:0], 3'b000); //Removed PM_Rise bits
+ `endif
+
+ mmcm_pll_count_calc =
+ {
+ // Upper Address
+ 6'h00, phase_calc[10:9], div_calc[13:12], phase_calc[5:0],
+ // Lower Address
+ phase_calc[8:6], 1'b0, div_calc[11:0]
+ };
+ end
+endfunction
+
+
+// This function takes in the divide, phase, and duty cycle
+// setting to calculate the upper and lower counter registers.
+// for fractional multiply/divide functions.
+//
+//
+function [37:0] mmcm_pll_frac_count_calc
+ (
+ input [7:0] divide, // Max divide is 128
+ input signed [31:0] phase,
+ input [31:0] duty_cycle, // Multiplied by 1,000
+ input [9:0] frac // Multiplied by 1000
+ );
+
+ //Required for fractional divide calculations
+ reg [7:0] lt_frac;
+ reg [7:0] ht_frac;
+
+ reg /*[7:0]*/ wf_fall_frac;
+ reg /*[7:0]*/ wf_rise_frac;
+
+ reg [31:0] a;
+ reg [7:0] pm_rise_frac_filtered ;
+ reg [7:0] pm_fall_frac_filtered ;
+ reg [7:0] clkout0_divide_int;
+ reg [2:0] clkout0_divide_frac;
+ reg [7:0] even_part_high;
+ reg [7:0] even_part_low;
+
+ reg [7:0] odd;
+ reg [7:0] odd_and_frac;
+
+ reg [7:0] pm_fall;
+ reg [7:0] pm_rise;
+ reg [7:0] dt;
+ reg [7:0] dt_int;
+ reg [63:0] dt_calc;
+
+ reg [7:0] pm_rise_frac;
+ reg [7:0] pm_fall_frac;
+
+ reg [31:0] a_per_in_octets;
+ reg [31:0] a_phase_in_cycles;
+
+ parameter precision = 0.125;
+
+ reg [31:0] phase_fixed; // changed to 31:0 from 32:1 jt 5/2/11
+ reg [31: 0] phase_pos;
+ reg [31: 0] phase_vco;
+ reg [31:0] temp;// changed to 31:0 from 32:1 jt 5/2/11
+ reg [13:0] div_calc;
+ reg [16:0] phase_calc;
+
+ begin
+ `ifdef DEBUG
+ $display("pll_frac_count_calc- divide:%h, phase:%d, duty_cycle:%d",
+ divide, phase, duty_cycle);
+ `endif
+
+ //convert phase to fixed
+ if ((phase < -360000) || (phase > 360000)) begin
+`ifndef SYNTHESIS
+ $display("ERROR: phase of $phase is not between -360000 and 360000");
+ `endif
+ $finish;
+ end
+
+
+ // Return value is
+ // Transfer data
+ // RESERVED [37:36]
+ // FRAC_TIME [35:33]
+ // FRAC_WF_FALL [32]
+ // Upper address is:
+ // RESERVED [31:26]
+ // MX [25:24]
+ // EDGE [23]
+ // NOCOUNT [22]
+ // DELAY_TIME [21:16]
+ // Lower Address is:
+ // PHASE_MUX [15:13]
+ // RESERVED [12]
+ // HIGH_TIME [11:6]
+ // LOW_TIME [5:0]
+
+
+
+ clkout0_divide_frac = frac / 125;
+ clkout0_divide_int = divide;
+
+ even_part_high = clkout0_divide_int >> 1;//$rtoi(clkout0_divide_int / 2);
+ even_part_low = even_part_high;
+
+ odd = clkout0_divide_int - even_part_high - even_part_low;
+ odd_and_frac = (8*odd) + clkout0_divide_frac;
+
+ lt_frac = even_part_high - (odd_and_frac <= 9);//IF(odd_and_frac>9,even_part_high, even_part_high - 1)
+ ht_frac = even_part_low - (odd_and_frac <= 8);//IF(odd_and_frac>8,even_part_low, even_part_low- 1)
+
+ pm_fall = {odd[6:0],2'b00} + {6'h00, clkout0_divide_frac[2:1]}; // using >> instead of clkout0_divide_frac / 2
+ pm_rise = 0; //0
+
+ wf_fall_frac = (odd_and_frac >=2) && (odd_and_frac <=9);//IF(odd_and_frac>=2,IF(odd_and_frac <= 9,1,0),0)
+ wf_rise_frac = (odd_and_frac >=1) && (odd_and_frac <=8);//IF(odd_and_frac>=1,IF(odd_and_frac <= 8,1,0),0)
+
+
+
+ //Calculate phase in fractional cycles
+ a_per_in_octets = (8 * divide) + (frac / 125) ;
+ a_phase_in_cycles = (phase+10) * a_per_in_octets / 360000 ;//Adding 1 due to rounding errors
+ pm_rise_frac = (a_phase_in_cycles[7:0] ==8'h00)?8'h00:a_phase_in_cycles[7:0] - {a_phase_in_cycles[7:3],3'b000};
+
+ dt_calc = ((phase+10) * a_per_in_octets / 8 )/360000 ;//TRUNC(phase* divide / 360); //or_simply (a_per_in_octets / 8)
+ dt = dt_calc[7:0];
+
+ pm_rise_frac_filtered = (pm_rise_frac >=8) ? (pm_rise_frac ) - 8: pm_rise_frac ; //((phase_fixed * (divide + frac / 1000)) / 360) - {pm_rise_frac[7:3],3'b000};//$rtoi(clkout0_phase * clkout0_divide / 45);//a;
+
+ dt_int = dt + (& pm_rise_frac[7:4]); //IF(pm_rise_overwriting>7,dt+1,dt)
+ pm_fall_frac = pm_fall + pm_rise_frac;
+ pm_fall_frac_filtered = pm_fall + pm_rise_frac - {pm_fall_frac[7:3], 3'b000};
+
+ div_calc = mmcm_pll_divider(divide, duty_cycle); //Use to determine edge[7], no count[6]
+ phase_calc = mmcm_pll_phase(divide, phase);// returns{mx[1:0], phase_mux[2:0], delay_time[5:0]}
+
+ mmcm_pll_frac_count_calc[37:0] =
+ { 2'b00, pm_fall_frac_filtered[2:0], wf_fall_frac,
+ 1'b0, clkout0_divide_frac[2:0], 1'b1, wf_rise_frac, phase_calc[10:9], div_calc[13:12], dt[5:0],
+ 3'b000, 1'b0, ht_frac[5:0], lt_frac[5:0] //Removed PM_Rise bits
+ } ;
+
+ `ifdef DEBUG
+ $display("-%d.%d p%d>> :DADDR_9_15 frac30to28.frac_en.wf_r_frac.dt:%b%d%d_%b:DADDR_7_13 pm_f_frac_filtered_29to27.wf_f_frac_26:%b%d:DADDR_8_14.pm_r_frac_filt_15to13.ht_frac.lt_frac:%b%b%b:", divide, frac, phase, clkout0_divide_frac, 1, wf_rise_frac, dt, pm_fall_frac_filtered, wf_fall_frac, 3'b000, ht_frac, lt_frac);
+ `endif
+
+ end
+endfunction
+
diff --git a/game.gen/sources_1/ip/clk_wiz_1/clk_wiz_1.v b/game.gen/sources_1/ip/clk_wiz_1/clk_wiz_1.v
new file mode 100644
index 0000000000000000000000000000000000000000..b0f48d88492a7b1d9ea3c6168b8fd45df0f16a58
--- /dev/null
+++ b/game.gen/sources_1/ip/clk_wiz_1/clk_wiz_1.v
@@ -0,0 +1,90 @@
+
+// file: clk_wiz_1.v
+//
+// (c) Copyright 2008 - 2013 Xilinx, Inc. All rights reserved.
+//
+// This file contains confidential and proprietary information
+// of Xilinx, Inc. and is protected under U.S. and
+// international copyright and other intellectual property
+// laws.
+//
+// DISCLAIMER
+// This disclaimer is not a license and does not grant any
+// rights to the materials distributed herewith. Except as
+// otherwise provided in a valid license issued to you by
+// Xilinx, and to the maximum extent permitted by applicable
+// law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
+// WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
+// AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
+// BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
+// INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
+// (2) Xilinx shall not be liable (whether in contract or tort,
+// including negligence, or under any other theory of
+// liability) for any loss or damage of any kind or nature
+// related to, arising under or in connection with these
+// materials, including for any direct, or any indirect,
+// special, incidental, or consequential loss or damage
+// (including loss of data, profits, goodwill, or any type of
+// loss or damage suffered as a result of any action brought
+// by a third party) even if such damage or loss was
+// reasonably foreseeable or Xilinx had been advised of the
+// possibility of the same.
+//
+// CRITICAL APPLICATIONS
+// Xilinx products are not designed or intended to be fail-
+// safe, or for use in any application requiring fail-safe
+// performance, such as life-support or safety devices or
+// systems, Class III medical devices, nuclear facilities,
+// applications related to the deployment of airbags, or any
+// other applications that could lead to death, personal
+// injury, or severe property or environmental damage
+// (individually and collectively, "Critical
+// Applications"). Customer assumes the sole risk and
+// liability of any use of Xilinx products in Critical
+// Applications, subject only to applicable laws and
+// regulations governing limitations on product liability.
+//
+// THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
+// PART OF THIS FILE AT ALL TIMES.
+//
+//----------------------------------------------------------------------------
+// User entered comments
+//----------------------------------------------------------------------------
+// None
+//
+//----------------------------------------------------------------------------
+// Output Output Phase Duty Cycle Pk-to-Pk Phase
+// Clock Freq (MHz) (degrees) (%) Jitter (ps) Error (ps)
+//----------------------------------------------------------------------------
+// clk_out1__25.00000______0.000______50.0______181.828____104.359
+//
+//----------------------------------------------------------------------------
+// Input Clock Freq (MHz) Input Jitter (UI)
+//----------------------------------------------------------------------------
+// __primary_________100.000____________0.010
+
+`timescale 1ps/1ps
+
+(* CORE_GENERATION_INFO = "clk_wiz_1,clk_wiz_v6_0_11_0_0,{component_name=clk_wiz_1,use_phase_alignment=true,use_min_o_jitter=false,use_max_i_jitter=false,use_dyn_phase_shift=false,use_inclk_switchover=false,use_dyn_reconfig=false,enable_axi=0,feedback_source=FDBK_AUTO,PRIMITIVE=MMCM,num_out_clk=1,clkin1_period=10.000,clkin2_period=10.000,use_power_down=false,use_reset=true,use_locked=false,use_inclk_stopped=false,feedback_type=SINGLE,CLOCK_MGR_TYPE=NA,manual_override=false}" *)
+
+module clk_wiz_1
+ (
+ // Clock out ports
+ output clk_out1,
+ // Status and control signals
+ input resetn,
+ // Clock in ports
+ input clk_in1
+ );
+
+ clk_wiz_1_clk_wiz inst
+ (
+ // Clock out ports
+ .clk_out1(clk_out1),
+ // Status and control signals
+ .resetn(resetn),
+ // Clock in ports
+ .clk_in1(clk_in1)
+ );
+
+endmodule
diff --git a/game.gen/sources_1/ip/clk_wiz_1/clk_wiz_1.vho b/game.gen/sources_1/ip/clk_wiz_1/clk_wiz_1.vho
new file mode 100644
index 0000000000000000000000000000000000000000..3bdc63cb4f58ddaab9569b66043511a372c9830b
--- /dev/null
+++ b/game.gen/sources_1/ip/clk_wiz_1/clk_wiz_1.vho
@@ -0,0 +1,92 @@
+
+--
+-- (c) Copyright 2008 - 2013 Xilinx, Inc. All rights reserved.
+--
+-- This file contains confidential and proprietary information
+-- of Xilinx, Inc. and is protected under U.S. and
+-- international copyright and other intellectual property
+-- laws.
+--
+-- DISCLAIMER
+-- This disclaimer is not a license and does not grant any
+-- rights to the materials distributed herewith. Except as
+-- otherwise provided in a valid license issued to you by
+-- Xilinx, and to the maximum extent permitted by applicable
+-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
+-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
+-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
+-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
+-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
+-- (2) Xilinx shall not be liable (whether in contract or tort,
+-- including negligence, or under any other theory of
+-- liability) for any loss or damage of any kind or nature
+-- related to, arising under or in connection with these
+-- materials, including for any direct, or any indirect,
+-- special, incidental, or consequential loss or damage
+-- (including loss of data, profits, goodwill, or any type of
+-- loss or damage suffered as a result of any action brought
+-- by a third party) even if such damage or loss was
+-- reasonably foreseeable or Xilinx had been advised of the
+-- possibility of the same.
+--
+-- CRITICAL APPLICATIONS
+-- Xilinx products are not designed or intended to be fail-
+-- safe, or for use in any application requiring fail-safe
+-- performance, such as life-support or safety devices or
+-- systems, Class III medical devices, nuclear facilities,
+-- applications related to the deployment of airbags, or any
+-- other applications that could lead to death, personal
+-- injury, or severe property or environmental damage
+-- (individually and collectively, "Critical
+-- Applications"). Customer assumes the sole risk and
+-- liability of any use of Xilinx products in Critical
+-- Applications, subject only to applicable laws and
+-- regulations governing limitations on product liability.
+--
+-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
+-- PART OF THIS FILE AT ALL TIMES.
+--
+------------------------------------------------------------------------------
+-- User entered comments
+------------------------------------------------------------------------------
+-- None
+--
+------------------------------------------------------------------------------
+-- Output Output Phase Duty Cycle Pk-to-Pk Phase
+-- Clock Freq (MHz) (degrees) (%) Jitter (ps) Error (ps)
+------------------------------------------------------------------------------
+-- clk_out1__25.00000______0.000______50.0______181.828____104.359
+--
+------------------------------------------------------------------------------
+-- Input Clock Freq (MHz) Input Jitter (UI)
+------------------------------------------------------------------------------
+-- __primary_________100.000____________0.010
+
+
+-- The following code must appear in the VHDL architecture header:
+------------- Begin Cut here for COMPONENT Declaration ------ COMP_TAG
+component clk_wiz_1
+port
+ (-- Clock in ports
+ -- Clock out ports
+ clk_out1 : out std_logic;
+ -- Status and control signals
+ resetn : in std_logic;
+ clk_in1 : in std_logic
+ );
+end component;
+
+-- COMP_TAG_END ------ End COMPONENT Declaration ------------
+-- The following code must appear in the VHDL architecture
+-- body. Substitute your own instance name and net names.
+------------- Begin Cut here for INSTANTIATION Template ----- INST_TAG
+your_instance_name : clk_wiz_1
+ port map (
+ -- Clock out ports
+ clk_out1 => clk_out1,
+ -- Status and control signals
+ resetn => resetn,
+ -- Clock in ports
+ clk_in1 => clk_in1
+ );
+-- INST_TAG_END ------ End INSTANTIATION Template ------------
diff --git a/game.gen/sources_1/ip/clk_wiz_1/clk_wiz_1.xdc b/game.gen/sources_1/ip/clk_wiz_1/clk_wiz_1.xdc
new file mode 100644
index 0000000000000000000000000000000000000000..71b30657b33174b05e87c021310c5a9139a10ca7
--- /dev/null
+++ b/game.gen/sources_1/ip/clk_wiz_1/clk_wiz_1.xdc
@@ -0,0 +1,60 @@
+
+# file: clk_wiz_1.xdc
+#
+# (c) Copyright 2008 - 2013 Xilinx, Inc. All rights reserved.
+#
+# This file contains confidential and proprietary information
+# of Xilinx, Inc. and is protected under U.S. and
+# international copyright and other intellectual property
+# laws.
+#
+# DISCLAIMER
+# This disclaimer is not a license and does not grant any
+# rights to the materials distributed herewith. Except as
+# otherwise provided in a valid license issued to you by
+# Xilinx, and to the maximum extent permitted by applicable
+# law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
+# WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
+# AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
+# BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
+# INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
+# (2) Xilinx shall not be liable (whether in contract or tort,
+# including negligence, or under any other theory of
+# liability) for any loss or damage of any kind or nature
+# related to, arising under or in connection with these
+# materials, including for any direct, or any indirect,
+# special, incidental, or consequential loss or damage
+# (including loss of data, profits, goodwill, or any type of
+# loss or damage suffered as a result of any action brought
+# by a third party) even if such damage or loss was
+# reasonably foreseeable or Xilinx had been advised of the
+# possibility of the same.
+#
+# CRITICAL APPLICATIONS
+# Xilinx products are not designed or intended to be fail-
+# safe, or for use in any application requiring fail-safe
+# performance, such as life-support or safety devices or
+# systems, Class III medical devices, nuclear facilities,
+# applications related to the deployment of airbags, or any
+# other applications that could lead to death, personal
+# injury, or severe property or environmental damage
+# (individually and collectively, "Critical
+# Applications"). Customer assumes the sole risk and
+# liability of any use of Xilinx products in Critical
+# Applications, subject only to applicable laws and
+# regulations governing limitations on product liability.
+#
+# THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
+# PART OF THIS FILE AT ALL TIMES.
+#
+
+# Input clock periods. These duplicate the values entered for the
+# input clocks. You can use these to time your system. If required
+# commented constraints can be used in the top level xdc
+#----------------------------------------------------------------
+# Connect to input port when clock capable pin is selected for input
+create_clock -period 10.000 [get_ports clk_in1]
+set_input_jitter [get_clocks -of_objects [get_ports clk_in1]] 0.100
+
+
+set_property PHASESHIFT_MODE WAVEFORM [get_cells -hierarchical *adv*]
diff --git a/game.gen/sources_1/ip/clk_wiz_1/clk_wiz_1.xml b/game.gen/sources_1/ip/clk_wiz_1/clk_wiz_1.xml
new file mode 100644
index 0000000000000000000000000000000000000000..6377405746ae5549007f2a5a596522dedbfea1a3
--- /dev/null
+++ b/game.gen/sources_1/ip/clk_wiz_1/clk_wiz_1.xml
@@ -0,0 +1,4945 @@
+<?xml version="1.0" encoding="UTF-8"?>
+<spirit:component xmlns:xilinx="http://www.xilinx.com" xmlns:spirit="http://www.spiritconsortium.org/XMLSchema/SPIRIT/1685-2009" xmlns:xsi="http://www.w3.org/2001/XMLSchema-instance">
+ <spirit:vendor>xilinx.com</spirit:vendor>
+ <spirit:library>customized_ip</spirit:library>
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+ </spirit:modelParameter>
+ <spirit:modelParameter spirit:dataType="INTEGER">
+ <spirit:name>C_USE_CLK_VALID</spirit:name>
+ <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C_USE_CLK_VALID" spirit:order="219">0</spirit:value>
+ </spirit:modelParameter>
+ <spirit:modelParameter spirit:dataType="STRING">
+ <spirit:name>C_PRIM_IN_FREQ</spirit:name>
+ <spirit:value spirit:format="float" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C_PRIM_IN_FREQ" spirit:order="220">100.000</spirit:value>
+ </spirit:modelParameter>
+ <spirit:modelParameter spirit:dataType="STRING">
+ <spirit:name>C_PRIM_IN_TIMEPERIOD</spirit:name>
+ <spirit:value spirit:format="float" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C_PRIM_IN_TIMEPERIOD" spirit:order="220.001">10.000</spirit:value>
+ </spirit:modelParameter>
+ <spirit:modelParameter spirit:dataType="STRING">
+ <spirit:name>C_IN_FREQ_UNITS</spirit:name>
+ <spirit:value spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C_IN_FREQ_UNITS" spirit:order="221">Units_MHz</spirit:value>
+ </spirit:modelParameter>
+ <spirit:modelParameter spirit:dataType="STRING">
+ <spirit:name>C_SECONDARY_IN_FREQ</spirit:name>
+ <spirit:value spirit:format="float" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C_SECONDARY_IN_FREQ" spirit:order="222">100.000</spirit:value>
+ </spirit:modelParameter>
+ <spirit:modelParameter spirit:dataType="STRING">
+ <spirit:name>C_SECONDARY_IN_TIMEPERIOD</spirit:name>
+ <spirit:value spirit:format="float" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C_SECONDARY_IN_TIMEPERIOD" spirit:order="222.001">10.000</spirit:value>
+ </spirit:modelParameter>
+ <spirit:modelParameter spirit:dataType="STRING">
+ <spirit:name>C_FEEDBACK_SOURCE</spirit:name>
+ <spirit:value spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C_FEEDBACK_SOURCE" spirit:order="223">FDBK_AUTO</spirit:value>
+ </spirit:modelParameter>
+ <spirit:modelParameter spirit:dataType="STRING">
+ <spirit:name>C_PRIM_SOURCE</spirit:name>
+ <spirit:value spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C_PRIM_SOURCE" spirit:order="224">Single_ended_clock_capable_pin</spirit:value>
+ </spirit:modelParameter>
+ <spirit:modelParameter spirit:dataType="STRING">
+ <spirit:name>C_PHASESHIFT_MODE</spirit:name>
+ <spirit:value spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C_PHASESHIFT_MODE" spirit:order="2240">WAVEFORM</spirit:value>
+ </spirit:modelParameter>
+ <spirit:modelParameter spirit:dataType="STRING">
+ <spirit:name>C_SECONDARY_SOURCE</spirit:name>
+ <spirit:value spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C_SECONDARY_SOURCE" spirit:order="225">Single_ended_clock_capable_pin</spirit:value>
+ </spirit:modelParameter>
+ <spirit:modelParameter spirit:dataType="STRING">
+ <spirit:name>C_CLKFB_IN_SIGNALING</spirit:name>
+ <spirit:value spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C_CLKFB_IN_SIGNALING" spirit:order="226">SINGLE</spirit:value>
+ </spirit:modelParameter>
+ <spirit:modelParameter spirit:dataType="INTEGER">
+ <spirit:name>C_USE_RESET</spirit:name>
+ <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C_USE_RESET" spirit:order="227">1</spirit:value>
+ </spirit:modelParameter>
+ <spirit:modelParameter spirit:dataType="INTEGER">
+ <spirit:name>C_RESET_LOW</spirit:name>
+ <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C_RESET_LOW" spirit:order="408">1</spirit:value>
+ </spirit:modelParameter>
+ <spirit:modelParameter spirit:dataType="INTEGER">
+ <spirit:name>C_USE_LOCKED</spirit:name>
+ <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C_USE_LOCKED" spirit:order="228">0</spirit:value>
+ </spirit:modelParameter>
+ <spirit:modelParameter spirit:dataType="INTEGER">
+ <spirit:name>C_USE_INCLK_STOPPED</spirit:name>
+ <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C_USE_INCLK_STOPPED" spirit:order="229">0</spirit:value>
+ </spirit:modelParameter>
+ <spirit:modelParameter spirit:dataType="INTEGER">
+ <spirit:name>C_USE_CLKFB_STOPPED</spirit:name>
+ <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C_USE_CLKFB_STOPPED" spirit:order="230">0</spirit:value>
+ </spirit:modelParameter>
+ <spirit:modelParameter spirit:dataType="INTEGER">
+ <spirit:name>C_USE_POWER_DOWN</spirit:name>
+ <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C_USE_POWER_DOWN" spirit:order="231">0</spirit:value>
+ </spirit:modelParameter>
+ <spirit:modelParameter spirit:dataType="INTEGER">
+ <spirit:name>C_USE_STATUS</spirit:name>
+ <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C_USE_STATUS" spirit:order="232">0</spirit:value>
+ </spirit:modelParameter>
+ <spirit:modelParameter spirit:dataType="INTEGER">
+ <spirit:name>C_USE_FREEZE</spirit:name>
+ <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C_USE_FREEZE" spirit:order="233">0</spirit:value>
+ </spirit:modelParameter>
+ <spirit:modelParameter spirit:dataType="INTEGER">
+ <spirit:name>C_NUM_OUT_CLKS</spirit:name>
+ <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C_NUM_OUT_CLKS" spirit:order="234">1</spirit:value>
+ </spirit:modelParameter>
+ <spirit:modelParameter spirit:dataType="STRING">
+ <spirit:name>C_CLKOUT1_DRIVES</spirit:name>
+ <spirit:value spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C_CLKOUT1_DRIVES" spirit:order="235">BUFG</spirit:value>
+ </spirit:modelParameter>
+ <spirit:modelParameter spirit:dataType="STRING">
+ <spirit:name>C_CLKOUT2_DRIVES</spirit:name>
+ <spirit:value spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C_CLKOUT2_DRIVES" spirit:order="236">BUFG</spirit:value>
+ </spirit:modelParameter>
+ <spirit:modelParameter spirit:dataType="STRING">
+ <spirit:name>C_CLKOUT3_DRIVES</spirit:name>
+ <spirit:value spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C_CLKOUT3_DRIVES" spirit:order="237">BUFG</spirit:value>
+ </spirit:modelParameter>
+ <spirit:modelParameter spirit:dataType="STRING">
+ <spirit:name>C_CLKOUT4_DRIVES</spirit:name>
+ <spirit:value spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C_CLKOUT4_DRIVES" spirit:order="238">BUFG</spirit:value>
+ </spirit:modelParameter>
+ <spirit:modelParameter spirit:dataType="STRING">
+ <spirit:name>C_CLKOUT5_DRIVES</spirit:name>
+ <spirit:value spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C_CLKOUT5_DRIVES" spirit:order="239">BUFG</spirit:value>
+ </spirit:modelParameter>
+ <spirit:modelParameter spirit:dataType="STRING">
+ <spirit:name>C_CLKOUT6_DRIVES</spirit:name>
+ <spirit:value spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C_CLKOUT6_DRIVES" spirit:order="240">BUFG</spirit:value>
+ </spirit:modelParameter>
+ <spirit:modelParameter spirit:dataType="STRING">
+ <spirit:name>C_CLKOUT7_DRIVES</spirit:name>
+ <spirit:value spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C_CLKOUT7_DRIVES" spirit:order="241">BUFG</spirit:value>
+ </spirit:modelParameter>
+ <spirit:modelParameter spirit:dataType="STRING">
+ <spirit:name>C_INCLK_SUM_ROW0</spirit:name>
+ <spirit:value spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C_INCLK_SUM_ROW0" spirit:order="242">Input Clock Freq (MHz) Input Jitter (UI)</spirit:value>
+ </spirit:modelParameter>
+ <spirit:modelParameter spirit:dataType="STRING">
+ <spirit:name>C_INCLK_SUM_ROW1</spirit:name>
+ <spirit:value spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C_INCLK_SUM_ROW1" spirit:order="243">__primary_________100.000____________0.010</spirit:value>
+ </spirit:modelParameter>
+ <spirit:modelParameter spirit:dataType="STRING">
+ <spirit:name>C_INCLK_SUM_ROW2</spirit:name>
+ <spirit:value spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C_INCLK_SUM_ROW2" spirit:order="244">no_secondary_input_clock </spirit:value>
+ </spirit:modelParameter>
+ <spirit:modelParameter spirit:dataType="STRING">
+ <spirit:name>C_OUTCLK_SUM_ROW0A</spirit:name>
+ <spirit:displayName>C Outclk Sum Row0a</spirit:displayName>
+ <spirit:value spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C_OUTCLK_SUM_ROW0A" spirit:order="245"> Output Output Phase Duty Cycle Pk-to-Pk Phase</spirit:value>
+ </spirit:modelParameter>
+ <spirit:modelParameter spirit:dataType="STRING">
+ <spirit:name>C_OUTCLK_SUM_ROW0B</spirit:name>
+ <spirit:value spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C_OUTCLK_SUM_ROW0B" spirit:order="246"> Clock Freq (MHz) (degrees) (%) Jitter (ps) Error (ps)</spirit:value>
+ </spirit:modelParameter>
+ <spirit:modelParameter spirit:dataType="STRING">
+ <spirit:name>C_OUTCLK_SUM_ROW1</spirit:name>
+ <spirit:value spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C_OUTCLK_SUM_ROW1" spirit:order="247">clk_out1__25.00000______0.000______50.0______181.828____104.359</spirit:value>
+ </spirit:modelParameter>
+ <spirit:modelParameter spirit:dataType="STRING">
+ <spirit:name>C_OUTCLK_SUM_ROW2</spirit:name>
+ <spirit:value spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C_OUTCLK_SUM_ROW2" spirit:order="248">no_CLK_OUT2_output</spirit:value>
+ </spirit:modelParameter>
+ <spirit:modelParameter spirit:dataType="STRING">
+ <spirit:name>C_OUTCLK_SUM_ROW3</spirit:name>
+ <spirit:value spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C_OUTCLK_SUM_ROW3" spirit:order="249">no_CLK_OUT3_output</spirit:value>
+ </spirit:modelParameter>
+ <spirit:modelParameter spirit:dataType="STRING">
+ <spirit:name>C_OUTCLK_SUM_ROW4</spirit:name>
+ <spirit:value spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C_OUTCLK_SUM_ROW4" spirit:order="250">no_CLK_OUT4_output</spirit:value>
+ </spirit:modelParameter>
+ <spirit:modelParameter spirit:dataType="STRING">
+ <spirit:name>C_OUTCLK_SUM_ROW5</spirit:name>
+ <spirit:value spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C_OUTCLK_SUM_ROW5" spirit:order="251">no_CLK_OUT5_output</spirit:value>
+ </spirit:modelParameter>
+ <spirit:modelParameter spirit:dataType="STRING">
+ <spirit:name>C_OUTCLK_SUM_ROW6</spirit:name>
+ <spirit:value spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C_OUTCLK_SUM_ROW6" spirit:order="252">no_CLK_OUT6_output</spirit:value>
+ </spirit:modelParameter>
+ <spirit:modelParameter spirit:dataType="STRING">
+ <spirit:name>C_OUTCLK_SUM_ROW7</spirit:name>
+ <spirit:value spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C_OUTCLK_SUM_ROW7" spirit:order="253">no_CLK_OUT7_output</spirit:value>
+ </spirit:modelParameter>
+ <spirit:modelParameter spirit:dataType="STRING">
+ <spirit:name>C_CLKOUT1_REQUESTED_OUT_FREQ</spirit:name>
+ <spirit:value spirit:format="float" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C_CLKOUT1_REQUESTED_OUT_FREQ" spirit:order="254">25.000</spirit:value>
+ </spirit:modelParameter>
+ <spirit:modelParameter spirit:dataType="STRING">
+ <spirit:name>C_CLKOUT2_REQUESTED_OUT_FREQ</spirit:name>
+ <spirit:value spirit:format="float" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C_CLKOUT2_REQUESTED_OUT_FREQ" spirit:order="255">100.000</spirit:value>
+ </spirit:modelParameter>
+ <spirit:modelParameter spirit:dataType="STRING">
+ <spirit:name>C_CLKOUT3_REQUESTED_OUT_FREQ</spirit:name>
+ <spirit:value spirit:format="float" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C_CLKOUT3_REQUESTED_OUT_FREQ" spirit:order="256">100.000</spirit:value>
+ </spirit:modelParameter>
+ <spirit:modelParameter spirit:dataType="STRING">
+ <spirit:name>C_CLKOUT4_REQUESTED_OUT_FREQ</spirit:name>
+ <spirit:value spirit:format="float" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C_CLKOUT4_REQUESTED_OUT_FREQ" spirit:order="257">100.000</spirit:value>
+ </spirit:modelParameter>
+ <spirit:modelParameter spirit:dataType="STRING">
+ <spirit:name>C_CLKOUT5_REQUESTED_OUT_FREQ</spirit:name>
+ <spirit:value spirit:format="float" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C_CLKOUT5_REQUESTED_OUT_FREQ" spirit:order="258">100.000</spirit:value>
+ </spirit:modelParameter>
+ <spirit:modelParameter spirit:dataType="STRING">
+ <spirit:name>C_CLKOUT6_REQUESTED_OUT_FREQ</spirit:name>
+ <spirit:value spirit:format="float" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C_CLKOUT6_REQUESTED_OUT_FREQ" spirit:order="259">100.000</spirit:value>
+ </spirit:modelParameter>
+ <spirit:modelParameter spirit:dataType="STRING">
+ <spirit:name>C_CLKOUT7_REQUESTED_OUT_FREQ</spirit:name>
+ <spirit:value spirit:format="float" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C_CLKOUT7_REQUESTED_OUT_FREQ" spirit:order="260">100.000</spirit:value>
+ </spirit:modelParameter>
+ <spirit:modelParameter spirit:dataType="STRING">
+ <spirit:name>C_CLKOUT1_REQUESTED_PHASE</spirit:name>
+ <spirit:value spirit:format="float" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C_CLKOUT1_REQUESTED_PHASE" spirit:order="261">0.000</spirit:value>
+ </spirit:modelParameter>
+ <spirit:modelParameter spirit:dataType="STRING">
+ <spirit:name>C_CLKOUT2_REQUESTED_PHASE</spirit:name>
+ <spirit:value spirit:format="float" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C_CLKOUT2_REQUESTED_PHASE" spirit:order="262">0.000</spirit:value>
+ </spirit:modelParameter>
+ <spirit:modelParameter spirit:dataType="STRING">
+ <spirit:name>C_CLKOUT3_REQUESTED_PHASE</spirit:name>
+ <spirit:value spirit:format="float" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C_CLKOUT3_REQUESTED_PHASE" spirit:order="263">0.000</spirit:value>
+ </spirit:modelParameter>
+ <spirit:modelParameter spirit:dataType="STRING">
+ <spirit:name>C_CLKOUT4_REQUESTED_PHASE</spirit:name>
+ <spirit:value spirit:format="float" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C_CLKOUT4_REQUESTED_PHASE" spirit:order="264">0.000</spirit:value>
+ </spirit:modelParameter>
+ <spirit:modelParameter spirit:dataType="STRING">
+ <spirit:name>C_CLKOUT5_REQUESTED_PHASE</spirit:name>
+ <spirit:value spirit:format="float" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C_CLKOUT5_REQUESTED_PHASE" spirit:order="265">0.000</spirit:value>
+ </spirit:modelParameter>
+ <spirit:modelParameter spirit:dataType="STRING">
+ <spirit:name>C_CLKOUT6_REQUESTED_PHASE</spirit:name>
+ <spirit:value spirit:format="float" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C_CLKOUT6_REQUESTED_PHASE" spirit:order="266">0.000</spirit:value>
+ </spirit:modelParameter>
+ <spirit:modelParameter spirit:dataType="STRING">
+ <spirit:name>C_CLKOUT7_REQUESTED_PHASE</spirit:name>
+ <spirit:value spirit:format="float" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C_CLKOUT7_REQUESTED_PHASE" spirit:order="267">0.000</spirit:value>
+ </spirit:modelParameter>
+ <spirit:modelParameter spirit:dataType="STRING">
+ <spirit:name>C_CLKOUT1_REQUESTED_DUTY_CYCLE</spirit:name>
+ <spirit:value spirit:format="float" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C_CLKOUT1_REQUESTED_DUTY_CYCLE" spirit:order="268">50.000</spirit:value>
+ </spirit:modelParameter>
+ <spirit:modelParameter spirit:dataType="STRING">
+ <spirit:name>C_CLKOUT2_REQUESTED_DUTY_CYCLE</spirit:name>
+ <spirit:value spirit:format="float" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C_CLKOUT2_REQUESTED_DUTY_CYCLE" spirit:order="269">50.000</spirit:value>
+ </spirit:modelParameter>
+ <spirit:modelParameter spirit:dataType="STRING">
+ <spirit:name>C_CLKOUT3_REQUESTED_DUTY_CYCLE</spirit:name>
+ <spirit:value spirit:format="float" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C_CLKOUT3_REQUESTED_DUTY_CYCLE" spirit:order="270">50.000</spirit:value>
+ </spirit:modelParameter>
+ <spirit:modelParameter spirit:dataType="STRING">
+ <spirit:name>C_CLKOUT4_REQUESTED_DUTY_CYCLE</spirit:name>
+ <spirit:value spirit:format="float" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C_CLKOUT4_REQUESTED_DUTY_CYCLE" spirit:order="271">50.000</spirit:value>
+ </spirit:modelParameter>
+ <spirit:modelParameter spirit:dataType="STRING">
+ <spirit:name>C_CLKOUT5_REQUESTED_DUTY_CYCLE</spirit:name>
+ <spirit:value spirit:format="float" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C_CLKOUT5_REQUESTED_DUTY_CYCLE" spirit:order="272">50.000</spirit:value>
+ </spirit:modelParameter>
+ <spirit:modelParameter spirit:dataType="STRING">
+ <spirit:name>C_CLKOUT6_REQUESTED_DUTY_CYCLE</spirit:name>
+ <spirit:value spirit:format="float" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C_CLKOUT6_REQUESTED_DUTY_CYCLE" spirit:order="273">50.000</spirit:value>
+ </spirit:modelParameter>
+ <spirit:modelParameter spirit:dataType="STRING">
+ <spirit:name>C_CLKOUT7_REQUESTED_DUTY_CYCLE</spirit:name>
+ <spirit:value spirit:format="float" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C_CLKOUT7_REQUESTED_DUTY_CYCLE" spirit:order="274">50.000</spirit:value>
+ </spirit:modelParameter>
+ <spirit:modelParameter spirit:dataType="STRING">
+ <spirit:name>C_CLKOUT1_OUT_FREQ</spirit:name>
+ <spirit:value spirit:format="float" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C_CLKOUT1_OUT_FREQ" spirit:order="275">25.00000</spirit:value>
+ </spirit:modelParameter>
+ <spirit:modelParameter spirit:dataType="STRING">
+ <spirit:name>C_CLKOUT2_OUT_FREQ</spirit:name>
+ <spirit:value spirit:format="float" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C_CLKOUT2_OUT_FREQ" spirit:order="276">100.000</spirit:value>
+ </spirit:modelParameter>
+ <spirit:modelParameter spirit:dataType="STRING">
+ <spirit:name>C_CLKOUT3_OUT_FREQ</spirit:name>
+ <spirit:value spirit:format="float" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C_CLKOUT3_OUT_FREQ" spirit:order="277">100.000</spirit:value>
+ </spirit:modelParameter>
+ <spirit:modelParameter spirit:dataType="STRING">
+ <spirit:name>C_CLKOUT4_OUT_FREQ</spirit:name>
+ <spirit:value spirit:format="float" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C_CLKOUT4_OUT_FREQ" spirit:order="278">100.000</spirit:value>
+ </spirit:modelParameter>
+ <spirit:modelParameter spirit:dataType="STRING">
+ <spirit:name>C_CLKOUT5_OUT_FREQ</spirit:name>
+ <spirit:value spirit:format="float" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C_CLKOUT5_OUT_FREQ" spirit:order="279">100.000</spirit:value>
+ </spirit:modelParameter>
+ <spirit:modelParameter spirit:dataType="STRING">
+ <spirit:name>C_CLKOUT6_OUT_FREQ</spirit:name>
+ <spirit:value spirit:format="float" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C_CLKOUT6_OUT_FREQ" spirit:order="280">100.000</spirit:value>
+ </spirit:modelParameter>
+ <spirit:modelParameter spirit:dataType="STRING">
+ <spirit:name>C_CLKOUT7_OUT_FREQ</spirit:name>
+ <spirit:value spirit:format="float" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C_CLKOUT7_OUT_FREQ" spirit:order="281">100.000</spirit:value>
+ </spirit:modelParameter>
+ <spirit:modelParameter spirit:dataType="STRING">
+ <spirit:name>C_CLKOUT1_PHASE</spirit:name>
+ <spirit:value spirit:format="float" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C_CLKOUT1_PHASE" spirit:order="282">0.000</spirit:value>
+ </spirit:modelParameter>
+ <spirit:modelParameter spirit:dataType="STRING">
+ <spirit:name>C_CLKOUT2_PHASE</spirit:name>
+ <spirit:value spirit:format="float" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C_CLKOUT2_PHASE" spirit:order="283">0.000</spirit:value>
+ </spirit:modelParameter>
+ <spirit:modelParameter spirit:dataType="STRING">
+ <spirit:name>C_CLKOUT3_PHASE</spirit:name>
+ <spirit:value spirit:format="float" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C_CLKOUT3_PHASE" spirit:order="284">0.000</spirit:value>
+ </spirit:modelParameter>
+ <spirit:modelParameter spirit:dataType="STRING">
+ <spirit:name>C_CLKOUT4_PHASE</spirit:name>
+ <spirit:value spirit:format="float" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C_CLKOUT4_PHASE" spirit:order="285">0.000</spirit:value>
+ </spirit:modelParameter>
+ <spirit:modelParameter spirit:dataType="STRING">
+ <spirit:name>C_CLKOUT5_PHASE</spirit:name>
+ <spirit:value spirit:format="float" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C_CLKOUT5_PHASE" spirit:order="286">0.000</spirit:value>
+ </spirit:modelParameter>
+ <spirit:modelParameter spirit:dataType="STRING">
+ <spirit:name>C_CLKOUT6_PHASE</spirit:name>
+ <spirit:value spirit:format="float" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C_CLKOUT6_PHASE" spirit:order="287">0.000</spirit:value>
+ </spirit:modelParameter>
+ <spirit:modelParameter spirit:dataType="STRING">
+ <spirit:name>C_CLKOUT7_PHASE</spirit:name>
+ <spirit:value spirit:format="float" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C_CLKOUT7_PHASE" spirit:order="288">0.000</spirit:value>
+ </spirit:modelParameter>
+ <spirit:modelParameter spirit:dataType="STRING">
+ <spirit:name>C_CLKOUT1_DUTY_CYCLE</spirit:name>
+ <spirit:value spirit:format="float" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C_CLKOUT1_DUTY_CYCLE" spirit:order="289">50.0</spirit:value>
+ </spirit:modelParameter>
+ <spirit:modelParameter spirit:dataType="STRING">
+ <spirit:name>C_CLKOUT2_DUTY_CYCLE</spirit:name>
+ <spirit:value spirit:format="float" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C_CLKOUT2_DUTY_CYCLE" spirit:order="290">50.000</spirit:value>
+ </spirit:modelParameter>
+ <spirit:modelParameter spirit:dataType="STRING">
+ <spirit:name>C_CLKOUT3_DUTY_CYCLE</spirit:name>
+ <spirit:value spirit:format="float" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C_CLKOUT3_DUTY_CYCLE" spirit:order="291">50.000</spirit:value>
+ </spirit:modelParameter>
+ <spirit:modelParameter spirit:dataType="STRING">
+ <spirit:name>C_CLKOUT4_DUTY_CYCLE</spirit:name>
+ <spirit:value spirit:format="float" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C_CLKOUT4_DUTY_CYCLE" spirit:order="292">50.000</spirit:value>
+ </spirit:modelParameter>
+ <spirit:modelParameter spirit:dataType="STRING">
+ <spirit:name>C_CLKOUT5_DUTY_CYCLE</spirit:name>
+ <spirit:value spirit:format="float" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C_CLKOUT5_DUTY_CYCLE" spirit:order="293">50.000</spirit:value>
+ </spirit:modelParameter>
+ <spirit:modelParameter spirit:dataType="STRING">
+ <spirit:name>C_CLKOUT6_DUTY_CYCLE</spirit:name>
+ <spirit:value spirit:format="float" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C_CLKOUT6_DUTY_CYCLE" spirit:order="294">50.000</spirit:value>
+ </spirit:modelParameter>
+ <spirit:modelParameter spirit:dataType="STRING">
+ <spirit:name>C_CLKOUT7_DUTY_CYCLE</spirit:name>
+ <spirit:value spirit:format="float" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C_CLKOUT7_DUTY_CYCLE" spirit:order="295">50.000</spirit:value>
+ </spirit:modelParameter>
+ <spirit:modelParameter spirit:dataType="INTEGER">
+ <spirit:name>C_USE_SAFE_CLOCK_STARTUP</spirit:name>
+ <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C_USE_SAFE_CLOCK_STARTUP" spirit:order="500">0</spirit:value>
+ </spirit:modelParameter>
+ <spirit:modelParameter spirit:dataType="INTEGER">
+ <spirit:name>C_USE_CLOCK_SEQUENCING</spirit:name>
+ <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C_USE_CLOCK_SEQUENCING" spirit:order="501">0</spirit:value>
+ </spirit:modelParameter>
+ <spirit:modelParameter spirit:dataType="INTEGER">
+ <spirit:name>C_CLKOUT1_SEQUENCE_NUMBER</spirit:name>
+ <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C_CLKOUT1_SEQUENCE_NUMBER" spirit:order="502">1</spirit:value>
+ </spirit:modelParameter>
+ <spirit:modelParameter spirit:dataType="INTEGER">
+ <spirit:name>C_CLKOUT2_SEQUENCE_NUMBER</spirit:name>
+ <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C_CLKOUT2_SEQUENCE_NUMBER" spirit:order="503">1</spirit:value>
+ </spirit:modelParameter>
+ <spirit:modelParameter spirit:dataType="INTEGER">
+ <spirit:name>C_CLKOUT3_SEQUENCE_NUMBER</spirit:name>
+ <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C_CLKOUT3_SEQUENCE_NUMBER" spirit:order="504">1</spirit:value>
+ </spirit:modelParameter>
+ <spirit:modelParameter spirit:dataType="INTEGER">
+ <spirit:name>C_CLKOUT4_SEQUENCE_NUMBER</spirit:name>
+ <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C_CLKOUT4_SEQUENCE_NUMBER" spirit:order="505">1</spirit:value>
+ </spirit:modelParameter>
+ <spirit:modelParameter spirit:dataType="INTEGER">
+ <spirit:name>C_CLKOUT5_SEQUENCE_NUMBER</spirit:name>
+ <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C_CLKOUT5_SEQUENCE_NUMBER" spirit:order="506">1</spirit:value>
+ </spirit:modelParameter>
+ <spirit:modelParameter spirit:dataType="INTEGER">
+ <spirit:name>C_CLKOUT6_SEQUENCE_NUMBER</spirit:name>
+ <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C_CLKOUT6_SEQUENCE_NUMBER" spirit:order="507">1</spirit:value>
+ </spirit:modelParameter>
+ <spirit:modelParameter spirit:dataType="INTEGER">
+ <spirit:name>C_CLKOUT7_SEQUENCE_NUMBER</spirit:name>
+ <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C_CLKOUT7_SEQUENCE_NUMBER" spirit:order="508">1</spirit:value>
+ </spirit:modelParameter>
+ <spirit:modelParameter spirit:dataType="STRING">
+ <spirit:name>C_MMCM_NOTES</spirit:name>
+ <spirit:value spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C_MMCM_NOTES" spirit:order="296">None</spirit:value>
+ </spirit:modelParameter>
+ <spirit:modelParameter spirit:dataType="STRING">
+ <spirit:name>C_MMCM_BANDWIDTH</spirit:name>
+ <spirit:value spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C_MMCM_BANDWIDTH" spirit:order="297">OPTIMIZED</spirit:value>
+ </spirit:modelParameter>
+ <spirit:modelParameter spirit:dataType="STRING">
+ <spirit:name>C_MMCM_CLKFBOUT_MULT_F</spirit:name>
+ <spirit:value spirit:format="float" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C_MMCM_CLKFBOUT_MULT_F" spirit:order="298">9.125</spirit:value>
+ </spirit:modelParameter>
+ <spirit:modelParameter spirit:dataType="STRING">
+ <spirit:name>C_MMCM_CLKIN1_PERIOD</spirit:name>
+ <spirit:value spirit:format="float" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C_MMCM_CLKIN1_PERIOD" spirit:order="299">10.000</spirit:value>
+ </spirit:modelParameter>
+ <spirit:modelParameter spirit:dataType="STRING">
+ <spirit:name>C_MMCM_CLKIN2_PERIOD</spirit:name>
+ <spirit:value spirit:format="float" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C_MMCM_CLKIN2_PERIOD" spirit:order="300">10.000</spirit:value>
+ </spirit:modelParameter>
+ <spirit:modelParameter spirit:dataType="STRING">
+ <spirit:name>C_MMCM_CLKOUT4_CASCADE</spirit:name>
+ <spirit:value spirit:format="bool" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C_MMCM_CLKOUT4_CASCADE" spirit:order="301">FALSE</spirit:value>
+ </spirit:modelParameter>
+ <spirit:modelParameter spirit:dataType="STRING">
+ <spirit:name>C_MMCM_CLOCK_HOLD</spirit:name>
+ <spirit:value spirit:format="bool" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C_MMCM_CLOCK_HOLD" spirit:order="302">FALSE</spirit:value>
+ </spirit:modelParameter>
+ <spirit:modelParameter spirit:dataType="STRING">
+ <spirit:name>C_MMCM_COMPENSATION</spirit:name>
+ <spirit:value spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C_MMCM_COMPENSATION" spirit:order="303">ZHOLD</spirit:value>
+ </spirit:modelParameter>
+ <spirit:modelParameter spirit:dataType="INTEGER">
+ <spirit:name>C_MMCM_DIVCLK_DIVIDE</spirit:name>
+ <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C_MMCM_DIVCLK_DIVIDE" spirit:order="304">1</spirit:value>
+ </spirit:modelParameter>
+ <spirit:modelParameter spirit:dataType="STRING">
+ <spirit:name>C_MMCM_REF_JITTER1</spirit:name>
+ <spirit:value spirit:format="float" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C_MMCM_REF_JITTER1" spirit:order="305">0.010</spirit:value>
+ </spirit:modelParameter>
+ <spirit:modelParameter spirit:dataType="STRING">
+ <spirit:name>C_MMCM_REF_JITTER2</spirit:name>
+ <spirit:value spirit:format="float" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C_MMCM_REF_JITTER2" spirit:order="306">0.010</spirit:value>
+ </spirit:modelParameter>
+ <spirit:modelParameter spirit:dataType="STRING">
+ <spirit:name>C_MMCM_STARTUP_WAIT</spirit:name>
+ <spirit:value spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C_MMCM_STARTUP_WAIT" spirit:order="307">FALSE</spirit:value>
+ </spirit:modelParameter>
+ <spirit:modelParameter spirit:dataType="STRING">
+ <spirit:name>C_MMCM_CLKOUT0_DIVIDE_F</spirit:name>
+ <spirit:value spirit:format="float" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C_MMCM_CLKOUT0_DIVIDE_F" spirit:order="308">36.500</spirit:value>
+ </spirit:modelParameter>
+ <spirit:modelParameter spirit:dataType="STRING">
+ <spirit:name>C_MMCM_CLKOUT1_DIVIDE</spirit:name>
+ <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C_MMCM_CLKOUT1_DIVIDE" spirit:order="309">1</spirit:value>
+ </spirit:modelParameter>
+ <spirit:modelParameter spirit:dataType="STRING">
+ <spirit:name>C_MMCM_CLKOUT2_DIVIDE</spirit:name>
+ <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C_MMCM_CLKOUT2_DIVIDE" spirit:order="310">1</spirit:value>
+ </spirit:modelParameter>
+ <spirit:modelParameter spirit:dataType="STRING">
+ <spirit:name>C_MMCM_CLKOUT3_DIVIDE</spirit:name>
+ <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C_MMCM_CLKOUT3_DIVIDE" spirit:order="311">1</spirit:value>
+ </spirit:modelParameter>
+ <spirit:modelParameter spirit:dataType="STRING">
+ <spirit:name>C_MMCM_CLKOUT4_DIVIDE</spirit:name>
+ <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C_MMCM_CLKOUT4_DIVIDE" spirit:order="312">1</spirit:value>
+ </spirit:modelParameter>
+ <spirit:modelParameter spirit:dataType="STRING">
+ <spirit:name>C_MMCM_CLKOUT5_DIVIDE</spirit:name>
+ <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C_MMCM_CLKOUT5_DIVIDE" spirit:order="313">1</spirit:value>
+ </spirit:modelParameter>
+ <spirit:modelParameter spirit:dataType="STRING">
+ <spirit:name>C_MMCM_CLKOUT6_DIVIDE</spirit:name>
+ <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C_MMCM_CLKOUT6_DIVIDE" spirit:order="314">1</spirit:value>
+ </spirit:modelParameter>
+ <spirit:modelParameter spirit:dataType="STRING">
+ <spirit:name>C_MMCM_CLKOUT0_DUTY_CYCLE</spirit:name>
+ <spirit:value spirit:format="float" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C_MMCM_CLKOUT0_DUTY_CYCLE" spirit:order="315">0.500</spirit:value>
+ </spirit:modelParameter>
+ <spirit:modelParameter spirit:dataType="STRING">
+ <spirit:name>C_MMCM_CLKOUT1_DUTY_CYCLE</spirit:name>
+ <spirit:value spirit:format="float" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C_MMCM_CLKOUT1_DUTY_CYCLE" spirit:order="316">0.500</spirit:value>
+ </spirit:modelParameter>
+ <spirit:modelParameter spirit:dataType="STRING">
+ <spirit:name>C_MMCM_CLKOUT2_DUTY_CYCLE</spirit:name>
+ <spirit:value spirit:format="float" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C_MMCM_CLKOUT2_DUTY_CYCLE" spirit:order="317">0.500</spirit:value>
+ </spirit:modelParameter>
+ <spirit:modelParameter spirit:dataType="STRING">
+ <spirit:name>C_MMCM_CLKOUT3_DUTY_CYCLE</spirit:name>
+ <spirit:value spirit:format="float" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C_MMCM_CLKOUT3_DUTY_CYCLE" spirit:order="318">0.500</spirit:value>
+ </spirit:modelParameter>
+ <spirit:modelParameter spirit:dataType="STRING">
+ <spirit:name>C_MMCM_CLKOUT4_DUTY_CYCLE</spirit:name>
+ <spirit:value spirit:format="float" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C_MMCM_CLKOUT4_DUTY_CYCLE" spirit:order="319">0.500</spirit:value>
+ </spirit:modelParameter>
+ <spirit:modelParameter spirit:dataType="STRING">
+ <spirit:name>C_MMCM_CLKOUT5_DUTY_CYCLE</spirit:name>
+ <spirit:value spirit:format="float" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C_MMCM_CLKOUT5_DUTY_CYCLE" spirit:order="320">0.500</spirit:value>
+ </spirit:modelParameter>
+ <spirit:modelParameter spirit:dataType="STRING">
+ <spirit:name>C_MMCM_CLKOUT6_DUTY_CYCLE</spirit:name>
+ <spirit:value spirit:format="float" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C_MMCM_CLKOUT6_DUTY_CYCLE" spirit:order="321">0.500</spirit:value>
+ </spirit:modelParameter>
+ <spirit:modelParameter spirit:dataType="STRING">
+ <spirit:name>C_MMCM_CLKFBOUT_PHASE</spirit:name>
+ <spirit:value spirit:format="float" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C_MMCM_CLKFBOUT_PHASE" spirit:order="322">0.000</spirit:value>
+ </spirit:modelParameter>
+ <spirit:modelParameter spirit:dataType="STRING">
+ <spirit:name>C_MMCM_CLKOUT0_PHASE</spirit:name>
+ <spirit:value spirit:format="float" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C_MMCM_CLKOUT0_PHASE" spirit:order="323">0.000</spirit:value>
+ </spirit:modelParameter>
+ <spirit:modelParameter spirit:dataType="STRING">
+ <spirit:name>C_MMCM_CLKOUT1_PHASE</spirit:name>
+ <spirit:value spirit:format="float" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C_MMCM_CLKOUT1_PHASE" spirit:order="324">0.000</spirit:value>
+ </spirit:modelParameter>
+ <spirit:modelParameter spirit:dataType="STRING">
+ <spirit:name>C_MMCM_CLKOUT2_PHASE</spirit:name>
+ <spirit:value spirit:format="float" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C_MMCM_CLKOUT2_PHASE" spirit:order="325">0.000</spirit:value>
+ </spirit:modelParameter>
+ <spirit:modelParameter spirit:dataType="STRING">
+ <spirit:name>C_MMCM_CLKOUT3_PHASE</spirit:name>
+ <spirit:value spirit:format="float" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C_MMCM_CLKOUT3_PHASE" spirit:order="326">0.000</spirit:value>
+ </spirit:modelParameter>
+ <spirit:modelParameter spirit:dataType="STRING">
+ <spirit:name>C_MMCM_CLKOUT4_PHASE</spirit:name>
+ <spirit:value spirit:format="float" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C_MMCM_CLKOUT4_PHASE" spirit:order="327">0.000</spirit:value>
+ </spirit:modelParameter>
+ <spirit:modelParameter spirit:dataType="STRING">
+ <spirit:name>C_MMCM_CLKOUT5_PHASE</spirit:name>
+ <spirit:value spirit:format="float" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C_MMCM_CLKOUT5_PHASE" spirit:order="328">0.000</spirit:value>
+ </spirit:modelParameter>
+ <spirit:modelParameter spirit:dataType="STRING">
+ <spirit:name>C_MMCM_CLKOUT6_PHASE</spirit:name>
+ <spirit:value spirit:format="float" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C_MMCM_CLKOUT6_PHASE" spirit:order="329">0.000</spirit:value>
+ </spirit:modelParameter>
+ <spirit:modelParameter spirit:dataType="STRING">
+ <spirit:name>C_MMCM_CLKFBOUT_USE_FINE_PS</spirit:name>
+ <spirit:value spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C_MMCM_CLKFBOUT_USE_FINE_PS" spirit:order="330">FALSE</spirit:value>
+ </spirit:modelParameter>
+ <spirit:modelParameter spirit:dataType="STRING">
+ <spirit:name>C_MMCM_CLKOUT0_USE_FINE_PS</spirit:name>
+ <spirit:value spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C_MMCM_CLKOUT0_USE_FINE_PS" spirit:order="331">FALSE</spirit:value>
+ </spirit:modelParameter>
+ <spirit:modelParameter spirit:dataType="STRING">
+ <spirit:name>C_MMCM_CLKOUT1_USE_FINE_PS</spirit:name>
+ <spirit:value spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C_MMCM_CLKOUT1_USE_FINE_PS" spirit:order="332">FALSE</spirit:value>
+ </spirit:modelParameter>
+ <spirit:modelParameter spirit:dataType="STRING">
+ <spirit:name>C_MMCM_CLKOUT2_USE_FINE_PS</spirit:name>
+ <spirit:value spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C_MMCM_CLKOUT2_USE_FINE_PS" spirit:order="333">FALSE</spirit:value>
+ </spirit:modelParameter>
+ <spirit:modelParameter spirit:dataType="STRING">
+ <spirit:name>C_MMCM_CLKOUT3_USE_FINE_PS</spirit:name>
+ <spirit:value spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C_MMCM_CLKOUT3_USE_FINE_PS" spirit:order="334">FALSE</spirit:value>
+ </spirit:modelParameter>
+ <spirit:modelParameter spirit:dataType="STRING">
+ <spirit:name>C_MMCM_CLKOUT4_USE_FINE_PS</spirit:name>
+ <spirit:value spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C_MMCM_CLKOUT4_USE_FINE_PS" spirit:order="335">FALSE</spirit:value>
+ </spirit:modelParameter>
+ <spirit:modelParameter spirit:dataType="STRING">
+ <spirit:name>C_MMCM_CLKOUT5_USE_FINE_PS</spirit:name>
+ <spirit:value spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C_MMCM_CLKOUT5_USE_FINE_PS" spirit:order="336">FALSE</spirit:value>
+ </spirit:modelParameter>
+ <spirit:modelParameter spirit:dataType="STRING">
+ <spirit:name>C_MMCM_CLKOUT6_USE_FINE_PS</spirit:name>
+ <spirit:value spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C_MMCM_CLKOUT6_USE_FINE_PS" spirit:order="337">FALSE</spirit:value>
+ </spirit:modelParameter>
+ <spirit:modelParameter spirit:dataType="STRING">
+ <spirit:name>C_PLL_NOTES</spirit:name>
+ <spirit:value spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C_PLL_NOTES" spirit:order="338">No notes</spirit:value>
+ </spirit:modelParameter>
+ <spirit:modelParameter spirit:dataType="STRING">
+ <spirit:name>C_PLL_BANDWIDTH</spirit:name>
+ <spirit:value spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C_PLL_BANDWIDTH" spirit:order="339">OPTIMIZED</spirit:value>
+ </spirit:modelParameter>
+ <spirit:modelParameter spirit:dataType="STRING">
+ <spirit:name>C_PLL_CLK_FEEDBACK</spirit:name>
+ <spirit:value spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C_PLL_CLK_FEEDBACK" spirit:order="340">CLKFBOUT</spirit:value>
+ </spirit:modelParameter>
+ <spirit:modelParameter spirit:dataType="INTEGER">
+ <spirit:name>C_PLL_CLKFBOUT_MULT</spirit:name>
+ <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C_PLL_CLKFBOUT_MULT" spirit:order="341">1</spirit:value>
+ </spirit:modelParameter>
+ <spirit:modelParameter spirit:dataType="STRING">
+ <spirit:name>C_PLL_CLKIN_PERIOD</spirit:name>
+ <spirit:value spirit:format="float" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C_PLL_CLKIN_PERIOD" spirit:order="342">1.000</spirit:value>
+ </spirit:modelParameter>
+ <spirit:modelParameter spirit:dataType="STRING">
+ <spirit:name>C_PLL_COMPENSATION</spirit:name>
+ <spirit:value spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C_PLL_COMPENSATION" spirit:order="343">SYSTEM_SYNCHRONOUS</spirit:value>
+ </spirit:modelParameter>
+ <spirit:modelParameter spirit:dataType="INTEGER">
+ <spirit:name>C_PLL_DIVCLK_DIVIDE</spirit:name>
+ <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C_PLL_DIVCLK_DIVIDE" spirit:order="344">1</spirit:value>
+ </spirit:modelParameter>
+ <spirit:modelParameter spirit:dataType="STRING">
+ <spirit:name>C_PLL_REF_JITTER</spirit:name>
+ <spirit:value spirit:format="float" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C_PLL_REF_JITTER" spirit:order="345">0.010</spirit:value>
+ </spirit:modelParameter>
+ <spirit:modelParameter spirit:dataType="INTEGER">
+ <spirit:name>C_PLL_CLKOUT0_DIVIDE</spirit:name>
+ <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C_PLL_CLKOUT0_DIVIDE" spirit:order="346">1</spirit:value>
+ </spirit:modelParameter>
+ <spirit:modelParameter spirit:dataType="INTEGER">
+ <spirit:name>C_PLL_CLKOUT1_DIVIDE</spirit:name>
+ <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C_PLL_CLKOUT1_DIVIDE" spirit:order="347">1</spirit:value>
+ </spirit:modelParameter>
+ <spirit:modelParameter spirit:dataType="INTEGER">
+ <spirit:name>C_PLL_CLKOUT2_DIVIDE</spirit:name>
+ <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C_PLL_CLKOUT2_DIVIDE" spirit:order="348">1</spirit:value>
+ </spirit:modelParameter>
+ <spirit:modelParameter spirit:dataType="INTEGER">
+ <spirit:name>C_PLL_CLKOUT3_DIVIDE</spirit:name>
+ <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C_PLL_CLKOUT3_DIVIDE" spirit:order="349">1</spirit:value>
+ </spirit:modelParameter>
+ <spirit:modelParameter spirit:dataType="INTEGER">
+ <spirit:name>C_PLL_CLKOUT4_DIVIDE</spirit:name>
+ <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C_PLL_CLKOUT4_DIVIDE" spirit:order="350">1</spirit:value>
+ </spirit:modelParameter>
+ <spirit:modelParameter spirit:dataType="INTEGER">
+ <spirit:name>C_PLL_CLKOUT5_DIVIDE</spirit:name>
+ <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C_PLL_CLKOUT5_DIVIDE" spirit:order="351">1</spirit:value>
+ </spirit:modelParameter>
+ <spirit:modelParameter spirit:dataType="STRING">
+ <spirit:name>C_PLL_CLKOUT0_DUTY_CYCLE</spirit:name>
+ <spirit:value spirit:format="float" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C_PLL_CLKOUT0_DUTY_CYCLE" spirit:order="352">0.500</spirit:value>
+ </spirit:modelParameter>
+ <spirit:modelParameter spirit:dataType="STRING">
+ <spirit:name>C_PLL_CLKOUT1_DUTY_CYCLE</spirit:name>
+ <spirit:value spirit:format="float" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C_PLL_CLKOUT1_DUTY_CYCLE" spirit:order="353">0.500</spirit:value>
+ </spirit:modelParameter>
+ <spirit:modelParameter spirit:dataType="STRING">
+ <spirit:name>C_PLL_CLKOUT2_DUTY_CYCLE</spirit:name>
+ <spirit:value spirit:format="float" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C_PLL_CLKOUT2_DUTY_CYCLE" spirit:order="354">0.500</spirit:value>
+ </spirit:modelParameter>
+ <spirit:modelParameter spirit:dataType="STRING">
+ <spirit:name>C_PLL_CLKOUT3_DUTY_CYCLE</spirit:name>
+ <spirit:value spirit:format="float" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C_PLL_CLKOUT3_DUTY_CYCLE" spirit:order="355">0.500</spirit:value>
+ </spirit:modelParameter>
+ <spirit:modelParameter spirit:dataType="STRING">
+ <spirit:name>C_PLL_CLKOUT4_DUTY_CYCLE</spirit:name>
+ <spirit:value spirit:format="float" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C_PLL_CLKOUT4_DUTY_CYCLE" spirit:order="356">0.500</spirit:value>
+ </spirit:modelParameter>
+ <spirit:modelParameter spirit:dataType="STRING">
+ <spirit:name>C_PLL_CLKOUT5_DUTY_CYCLE</spirit:name>
+ <spirit:value spirit:format="float" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C_PLL_CLKOUT5_DUTY_CYCLE" spirit:order="357">0.500</spirit:value>
+ </spirit:modelParameter>
+ <spirit:modelParameter spirit:dataType="STRING">
+ <spirit:name>C_PLL_CLKFBOUT_PHASE</spirit:name>
+ <spirit:value spirit:format="float" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C_PLL_CLKFBOUT_PHASE" spirit:order="358">0.000</spirit:value>
+ </spirit:modelParameter>
+ <spirit:modelParameter spirit:dataType="STRING">
+ <spirit:name>C_PLL_CLKOUT0_PHASE</spirit:name>
+ <spirit:value spirit:format="float" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C_PLL_CLKOUT0_PHASE" spirit:order="359">0.000</spirit:value>
+ </spirit:modelParameter>
+ <spirit:modelParameter spirit:dataType="STRING">
+ <spirit:name>C_PLL_CLKOUT1_PHASE</spirit:name>
+ <spirit:value spirit:format="float" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C_PLL_CLKOUT1_PHASE" spirit:order="360">0.000</spirit:value>
+ </spirit:modelParameter>
+ <spirit:modelParameter spirit:dataType="STRING">
+ <spirit:name>C_PLL_CLKOUT2_PHASE</spirit:name>
+ <spirit:value spirit:format="float" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C_PLL_CLKOUT2_PHASE" spirit:order="361">0.000</spirit:value>
+ </spirit:modelParameter>
+ <spirit:modelParameter spirit:dataType="STRING">
+ <spirit:name>C_PLL_CLKOUT3_PHASE</spirit:name>
+ <spirit:value spirit:format="float" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C_PLL_CLKOUT3_PHASE" spirit:order="362">0.000</spirit:value>
+ </spirit:modelParameter>
+ <spirit:modelParameter spirit:dataType="STRING">
+ <spirit:name>C_PLL_CLKOUT4_PHASE</spirit:name>
+ <spirit:value spirit:format="float" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C_PLL_CLKOUT4_PHASE" spirit:order="363">0.000</spirit:value>
+ </spirit:modelParameter>
+ <spirit:modelParameter spirit:dataType="STRING">
+ <spirit:name>C_PLL_CLKOUT5_PHASE</spirit:name>
+ <spirit:value spirit:format="float" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C_PLL_CLKOUT5_PHASE" spirit:order="364">0.000</spirit:value>
+ </spirit:modelParameter>
+ <spirit:modelParameter spirit:dataType="STRING">
+ <spirit:name>C_CLOCK_MGR_TYPE</spirit:name>
+ <spirit:value spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C_CLOCK_MGR_TYPE" spirit:order="365">NA</spirit:value>
+ </spirit:modelParameter>
+ <spirit:modelParameter spirit:dataType="INTEGER">
+ <spirit:name>C_OVERRIDE_MMCM</spirit:name>
+ <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C_OVERRIDE_MMCM" spirit:order="366">0</spirit:value>
+ </spirit:modelParameter>
+ <spirit:modelParameter spirit:dataType="INTEGER">
+ <spirit:name>C_OVERRIDE_PLL</spirit:name>
+ <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C_OVERRIDE_PLL" spirit:order="367">0</spirit:value>
+ </spirit:modelParameter>
+ <spirit:modelParameter spirit:dataType="STRING">
+ <spirit:name>C_PRIMARY_PORT</spirit:name>
+ <spirit:value spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C_PRIMARY_PORT" spirit:order="368">clk_in1</spirit:value>
+ </spirit:modelParameter>
+ <spirit:modelParameter spirit:dataType="STRING">
+ <spirit:name>C_SECONDARY_PORT</spirit:name>
+ <spirit:value spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C_SECONDARY_PORT" spirit:order="369">clk_in2</spirit:value>
+ </spirit:modelParameter>
+ <spirit:modelParameter spirit:dataType="STRING">
+ <spirit:name>C_CLK_OUT1_PORT</spirit:name>
+ <spirit:value spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C_CLK_OUT1_PORT" spirit:order="370">clk_out1</spirit:value>
+ </spirit:modelParameter>
+ <spirit:modelParameter spirit:dataType="STRING">
+ <spirit:name>C_CLK_OUT2_PORT</spirit:name>
+ <spirit:value spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C_CLK_OUT2_PORT" spirit:order="371">clk_out2</spirit:value>
+ </spirit:modelParameter>
+ <spirit:modelParameter spirit:dataType="STRING">
+ <spirit:name>C_CLK_OUT3_PORT</spirit:name>
+ <spirit:value spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C_CLK_OUT3_PORT" spirit:order="372">clk_out3</spirit:value>
+ </spirit:modelParameter>
+ <spirit:modelParameter spirit:dataType="STRING">
+ <spirit:name>C_CLK_OUT4_PORT</spirit:name>
+ <spirit:value spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C_CLK_OUT4_PORT" spirit:order="373">clk_out4</spirit:value>
+ </spirit:modelParameter>
+ <spirit:modelParameter spirit:dataType="STRING">
+ <spirit:name>C_CLK_OUT5_PORT</spirit:name>
+ <spirit:value spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C_CLK_OUT5_PORT" spirit:order="374">clk_out5</spirit:value>
+ </spirit:modelParameter>
+ <spirit:modelParameter spirit:dataType="STRING">
+ <spirit:name>C_CLK_OUT6_PORT</spirit:name>
+ <spirit:value spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C_CLK_OUT6_PORT" spirit:order="375">clk_out6</spirit:value>
+ </spirit:modelParameter>
+ <spirit:modelParameter spirit:dataType="STRING">
+ <spirit:name>C_CLK_OUT7_PORT</spirit:name>
+ <spirit:value spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C_CLK_OUT7_PORT" spirit:order="376">clk_out7</spirit:value>
+ </spirit:modelParameter>
+ <spirit:modelParameter spirit:dataType="STRING">
+ <spirit:name>C_RESET_PORT</spirit:name>
+ <spirit:value spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C_RESET_PORT" spirit:order="377">resetn</spirit:value>
+ </spirit:modelParameter>
+ <spirit:modelParameter spirit:dataType="STRING">
+ <spirit:name>C_LOCKED_PORT</spirit:name>
+ <spirit:value spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C_LOCKED_PORT" spirit:order="378">locked</spirit:value>
+ </spirit:modelParameter>
+ <spirit:modelParameter spirit:dataType="STRING">
+ <spirit:name>C_CLKFB_IN_PORT</spirit:name>
+ <spirit:value spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C_CLKFB_IN_PORT" spirit:order="379">clkfb_in</spirit:value>
+ </spirit:modelParameter>
+ <spirit:modelParameter spirit:dataType="STRING">
+ <spirit:name>C_CLKFB_IN_P_PORT</spirit:name>
+ <spirit:value spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C_CLKFB_IN_P_PORT" spirit:order="380">clkfb_in_p</spirit:value>
+ </spirit:modelParameter>
+ <spirit:modelParameter spirit:dataType="STRING">
+ <spirit:name>C_CLKFB_IN_N_PORT</spirit:name>
+ <spirit:value spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C_CLKFB_IN_N_PORT" spirit:order="381">clkfb_in_n</spirit:value>
+ </spirit:modelParameter>
+ <spirit:modelParameter spirit:dataType="STRING">
+ <spirit:name>C_CLKFB_OUT_PORT</spirit:name>
+ <spirit:value spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C_CLKFB_OUT_PORT" spirit:order="382">clkfb_out</spirit:value>
+ </spirit:modelParameter>
+ <spirit:modelParameter spirit:dataType="STRING">
+ <spirit:name>C_CLKFB_OUT_P_PORT</spirit:name>
+ <spirit:value spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C_CLKFB_OUT_P_PORT" spirit:order="383">clkfb_out_p</spirit:value>
+ </spirit:modelParameter>
+ <spirit:modelParameter spirit:dataType="STRING">
+ <spirit:name>C_CLKFB_OUT_N_PORT</spirit:name>
+ <spirit:value spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C_CLKFB_OUT_N_PORT" spirit:order="384">clkfb_out_n</spirit:value>
+ </spirit:modelParameter>
+ <spirit:modelParameter spirit:dataType="STRING">
+ <spirit:name>C_POWER_DOWN_PORT</spirit:name>
+ <spirit:value spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C_POWER_DOWN_PORT" spirit:order="385">power_down</spirit:value>
+ </spirit:modelParameter>
+ <spirit:modelParameter spirit:dataType="STRING">
+ <spirit:name>C_DADDR_PORT</spirit:name>
+ <spirit:value spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C_DADDR_PORT" spirit:order="386">daddr</spirit:value>
+ </spirit:modelParameter>
+ <spirit:modelParameter spirit:dataType="STRING">
+ <spirit:name>C_DCLK_PORT</spirit:name>
+ <spirit:value spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C_DCLK_PORT" spirit:order="387">dclk</spirit:value>
+ </spirit:modelParameter>
+ <spirit:modelParameter spirit:dataType="STRING">
+ <spirit:name>C_DRDY_PORT</spirit:name>
+ <spirit:value spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C_DRDY_PORT" spirit:order="388">drdy</spirit:value>
+ </spirit:modelParameter>
+ <spirit:modelParameter spirit:dataType="STRING">
+ <spirit:name>C_DWE_PORT</spirit:name>
+ <spirit:value spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C_DWE_PORT" spirit:order="389">dwe</spirit:value>
+ </spirit:modelParameter>
+ <spirit:modelParameter spirit:dataType="STRING">
+ <spirit:name>C_DIN_PORT</spirit:name>
+ <spirit:value spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C_DIN_PORT" spirit:order="390">din</spirit:value>
+ </spirit:modelParameter>
+ <spirit:modelParameter spirit:dataType="STRING">
+ <spirit:name>C_DOUT_PORT</spirit:name>
+ <spirit:value spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C_DOUT_PORT" spirit:order="391">dout</spirit:value>
+ </spirit:modelParameter>
+ <spirit:modelParameter spirit:dataType="STRING">
+ <spirit:name>C_DEN_PORT</spirit:name>
+ <spirit:value spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C_DEN_PORT" spirit:order="392">den</spirit:value>
+ </spirit:modelParameter>
+ <spirit:modelParameter spirit:dataType="STRING">
+ <spirit:name>C_PSCLK_PORT</spirit:name>
+ <spirit:value spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C_PSCLK_PORT" spirit:order="393">psclk</spirit:value>
+ </spirit:modelParameter>
+ <spirit:modelParameter spirit:dataType="STRING">
+ <spirit:name>C_PSEN_PORT</spirit:name>
+ <spirit:value spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C_PSEN_PORT" spirit:order="394">psen</spirit:value>
+ </spirit:modelParameter>
+ <spirit:modelParameter spirit:dataType="STRING">
+ <spirit:name>C_PSINCDEC_PORT</spirit:name>
+ <spirit:value spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C_PSINCDEC_PORT" spirit:order="395">psincdec</spirit:value>
+ </spirit:modelParameter>
+ <spirit:modelParameter spirit:dataType="STRING">
+ <spirit:name>C_PSDONE_PORT</spirit:name>
+ <spirit:value spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C_PSDONE_PORT" spirit:order="396">psdone</spirit:value>
+ </spirit:modelParameter>
+ <spirit:modelParameter spirit:dataType="STRING">
+ <spirit:name>C_CLK_VALID_PORT</spirit:name>
+ <spirit:value spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C_CLK_VALID_PORT" spirit:order="397">CLK_VALID</spirit:value>
+ </spirit:modelParameter>
+ <spirit:modelParameter spirit:dataType="STRING">
+ <spirit:name>C_STATUS_PORT</spirit:name>
+ <spirit:value spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C_STATUS_PORT" spirit:order="398">STATUS</spirit:value>
+ </spirit:modelParameter>
+ <spirit:modelParameter spirit:dataType="STRING">
+ <spirit:name>C_CLK_IN_SEL_PORT</spirit:name>
+ <spirit:value spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C_CLK_IN_SEL_PORT" spirit:order="399">clk_in_sel</spirit:value>
+ </spirit:modelParameter>
+ <spirit:modelParameter spirit:dataType="STRING">
+ <spirit:name>C_INPUT_CLK_STOPPED_PORT</spirit:name>
+ <spirit:value spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C_INPUT_CLK_STOPPED_PORT" spirit:order="400">input_clk_stopped</spirit:value>
+ </spirit:modelParameter>
+ <spirit:modelParameter spirit:dataType="STRING">
+ <spirit:name>C_CLKFB_STOPPED_PORT</spirit:name>
+ <spirit:value spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C_CLKFB_STOPPED_PORT" spirit:order="401">clkfb_stopped</spirit:value>
+ </spirit:modelParameter>
+ <spirit:modelParameter spirit:dataType="STRING">
+ <spirit:name>C_CLKIN1_JITTER_PS</spirit:name>
+ <spirit:value spirit:format="float" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C_CLKIN1_JITTER_PS" spirit:order="402">100.0</spirit:value>
+ </spirit:modelParameter>
+ <spirit:modelParameter spirit:dataType="STRING">
+ <spirit:name>C_CLKIN2_JITTER_PS</spirit:name>
+ <spirit:value spirit:format="float" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C_CLKIN2_JITTER_PS" spirit:order="403">100.0</spirit:value>
+ </spirit:modelParameter>
+ <spirit:modelParameter spirit:dataType="STRING">
+ <spirit:name>C_PRIMITIVE</spirit:name>
+ <spirit:value spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C_PRIMITIVE" spirit:order="404">MMCM</spirit:value>
+ </spirit:modelParameter>
+ <spirit:modelParameter spirit:dataType="STRING">
+ <spirit:name>C_SS_MODE</spirit:name>
+ <spirit:value spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C_SS_MODE" spirit:order="405">CENTER_HIGH</spirit:value>
+ </spirit:modelParameter>
+ <spirit:modelParameter spirit:dataType="INTEGER">
+ <spirit:name>C_SS_MOD_PERIOD</spirit:name>
+ <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C_SS_MOD_PERIOD" spirit:order="406">4000</spirit:value>
+ </spirit:modelParameter>
+ <spirit:modelParameter spirit:dataType="STRING">
+ <spirit:name>C_SS_MOD_TIME</spirit:name>
+ <spirit:value spirit:format="float" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C_SS_MOD_TIME" spirit:order="406.001">0.004</spirit:value>
+ </spirit:modelParameter>
+ <spirit:modelParameter spirit:dataType="INTEGER">
+ <spirit:name>C_HAS_CDDC</spirit:name>
+ <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C_HAS_CDDC" spirit:order="407">0</spirit:value>
+ </spirit:modelParameter>
+ <spirit:modelParameter spirit:dataType="STRING">
+ <spirit:name>C_CDDCDONE_PORT</spirit:name>
+ <spirit:value spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C_CDDCDONE_PORT" spirit:order="408">cddcdone</spirit:value>
+ </spirit:modelParameter>
+ <spirit:modelParameter spirit:dataType="STRING">
+ <spirit:name>C_CDDCREQ_PORT</spirit:name>
+ <spirit:value spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C_CDDCREQ_PORT" spirit:order="409">cddcreq</spirit:value>
+ </spirit:modelParameter>
+ <spirit:modelParameter spirit:dataType="STRING">
+ <spirit:name>C_CLKOUTPHY_MODE</spirit:name>
+ <spirit:value spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C_CLKOUTPHY_MODE" spirit:order="410">VCO</spirit:value>
+ </spirit:modelParameter>
+ <spirit:modelParameter spirit:dataType="INTEGER">
+ <spirit:name>C_ENABLE_CLKOUTPHY</spirit:name>
+ <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C_ENABLE_CLKOUTPHY" spirit:order="411">0</spirit:value>
+ </spirit:modelParameter>
+ <spirit:modelParameter spirit:dataType="INTEGER">
+ <spirit:name>C_INTERFACE_SELECTION</spirit:name>
+ <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C_INTERFACE_SELECTION" spirit:order="412">0</spirit:value>
+ </spirit:modelParameter>
+ <spirit:modelParameter spirit:dataType="INTEGER">
+ <spirit:name>C_S_AXI_ADDR_WIDTH</spirit:name>
+ <spirit:displayName>C S Axi Addr Width</spirit:displayName>
+ <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C_S_AXI_ADDR_WIDTH" spirit:order="215" spirit:minimum="2" spirit:maximum="32" spirit:rangeType="long">11</spirit:value>
+ </spirit:modelParameter>
+ <spirit:modelParameter spirit:dataType="INTEGER">
+ <spirit:name>C_S_AXI_DATA_WIDTH</spirit:name>
+ <spirit:displayName>C S Axi Data Width</spirit:displayName>
+ <spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C_S_AXI_DATA_WIDTH" spirit:order="216" spirit:minimum="32" spirit:maximum="128" spirit:rangeType="long">32</spirit:value>
+ </spirit:modelParameter>
+ <spirit:modelParameter spirit:dataType="STRING">
+ <spirit:name>C_POWER_REG</spirit:name>
+ <spirit:value spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C_POWER_REG" spirit:order="409">0000</spirit:value>
+ </spirit:modelParameter>
+ <spirit:modelParameter spirit:dataType="STRING">
+ <spirit:name>C_CLKOUT0_1</spirit:name>
+ <spirit:value spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C_CLKOUT0_1" spirit:order="410">0000</spirit:value>
+ </spirit:modelParameter>
+ <spirit:modelParameter spirit:dataType="STRING">
+ <spirit:name>C_CLKOUT0_2</spirit:name>
+ <spirit:value spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C_CLKOUT0_2" spirit:order="411">0000</spirit:value>
+ </spirit:modelParameter>
+ <spirit:modelParameter spirit:dataType="STRING">
+ <spirit:name>C_CLKOUT1_1</spirit:name>
+ <spirit:value spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C_CLKOUT1_1" spirit:order="410">0000</spirit:value>
+ </spirit:modelParameter>
+ <spirit:modelParameter spirit:dataType="STRING">
+ <spirit:name>C_CLKOUT1_2</spirit:name>
+ <spirit:value spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C_CLKOUT1_2" spirit:order="410">0000</spirit:value>
+ </spirit:modelParameter>
+ <spirit:modelParameter spirit:dataType="STRING">
+ <spirit:name>C_CLKOUT2_1</spirit:name>
+ <spirit:value spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C_CLKOUT2_1" spirit:order="411">0000</spirit:value>
+ </spirit:modelParameter>
+ <spirit:modelParameter spirit:dataType="STRING">
+ <spirit:name>C_CLKOUT2_2</spirit:name>
+ <spirit:value spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C_CLKOUT2_2" spirit:order="411">0000</spirit:value>
+ </spirit:modelParameter>
+ <spirit:modelParameter spirit:dataType="STRING">
+ <spirit:name>C_CLKOUT3_1</spirit:name>
+ <spirit:value spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C_CLKOUT3_1" spirit:order="410">0000</spirit:value>
+ </spirit:modelParameter>
+ <spirit:modelParameter spirit:dataType="STRING">
+ <spirit:name>C_CLKOUT3_2</spirit:name>
+ <spirit:value spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C_CLKOUT3_2" spirit:order="411">0000</spirit:value>
+ </spirit:modelParameter>
+ <spirit:modelParameter spirit:dataType="STRING">
+ <spirit:name>C_CLKOUT4_1</spirit:name>
+ <spirit:value spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C_CLKOUT4_1" spirit:order="410">0000</spirit:value>
+ </spirit:modelParameter>
+ <spirit:modelParameter spirit:dataType="STRING">
+ <spirit:name>C_CLKOUT4_2</spirit:name>
+ <spirit:value spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C_CLKOUT4_2" spirit:order="411">0000</spirit:value>
+ </spirit:modelParameter>
+ <spirit:modelParameter spirit:dataType="STRING">
+ <spirit:name>C_CLKOUT5_1</spirit:name>
+ <spirit:value spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C_CLKOUT5_1" spirit:order="410">0000</spirit:value>
+ </spirit:modelParameter>
+ <spirit:modelParameter spirit:dataType="STRING">
+ <spirit:name>C_CLKOUT5_2</spirit:name>
+ <spirit:value spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C_CLKOUT5_2" spirit:order="411">0000</spirit:value>
+ </spirit:modelParameter>
+ <spirit:modelParameter spirit:dataType="STRING">
+ <spirit:name>C_CLKOUT6_1</spirit:name>
+ <spirit:value spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C_CLKOUT6_1" spirit:order="410">0000</spirit:value>
+ </spirit:modelParameter>
+ <spirit:modelParameter spirit:dataType="STRING">
+ <spirit:name>C_CLKOUT6_2</spirit:name>
+ <spirit:value spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C_CLKOUT6_2" spirit:order="411">0000</spirit:value>
+ </spirit:modelParameter>
+ <spirit:modelParameter spirit:dataType="STRING">
+ <spirit:name>C_CLKFBOUT_1</spirit:name>
+ <spirit:value spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C_CLKFBOUT_1" spirit:order="410">0000</spirit:value>
+ </spirit:modelParameter>
+ <spirit:modelParameter spirit:dataType="STRING">
+ <spirit:name>C_CLKFBOUT_2</spirit:name>
+ <spirit:value spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C_CLKFBOUT_2" spirit:order="411">0000</spirit:value>
+ </spirit:modelParameter>
+ <spirit:modelParameter spirit:dataType="STRING">
+ <spirit:name>C_DIVCLK</spirit:name>
+ <spirit:value spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C_DIVCLK" spirit:order="411">0000</spirit:value>
+ </spirit:modelParameter>
+ <spirit:modelParameter spirit:dataType="STRING">
+ <spirit:name>C_LOCK_1</spirit:name>
+ <spirit:value spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C_LOCK_1" spirit:order="411">0000</spirit:value>
+ </spirit:modelParameter>
+ <spirit:modelParameter spirit:dataType="STRING">
+ <spirit:name>C_LOCK_2</spirit:name>
+ <spirit:value spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C_LOCK_2" spirit:order="411">0000</spirit:value>
+ </spirit:modelParameter>
+ <spirit:modelParameter spirit:dataType="STRING">
+ <spirit:name>C_LOCK_3</spirit:name>
+ <spirit:value spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C_LOCK_3" spirit:order="411">0000</spirit:value>
+ </spirit:modelParameter>
+ <spirit:modelParameter spirit:dataType="STRING">
+ <spirit:name>C_FILTER_1</spirit:name>
+ <spirit:value spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C_FILTER_1" spirit:order="411">0000</spirit:value>
+ </spirit:modelParameter>
+ <spirit:modelParameter spirit:dataType="STRING">
+ <spirit:name>C_FILTER_2</spirit:name>
+ <spirit:value spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C_FILTER_2" spirit:order="411">0000</spirit:value>
+ </spirit:modelParameter>
+ <spirit:modelParameter spirit:dataType="STRING">
+ <spirit:name>C_DIVIDE1_AUTO</spirit:name>
+ <spirit:value spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C_DIVIDE1_AUTO" spirit:order="411">1</spirit:value>
+ </spirit:modelParameter>
+ <spirit:modelParameter spirit:dataType="STRING">
+ <spirit:name>C_DIVIDE2_AUTO</spirit:name>
+ <spirit:value spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C_DIVIDE2_AUTO" spirit:order="411">0.0273972602739726</spirit:value>
+ </spirit:modelParameter>
+ <spirit:modelParameter spirit:dataType="STRING">
+ <spirit:name>C_DIVIDE3_AUTO</spirit:name>
+ <spirit:value spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C_DIVIDE3_AUTO" spirit:order="411">0.0273972602739726</spirit:value>
+ </spirit:modelParameter>
+ <spirit:modelParameter spirit:dataType="STRING">
+ <spirit:name>C_DIVIDE4_AUTO</spirit:name>
+ <spirit:value spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C_DIVIDE4_AUTO" spirit:order="411">0.0273972602739726</spirit:value>
+ </spirit:modelParameter>
+ <spirit:modelParameter spirit:dataType="STRING">
+ <spirit:name>C_DIVIDE5_AUTO</spirit:name>
+ <spirit:value spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C_DIVIDE5_AUTO" spirit:order="411">0.0273972602739726</spirit:value>
+ </spirit:modelParameter>
+ <spirit:modelParameter spirit:dataType="STRING">
+ <spirit:name>C_DIVIDE6_AUTO</spirit:name>
+ <spirit:value spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C_DIVIDE6_AUTO" spirit:order="411">0.0273972602739726</spirit:value>
+ </spirit:modelParameter>
+ <spirit:modelParameter spirit:dataType="STRING">
+ <spirit:name>C_DIVIDE7_AUTO</spirit:name>
+ <spirit:value spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C_DIVIDE7_AUTO" spirit:order="411">0.0273972602739726</spirit:value>
+ </spirit:modelParameter>
+ <spirit:modelParameter spirit:dataType="STRING">
+ <spirit:name>C_PLLBUFGCEDIV</spirit:name>
+ <spirit:value spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C_PLLBUFGCEDIV" spirit:order="411">false</spirit:value>
+ </spirit:modelParameter>
+ <spirit:modelParameter spirit:dataType="STRING">
+ <spirit:name>C_MMCMBUFGCEDIV</spirit:name>
+ <spirit:value spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C_MMCMBUFGCEDIV" spirit:order="411">false</spirit:value>
+ </spirit:modelParameter>
+ <spirit:modelParameter spirit:dataType="STRING">
+ <spirit:name>C_PLLBUFGCEDIV1</spirit:name>
+ <spirit:value spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C_PLLBUFGCEDIV1" spirit:order="411">false</spirit:value>
+ </spirit:modelParameter>
+ <spirit:modelParameter spirit:dataType="STRING">
+ <spirit:name>C_PLLBUFGCEDIV2</spirit:name>
+ <spirit:value spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C_PLLBUFGCEDIV2" spirit:order="411">false</spirit:value>
+ </spirit:modelParameter>
+ <spirit:modelParameter spirit:dataType="STRING">
+ <spirit:name>C_PLLBUFGCEDIV3</spirit:name>
+ <spirit:value spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C_PLLBUFGCEDIV3" spirit:order="411">false</spirit:value>
+ </spirit:modelParameter>
+ <spirit:modelParameter spirit:dataType="STRING">
+ <spirit:name>C_PLLBUFGCEDIV4</spirit:name>
+ <spirit:value spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C_PLLBUFGCEDIV4" spirit:order="411">false</spirit:value>
+ </spirit:modelParameter>
+ <spirit:modelParameter spirit:dataType="STRING">
+ <spirit:name>C_MMCMBUFGCEDIV1</spirit:name>
+ <spirit:value spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C_MMCMBUFGCEDIV1" spirit:order="411">false</spirit:value>
+ </spirit:modelParameter>
+ <spirit:modelParameter spirit:dataType="STRING">
+ <spirit:name>C_MMCMBUFGCEDIV2</spirit:name>
+ <spirit:value spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C_MMCMBUFGCEDIV2" spirit:order="411">false</spirit:value>
+ </spirit:modelParameter>
+ <spirit:modelParameter spirit:dataType="STRING">
+ <spirit:name>C_MMCMBUFGCEDIV3</spirit:name>
+ <spirit:value spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C_MMCMBUFGCEDIV3" spirit:order="411">false</spirit:value>
+ </spirit:modelParameter>
+ <spirit:modelParameter spirit:dataType="STRING">
+ <spirit:name>C_MMCMBUFGCEDIV4</spirit:name>
+ <spirit:value spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C_MMCMBUFGCEDIV4" spirit:order="411">false</spirit:value>
+ </spirit:modelParameter>
+ <spirit:modelParameter spirit:dataType="STRING">
+ <spirit:name>C_MMCMBUFGCEDIV5</spirit:name>
+ <spirit:value spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C_MMCMBUFGCEDIV5" spirit:order="411">false</spirit:value>
+ </spirit:modelParameter>
+ <spirit:modelParameter spirit:dataType="STRING">
+ <spirit:name>C_MMCMBUFGCEDIV6</spirit:name>
+ <spirit:value spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C_MMCMBUFGCEDIV6" spirit:order="411">false</spirit:value>
+ </spirit:modelParameter>
+ <spirit:modelParameter spirit:dataType="STRING">
+ <spirit:name>C_MMCMBUFGCEDIV7</spirit:name>
+ <spirit:value spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C_MMCMBUFGCEDIV7" spirit:order="411">false</spirit:value>
+ </spirit:modelParameter>
+ <spirit:modelParameter spirit:dataType="STRING">
+ <spirit:name>C_CLKOUT1_MATCHED_ROUTING</spirit:name>
+ <spirit:value spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C_CLKOUT1_MATCHED_ROUTING" spirit:order="411">false</spirit:value>
+ </spirit:modelParameter>
+ <spirit:modelParameter spirit:dataType="STRING">
+ <spirit:name>C_CLKOUT2_MATCHED_ROUTING</spirit:name>
+ <spirit:value spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C_CLKOUT2_MATCHED_ROUTING" spirit:order="411">false</spirit:value>
+ </spirit:modelParameter>
+ <spirit:modelParameter spirit:dataType="STRING">
+ <spirit:name>C_CLKOUT3_MATCHED_ROUTING</spirit:name>
+ <spirit:value spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C_CLKOUT3_MATCHED_ROUTING" spirit:order="411">false</spirit:value>
+ </spirit:modelParameter>
+ <spirit:modelParameter spirit:dataType="STRING">
+ <spirit:name>C_CLKOUT4_MATCHED_ROUTING</spirit:name>
+ <spirit:value spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C_CLKOUT4_MATCHED_ROUTING" spirit:order="411">false</spirit:value>
+ </spirit:modelParameter>
+ <spirit:modelParameter spirit:dataType="STRING">
+ <spirit:name>C_CLKOUT5_MATCHED_ROUTING</spirit:name>
+ <spirit:value spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C_CLKOUT5_MATCHED_ROUTING" spirit:order="411">false</spirit:value>
+ </spirit:modelParameter>
+ <spirit:modelParameter spirit:dataType="STRING">
+ <spirit:name>C_CLKOUT6_MATCHED_ROUTING</spirit:name>
+ <spirit:value spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C_CLKOUT6_MATCHED_ROUTING" spirit:order="411">false</spirit:value>
+ </spirit:modelParameter>
+ <spirit:modelParameter spirit:dataType="STRING">
+ <spirit:name>C_CLKOUT7_MATCHED_ROUTING</spirit:name>
+ <spirit:value spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C_CLKOUT7_MATCHED_ROUTING" spirit:order="411">false</spirit:value>
+ </spirit:modelParameter>
+ <spirit:modelParameter spirit:dataType="STRING">
+ <spirit:name>C_CLKOUT0_ACTUAL_FREQ</spirit:name>
+ <spirit:value spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C_CLKOUT0_ACTUAL_FREQ" spirit:order="711">25.00000</spirit:value>
+ </spirit:modelParameter>
+ <spirit:modelParameter spirit:dataType="STRING">
+ <spirit:name>C_CLKOUT1_ACTUAL_FREQ</spirit:name>
+ <spirit:value spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C_CLKOUT1_ACTUAL_FREQ" spirit:order="712">100.000</spirit:value>
+ </spirit:modelParameter>
+ <spirit:modelParameter spirit:dataType="STRING">
+ <spirit:name>C_CLKOUT2_ACTUAL_FREQ</spirit:name>
+ <spirit:value spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C_CLKOUT2_ACTUAL_FREQ" spirit:order="713">100.000</spirit:value>
+ </spirit:modelParameter>
+ <spirit:modelParameter spirit:dataType="STRING">
+ <spirit:name>C_CLKOUT3_ACTUAL_FREQ</spirit:name>
+ <spirit:value spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C_CLKOUT3_ACTUAL_FREQ" spirit:order="714">100.000</spirit:value>
+ </spirit:modelParameter>
+ <spirit:modelParameter spirit:dataType="STRING">
+ <spirit:name>C_CLKOUT4_ACTUAL_FREQ</spirit:name>
+ <spirit:value spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C_CLKOUT4_ACTUAL_FREQ" spirit:order="715">100.000</spirit:value>
+ </spirit:modelParameter>
+ <spirit:modelParameter spirit:dataType="STRING">
+ <spirit:name>C_CLKOUT5_ACTUAL_FREQ</spirit:name>
+ <spirit:value spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C_CLKOUT5_ACTUAL_FREQ" spirit:order="716">100.000</spirit:value>
+ </spirit:modelParameter>
+ <spirit:modelParameter spirit:dataType="STRING">
+ <spirit:name>C_CLKOUT6_ACTUAL_FREQ</spirit:name>
+ <spirit:value spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C_CLKOUT6_ACTUAL_FREQ" spirit:order="717">100.000</spirit:value>
+ </spirit:modelParameter>
+ <spirit:modelParameter spirit:dataType="REAL">
+ <spirit:name>C_M_MAX</spirit:name>
+ <spirit:value spirit:format="float" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C_M_MAX" spirit:order="403">64.000</spirit:value>
+ </spirit:modelParameter>
+ <spirit:modelParameter spirit:dataType="REAL">
+ <spirit:name>C_M_MIN</spirit:name>
+ <spirit:value spirit:format="float" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C_M_MIN" spirit:order="403">2.000</spirit:value>
+ </spirit:modelParameter>
+ <spirit:modelParameter spirit:dataType="REAL">
+ <spirit:name>C_D_MAX</spirit:name>
+ <spirit:value spirit:format="float" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C_D_MAX" spirit:order="403">80.000</spirit:value>
+ </spirit:modelParameter>
+ <spirit:modelParameter spirit:dataType="REAL">
+ <spirit:name>C_D_MIN</spirit:name>
+ <spirit:value spirit:format="float" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C_D_MIN" spirit:order="403">1.000</spirit:value>
+ </spirit:modelParameter>
+ <spirit:modelParameter spirit:dataType="REAL">
+ <spirit:name>C_O_MAX</spirit:name>
+ <spirit:value spirit:format="float" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C_O_MAX" spirit:order="403">128.000</spirit:value>
+ </spirit:modelParameter>
+ <spirit:modelParameter spirit:dataType="REAL">
+ <spirit:name>C_O_MIN</spirit:name>
+ <spirit:value spirit:format="float" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C_O_MIN" spirit:order="403">1.000</spirit:value>
+ </spirit:modelParameter>
+ <spirit:modelParameter spirit:dataType="REAL">
+ <spirit:name>C_VCO_MIN</spirit:name>
+ <spirit:value spirit:format="float" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C_VCO_MIN" spirit:order="403">600.000</spirit:value>
+ </spirit:modelParameter>
+ <spirit:modelParameter spirit:dataType="REAL">
+ <spirit:name>C_VCO_MAX</spirit:name>
+ <spirit:value spirit:format="float" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C_VCO_MAX" spirit:order="403">1200.000</spirit:value>
+ </spirit:modelParameter>
+ </spirit:modelParameters>
+ </spirit:model>
+ <spirit:choices>
+ <spirit:choice>
+ <spirit:name>choice_list_1d3de01d</spirit:name>
+ <spirit:enumeration>WAVEFORM</spirit:enumeration>
+ <spirit:enumeration>LATENCY</spirit:enumeration>
+ </spirit:choice>
+ <spirit:choice>
+ <spirit:name>choice_list_876bfc32</spirit:name>
+ <spirit:enumeration>UI</spirit:enumeration>
+ <spirit:enumeration>PS</spirit:enumeration>
+ </spirit:choice>
+ <spirit:choice>
+ <spirit:name>choice_list_a9bdfce0</spirit:name>
+ <spirit:enumeration>LOW</spirit:enumeration>
+ <spirit:enumeration>HIGH</spirit:enumeration>
+ <spirit:enumeration>OPTIMIZED</spirit:enumeration>
+ </spirit:choice>
+ <spirit:choice>
+ <spirit:name>choice_list_ac75ef1e</spirit:name>
+ <spirit:enumeration>Custom</spirit:enumeration>
+ </spirit:choice>
+ <spirit:choice>
+ <spirit:name>choice_list_b9d38208</spirit:name>
+ <spirit:enumeration>CLKFBOUT</spirit:enumeration>
+ <spirit:enumeration>CLKOUT0</spirit:enumeration>
+ </spirit:choice>
+ <spirit:choice>
+ <spirit:name>choice_list_e099fe6c</spirit:name>
+ <spirit:enumeration>MMCM</spirit:enumeration>
+ <spirit:enumeration>PLL</spirit:enumeration>
+ </spirit:choice>
+ <spirit:choice>
+ <spirit:name>choice_pairs_035ca1c3</spirit:name>
+ <spirit:enumeration spirit:text="SYSTEM SYNCHRONOUS">SYSTEM_SYNCHRONOUS</spirit:enumeration>
+ <spirit:enumeration spirit:text="SOURCE SYNCHRONOUS">SOURCE_SYNCHRONOUS</spirit:enumeration>
+ <spirit:enumeration spirit:text="INTERNAL">INTERNAL</spirit:enumeration>
+ <spirit:enumeration spirit:text="EXTERNAL">EXTERNAL</spirit:enumeration>
+ </spirit:choice>
+ <spirit:choice>
+ <spirit:name>choice_pairs_0920eb1b</spirit:name>
+ <spirit:enumeration spirit:text="Custom">Custom</spirit:enumeration>
+ <spirit:enumeration spirit:text="sys diff clock">sys_diff_clock</spirit:enumeration>
+ </spirit:choice>
+ <spirit:choice>
+ <spirit:name>choice_pairs_11d71346</spirit:name>
+ <spirit:enumeration spirit:text="Single ended clock capable pin">Single_ended_clock_capable_pin</spirit:enumeration>
+ <spirit:enumeration spirit:text="Differential clock capable pin">Differential_clock_capable_pin</spirit:enumeration>
+ <spirit:enumeration spirit:text="Global buffer">Global_buffer</spirit:enumeration>
+ <spirit:enumeration spirit:text="No buffer">No_buffer</spirit:enumeration>
+ </spirit:choice>
+ <spirit:choice>
+ <spirit:name>choice_pairs_15c806d5</spirit:name>
+ <spirit:enumeration spirit:text="Automatic Control On-Chip">FDBK_AUTO</spirit:enumeration>
+ <spirit:enumeration spirit:text="Automatic Control Off-Chip">FDBK_AUTO_OFFCHIP</spirit:enumeration>
+ <spirit:enumeration spirit:text="User-Controlled On-Chip">FDBK_ONCHIP</spirit:enumeration>
+ <spirit:enumeration spirit:text="User-Controlled Off-Chip">FDBK_OFFCHIP</spirit:enumeration>
+ </spirit:choice>
+ <spirit:choice>
+ <spirit:name>choice_pairs_340369e0</spirit:name>
+ <spirit:enumeration spirit:text="Custom">Custom</spirit:enumeration>
+ <spirit:enumeration spirit:text="sys clock">sys_clock</spirit:enumeration>
+ <spirit:enumeration spirit:text="sys diff clock">sys_diff_clock</spirit:enumeration>
+ </spirit:choice>
+ <spirit:choice>
+ <spirit:name>choice_pairs_3c2d3ec7</spirit:name>
+ <spirit:enumeration spirit:text="Single-ended">SINGLE</spirit:enumeration>
+ <spirit:enumeration spirit:text="Differential">DIFF</spirit:enumeration>
+ </spirit:choice>
+ <spirit:choice>
+ <spirit:name>choice_pairs_502d9f23</spirit:name>
+ <spirit:enumeration spirit:text="ZHOLD">ZHOLD</spirit:enumeration>
+ <spirit:enumeration spirit:text="EXTERNAL">EXTERNAL</spirit:enumeration>
+ <spirit:enumeration spirit:text="INTERNAL">INTERNAL</spirit:enumeration>
+ <spirit:enumeration spirit:text="BUF IN">BUF_IN</spirit:enumeration>
+ </spirit:choice>
+ <spirit:choice>
+ <spirit:name>choice_pairs_66e4c81f</spirit:name>
+ <spirit:enumeration spirit:text="BUFG">BUFG</spirit:enumeration>
+ <spirit:enumeration spirit:text="BUFH">BUFH</spirit:enumeration>
+ <spirit:enumeration spirit:text="BUFGCE">BUFGCE</spirit:enumeration>
+ <spirit:enumeration spirit:text="BUFHCE">BUFHCE</spirit:enumeration>
+ <spirit:enumeration spirit:text="No buffer">No_buffer</spirit:enumeration>
+ </spirit:choice>
+ <spirit:choice>
+ <spirit:name>choice_pairs_77d3d587</spirit:name>
+ <spirit:enumeration spirit:text="MMCM">MMCM</spirit:enumeration>
+ <spirit:enumeration spirit:text="PLL">PLL</spirit:enumeration>
+ <spirit:enumeration spirit:text="BUFGCE DIV">BUFGCE_DIV</spirit:enumeration>
+ </spirit:choice>
+ <spirit:choice>
+ <spirit:name>choice_pairs_8b28f1f7</spirit:name>
+ <spirit:enumeration spirit:text="AXI4Lite">Enable_AXI</spirit:enumeration>
+ <spirit:enumeration spirit:text="DRP">Enable_DRP</spirit:enumeration>
+ </spirit:choice>
+ <spirit:choice>
+ <spirit:name>choice_pairs_8eea9b32</spirit:name>
+ <spirit:enumeration spirit:text="Units MHz">Units_MHz</spirit:enumeration>
+ <spirit:enumeration spirit:text="Units ns">Units_ns</spirit:enumeration>
+ </spirit:choice>
+ <spirit:choice>
+ <spirit:name>choice_pairs_a4fbc00c</spirit:name>
+ <spirit:enumeration spirit:text="Active High">ACTIVE_HIGH</spirit:enumeration>
+ <spirit:enumeration spirit:text="Active Low">ACTIVE_LOW</spirit:enumeration>
+ </spirit:choice>
+ <spirit:choice>
+ <spirit:name>choice_pairs_a8642b4c</spirit:name>
+ <spirit:enumeration spirit:text="Balanced">No_Jitter</spirit:enumeration>
+ <spirit:enumeration spirit:text="Minimize Output Jitter">Min_O_Jitter</spirit:enumeration>
+ <spirit:enumeration spirit:text="Maximize Input Jitter filtering">Max_I_Jitter</spirit:enumeration>
+ </spirit:choice>
+ <spirit:choice>
+ <spirit:name>choice_pairs_c5ef7212</spirit:name>
+ <spirit:enumeration spirit:text="Units UI">Units_UI</spirit:enumeration>
+ <spirit:enumeration spirit:text="Units ps">Units_ps</spirit:enumeration>
+ </spirit:choice>
+ <spirit:choice>
+ <spirit:name>choice_pairs_e1c87518</spirit:name>
+ <spirit:enumeration spirit:text="Primary Clock">REL_PRIMARY</spirit:enumeration>
+ <spirit:enumeration spirit:text="Secondary Clock">REL_SECONDARY</spirit:enumeration>
+ </spirit:choice>
+ <spirit:choice>
+ <spirit:name>choice_pairs_f4e10086</spirit:name>
+ <spirit:enumeration spirit:text="CENTER HIGH">CENTER_HIGH</spirit:enumeration>
+ <spirit:enumeration spirit:text="CENTER LOW">CENTER_LOW</spirit:enumeration>
+ <spirit:enumeration spirit:text="DOWN HIGH">DOWN_HIGH</spirit:enumeration>
+ <spirit:enumeration spirit:text="DOWN LOW">DOWN_LOW</spirit:enumeration>
+ </spirit:choice>
+ <spirit:choice>
+ <spirit:name>choice_pairs_f669c2f5</spirit:name>
+ <spirit:enumeration spirit:text="Frequency">frequency</spirit:enumeration>
+ <spirit:enumeration spirit:text="Time">Time</spirit:enumeration>
+ </spirit:choice>
+ </spirit:choices>
+ <spirit:fileSets>
+ <spirit:fileSet>
+ <spirit:name>xilinx_vhdlinstantiationtemplate_view_fileset</spirit:name>
+ <spirit:file>
+ <spirit:name>clk_wiz_1.vho</spirit:name>
+ <spirit:userFileType>vhdlTemplate</spirit:userFileType>
+ </spirit:file>
+ </spirit:fileSet>
+ <spirit:fileSet>
+ <spirit:name>xilinx_anylanguagesynthesis_view_fileset</spirit:name>
+ <spirit:file>
+ <spirit:name>clk_wiz_1.xdc</spirit:name>
+ <spirit:userFileType>xdc</spirit:userFileType>
+ <spirit:define>
+ <spirit:name>processing_order</spirit:name>
+ <spirit:value>early</spirit:value>
+ </spirit:define>
+ </spirit:file>
+ <spirit:file>
+ <spirit:name>clk_wiz_1_ooc.xdc</spirit:name>
+ <spirit:userFileType>xdc</spirit:userFileType>
+ <spirit:userFileType>USED_IN_implementation</spirit:userFileType>
+ <spirit:userFileType>USED_IN_out_of_context</spirit:userFileType>
+ <spirit:userFileType>USED_IN_synthesis</spirit:userFileType>
+ </spirit:file>
+ <spirit:file>
+ <spirit:name>mmcm_pll_drp_func_7s_mmcm.vh</spirit:name>
+ <spirit:fileType>verilogSource</spirit:fileType>
+ <spirit:isIncludeFile>true</spirit:isIncludeFile>
+ <spirit:logicalName>clk_wiz_v6_0_11</spirit:logicalName>
+ </spirit:file>
+ <spirit:file>
+ <spirit:name>mmcm_pll_drp_func_7s_pll.vh</spirit:name>
+ <spirit:fileType>verilogSource</spirit:fileType>
+ <spirit:isIncludeFile>true</spirit:isIncludeFile>
+ <spirit:logicalName>clk_wiz_v6_0_11</spirit:logicalName>
+ </spirit:file>
+ <spirit:file>
+ <spirit:name>mmcm_pll_drp_func_us_mmcm.vh</spirit:name>
+ <spirit:fileType>verilogSource</spirit:fileType>
+ <spirit:isIncludeFile>true</spirit:isIncludeFile>
+ <spirit:logicalName>clk_wiz_v6_0_11</spirit:logicalName>
+ </spirit:file>
+ <spirit:file>
+ <spirit:name>mmcm_pll_drp_func_us_pll.vh</spirit:name>
+ <spirit:fileType>verilogSource</spirit:fileType>
+ <spirit:isIncludeFile>true</spirit:isIncludeFile>
+ <spirit:logicalName>clk_wiz_v6_0_11</spirit:logicalName>
+ </spirit:file>
+ <spirit:file>
+ <spirit:name>mmcm_pll_drp_func_us_plus_pll.vh</spirit:name>
+ <spirit:fileType>verilogSource</spirit:fileType>
+ <spirit:isIncludeFile>true</spirit:isIncludeFile>
+ <spirit:logicalName>clk_wiz_v6_0_11</spirit:logicalName>
+ </spirit:file>
+ <spirit:file>
+ <spirit:name>mmcm_pll_drp_func_us_plus_mmcm.vh</spirit:name>
+ <spirit:fileType>verilogSource</spirit:fileType>
+ <spirit:isIncludeFile>true</spirit:isIncludeFile>
+ <spirit:logicalName>clk_wiz_v6_0_11</spirit:logicalName>
+ </spirit:file>
+ <spirit:file>
+ <spirit:name>clk_wiz_1_clk_wiz.v</spirit:name>
+ <spirit:fileType>verilogSource</spirit:fileType>
+ </spirit:file>
+ </spirit:fileSet>
+ <spirit:fileSet>
+ <spirit:name>xilinx_anylanguagesynthesiswrapper_view_fileset</spirit:name>
+ <spirit:file>
+ <spirit:name>clk_wiz_1.v</spirit:name>
+ <spirit:fileType>verilogSource</spirit:fileType>
+ </spirit:file>
+ </spirit:fileSet>
+ <spirit:fileSet>
+ <spirit:name>xilinx_anylanguagebehavioralsimulation_view_fileset</spirit:name>
+ <spirit:file>
+ <spirit:name>mmcm_pll_drp_func_7s_mmcm.vh</spirit:name>
+ <spirit:fileType>verilogSource</spirit:fileType>
+ <spirit:userFileType>USED_IN_ipstatic</spirit:userFileType>
+ <spirit:isIncludeFile>true</spirit:isIncludeFile>
+ <spirit:logicalName>clk_wiz_v6_0_11</spirit:logicalName>
+ </spirit:file>
+ <spirit:file>
+ <spirit:name>mmcm_pll_drp_func_7s_pll.vh</spirit:name>
+ <spirit:fileType>verilogSource</spirit:fileType>
+ <spirit:userFileType>USED_IN_ipstatic</spirit:userFileType>
+ <spirit:isIncludeFile>true</spirit:isIncludeFile>
+ <spirit:logicalName>clk_wiz_v6_0_11</spirit:logicalName>
+ </spirit:file>
+ <spirit:file>
+ <spirit:name>mmcm_pll_drp_func_us_mmcm.vh</spirit:name>
+ <spirit:fileType>verilogSource</spirit:fileType>
+ <spirit:userFileType>USED_IN_ipstatic</spirit:userFileType>
+ <spirit:isIncludeFile>true</spirit:isIncludeFile>
+ <spirit:logicalName>clk_wiz_v6_0_11</spirit:logicalName>
+ </spirit:file>
+ <spirit:file>
+ <spirit:name>mmcm_pll_drp_func_us_pll.vh</spirit:name>
+ <spirit:fileType>verilogSource</spirit:fileType>
+ <spirit:userFileType>USED_IN_ipstatic</spirit:userFileType>
+ <spirit:isIncludeFile>true</spirit:isIncludeFile>
+ <spirit:logicalName>clk_wiz_v6_0_11</spirit:logicalName>
+ </spirit:file>
+ <spirit:file>
+ <spirit:name>mmcm_pll_drp_func_us_plus_pll.vh</spirit:name>
+ <spirit:fileType>verilogSource</spirit:fileType>
+ <spirit:userFileType>USED_IN_ipstatic</spirit:userFileType>
+ <spirit:isIncludeFile>true</spirit:isIncludeFile>
+ <spirit:logicalName>clk_wiz_v6_0_11</spirit:logicalName>
+ </spirit:file>
+ <spirit:file>
+ <spirit:name>mmcm_pll_drp_func_us_plus_mmcm.vh</spirit:name>
+ <spirit:fileType>verilogSource</spirit:fileType>
+ <spirit:userFileType>USED_IN_ipstatic</spirit:userFileType>
+ <spirit:isIncludeFile>true</spirit:isIncludeFile>
+ <spirit:logicalName>clk_wiz_v6_0_11</spirit:logicalName>
+ </spirit:file>
+ <spirit:file>
+ <spirit:name>clk_wiz_1_clk_wiz.v</spirit:name>
+ <spirit:fileType>verilogSource</spirit:fileType>
+ </spirit:file>
+ </spirit:fileSet>
+ <spirit:fileSet>
+ <spirit:name>xilinx_anylanguagesimulationwrapper_view_fileset</spirit:name>
+ <spirit:file>
+ <spirit:name>clk_wiz_1.v</spirit:name>
+ <spirit:fileType>verilogSource</spirit:fileType>
+ </spirit:file>
+ </spirit:fileSet>
+ <spirit:fileSet>
+ <spirit:name>xilinx_implementation_view_fileset</spirit:name>
+ <spirit:file>
+ <spirit:name>clk_wiz_1_board.xdc</spirit:name>
+ <spirit:userFileType>xdc</spirit:userFileType>
+ <spirit:userFileType>USED_IN_board</spirit:userFileType>
+ <spirit:userFileType>USED_IN_implementation</spirit:userFileType>
+ <spirit:userFileType>USED_IN_synthesis</spirit:userFileType>
+ </spirit:file>
+ </spirit:fileSet>
+ <spirit:fileSet>
+ <spirit:name>xilinx_versioninformation_view_fileset</spirit:name>
+ <spirit:file>
+ <spirit:name>doc/clk_wiz_v6_0_changelog.txt</spirit:name>
+ <spirit:userFileType>text</spirit:userFileType>
+ </spirit:file>
+ </spirit:fileSet>
+ </spirit:fileSets>
+ <spirit:description>The Clocking Wizard creates an HDL file (Verilog or VHDL) that contains a clocking circuit customized to the user's clocking requirements.</spirit:description>
+ <spirit:parameters>
+ <spirit:parameter>
+ <spirit:name>Component_Name</spirit:name>
+ <spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.Component_Name" spirit:order="1">clk_wiz_1</spirit:value>
+ </spirit:parameter>
+ <spirit:parameter>
+ <spirit:name>USER_CLK_FREQ0</spirit:name>
+ <spirit:displayName>User Frequency(MHz)</spirit:displayName>
+ <spirit:value spirit:format="float" spirit:resolve="user" spirit:id="PARAM_VALUE.USER_CLK_FREQ0" spirit:order="15200" spirit:minimum="1" spirit:maximum="300">100.0</spirit:value>
+ </spirit:parameter>
+ <spirit:parameter>
+ <spirit:name>USER_CLK_FREQ1</spirit:name>
+ <spirit:displayName>User Frequency(MHz)</spirit:displayName>
+ <spirit:value spirit:format="float" spirit:resolve="user" spirit:id="PARAM_VALUE.USER_CLK_FREQ1" spirit:order="15200" spirit:minimum="1" spirit:maximum="300">100.0</spirit:value>
+ </spirit:parameter>
+ <spirit:parameter>
+ <spirit:name>USER_CLK_FREQ2</spirit:name>
+ <spirit:displayName>User Frequency(MHz)</spirit:displayName>
+ <spirit:value spirit:format="float" spirit:resolve="user" spirit:id="PARAM_VALUE.USER_CLK_FREQ2" spirit:order="15200" spirit:minimum="1" spirit:maximum="300">100.0</spirit:value>
+ </spirit:parameter>
+ <spirit:parameter>
+ <spirit:name>USER_CLK_FREQ3</spirit:name>
+ <spirit:displayName>User Frequency(MHz)</spirit:displayName>
+ <spirit:value spirit:format="float" spirit:resolve="user" spirit:id="PARAM_VALUE.USER_CLK_FREQ3" spirit:order="15200" spirit:minimum="1" spirit:maximum="300">100.0</spirit:value>
+ </spirit:parameter>
+ <spirit:parameter>
+ <spirit:name>ENABLE_CLOCK_MONITOR</spirit:name>
+ <spirit:displayName>Enable Clock Monitoring</spirit:displayName>
+ <spirit:value spirit:format="bool" spirit:resolve="user" spirit:id="PARAM_VALUE.ENABLE_CLOCK_MONITOR" spirit:order="10.1">false</spirit:value>
+ </spirit:parameter>
+ <spirit:parameter>
+ <spirit:name>OPTIMIZE_CLOCKING_STRUCTURE_EN</spirit:name>
+ <spirit:displayName>Optimize Clocking Structure</spirit:displayName>
+ <spirit:value spirit:format="bool" spirit:resolve="user" spirit:id="PARAM_VALUE.OPTIMIZE_CLOCKING_STRUCTURE_EN" spirit:order="10.1">false</spirit:value>
+ </spirit:parameter>
+ <spirit:parameter>
+ <spirit:name>ENABLE_USER_CLOCK0</spirit:name>
+ <spirit:displayName>User Clock</spirit:displayName>
+ <spirit:value spirit:format="bool" spirit:resolve="user" spirit:id="PARAM_VALUE.ENABLE_USER_CLOCK0" spirit:order="1090">false</spirit:value>
+ </spirit:parameter>
+ <spirit:parameter>
+ <spirit:name>ENABLE_USER_CLOCK1</spirit:name>
+ <spirit:displayName>User Clock</spirit:displayName>
+ <spirit:value spirit:format="bool" spirit:resolve="user" spirit:id="PARAM_VALUE.ENABLE_USER_CLOCK1" spirit:order="1090">false</spirit:value>
+ </spirit:parameter>
+ <spirit:parameter>
+ <spirit:name>ENABLE_USER_CLOCK2</spirit:name>
+ <spirit:displayName>User Clock</spirit:displayName>
+ <spirit:value spirit:format="bool" spirit:resolve="user" spirit:id="PARAM_VALUE.ENABLE_USER_CLOCK2" spirit:order="1090">false</spirit:value>
+ </spirit:parameter>
+ <spirit:parameter>
+ <spirit:name>ENABLE_USER_CLOCK3</spirit:name>
+ <spirit:displayName>User Clock</spirit:displayName>
+ <spirit:value spirit:format="bool" spirit:resolve="user" spirit:id="PARAM_VALUE.ENABLE_USER_CLOCK3" spirit:order="1090">false</spirit:value>
+ </spirit:parameter>
+ <spirit:parameter>
+ <spirit:name>Enable_PLL0</spirit:name>
+ <spirit:displayName>User Clock</spirit:displayName>
+ <spirit:value spirit:format="bool" spirit:resolve="user" spirit:id="PARAM_VALUE.Enable_PLL0" spirit:order="1090">false</spirit:value>
+ </spirit:parameter>
+ <spirit:parameter>
+ <spirit:name>Enable_PLL1</spirit:name>
+ <spirit:displayName>User Clock</spirit:displayName>
+ <spirit:value spirit:format="bool" spirit:resolve="user" spirit:id="PARAM_VALUE.Enable_PLL1" spirit:order="1090">false</spirit:value>
+ </spirit:parameter>
+ <spirit:parameter>
+ <spirit:name>REF_CLK_FREQ</spirit:name>
+ <spirit:displayName>Reference Frequency(MHz)</spirit:displayName>
+ <spirit:value spirit:format="float" spirit:resolve="user" spirit:id="PARAM_VALUE.REF_CLK_FREQ" spirit:order="15300" spirit:minimum="1" spirit:maximum="300">100.0</spirit:value>
+ </spirit:parameter>
+ <spirit:parameter>
+ <spirit:name>PRECISION</spirit:name>
+ <spirit:displayName>Tolerance(MHz)</spirit:displayName>
+ <spirit:value spirit:format="float" spirit:resolve="user" spirit:id="PARAM_VALUE.PRECISION" spirit:order="15400" spirit:minimum="1" spirit:maximum="100">1</spirit:value>
+ </spirit:parameter>
+ <spirit:parameter>
+ <spirit:name>PRIMITIVE</spirit:name>
+ <spirit:displayName>Primitive</spirit:displayName>
+ <spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.PRIMITIVE" spirit:choiceRef="choice_list_e099fe6c" spirit:order="2">MMCM</spirit:value>
+ </spirit:parameter>
+ <spirit:parameter>
+ <spirit:name>PRIMTYPE_SEL</spirit:name>
+ <spirit:displayName>Primtype Sel</spirit:displayName>
+ <spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.PRIMTYPE_SEL" spirit:order="3">mmcm_adv</spirit:value>
+ </spirit:parameter>
+ <spirit:parameter>
+ <spirit:name>CLOCK_MGR_TYPE</spirit:name>
+ <spirit:displayName>Clock Mgr Type</spirit:displayName>
+ <spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.CLOCK_MGR_TYPE" spirit:order="410">auto</spirit:value>
+ </spirit:parameter>
+ <spirit:parameter>
+ <spirit:name>USE_FREQ_SYNTH</spirit:name>
+ <spirit:value spirit:format="bool" spirit:resolve="user" spirit:id="PARAM_VALUE.USE_FREQ_SYNTH" spirit:order="6" spirit:configGroups="0 NoDisplay">true</spirit:value>
+ </spirit:parameter>
+ <spirit:parameter>
+ <spirit:name>USE_SPREAD_SPECTRUM</spirit:name>
+ <spirit:value spirit:format="bool" spirit:resolve="user" spirit:id="PARAM_VALUE.USE_SPREAD_SPECTRUM" spirit:order="7" spirit:configGroups="0 NoDisplay">false</spirit:value>
+ </spirit:parameter>
+ <spirit:parameter>
+ <spirit:name>USE_PHASE_ALIGNMENT</spirit:name>
+ <spirit:value spirit:format="bool" spirit:resolve="user" spirit:id="PARAM_VALUE.USE_PHASE_ALIGNMENT" spirit:order="8" spirit:configGroups="0 NoDisplay">true</spirit:value>
+ </spirit:parameter>
+ <spirit:parameter>
+ <spirit:name>USE_MIN_POWER</spirit:name>
+ <spirit:value spirit:format="bool" spirit:resolve="user" spirit:id="PARAM_VALUE.USE_MIN_POWER" spirit:order="9" spirit:configGroups="0 NoDisplay">false</spirit:value>
+ </spirit:parameter>
+ <spirit:parameter>
+ <spirit:name>USE_DYN_PHASE_SHIFT</spirit:name>
+ <spirit:value spirit:format="bool" spirit:resolve="user" spirit:id="PARAM_VALUE.USE_DYN_PHASE_SHIFT" spirit:order="10" spirit:configGroups="0 NoDisplay">false</spirit:value>
+ </spirit:parameter>
+ <spirit:parameter>
+ <spirit:name>USE_DYN_RECONFIG</spirit:name>
+ <spirit:value spirit:format="bool" spirit:resolve="user" spirit:id="PARAM_VALUE.USE_DYN_RECONFIG" spirit:order="11" spirit:configGroups="0 NoDisplay">false</spirit:value>
+ </spirit:parameter>
+ <spirit:parameter>
+ <spirit:name>JITTER_SEL</spirit:name>
+ <spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.JITTER_SEL" spirit:choiceRef="choice_pairs_a8642b4c" spirit:order="13" spirit:configGroups="0 NoDisplay">No_Jitter</spirit:value>
+ </spirit:parameter>
+ <spirit:parameter>
+ <spirit:name>PRIM_IN_FREQ</spirit:name>
+ <spirit:value spirit:format="float" spirit:resolve="user" spirit:id="PARAM_VALUE.PRIM_IN_FREQ" spirit:order="14.401" spirit:configGroups="0 NoDisplay">100.000</spirit:value>
+ </spirit:parameter>
+ <spirit:parameter>
+ <spirit:name>PRIM_IN_TIMEPERIOD</spirit:name>
+ <spirit:value spirit:format="float" spirit:resolve="user" spirit:id="PARAM_VALUE.PRIM_IN_TIMEPERIOD" spirit:order="14.9" spirit:configGroups="0 NoDisplay">10.000</spirit:value>
+ </spirit:parameter>
+ <spirit:parameter>
+ <spirit:name>IN_FREQ_UNITS</spirit:name>
+ <spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.IN_FREQ_UNITS" spirit:choiceRef="choice_pairs_8eea9b32" spirit:order="15" spirit:configGroups="0 NoDisplay">Units_MHz</spirit:value>
+ </spirit:parameter>
+ <spirit:parameter>
+ <spirit:name>PHASESHIFT_MODE</spirit:name>
+ <spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.PHASESHIFT_MODE" spirit:choiceRef="choice_list_1d3de01d" spirit:order="116" spirit:configGroups="0 NoDisplay">WAVEFORM</spirit:value>
+ </spirit:parameter>
+ <spirit:parameter>
+ <spirit:name>IN_JITTER_UNITS</spirit:name>
+ <spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.IN_JITTER_UNITS" spirit:choiceRef="choice_pairs_c5ef7212" spirit:order="16" spirit:configGroups="0 NoDisplay">Units_UI</spirit:value>
+ </spirit:parameter>
+ <spirit:parameter>
+ <spirit:name>RELATIVE_INCLK</spirit:name>
+ <spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.RELATIVE_INCLK" spirit:choiceRef="choice_pairs_e1c87518" spirit:order="17" spirit:configGroups="0 NoDisplay">REL_PRIMARY</spirit:value>
+ </spirit:parameter>
+ <spirit:parameter>
+ <spirit:name>USE_INCLK_SWITCHOVER</spirit:name>
+ <spirit:value spirit:format="bool" spirit:resolve="user" spirit:id="PARAM_VALUE.USE_INCLK_SWITCHOVER" spirit:order="13.9" spirit:configGroups="0 NoDisplay">false</spirit:value>
+ </spirit:parameter>
+ <spirit:parameter>
+ <spirit:name>SECONDARY_IN_FREQ</spirit:name>
+ <spirit:value spirit:format="float" spirit:resolve="user" spirit:id="PARAM_VALUE.SECONDARY_IN_FREQ" spirit:order="21.3" spirit:configGroups="0 NoDisplay">100.000</spirit:value>
+ </spirit:parameter>
+ <spirit:parameter>
+ <spirit:name>SECONDARY_IN_TIMEPERIOD</spirit:name>
+ <spirit:value spirit:format="float" spirit:resolve="user" spirit:id="PARAM_VALUE.SECONDARY_IN_TIMEPERIOD" spirit:order="21.299" spirit:configGroups="0 NoDisplay">10.000</spirit:value>
+ </spirit:parameter>
+ <spirit:parameter>
+ <spirit:name>SECONDARY_PORT</spirit:name>
+ <spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.SECONDARY_PORT" spirit:order="20" spirit:configGroups="0 NoDisplay">clk_in2</spirit:value>
+ </spirit:parameter>
+ <spirit:parameter>
+ <spirit:name>SECONDARY_SOURCE</spirit:name>
+ <spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.SECONDARY_SOURCE" spirit:choiceRef="choice_pairs_11d71346" spirit:order="21" spirit:configGroups="0 NoDisplay">Single_ended_clock_capable_pin</spirit:value>
+ </spirit:parameter>
+ <spirit:parameter>
+ <spirit:name>JITTER_OPTIONS</spirit:name>
+ <spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.JITTER_OPTIONS" spirit:choiceRef="choice_list_876bfc32" spirit:order="22" spirit:configGroups="0 NoDisplay">UI</spirit:value>
+ </spirit:parameter>
+ <spirit:parameter>
+ <spirit:name>CLKIN1_UI_JITTER</spirit:name>
+ <spirit:value spirit:format="float" spirit:resolve="user" spirit:id="PARAM_VALUE.CLKIN1_UI_JITTER" spirit:order="23" spirit:configGroups="0 NoDisplay">0.010</spirit:value>
+ </spirit:parameter>
+ <spirit:parameter>
+ <spirit:name>CLKIN2_UI_JITTER</spirit:name>
+ <spirit:value spirit:format="float" spirit:resolve="user" spirit:id="PARAM_VALUE.CLKIN2_UI_JITTER" spirit:order="24" spirit:configGroups="0 NoDisplay">0.010</spirit:value>
+ </spirit:parameter>
+ <spirit:parameter>
+ <spirit:name>PRIM_IN_JITTER</spirit:name>
+ <spirit:value spirit:format="float" spirit:resolve="user" spirit:id="PARAM_VALUE.PRIM_IN_JITTER" spirit:order="25" spirit:configGroups="0 NoDisplay">0.010</spirit:value>
+ </spirit:parameter>
+ <spirit:parameter>
+ <spirit:name>SECONDARY_IN_JITTER</spirit:name>
+ <spirit:value spirit:format="float" spirit:resolve="user" spirit:id="PARAM_VALUE.SECONDARY_IN_JITTER" spirit:order="26" spirit:configGroups="0 NoDisplay">0.010</spirit:value>
+ </spirit:parameter>
+ <spirit:parameter>
+ <spirit:name>CLKIN1_JITTER_PS</spirit:name>
+ <spirit:value spirit:format="float" spirit:resolve="user" spirit:id="PARAM_VALUE.CLKIN1_JITTER_PS" spirit:order="27" spirit:configGroups="0 NoDisplay">100.0</spirit:value>
+ </spirit:parameter>
+ <spirit:parameter>
+ <spirit:name>CLKIN2_JITTER_PS</spirit:name>
+ <spirit:value spirit:format="float" spirit:resolve="user" spirit:id="PARAM_VALUE.CLKIN2_JITTER_PS" spirit:order="28" spirit:configGroups="0 NoDisplay">100.0</spirit:value>
+ </spirit:parameter>
+ <spirit:parameter>
+ <spirit:name>CLKOUT1_USED</spirit:name>
+ <spirit:value spirit:format="bool" spirit:resolve="user" spirit:id="PARAM_VALUE.CLKOUT1_USED" spirit:order="4" spirit:configGroups="0 NoDisplay">true</spirit:value>
+ </spirit:parameter>
+ <spirit:parameter>
+ <spirit:name>CLKOUT2_USED</spirit:name>
+ <spirit:value spirit:format="bool" spirit:resolve="user" spirit:id="PARAM_VALUE.CLKOUT2_USED" spirit:order="29" spirit:configGroups="0 NoDisplay">false</spirit:value>
+ </spirit:parameter>
+ <spirit:parameter>
+ <spirit:name>CLKOUT3_USED</spirit:name>
+ <spirit:value spirit:format="bool" spirit:resolve="user" spirit:id="PARAM_VALUE.CLKOUT3_USED" spirit:order="30" spirit:configGroups="0 NoDisplay">false</spirit:value>
+ </spirit:parameter>
+ <spirit:parameter>
+ <spirit:name>CLKOUT4_USED</spirit:name>
+ <spirit:value spirit:format="bool" spirit:resolve="user" spirit:id="PARAM_VALUE.CLKOUT4_USED" spirit:order="31" spirit:configGroups="0 NoDisplay">false</spirit:value>
+ </spirit:parameter>
+ <spirit:parameter>
+ <spirit:name>CLKOUT5_USED</spirit:name>
+ <spirit:value spirit:format="bool" spirit:resolve="user" spirit:id="PARAM_VALUE.CLKOUT5_USED" spirit:order="32" spirit:configGroups="0 NoDisplay">false</spirit:value>
+ </spirit:parameter>
+ <spirit:parameter>
+ <spirit:name>CLKOUT6_USED</spirit:name>
+ <spirit:value spirit:format="bool" spirit:resolve="user" spirit:id="PARAM_VALUE.CLKOUT6_USED" spirit:order="33" spirit:configGroups="0 NoDisplay">false</spirit:value>
+ </spirit:parameter>
+ <spirit:parameter>
+ <spirit:name>CLKOUT7_USED</spirit:name>
+ <spirit:value spirit:format="bool" spirit:resolve="user" spirit:id="PARAM_VALUE.CLKOUT7_USED" spirit:order="34" spirit:configGroups="0 NoDisplay">false</spirit:value>
+ </spirit:parameter>
+ <spirit:parameter>
+ <spirit:name>NUM_OUT_CLKS</spirit:name>
+ <spirit:value spirit:format="long" spirit:resolve="user" spirit:id="PARAM_VALUE.NUM_OUT_CLKS" spirit:order="407" spirit:configGroups="0 NoDisplay" spirit:minimum="1" spirit:maximum="7" spirit:rangeType="long">1</spirit:value>
+ </spirit:parameter>
+ <spirit:parameter>
+ <spirit:name>CLK_OUT1_USE_FINE_PS_GUI</spirit:name>
+ <spirit:value spirit:format="bool" spirit:resolve="user" spirit:id="PARAM_VALUE.CLK_OUT1_USE_FINE_PS_GUI" spirit:order="36" spirit:configGroups="0 NoDisplay">false</spirit:value>
+ </spirit:parameter>
+ <spirit:parameter>
+ <spirit:name>CLK_OUT2_USE_FINE_PS_GUI</spirit:name>
+ <spirit:value spirit:format="bool" spirit:resolve="user" spirit:id="PARAM_VALUE.CLK_OUT2_USE_FINE_PS_GUI" spirit:order="37" spirit:configGroups="0 NoDisplay">false</spirit:value>
+ </spirit:parameter>
+ <spirit:parameter>
+ <spirit:name>CLK_OUT3_USE_FINE_PS_GUI</spirit:name>
+ <spirit:value spirit:format="bool" spirit:resolve="user" spirit:id="PARAM_VALUE.CLK_OUT3_USE_FINE_PS_GUI" spirit:order="38" spirit:configGroups="0 NoDisplay">false</spirit:value>
+ </spirit:parameter>
+ <spirit:parameter>
+ <spirit:name>CLK_OUT4_USE_FINE_PS_GUI</spirit:name>
+ <spirit:value spirit:format="bool" spirit:resolve="user" spirit:id="PARAM_VALUE.CLK_OUT4_USE_FINE_PS_GUI" spirit:order="39" spirit:configGroups="0 NoDisplay">false</spirit:value>
+ </spirit:parameter>
+ <spirit:parameter>
+ <spirit:name>CLK_OUT5_USE_FINE_PS_GUI</spirit:name>
+ <spirit:value spirit:format="bool" spirit:resolve="user" spirit:id="PARAM_VALUE.CLK_OUT5_USE_FINE_PS_GUI" spirit:order="40" spirit:configGroups="0 NoDisplay">false</spirit:value>
+ </spirit:parameter>
+ <spirit:parameter>
+ <spirit:name>CLK_OUT6_USE_FINE_PS_GUI</spirit:name>
+ <spirit:value spirit:format="bool" spirit:resolve="user" spirit:id="PARAM_VALUE.CLK_OUT6_USE_FINE_PS_GUI" spirit:order="41" spirit:configGroups="0 NoDisplay">false</spirit:value>
+ </spirit:parameter>
+ <spirit:parameter>
+ <spirit:name>CLK_OUT7_USE_FINE_PS_GUI</spirit:name>
+ <spirit:value spirit:format="bool" spirit:resolve="user" spirit:id="PARAM_VALUE.CLK_OUT7_USE_FINE_PS_GUI" spirit:order="42" spirit:configGroups="0 NoDisplay">false</spirit:value>
+ </spirit:parameter>
+ <spirit:parameter>
+ <spirit:name>PRIMARY_PORT</spirit:name>
+ <spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.PRIMARY_PORT" spirit:order="43" spirit:configGroups="0 NoDisplay">clk_in1</spirit:value>
+ </spirit:parameter>
+ <spirit:parameter>
+ <spirit:name>CLK_OUT1_PORT</spirit:name>
+ <spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.CLK_OUT1_PORT" spirit:order="44" spirit:configGroups="0 NoDisplay">clk_out1</spirit:value>
+ </spirit:parameter>
+ <spirit:parameter>
+ <spirit:name>CLK_OUT2_PORT</spirit:name>
+ <spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.CLK_OUT2_PORT" spirit:order="45" spirit:configGroups="0 NoDisplay">clk_out2</spirit:value>
+ </spirit:parameter>
+ <spirit:parameter>
+ <spirit:name>CLK_OUT3_PORT</spirit:name>
+ <spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.CLK_OUT3_PORT" spirit:order="46" spirit:configGroups="0 NoDisplay">clk_out3</spirit:value>
+ </spirit:parameter>
+ <spirit:parameter>
+ <spirit:name>CLK_OUT4_PORT</spirit:name>
+ <spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.CLK_OUT4_PORT" spirit:order="47" spirit:configGroups="0 NoDisplay">clk_out4</spirit:value>
+ </spirit:parameter>
+ <spirit:parameter>
+ <spirit:name>CLK_OUT5_PORT</spirit:name>
+ <spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.CLK_OUT5_PORT" spirit:order="48" spirit:configGroups="0 NoDisplay">clk_out5</spirit:value>
+ </spirit:parameter>
+ <spirit:parameter>
+ <spirit:name>CLK_OUT6_PORT</spirit:name>
+ <spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.CLK_OUT6_PORT" spirit:order="49" spirit:configGroups="0 NoDisplay">clk_out6</spirit:value>
+ </spirit:parameter>
+ <spirit:parameter>
+ <spirit:name>CLK_OUT7_PORT</spirit:name>
+ <spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.CLK_OUT7_PORT" spirit:order="50" spirit:configGroups="0 NoDisplay">clk_out7</spirit:value>
+ </spirit:parameter>
+ <spirit:parameter>
+ <spirit:name>DADDR_PORT</spirit:name>
+ <spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.DADDR_PORT" spirit:order="51" spirit:configGroups="0 NoDisplay">daddr</spirit:value>
+ </spirit:parameter>
+ <spirit:parameter>
+ <spirit:name>DCLK_PORT</spirit:name>
+ <spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.DCLK_PORT" spirit:order="52" spirit:configGroups="0 NoDisplay">dclk</spirit:value>
+ </spirit:parameter>
+ <spirit:parameter>
+ <spirit:name>DRDY_PORT</spirit:name>
+ <spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.DRDY_PORT" spirit:order="53" spirit:configGroups="0 NoDisplay">drdy</spirit:value>
+ </spirit:parameter>
+ <spirit:parameter>
+ <spirit:name>DWE_PORT</spirit:name>
+ <spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.DWE_PORT" spirit:order="54" spirit:configGroups="0 NoDisplay">dwe</spirit:value>
+ </spirit:parameter>
+ <spirit:parameter>
+ <spirit:name>DIN_PORT</spirit:name>
+ <spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.DIN_PORT" spirit:order="55" spirit:configGroups="0 NoDisplay">din</spirit:value>
+ </spirit:parameter>
+ <spirit:parameter>
+ <spirit:name>DOUT_PORT</spirit:name>
+ <spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.DOUT_PORT" spirit:order="56" spirit:configGroups="0 NoDisplay">dout</spirit:value>
+ </spirit:parameter>
+ <spirit:parameter>
+ <spirit:name>DEN_PORT</spirit:name>
+ <spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.DEN_PORT" spirit:order="57" spirit:configGroups="0 NoDisplay">den</spirit:value>
+ </spirit:parameter>
+ <spirit:parameter>
+ <spirit:name>PSCLK_PORT</spirit:name>
+ <spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.PSCLK_PORT" spirit:order="58" spirit:configGroups="0 NoDisplay">psclk</spirit:value>
+ </spirit:parameter>
+ <spirit:parameter>
+ <spirit:name>PSEN_PORT</spirit:name>
+ <spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.PSEN_PORT" spirit:order="59" spirit:configGroups="0 NoDisplay">psen</spirit:value>
+ </spirit:parameter>
+ <spirit:parameter>
+ <spirit:name>PSINCDEC_PORT</spirit:name>
+ <spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.PSINCDEC_PORT" spirit:order="60" spirit:configGroups="0 NoDisplay">psincdec</spirit:value>
+ </spirit:parameter>
+ <spirit:parameter>
+ <spirit:name>PSDONE_PORT</spirit:name>
+ <spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.PSDONE_PORT" spirit:order="61" spirit:configGroups="0 NoDisplay">psdone</spirit:value>
+ </spirit:parameter>
+ <spirit:parameter>
+ <spirit:name>CLKOUT1_REQUESTED_OUT_FREQ</spirit:name>
+ <spirit:value spirit:format="float" spirit:resolve="user" spirit:id="PARAM_VALUE.CLKOUT1_REQUESTED_OUT_FREQ" spirit:order="62" spirit:configGroups="0 NoDisplay">25.000</spirit:value>
+ </spirit:parameter>
+ <spirit:parameter>
+ <spirit:name>CLKOUT1_REQUESTED_PHASE</spirit:name>
+ <spirit:value spirit:format="float" spirit:resolve="user" spirit:id="PARAM_VALUE.CLKOUT1_REQUESTED_PHASE" spirit:order="63" spirit:configGroups="0 NoDisplay">0.000</spirit:value>
+ </spirit:parameter>
+ <spirit:parameter>
+ <spirit:name>CLKOUT1_REQUESTED_DUTY_CYCLE</spirit:name>
+ <spirit:value spirit:format="float" spirit:resolve="user" spirit:id="PARAM_VALUE.CLKOUT1_REQUESTED_DUTY_CYCLE" spirit:order="64" spirit:configGroups="0 NoDisplay">50.000</spirit:value>
+ </spirit:parameter>
+ <spirit:parameter>
+ <spirit:name>CLKOUT2_REQUESTED_OUT_FREQ</spirit:name>
+ <spirit:value spirit:format="float" spirit:resolve="user" spirit:id="PARAM_VALUE.CLKOUT2_REQUESTED_OUT_FREQ" spirit:order="65" spirit:configGroups="0 NoDisplay">100.000</spirit:value>
+ </spirit:parameter>
+ <spirit:parameter>
+ <spirit:name>CLKOUT2_REQUESTED_PHASE</spirit:name>
+ <spirit:value spirit:format="float" spirit:resolve="user" spirit:id="PARAM_VALUE.CLKOUT2_REQUESTED_PHASE" spirit:order="66" spirit:configGroups="0 NoDisplay">0.000</spirit:value>
+ </spirit:parameter>
+ <spirit:parameter>
+ <spirit:name>CLKOUT2_REQUESTED_DUTY_CYCLE</spirit:name>
+ <spirit:value spirit:format="float" spirit:resolve="user" spirit:id="PARAM_VALUE.CLKOUT2_REQUESTED_DUTY_CYCLE" spirit:order="67" spirit:configGroups="0 NoDisplay">50.000</spirit:value>
+ </spirit:parameter>
+ <spirit:parameter>
+ <spirit:name>CLKOUT3_REQUESTED_OUT_FREQ</spirit:name>
+ <spirit:value spirit:format="float" spirit:resolve="user" spirit:id="PARAM_VALUE.CLKOUT3_REQUESTED_OUT_FREQ" spirit:order="68" spirit:configGroups="0 NoDisplay">100.000</spirit:value>
+ </spirit:parameter>
+ <spirit:parameter>
+ <spirit:name>CLKOUT3_REQUESTED_PHASE</spirit:name>
+ <spirit:value spirit:format="float" spirit:resolve="user" spirit:id="PARAM_VALUE.CLKOUT3_REQUESTED_PHASE" spirit:order="69" spirit:configGroups="0 NoDisplay">0.000</spirit:value>
+ </spirit:parameter>
+ <spirit:parameter>
+ <spirit:name>CLKOUT3_REQUESTED_DUTY_CYCLE</spirit:name>
+ <spirit:value spirit:format="float" spirit:resolve="user" spirit:id="PARAM_VALUE.CLKOUT3_REQUESTED_DUTY_CYCLE" spirit:order="70" spirit:configGroups="0 NoDisplay">50.000</spirit:value>
+ </spirit:parameter>
+ <spirit:parameter>
+ <spirit:name>CLKOUT4_REQUESTED_OUT_FREQ</spirit:name>
+ <spirit:value spirit:format="float" spirit:resolve="user" spirit:id="PARAM_VALUE.CLKOUT4_REQUESTED_OUT_FREQ" spirit:order="71" spirit:configGroups="0 NoDisplay">100.000</spirit:value>
+ </spirit:parameter>
+ <spirit:parameter>
+ <spirit:name>CLKOUT4_REQUESTED_PHASE</spirit:name>
+ <spirit:value spirit:format="float" spirit:resolve="user" spirit:id="PARAM_VALUE.CLKOUT4_REQUESTED_PHASE" spirit:order="72" spirit:configGroups="0 NoDisplay">0.000</spirit:value>
+ </spirit:parameter>
+ <spirit:parameter>
+ <spirit:name>CLKOUT4_REQUESTED_DUTY_CYCLE</spirit:name>
+ <spirit:value spirit:format="float" spirit:resolve="user" spirit:id="PARAM_VALUE.CLKOUT4_REQUESTED_DUTY_CYCLE" spirit:order="73" spirit:configGroups="0 NoDisplay">50.000</spirit:value>
+ </spirit:parameter>
+ <spirit:parameter>
+ <spirit:name>CLKOUT5_REQUESTED_OUT_FREQ</spirit:name>
+ <spirit:value spirit:format="float" spirit:resolve="user" spirit:id="PARAM_VALUE.CLKOUT5_REQUESTED_OUT_FREQ" spirit:order="74" spirit:configGroups="0 NoDisplay">100.000</spirit:value>
+ </spirit:parameter>
+ <spirit:parameter>
+ <spirit:name>CLKOUT5_REQUESTED_PHASE</spirit:name>
+ <spirit:value spirit:format="float" spirit:resolve="user" spirit:id="PARAM_VALUE.CLKOUT5_REQUESTED_PHASE" spirit:order="75" spirit:configGroups="0 NoDisplay">0.000</spirit:value>
+ </spirit:parameter>
+ <spirit:parameter>
+ <spirit:name>CLKOUT5_REQUESTED_DUTY_CYCLE</spirit:name>
+ <spirit:value spirit:format="float" spirit:resolve="user" spirit:id="PARAM_VALUE.CLKOUT5_REQUESTED_DUTY_CYCLE" spirit:order="76" spirit:configGroups="0 NoDisplay">50.000</spirit:value>
+ </spirit:parameter>
+ <spirit:parameter>
+ <spirit:name>CLKOUT6_REQUESTED_OUT_FREQ</spirit:name>
+ <spirit:value spirit:format="float" spirit:resolve="user" spirit:id="PARAM_VALUE.CLKOUT6_REQUESTED_OUT_FREQ" spirit:order="77" spirit:configGroups="0 NoDisplay">100.000</spirit:value>
+ </spirit:parameter>
+ <spirit:parameter>
+ <spirit:name>CLKOUT6_REQUESTED_PHASE</spirit:name>
+ <spirit:value spirit:format="float" spirit:resolve="user" spirit:id="PARAM_VALUE.CLKOUT6_REQUESTED_PHASE" spirit:order="78" spirit:configGroups="0 NoDisplay">0.000</spirit:value>
+ </spirit:parameter>
+ <spirit:parameter>
+ <spirit:name>CLKOUT6_REQUESTED_DUTY_CYCLE</spirit:name>
+ <spirit:value spirit:format="float" spirit:resolve="user" spirit:id="PARAM_VALUE.CLKOUT6_REQUESTED_DUTY_CYCLE" spirit:order="79" spirit:configGroups="0 NoDisplay">50.000</spirit:value>
+ </spirit:parameter>
+ <spirit:parameter>
+ <spirit:name>CLKOUT7_REQUESTED_OUT_FREQ</spirit:name>
+ <spirit:value spirit:format="float" spirit:resolve="user" spirit:id="PARAM_VALUE.CLKOUT7_REQUESTED_OUT_FREQ" spirit:order="80" spirit:configGroups="0 NoDisplay">100.000</spirit:value>
+ </spirit:parameter>
+ <spirit:parameter>
+ <spirit:name>CLKOUT7_REQUESTED_PHASE</spirit:name>
+ <spirit:value spirit:format="float" spirit:resolve="user" spirit:id="PARAM_VALUE.CLKOUT7_REQUESTED_PHASE" spirit:order="81" spirit:configGroups="0 NoDisplay">0.000</spirit:value>
+ </spirit:parameter>
+ <spirit:parameter>
+ <spirit:name>CLKOUT7_REQUESTED_DUTY_CYCLE</spirit:name>
+ <spirit:value spirit:format="float" spirit:resolve="user" spirit:id="PARAM_VALUE.CLKOUT7_REQUESTED_DUTY_CYCLE" spirit:order="82" spirit:configGroups="0 NoDisplay">50.000</spirit:value>
+ </spirit:parameter>
+ <spirit:parameter>
+ <spirit:name>USE_MAX_I_JITTER</spirit:name>
+ <spirit:value spirit:format="bool" spirit:resolve="user" spirit:id="PARAM_VALUE.USE_MAX_I_JITTER" spirit:order="83" spirit:configGroups="0 NoDisplay">false</spirit:value>
+ </spirit:parameter>
+ <spirit:parameter>
+ <spirit:name>USE_MIN_O_JITTER</spirit:name>
+ <spirit:value spirit:format="bool" spirit:resolve="user" spirit:id="PARAM_VALUE.USE_MIN_O_JITTER" spirit:order="84" spirit:configGroups="0 NoDisplay">false</spirit:value>
+ </spirit:parameter>
+ <spirit:parameter>
+ <spirit:name>CLKOUT1_MATCHED_ROUTING</spirit:name>
+ <spirit:value spirit:format="bool" spirit:resolve="user" spirit:id="PARAM_VALUE.CLKOUT1_MATCHED_ROUTING" spirit:order="984" spirit:configGroups="0 NoDisplay">false</spirit:value>
+ </spirit:parameter>
+ <spirit:parameter>
+ <spirit:name>CLKOUT2_MATCHED_ROUTING</spirit:name>
+ <spirit:value spirit:format="bool" spirit:resolve="user" spirit:id="PARAM_VALUE.CLKOUT2_MATCHED_ROUTING" spirit:order="985" spirit:configGroups="0 NoDisplay">false</spirit:value>
+ </spirit:parameter>
+ <spirit:parameter>
+ <spirit:name>CLKOUT3_MATCHED_ROUTING</spirit:name>
+ <spirit:value spirit:format="bool" spirit:resolve="user" spirit:id="PARAM_VALUE.CLKOUT3_MATCHED_ROUTING" spirit:order="986" spirit:configGroups="0 NoDisplay">false</spirit:value>
+ </spirit:parameter>
+ <spirit:parameter>
+ <spirit:name>CLKOUT4_MATCHED_ROUTING</spirit:name>
+ <spirit:value spirit:format="bool" spirit:resolve="user" spirit:id="PARAM_VALUE.CLKOUT4_MATCHED_ROUTING" spirit:order="987" spirit:configGroups="0 NoDisplay">false</spirit:value>
+ </spirit:parameter>
+ <spirit:parameter>
+ <spirit:name>CLKOUT5_MATCHED_ROUTING</spirit:name>
+ <spirit:value spirit:format="bool" spirit:resolve="user" spirit:id="PARAM_VALUE.CLKOUT5_MATCHED_ROUTING" spirit:order="988" spirit:configGroups="0 NoDisplay">false</spirit:value>
+ </spirit:parameter>
+ <spirit:parameter>
+ <spirit:name>CLKOUT6_MATCHED_ROUTING</spirit:name>
+ <spirit:value spirit:format="bool" spirit:resolve="user" spirit:id="PARAM_VALUE.CLKOUT6_MATCHED_ROUTING" spirit:order="989" spirit:configGroups="0 NoDisplay">false</spirit:value>
+ </spirit:parameter>
+ <spirit:parameter>
+ <spirit:name>CLKOUT7_MATCHED_ROUTING</spirit:name>
+ <spirit:value spirit:format="bool" spirit:resolve="user" spirit:id="PARAM_VALUE.CLKOUT7_MATCHED_ROUTING" spirit:order="990" spirit:configGroups="0 NoDisplay">false</spirit:value>
+ </spirit:parameter>
+ <spirit:parameter>
+ <spirit:name>PRIM_SOURCE</spirit:name>
+ <spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.PRIM_SOURCE" spirit:choiceRef="choice_pairs_11d71346" spirit:order="14.1" spirit:configGroups="0 NoDisplay">Single_ended_clock_capable_pin</spirit:value>
+ </spirit:parameter>
+ <spirit:parameter>
+ <spirit:name>CLKOUT1_DRIVES</spirit:name>
+ <spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.CLKOUT1_DRIVES" spirit:choiceRef="choice_pairs_66e4c81f" spirit:order="86" spirit:configGroups="0 NoDisplay">BUFG</spirit:value>
+ </spirit:parameter>
+ <spirit:parameter>
+ <spirit:name>CLKOUT2_DRIVES</spirit:name>
+ <spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.CLKOUT2_DRIVES" spirit:choiceRef="choice_pairs_66e4c81f" spirit:order="87" spirit:configGroups="0 NoDisplay">BUFG</spirit:value>
+ </spirit:parameter>
+ <spirit:parameter>
+ <spirit:name>CLKOUT3_DRIVES</spirit:name>
+ <spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.CLKOUT3_DRIVES" spirit:choiceRef="choice_pairs_66e4c81f" spirit:order="88" spirit:configGroups="0 NoDisplay">BUFG</spirit:value>
+ </spirit:parameter>
+ <spirit:parameter>
+ <spirit:name>CLKOUT4_DRIVES</spirit:name>
+ <spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.CLKOUT4_DRIVES" spirit:choiceRef="choice_pairs_66e4c81f" spirit:order="89" spirit:configGroups="0 NoDisplay">BUFG</spirit:value>
+ </spirit:parameter>
+ <spirit:parameter>
+ <spirit:name>CLKOUT5_DRIVES</spirit:name>
+ <spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.CLKOUT5_DRIVES" spirit:choiceRef="choice_pairs_66e4c81f" spirit:order="90" spirit:configGroups="0 NoDisplay">BUFG</spirit:value>
+ </spirit:parameter>
+ <spirit:parameter>
+ <spirit:name>CLKOUT6_DRIVES</spirit:name>
+ <spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.CLKOUT6_DRIVES" spirit:choiceRef="choice_pairs_66e4c81f" spirit:order="91" spirit:configGroups="0 NoDisplay">BUFG</spirit:value>
+ </spirit:parameter>
+ <spirit:parameter>
+ <spirit:name>CLKOUT7_DRIVES</spirit:name>
+ <spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.CLKOUT7_DRIVES" spirit:choiceRef="choice_pairs_66e4c81f" spirit:order="92" spirit:configGroups="0 NoDisplay">BUFG</spirit:value>
+ </spirit:parameter>
+ <spirit:parameter>
+ <spirit:name>FEEDBACK_SOURCE</spirit:name>
+ <spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.FEEDBACK_SOURCE" spirit:choiceRef="choice_pairs_15c806d5" spirit:order="93" spirit:configGroups="0 NoDisplay">FDBK_AUTO</spirit:value>
+ </spirit:parameter>
+ <spirit:parameter>
+ <spirit:name>CLKFB_IN_SIGNALING</spirit:name>
+ <spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.CLKFB_IN_SIGNALING" spirit:choiceRef="choice_pairs_3c2d3ec7" spirit:order="94" spirit:configGroups="0 NoDisplay">SINGLE</spirit:value>
+ </spirit:parameter>
+ <spirit:parameter>
+ <spirit:name>CLKFB_IN_PORT</spirit:name>
+ <spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.CLKFB_IN_PORT" spirit:order="95" spirit:configGroups="0 NoDisplay">clkfb_in</spirit:value>
+ </spirit:parameter>
+ <spirit:parameter>
+ <spirit:name>CLKFB_IN_P_PORT</spirit:name>
+ <spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.CLKFB_IN_P_PORT" spirit:order="96" spirit:configGroups="0 NoDisplay">clkfb_in_p</spirit:value>
+ </spirit:parameter>
+ <spirit:parameter>
+ <spirit:name>CLKFB_IN_N_PORT</spirit:name>
+ <spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.CLKFB_IN_N_PORT" spirit:order="97" spirit:configGroups="0 NoDisplay">clkfb_in_n</spirit:value>
+ </spirit:parameter>
+ <spirit:parameter>
+ <spirit:name>CLKFB_OUT_PORT</spirit:name>
+ <spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.CLKFB_OUT_PORT" spirit:order="98" spirit:configGroups="0 NoDisplay">clkfb_out</spirit:value>
+ </spirit:parameter>
+ <spirit:parameter>
+ <spirit:name>CLKFB_OUT_P_PORT</spirit:name>
+ <spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.CLKFB_OUT_P_PORT" spirit:order="99" spirit:configGroups="0 NoDisplay">clkfb_out_p</spirit:value>
+ </spirit:parameter>
+ <spirit:parameter>
+ <spirit:name>CLKFB_OUT_N_PORT</spirit:name>
+ <spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.CLKFB_OUT_N_PORT" spirit:order="100" spirit:configGroups="0 NoDisplay">clkfb_out_n</spirit:value>
+ </spirit:parameter>
+ <spirit:parameter>
+ <spirit:name>PLATFORM</spirit:name>
+ <spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.PLATFORM" spirit:order="101" spirit:configGroups="0 NoDisplay">UNKNOWN</spirit:value>
+ </spirit:parameter>
+ <spirit:parameter>
+ <spirit:name>SUMMARY_STRINGS</spirit:name>
+ <spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.SUMMARY_STRINGS" spirit:order="102" spirit:configGroups="0 NoDisplay">empty</spirit:value>
+ </spirit:parameter>
+ <spirit:parameter>
+ <spirit:name>USE_LOCKED</spirit:name>
+ <spirit:value spirit:format="bool" spirit:resolve="user" spirit:id="PARAM_VALUE.USE_LOCKED" spirit:order="103" spirit:configGroups="0 NoDisplay">false</spirit:value>
+ </spirit:parameter>
+ <spirit:parameter>
+ <spirit:name>CALC_DONE</spirit:name>
+ <spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.CALC_DONE" spirit:order="104" spirit:configGroups="0 NoDisplay">empty</spirit:value>
+ </spirit:parameter>
+ <spirit:parameter>
+ <spirit:name>USE_RESET</spirit:name>
+ <spirit:value spirit:format="bool" spirit:resolve="user" spirit:id="PARAM_VALUE.USE_RESET" spirit:order="105" spirit:configGroups="0 NoDisplay">true</spirit:value>
+ </spirit:parameter>
+ <spirit:parameter>
+ <spirit:name>USE_POWER_DOWN</spirit:name>
+ <spirit:value spirit:format="bool" spirit:resolve="user" spirit:id="PARAM_VALUE.USE_POWER_DOWN" spirit:order="106" spirit:configGroups="0 NoDisplay">false</spirit:value>
+ </spirit:parameter>
+ <spirit:parameter>
+ <spirit:name>USE_STATUS</spirit:name>
+ <spirit:value spirit:format="bool" spirit:resolve="user" spirit:id="PARAM_VALUE.USE_STATUS" spirit:order="107" spirit:configGroups="0 NoDisplay">false</spirit:value>
+ </spirit:parameter>
+ <spirit:parameter>
+ <spirit:name>USE_FREEZE</spirit:name>
+ <spirit:value spirit:format="bool" spirit:resolve="user" spirit:id="PARAM_VALUE.USE_FREEZE" spirit:order="108" spirit:configGroups="0 NoDisplay">false</spirit:value>
+ </spirit:parameter>
+ <spirit:parameter>
+ <spirit:name>USE_CLK_VALID</spirit:name>
+ <spirit:value spirit:format="bool" spirit:resolve="user" spirit:id="PARAM_VALUE.USE_CLK_VALID" spirit:order="109" spirit:configGroups="0 NoDisplay">false</spirit:value>
+ </spirit:parameter>
+ <spirit:parameter>
+ <spirit:name>USE_INCLK_STOPPED</spirit:name>
+ <spirit:value spirit:format="bool" spirit:resolve="user" spirit:id="PARAM_VALUE.USE_INCLK_STOPPED" spirit:order="110" spirit:configGroups="0 NoDisplay">false</spirit:value>
+ </spirit:parameter>
+ <spirit:parameter>
+ <spirit:name>USE_CLKFB_STOPPED</spirit:name>
+ <spirit:value spirit:format="bool" spirit:resolve="user" spirit:id="PARAM_VALUE.USE_CLKFB_STOPPED" spirit:order="111" spirit:configGroups="0 NoDisplay">false</spirit:value>
+ </spirit:parameter>
+ <spirit:parameter>
+ <spirit:name>RESET_PORT</spirit:name>
+ <spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.RESET_PORT" spirit:order="409" spirit:configGroups="0 NoDisplay">resetn</spirit:value>
+ </spirit:parameter>
+ <spirit:parameter>
+ <spirit:name>LOCKED_PORT</spirit:name>
+ <spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.LOCKED_PORT" spirit:order="113" spirit:configGroups="0 NoDisplay">locked</spirit:value>
+ </spirit:parameter>
+ <spirit:parameter>
+ <spirit:name>POWER_DOWN_PORT</spirit:name>
+ <spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.POWER_DOWN_PORT" spirit:order="114" spirit:configGroups="0 NoDisplay">power_down</spirit:value>
+ </spirit:parameter>
+ <spirit:parameter>
+ <spirit:name>CLK_VALID_PORT</spirit:name>
+ <spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.CLK_VALID_PORT" spirit:order="115" spirit:configGroups="0 NoDisplay">CLK_VALID</spirit:value>
+ </spirit:parameter>
+ <spirit:parameter>
+ <spirit:name>STATUS_PORT</spirit:name>
+ <spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.STATUS_PORT" spirit:order="116" spirit:configGroups="0 NoDisplay">STATUS</spirit:value>
+ </spirit:parameter>
+ <spirit:parameter>
+ <spirit:name>CLK_IN_SEL_PORT</spirit:name>
+ <spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.CLK_IN_SEL_PORT" spirit:order="117" spirit:configGroups="0 NoDisplay">clk_in_sel</spirit:value>
+ </spirit:parameter>
+ <spirit:parameter>
+ <spirit:name>INPUT_CLK_STOPPED_PORT</spirit:name>
+ <spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.INPUT_CLK_STOPPED_PORT" spirit:order="118" spirit:configGroups="0 NoDisplay">input_clk_stopped</spirit:value>
+ </spirit:parameter>
+ <spirit:parameter>
+ <spirit:name>CLKFB_STOPPED_PORT</spirit:name>
+ <spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.CLKFB_STOPPED_PORT" spirit:order="119" spirit:configGroups="0 NoDisplay">clkfb_stopped</spirit:value>
+ </spirit:parameter>
+ <spirit:parameter>
+ <spirit:name>SS_MODE</spirit:name>
+ <spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.SS_MODE" spirit:choiceRef="choice_pairs_f4e10086" spirit:order="120" spirit:configGroups="0 NoDisplay">CENTER_HIGH</spirit:value>
+ </spirit:parameter>
+ <spirit:parameter>
+ <spirit:name>SS_MOD_FREQ</spirit:name>
+ <spirit:value spirit:format="float" spirit:resolve="user" spirit:id="PARAM_VALUE.SS_MOD_FREQ" spirit:order="121" spirit:configGroups="0 NoDisplay">250</spirit:value>
+ </spirit:parameter>
+ <spirit:parameter>
+ <spirit:name>SS_MOD_TIME</spirit:name>
+ <spirit:value spirit:format="float" spirit:resolve="user" spirit:id="PARAM_VALUE.SS_MOD_TIME" spirit:order="121.001" spirit:configGroups="0 NoDisplay">0.004</spirit:value>
+ </spirit:parameter>
+ <spirit:parameter>
+ <spirit:name>OVERRIDE_MMCM</spirit:name>
+ <spirit:value spirit:format="bool" spirit:resolve="user" spirit:id="PARAM_VALUE.OVERRIDE_MMCM" spirit:order="122" spirit:configGroups="0 NoDisplay">false</spirit:value>
+ </spirit:parameter>
+ <spirit:parameter>
+ <spirit:name>MMCM_NOTES</spirit:name>
+ <spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.MMCM_NOTES" spirit:order="123" spirit:configGroups="0 NoDisplay">None</spirit:value>
+ </spirit:parameter>
+ <spirit:parameter>
+ <spirit:name>MMCM_DIVCLK_DIVIDE</spirit:name>
+ <spirit:value spirit:format="long" spirit:resolve="user" spirit:id="PARAM_VALUE.MMCM_DIVCLK_DIVIDE" spirit:order="124" spirit:configGroups="0 NoDisplay">1</spirit:value>
+ </spirit:parameter>
+ <spirit:parameter>
+ <spirit:name>MMCM_BANDWIDTH</spirit:name>
+ <spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.MMCM_BANDWIDTH" spirit:choiceRef="choice_list_a9bdfce0" spirit:order="125" spirit:configGroups="0 NoDisplay">OPTIMIZED</spirit:value>
+ </spirit:parameter>
+ <spirit:parameter>
+ <spirit:name>MMCM_CLKFBOUT_MULT_F</spirit:name>
+ <spirit:value spirit:format="float" spirit:resolve="user" spirit:id="PARAM_VALUE.MMCM_CLKFBOUT_MULT_F" spirit:order="126" spirit:configGroups="0 NoDisplay">9.125</spirit:value>
+ </spirit:parameter>
+ <spirit:parameter>
+ <spirit:name>MMCM_CLKFBOUT_PHASE</spirit:name>
+ <spirit:value spirit:format="float" spirit:resolve="user" spirit:id="PARAM_VALUE.MMCM_CLKFBOUT_PHASE" spirit:order="127" spirit:configGroups="0 NoDisplay">0.000</spirit:value>
+ </spirit:parameter>
+ <spirit:parameter>
+ <spirit:name>MMCM_CLKFBOUT_USE_FINE_PS</spirit:name>
+ <spirit:value spirit:format="bool" spirit:resolve="user" spirit:id="PARAM_VALUE.MMCM_CLKFBOUT_USE_FINE_PS" spirit:order="128" spirit:configGroups="0 NoDisplay">false</spirit:value>
+ </spirit:parameter>
+ <spirit:parameter>
+ <spirit:name>MMCM_CLKIN1_PERIOD</spirit:name>
+ <spirit:value spirit:format="float" spirit:resolve="user" spirit:id="PARAM_VALUE.MMCM_CLKIN1_PERIOD" spirit:order="129" spirit:configGroups="0 NoDisplay">10.000</spirit:value>
+ </spirit:parameter>
+ <spirit:parameter>
+ <spirit:name>MMCM_CLKIN2_PERIOD</spirit:name>
+ <spirit:value spirit:format="float" spirit:resolve="user" spirit:id="PARAM_VALUE.MMCM_CLKIN2_PERIOD" spirit:order="130" spirit:configGroups="0 NoDisplay">10.000</spirit:value>
+ </spirit:parameter>
+ <spirit:parameter>
+ <spirit:name>MMCM_CLKOUT4_CASCADE</spirit:name>
+ <spirit:value spirit:format="bool" spirit:resolve="user" spirit:id="PARAM_VALUE.MMCM_CLKOUT4_CASCADE" spirit:order="131" spirit:configGroups="0 NoDisplay">false</spirit:value>
+ </spirit:parameter>
+ <spirit:parameter>
+ <spirit:name>MMCM_CLOCK_HOLD</spirit:name>
+ <spirit:value spirit:format="bool" spirit:resolve="user" spirit:id="PARAM_VALUE.MMCM_CLOCK_HOLD" spirit:order="132" spirit:configGroups="0 NoDisplay">false</spirit:value>
+ </spirit:parameter>
+ <spirit:parameter>
+ <spirit:name>MMCM_COMPENSATION</spirit:name>
+ <spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.MMCM_COMPENSATION" spirit:choiceRef="choice_pairs_502d9f23" spirit:order="133" spirit:configGroups="0 NoDisplay">ZHOLD</spirit:value>
+ </spirit:parameter>
+ <spirit:parameter>
+ <spirit:name>MMCM_REF_JITTER1</spirit:name>
+ <spirit:value spirit:format="float" spirit:resolve="user" spirit:id="PARAM_VALUE.MMCM_REF_JITTER1" spirit:order="134" spirit:configGroups="0 NoDisplay">0.010</spirit:value>
+ </spirit:parameter>
+ <spirit:parameter>
+ <spirit:name>MMCM_REF_JITTER2</spirit:name>
+ <spirit:value spirit:format="float" spirit:resolve="user" spirit:id="PARAM_VALUE.MMCM_REF_JITTER2" spirit:order="135" spirit:configGroups="0 NoDisplay">0.010</spirit:value>
+ </spirit:parameter>
+ <spirit:parameter>
+ <spirit:name>MMCM_STARTUP_WAIT</spirit:name>
+ <spirit:value spirit:format="bool" spirit:resolve="user" spirit:id="PARAM_VALUE.MMCM_STARTUP_WAIT" spirit:order="136" spirit:configGroups="0 NoDisplay">false</spirit:value>
+ </spirit:parameter>
+ <spirit:parameter>
+ <spirit:name>MMCM_CLKOUT0_DIVIDE_F</spirit:name>
+ <spirit:value spirit:format="float" spirit:resolve="user" spirit:id="PARAM_VALUE.MMCM_CLKOUT0_DIVIDE_F" spirit:order="137" spirit:configGroups="0 NoDisplay">36.500</spirit:value>
+ </spirit:parameter>
+ <spirit:parameter>
+ <spirit:name>MMCM_CLKOUT0_DUTY_CYCLE</spirit:name>
+ <spirit:value spirit:format="float" spirit:resolve="user" spirit:id="PARAM_VALUE.MMCM_CLKOUT0_DUTY_CYCLE" spirit:order="138" spirit:configGroups="0 NoDisplay">0.500</spirit:value>
+ </spirit:parameter>
+ <spirit:parameter>
+ <spirit:name>MMCM_CLKOUT0_PHASE</spirit:name>
+ <spirit:value spirit:format="float" spirit:resolve="user" spirit:id="PARAM_VALUE.MMCM_CLKOUT0_PHASE" spirit:order="139" spirit:configGroups="0 NoDisplay">0.000</spirit:value>
+ </spirit:parameter>
+ <spirit:parameter>
+ <spirit:name>MMCM_CLKOUT0_USE_FINE_PS</spirit:name>
+ <spirit:value spirit:format="bool" spirit:resolve="user" spirit:id="PARAM_VALUE.MMCM_CLKOUT0_USE_FINE_PS" spirit:order="140" spirit:configGroups="0 NoDisplay">false</spirit:value>
+ </spirit:parameter>
+ <spirit:parameter>
+ <spirit:name>MMCM_CLKOUT1_DIVIDE</spirit:name>
+ <spirit:value spirit:format="long" spirit:resolve="user" spirit:id="PARAM_VALUE.MMCM_CLKOUT1_DIVIDE" spirit:order="141" spirit:configGroups="0 NoDisplay">1</spirit:value>
+ </spirit:parameter>
+ <spirit:parameter>
+ <spirit:name>MMCM_CLKOUT1_DUTY_CYCLE</spirit:name>
+ <spirit:value spirit:format="float" spirit:resolve="user" spirit:id="PARAM_VALUE.MMCM_CLKOUT1_DUTY_CYCLE" spirit:order="142" spirit:configGroups="0 NoDisplay">0.500</spirit:value>
+ </spirit:parameter>
+ <spirit:parameter>
+ <spirit:name>MMCM_CLKOUT1_PHASE</spirit:name>
+ <spirit:value spirit:format="float" spirit:resolve="user" spirit:id="PARAM_VALUE.MMCM_CLKOUT1_PHASE" spirit:order="143" spirit:configGroups="0 NoDisplay">0.000</spirit:value>
+ </spirit:parameter>
+ <spirit:parameter>
+ <spirit:name>MMCM_CLKOUT1_USE_FINE_PS</spirit:name>
+ <spirit:value spirit:format="bool" spirit:resolve="user" spirit:id="PARAM_VALUE.MMCM_CLKOUT1_USE_FINE_PS" spirit:order="144" spirit:configGroups="0 NoDisplay">false</spirit:value>
+ </spirit:parameter>
+ <spirit:parameter>
+ <spirit:name>MMCM_CLKOUT2_DIVIDE</spirit:name>
+ <spirit:value spirit:format="long" spirit:resolve="user" spirit:id="PARAM_VALUE.MMCM_CLKOUT2_DIVIDE" spirit:order="145" spirit:configGroups="0 NoDisplay">1</spirit:value>
+ </spirit:parameter>
+ <spirit:parameter>
+ <spirit:name>MMCM_CLKOUT2_DUTY_CYCLE</spirit:name>
+ <spirit:value spirit:format="float" spirit:resolve="user" spirit:id="PARAM_VALUE.MMCM_CLKOUT2_DUTY_CYCLE" spirit:order="146" spirit:configGroups="0 NoDisplay">0.500</spirit:value>
+ </spirit:parameter>
+ <spirit:parameter>
+ <spirit:name>MMCM_CLKOUT2_PHASE</spirit:name>
+ <spirit:value spirit:format="float" spirit:resolve="user" spirit:id="PARAM_VALUE.MMCM_CLKOUT2_PHASE" spirit:order="147" spirit:configGroups="0 NoDisplay">0.000</spirit:value>
+ </spirit:parameter>
+ <spirit:parameter>
+ <spirit:name>MMCM_CLKOUT2_USE_FINE_PS</spirit:name>
+ <spirit:value spirit:format="bool" spirit:resolve="user" spirit:id="PARAM_VALUE.MMCM_CLKOUT2_USE_FINE_PS" spirit:order="148" spirit:configGroups="0 NoDisplay">false</spirit:value>
+ </spirit:parameter>
+ <spirit:parameter>
+ <spirit:name>MMCM_CLKOUT3_DIVIDE</spirit:name>
+ <spirit:value spirit:format="long" spirit:resolve="user" spirit:id="PARAM_VALUE.MMCM_CLKOUT3_DIVIDE" spirit:order="149" spirit:configGroups="0 NoDisplay">1</spirit:value>
+ </spirit:parameter>
+ <spirit:parameter>
+ <spirit:name>MMCM_CLKOUT3_DUTY_CYCLE</spirit:name>
+ <spirit:value spirit:format="float" spirit:resolve="user" spirit:id="PARAM_VALUE.MMCM_CLKOUT3_DUTY_CYCLE" spirit:order="150" spirit:configGroups="0 NoDisplay">0.500</spirit:value>
+ </spirit:parameter>
+ <spirit:parameter>
+ <spirit:name>MMCM_CLKOUT3_PHASE</spirit:name>
+ <spirit:value spirit:format="float" spirit:resolve="user" spirit:id="PARAM_VALUE.MMCM_CLKOUT3_PHASE" spirit:order="151" spirit:configGroups="0 NoDisplay">0.000</spirit:value>
+ </spirit:parameter>
+ <spirit:parameter>
+ <spirit:name>MMCM_CLKOUT3_USE_FINE_PS</spirit:name>
+ <spirit:value spirit:format="bool" spirit:resolve="user" spirit:id="PARAM_VALUE.MMCM_CLKOUT3_USE_FINE_PS" spirit:order="152" spirit:configGroups="0 NoDisplay">false</spirit:value>
+ </spirit:parameter>
+ <spirit:parameter>
+ <spirit:name>MMCM_CLKOUT4_DIVIDE</spirit:name>
+ <spirit:value spirit:format="long" spirit:resolve="user" spirit:id="PARAM_VALUE.MMCM_CLKOUT4_DIVIDE" spirit:order="153" spirit:configGroups="0 NoDisplay">1</spirit:value>
+ </spirit:parameter>
+ <spirit:parameter>
+ <spirit:name>MMCM_CLKOUT4_DUTY_CYCLE</spirit:name>
+ <spirit:value spirit:format="float" spirit:resolve="user" spirit:id="PARAM_VALUE.MMCM_CLKOUT4_DUTY_CYCLE" spirit:order="154" spirit:configGroups="0 NoDisplay">0.500</spirit:value>
+ </spirit:parameter>
+ <spirit:parameter>
+ <spirit:name>MMCM_CLKOUT4_PHASE</spirit:name>
+ <spirit:value spirit:format="float" spirit:resolve="user" spirit:id="PARAM_VALUE.MMCM_CLKOUT4_PHASE" spirit:order="155" spirit:configGroups="0 NoDisplay">0.000</spirit:value>
+ </spirit:parameter>
+ <spirit:parameter>
+ <spirit:name>MMCM_CLKOUT4_USE_FINE_PS</spirit:name>
+ <spirit:value spirit:format="bool" spirit:resolve="user" spirit:id="PARAM_VALUE.MMCM_CLKOUT4_USE_FINE_PS" spirit:order="156" spirit:configGroups="0 NoDisplay">false</spirit:value>
+ </spirit:parameter>
+ <spirit:parameter>
+ <spirit:name>MMCM_CLKOUT5_DIVIDE</spirit:name>
+ <spirit:value spirit:format="long" spirit:resolve="user" spirit:id="PARAM_VALUE.MMCM_CLKOUT5_DIVIDE" spirit:order="157" spirit:configGroups="0 NoDisplay">1</spirit:value>
+ </spirit:parameter>
+ <spirit:parameter>
+ <spirit:name>MMCM_CLKOUT5_DUTY_CYCLE</spirit:name>
+ <spirit:value spirit:format="float" spirit:resolve="user" spirit:id="PARAM_VALUE.MMCM_CLKOUT5_DUTY_CYCLE" spirit:order="158" spirit:configGroups="0 NoDisplay">0.500</spirit:value>
+ </spirit:parameter>
+ <spirit:parameter>
+ <spirit:name>MMCM_CLKOUT5_PHASE</spirit:name>
+ <spirit:value spirit:format="float" spirit:resolve="user" spirit:id="PARAM_VALUE.MMCM_CLKOUT5_PHASE" spirit:order="159" spirit:configGroups="0 NoDisplay">0.000</spirit:value>
+ </spirit:parameter>
+ <spirit:parameter>
+ <spirit:name>MMCM_CLKOUT5_USE_FINE_PS</spirit:name>
+ <spirit:value spirit:format="bool" spirit:resolve="user" spirit:id="PARAM_VALUE.MMCM_CLKOUT5_USE_FINE_PS" spirit:order="160" spirit:configGroups="0 NoDisplay">false</spirit:value>
+ </spirit:parameter>
+ <spirit:parameter>
+ <spirit:name>MMCM_CLKOUT6_DIVIDE</spirit:name>
+ <spirit:value spirit:format="long" spirit:resolve="user" spirit:id="PARAM_VALUE.MMCM_CLKOUT6_DIVIDE" spirit:order="161" spirit:configGroups="0 NoDisplay">1</spirit:value>
+ </spirit:parameter>
+ <spirit:parameter>
+ <spirit:name>MMCM_CLKOUT6_DUTY_CYCLE</spirit:name>
+ <spirit:value spirit:format="float" spirit:resolve="user" spirit:id="PARAM_VALUE.MMCM_CLKOUT6_DUTY_CYCLE" spirit:order="162" spirit:configGroups="0 NoDisplay">0.500</spirit:value>
+ </spirit:parameter>
+ <spirit:parameter>
+ <spirit:name>MMCM_CLKOUT6_PHASE</spirit:name>
+ <spirit:value spirit:format="float" spirit:resolve="user" spirit:id="PARAM_VALUE.MMCM_CLKOUT6_PHASE" spirit:order="163" spirit:configGroups="0 NoDisplay">0.000</spirit:value>
+ </spirit:parameter>
+ <spirit:parameter>
+ <spirit:name>MMCM_CLKOUT6_USE_FINE_PS</spirit:name>
+ <spirit:value spirit:format="bool" spirit:resolve="user" spirit:id="PARAM_VALUE.MMCM_CLKOUT6_USE_FINE_PS" spirit:order="164" spirit:configGroups="0 NoDisplay">false</spirit:value>
+ </spirit:parameter>
+ <spirit:parameter>
+ <spirit:name>OVERRIDE_PLL</spirit:name>
+ <spirit:value spirit:format="bool" spirit:resolve="user" spirit:id="PARAM_VALUE.OVERRIDE_PLL" spirit:order="165" spirit:configGroups="0 NoDisplay">false</spirit:value>
+ </spirit:parameter>
+ <spirit:parameter>
+ <spirit:name>PLL_NOTES</spirit:name>
+ <spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.PLL_NOTES" spirit:order="166" spirit:configGroups="0 NoDisplay">None</spirit:value>
+ </spirit:parameter>
+ <spirit:parameter>
+ <spirit:name>PLL_BANDWIDTH</spirit:name>
+ <spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.PLL_BANDWIDTH" spirit:choiceRef="choice_list_a9bdfce0" spirit:order="167" spirit:configGroups="0 NoDisplay">OPTIMIZED</spirit:value>
+ </spirit:parameter>
+ <spirit:parameter>
+ <spirit:name>PLL_CLKFBOUT_MULT</spirit:name>
+ <spirit:value spirit:format="long" spirit:resolve="user" spirit:id="PARAM_VALUE.PLL_CLKFBOUT_MULT" spirit:order="168" spirit:configGroups="0 NoDisplay" spirit:minimum="1" spirit:maximum="64" spirit:rangeType="long">4</spirit:value>
+ </spirit:parameter>
+ <spirit:parameter>
+ <spirit:name>PLL_CLKFBOUT_PHASE</spirit:name>
+ <spirit:value spirit:format="float" spirit:resolve="user" spirit:id="PARAM_VALUE.PLL_CLKFBOUT_PHASE" spirit:order="169" spirit:configGroups="0 NoDisplay">0.000</spirit:value>
+ </spirit:parameter>
+ <spirit:parameter>
+ <spirit:name>PLL_CLK_FEEDBACK</spirit:name>
+ <spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.PLL_CLK_FEEDBACK" spirit:choiceRef="choice_list_b9d38208" spirit:order="170" spirit:configGroups="0 NoDisplay">CLKFBOUT</spirit:value>
+ </spirit:parameter>
+ <spirit:parameter>
+ <spirit:name>PLL_DIVCLK_DIVIDE</spirit:name>
+ <spirit:value spirit:format="long" spirit:resolve="user" spirit:id="PARAM_VALUE.PLL_DIVCLK_DIVIDE" spirit:order="171" spirit:configGroups="0 NoDisplay" spirit:minimum="1" spirit:maximum="52" spirit:rangeType="long">1</spirit:value>
+ </spirit:parameter>
+ <spirit:parameter>
+ <spirit:name>PLL_CLKIN_PERIOD</spirit:name>
+ <spirit:value spirit:format="float" spirit:resolve="user" spirit:id="PARAM_VALUE.PLL_CLKIN_PERIOD" spirit:order="172" spirit:configGroups="0 NoDisplay">10.000</spirit:value>
+ </spirit:parameter>
+ <spirit:parameter>
+ <spirit:name>PLL_COMPENSATION</spirit:name>
+ <spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.PLL_COMPENSATION" spirit:choiceRef="choice_pairs_035ca1c3" spirit:order="173" spirit:configGroups="0 NoDisplay">SYSTEM_SYNCHRONOUS</spirit:value>
+ </spirit:parameter>
+ <spirit:parameter>
+ <spirit:name>PLL_REF_JITTER</spirit:name>
+ <spirit:value spirit:format="float" spirit:resolve="user" spirit:id="PARAM_VALUE.PLL_REF_JITTER" spirit:order="174" spirit:configGroups="0 NoDisplay">0.010</spirit:value>
+ </spirit:parameter>
+ <spirit:parameter>
+ <spirit:name>PLL_CLKOUT0_DIVIDE</spirit:name>
+ <spirit:value spirit:format="long" spirit:resolve="user" spirit:id="PARAM_VALUE.PLL_CLKOUT0_DIVIDE" spirit:order="175" spirit:configGroups="0 NoDisplay" spirit:minimum="1" spirit:maximum="128" spirit:rangeType="long">1</spirit:value>
+ </spirit:parameter>
+ <spirit:parameter>
+ <spirit:name>PLL_CLKOUT0_DUTY_CYCLE</spirit:name>
+ <spirit:value spirit:format="float" spirit:resolve="user" spirit:id="PARAM_VALUE.PLL_CLKOUT0_DUTY_CYCLE" spirit:order="176" spirit:configGroups="0 NoDisplay">0.500</spirit:value>
+ </spirit:parameter>
+ <spirit:parameter>
+ <spirit:name>PLL_CLKOUT0_PHASE</spirit:name>
+ <spirit:value spirit:format="float" spirit:resolve="user" spirit:id="PARAM_VALUE.PLL_CLKOUT0_PHASE" spirit:order="177" spirit:configGroups="0 NoDisplay">0.000</spirit:value>
+ </spirit:parameter>
+ <spirit:parameter>
+ <spirit:name>PLL_CLKOUT1_DIVIDE</spirit:name>
+ <spirit:value spirit:format="long" spirit:resolve="user" spirit:id="PARAM_VALUE.PLL_CLKOUT1_DIVIDE" spirit:order="178" spirit:configGroups="0 NoDisplay" spirit:minimum="1" spirit:maximum="128" spirit:rangeType="long">1</spirit:value>
+ </spirit:parameter>
+ <spirit:parameter>
+ <spirit:name>PLL_CLKOUT1_DUTY_CYCLE</spirit:name>
+ <spirit:value spirit:format="float" spirit:resolve="user" spirit:id="PARAM_VALUE.PLL_CLKOUT1_DUTY_CYCLE" spirit:order="179" spirit:configGroups="0 NoDisplay">0.500</spirit:value>
+ </spirit:parameter>
+ <spirit:parameter>
+ <spirit:name>PLL_CLKOUT1_PHASE</spirit:name>
+ <spirit:value spirit:format="float" spirit:resolve="user" spirit:id="PARAM_VALUE.PLL_CLKOUT1_PHASE" spirit:order="180" spirit:configGroups="0 NoDisplay">0.000</spirit:value>
+ </spirit:parameter>
+ <spirit:parameter>
+ <spirit:name>PLL_CLKOUT2_DIVIDE</spirit:name>
+ <spirit:value spirit:format="long" spirit:resolve="user" spirit:id="PARAM_VALUE.PLL_CLKOUT2_DIVIDE" spirit:order="181" spirit:configGroups="0 NoDisplay" spirit:minimum="1" spirit:maximum="128" spirit:rangeType="long">1</spirit:value>
+ </spirit:parameter>
+ <spirit:parameter>
+ <spirit:name>PLL_CLKOUT2_DUTY_CYCLE</spirit:name>
+ <spirit:value spirit:format="float" spirit:resolve="user" spirit:id="PARAM_VALUE.PLL_CLKOUT2_DUTY_CYCLE" spirit:order="182" spirit:configGroups="0 NoDisplay">0.500</spirit:value>
+ </spirit:parameter>
+ <spirit:parameter>
+ <spirit:name>PLL_CLKOUT2_PHASE</spirit:name>
+ <spirit:value spirit:format="float" spirit:resolve="user" spirit:id="PARAM_VALUE.PLL_CLKOUT2_PHASE" spirit:order="183" spirit:configGroups="0 NoDisplay">0.000</spirit:value>
+ </spirit:parameter>
+ <spirit:parameter>
+ <spirit:name>PLL_CLKOUT3_DIVIDE</spirit:name>
+ <spirit:value spirit:format="long" spirit:resolve="user" spirit:id="PARAM_VALUE.PLL_CLKOUT3_DIVIDE" spirit:order="184" spirit:configGroups="0 NoDisplay" spirit:minimum="1" spirit:maximum="128" spirit:rangeType="long">1</spirit:value>
+ </spirit:parameter>
+ <spirit:parameter>
+ <spirit:name>PLL_CLKOUT3_DUTY_CYCLE</spirit:name>
+ <spirit:value spirit:format="float" spirit:resolve="user" spirit:id="PARAM_VALUE.PLL_CLKOUT3_DUTY_CYCLE" spirit:order="185" spirit:configGroups="0 NoDisplay">0.500</spirit:value>
+ </spirit:parameter>
+ <spirit:parameter>
+ <spirit:name>PLL_CLKOUT3_PHASE</spirit:name>
+ <spirit:value spirit:format="float" spirit:resolve="user" spirit:id="PARAM_VALUE.PLL_CLKOUT3_PHASE" spirit:order="186" spirit:configGroups="0 NoDisplay">0.000</spirit:value>
+ </spirit:parameter>
+ <spirit:parameter>
+ <spirit:name>PLL_CLKOUT4_DIVIDE</spirit:name>
+ <spirit:value spirit:format="long" spirit:resolve="user" spirit:id="PARAM_VALUE.PLL_CLKOUT4_DIVIDE" spirit:order="187" spirit:configGroups="0 NoDisplay" spirit:minimum="1" spirit:maximum="128" spirit:rangeType="long">1</spirit:value>
+ </spirit:parameter>
+ <spirit:parameter>
+ <spirit:name>PLL_CLKOUT4_DUTY_CYCLE</spirit:name>
+ <spirit:value spirit:format="float" spirit:resolve="user" spirit:id="PARAM_VALUE.PLL_CLKOUT4_DUTY_CYCLE" spirit:order="188" spirit:configGroups="0 NoDisplay">0.500</spirit:value>
+ </spirit:parameter>
+ <spirit:parameter>
+ <spirit:name>PLL_CLKOUT4_PHASE</spirit:name>
+ <spirit:value spirit:format="float" spirit:resolve="user" spirit:id="PARAM_VALUE.PLL_CLKOUT4_PHASE" spirit:order="189" spirit:configGroups="0 NoDisplay">0.000</spirit:value>
+ </spirit:parameter>
+ <spirit:parameter>
+ <spirit:name>PLL_CLKOUT5_DIVIDE</spirit:name>
+ <spirit:value spirit:format="long" spirit:resolve="user" spirit:id="PARAM_VALUE.PLL_CLKOUT5_DIVIDE" spirit:order="190" spirit:configGroups="0 NoDisplay" spirit:minimum="1" spirit:maximum="128" spirit:rangeType="long">1</spirit:value>
+ </spirit:parameter>
+ <spirit:parameter>
+ <spirit:name>PLL_CLKOUT5_DUTY_CYCLE</spirit:name>
+ <spirit:value spirit:format="float" spirit:resolve="user" spirit:id="PARAM_VALUE.PLL_CLKOUT5_DUTY_CYCLE" spirit:order="191" spirit:configGroups="0 NoDisplay">0.500</spirit:value>
+ </spirit:parameter>
+ <spirit:parameter>
+ <spirit:name>PLL_CLKOUT5_PHASE</spirit:name>
+ <spirit:value spirit:format="float" spirit:resolve="user" spirit:id="PARAM_VALUE.PLL_CLKOUT5_PHASE" spirit:order="192" spirit:configGroups="0 NoDisplay">0.000</spirit:value>
+ </spirit:parameter>
+ <spirit:parameter>
+ <spirit:name>RESET_TYPE</spirit:name>
+ <spirit:displayName>Reset Type</spirit:displayName>
+ <spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.RESET_TYPE" spirit:choiceRef="choice_pairs_a4fbc00c" spirit:order="408" spirit:configGroups="0 NoDisplay">ACTIVE_LOW</spirit:value>
+ </spirit:parameter>
+ <spirit:parameter>
+ <spirit:name>USE_SAFE_CLOCK_STARTUP</spirit:name>
+ <spirit:value spirit:format="bool" spirit:resolve="user" spirit:id="PARAM_VALUE.USE_SAFE_CLOCK_STARTUP" spirit:order="85.5" spirit:configGroups="0; NoDisplay">false</spirit:value>
+ </spirit:parameter>
+ <spirit:parameter>
+ <spirit:name>USE_CLOCK_SEQUENCING</spirit:name>
+ <spirit:value spirit:format="bool" spirit:resolve="user" spirit:id="PARAM_VALUE.USE_CLOCK_SEQUENCING" spirit:order="501" spirit:configGroups="0; NoDisplay">false</spirit:value>
+ </spirit:parameter>
+ <spirit:parameter>
+ <spirit:name>CLKOUT1_SEQUENCE_NUMBER</spirit:name>
+ <spirit:value spirit:format="long" spirit:resolve="user" spirit:id="PARAM_VALUE.CLKOUT1_SEQUENCE_NUMBER" spirit:order="502" spirit:configGroups="0; NoDisplay" spirit:minimum="1" spirit:maximum="7" spirit:rangeType="long">1</spirit:value>
+ </spirit:parameter>
+ <spirit:parameter>
+ <spirit:name>CLKOUT2_SEQUENCE_NUMBER</spirit:name>
+ <spirit:value spirit:format="long" spirit:resolve="user" spirit:id="PARAM_VALUE.CLKOUT2_SEQUENCE_NUMBER" spirit:order="503" spirit:configGroups="0; NoDisplay" spirit:minimum="1" spirit:maximum="7" spirit:rangeType="long">1</spirit:value>
+ </spirit:parameter>
+ <spirit:parameter>
+ <spirit:name>CLKOUT3_SEQUENCE_NUMBER</spirit:name>
+ <spirit:value spirit:format="long" spirit:resolve="user" spirit:id="PARAM_VALUE.CLKOUT3_SEQUENCE_NUMBER" spirit:order="504" spirit:configGroups="0; NoDisplay" spirit:minimum="1" spirit:maximum="7" spirit:rangeType="long">1</spirit:value>
+ </spirit:parameter>
+ <spirit:parameter>
+ <spirit:name>CLKOUT4_SEQUENCE_NUMBER</spirit:name>
+ <spirit:value spirit:format="long" spirit:resolve="user" spirit:id="PARAM_VALUE.CLKOUT4_SEQUENCE_NUMBER" spirit:order="505" spirit:configGroups="0; NoDisplay" spirit:minimum="1" spirit:maximum="7" spirit:rangeType="long">1</spirit:value>
+ </spirit:parameter>
+ <spirit:parameter>
+ <spirit:name>CLKOUT5_SEQUENCE_NUMBER</spirit:name>
+ <spirit:value spirit:format="long" spirit:resolve="user" spirit:id="PARAM_VALUE.CLKOUT5_SEQUENCE_NUMBER" spirit:order="506" spirit:configGroups="0; NoDisplay" spirit:minimum="1" spirit:maximum="7" spirit:rangeType="long">1</spirit:value>
+ </spirit:parameter>
+ <spirit:parameter>
+ <spirit:name>CLKOUT6_SEQUENCE_NUMBER</spirit:name>
+ <spirit:value spirit:format="long" spirit:resolve="user" spirit:id="PARAM_VALUE.CLKOUT6_SEQUENCE_NUMBER" spirit:order="507" spirit:configGroups="0; NoDisplay" spirit:minimum="1" spirit:maximum="7" spirit:rangeType="long">1</spirit:value>
+ </spirit:parameter>
+ <spirit:parameter>
+ <spirit:name>CLKOUT7_SEQUENCE_NUMBER</spirit:name>
+ <spirit:value spirit:format="long" spirit:resolve="user" spirit:id="PARAM_VALUE.CLKOUT7_SEQUENCE_NUMBER" spirit:order="508" spirit:configGroups="0; NoDisplay" spirit:minimum="1" spirit:maximum="7" spirit:rangeType="long">1</spirit:value>
+ </spirit:parameter>
+ <spirit:parameter>
+ <spirit:name>USE_BOARD_FLOW</spirit:name>
+ <spirit:displayName>Generate Board based IO Constraints</spirit:displayName>
+ <spirit:value spirit:format="bool" spirit:resolve="user" spirit:id="PARAM_VALUE.USE_BOARD_FLOW" spirit:order="1.1">false</spirit:value>
+ </spirit:parameter>
+ <spirit:parameter>
+ <spirit:name>CLK_IN1_BOARD_INTERFACE</spirit:name>
+ <spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.CLK_IN1_BOARD_INTERFACE" spirit:choiceRef="choice_pairs_340369e0" spirit:order="13.8">Custom</spirit:value>
+ </spirit:parameter>
+ <spirit:parameter>
+ <spirit:name>CLK_IN2_BOARD_INTERFACE</spirit:name>
+ <spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.CLK_IN2_BOARD_INTERFACE" spirit:choiceRef="choice_pairs_340369e0" spirit:order="13.9">Custom</spirit:value>
+ </spirit:parameter>
+ <spirit:parameter>
+ <spirit:name>DIFF_CLK_IN1_BOARD_INTERFACE</spirit:name>
+ <spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.DIFF_CLK_IN1_BOARD_INTERFACE" spirit:choiceRef="choice_pairs_0920eb1b" spirit:order="13.1">Custom</spirit:value>
+ </spirit:parameter>
+ <spirit:parameter>
+ <spirit:name>DIFF_CLK_IN2_BOARD_INTERFACE</spirit:name>
+ <spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.DIFF_CLK_IN2_BOARD_INTERFACE" spirit:choiceRef="choice_pairs_0920eb1b" spirit:order="13.2">Custom</spirit:value>
+ </spirit:parameter>
+ <spirit:parameter>
+ <spirit:name>AUTO_PRIMITIVE</spirit:name>
+ <spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.AUTO_PRIMITIVE" spirit:choiceRef="choice_pairs_77d3d587" spirit:order="13212">MMCM</spirit:value>
+ </spirit:parameter>
+ <spirit:parameter>
+ <spirit:name>RESET_BOARD_INTERFACE</spirit:name>
+ <spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.RESET_BOARD_INTERFACE" spirit:choiceRef="choice_list_ac75ef1e" spirit:order="21.4">Custom</spirit:value>
+ </spirit:parameter>
+ <spirit:parameter>
+ <spirit:name>ENABLE_CDDC</spirit:name>
+ <spirit:value spirit:format="bool" spirit:resolve="user" spirit:id="PARAM_VALUE.ENABLE_CDDC" spirit:order="509">false</spirit:value>
+ </spirit:parameter>
+ <spirit:parameter>
+ <spirit:name>CDDCDONE_PORT</spirit:name>
+ <spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.CDDCDONE_PORT" spirit:order="510" spirit:configGroups="0 NoDisplay">cddcdone</spirit:value>
+ </spirit:parameter>
+ <spirit:parameter>
+ <spirit:name>CDDCREQ_PORT</spirit:name>
+ <spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.CDDCREQ_PORT" spirit:order="511" spirit:configGroups="0 NoDisplay">cddcreq</spirit:value>
+ </spirit:parameter>
+ <spirit:parameter>
+ <spirit:name>ENABLE_CLKOUTPHY</spirit:name>
+ <spirit:value spirit:format="bool" spirit:resolve="user" spirit:id="PARAM_VALUE.ENABLE_CLKOUTPHY" spirit:order="123.1">false</spirit:value>
+ </spirit:parameter>
+ <spirit:parameter>
+ <spirit:name>CLKOUTPHY_REQUESTED_FREQ</spirit:name>
+ <spirit:value spirit:format="float" spirit:resolve="user" spirit:id="PARAM_VALUE.CLKOUTPHY_REQUESTED_FREQ" spirit:order="123.2" spirit:configGroups="0 NoDisplay">600.000</spirit:value>
+ </spirit:parameter>
+ <spirit:parameter>
+ <spirit:name>CLKOUT1_JITTER</spirit:name>
+ <spirit:displayName>Clkout1 Jitter</spirit:displayName>
+ <spirit:value spirit:format="float" spirit:resolve="user" spirit:id="PARAM_VALUE.CLKOUT1_JITTER" spirit:order="1000">181.828</spirit:value>
+ </spirit:parameter>
+ <spirit:parameter>
+ <spirit:name>CLKOUT1_PHASE_ERROR</spirit:name>
+ <spirit:displayName>Clkout1 Phase</spirit:displayName>
+ <spirit:value spirit:format="float" spirit:resolve="user" spirit:id="PARAM_VALUE.CLKOUT1_PHASE_ERROR" spirit:order="1001">104.359</spirit:value>
+ </spirit:parameter>
+ <spirit:parameter>
+ <spirit:name>CLKOUT2_JITTER</spirit:name>
+ <spirit:displayName>Clkout2 Jitter</spirit:displayName>
+ <spirit:value spirit:format="float" spirit:resolve="user" spirit:id="PARAM_VALUE.CLKOUT2_JITTER" spirit:order="1002">0.0</spirit:value>
+ </spirit:parameter>
+ <spirit:parameter>
+ <spirit:name>CLKOUT2_PHASE_ERROR</spirit:name>
+ <spirit:displayName>Clkout2 Phase</spirit:displayName>
+ <spirit:value spirit:format="float" spirit:resolve="user" spirit:id="PARAM_VALUE.CLKOUT2_PHASE_ERROR" spirit:order="1003">0.0</spirit:value>
+ </spirit:parameter>
+ <spirit:parameter>
+ <spirit:name>CLKOUT3_JITTER</spirit:name>
+ <spirit:displayName>Clkout3 Jitter</spirit:displayName>
+ <spirit:value spirit:format="float" spirit:resolve="user" spirit:id="PARAM_VALUE.CLKOUT3_JITTER" spirit:order="1004">0.0</spirit:value>
+ </spirit:parameter>
+ <spirit:parameter>
+ <spirit:name>CLKOUT3_PHASE_ERROR</spirit:name>
+ <spirit:displayName>Clkout3 Phase</spirit:displayName>
+ <spirit:value spirit:format="float" spirit:resolve="user" spirit:id="PARAM_VALUE.CLKOUT3_PHASE_ERROR" spirit:order="1005">0.0</spirit:value>
+ </spirit:parameter>
+ <spirit:parameter>
+ <spirit:name>CLKOUT4_JITTER</spirit:name>
+ <spirit:displayName>Clkout4 Jitter</spirit:displayName>
+ <spirit:value spirit:format="float" spirit:resolve="user" spirit:id="PARAM_VALUE.CLKOUT4_JITTER" spirit:order="1006">0.0</spirit:value>
+ </spirit:parameter>
+ <spirit:parameter>
+ <spirit:name>CLKOUT4_PHASE_ERROR</spirit:name>
+ <spirit:displayName>Clkout4 Phase</spirit:displayName>
+ <spirit:value spirit:format="float" spirit:resolve="user" spirit:id="PARAM_VALUE.CLKOUT4_PHASE_ERROR" spirit:order="1007">0.0</spirit:value>
+ </spirit:parameter>
+ <spirit:parameter>
+ <spirit:name>CLKOUT5_JITTER</spirit:name>
+ <spirit:displayName>Clkout5 Jitter</spirit:displayName>
+ <spirit:value spirit:format="float" spirit:resolve="user" spirit:id="PARAM_VALUE.CLKOUT5_JITTER" spirit:order="1008">0.0</spirit:value>
+ </spirit:parameter>
+ <spirit:parameter>
+ <spirit:name>CLKOUT5_PHASE_ERROR</spirit:name>
+ <spirit:displayName>Clkout5 Phase</spirit:displayName>
+ <spirit:value spirit:format="float" spirit:resolve="user" spirit:id="PARAM_VALUE.CLKOUT5_PHASE_ERROR" spirit:order="1009">0.0</spirit:value>
+ </spirit:parameter>
+ <spirit:parameter>
+ <spirit:name>CLKOUT6_JITTER</spirit:name>
+ <spirit:displayName>Clkout6 Jitter</spirit:displayName>
+ <spirit:value spirit:format="float" spirit:resolve="user" spirit:id="PARAM_VALUE.CLKOUT6_JITTER" spirit:order="1010">0.0</spirit:value>
+ </spirit:parameter>
+ <spirit:parameter>
+ <spirit:name>CLKOUT6_PHASE_ERROR</spirit:name>
+ <spirit:displayName>Clkout6 Phase</spirit:displayName>
+ <spirit:value spirit:format="float" spirit:resolve="user" spirit:id="PARAM_VALUE.CLKOUT6_PHASE_ERROR" spirit:order="1011">0.0</spirit:value>
+ </spirit:parameter>
+ <spirit:parameter>
+ <spirit:name>CLKOUT7_JITTER</spirit:name>
+ <spirit:displayName>Clkout7 Jitter</spirit:displayName>
+ <spirit:value spirit:format="float" spirit:resolve="user" spirit:id="PARAM_VALUE.CLKOUT7_JITTER" spirit:order="1012">0.0</spirit:value>
+ </spirit:parameter>
+ <spirit:parameter>
+ <spirit:name>CLKOUT7_PHASE_ERROR</spirit:name>
+ <spirit:displayName>Clkout7 Phase</spirit:displayName>
+ <spirit:value spirit:format="float" spirit:resolve="user" spirit:id="PARAM_VALUE.CLKOUT7_PHASE_ERROR" spirit:order="1013">0.0</spirit:value>
+ </spirit:parameter>
+ <spirit:parameter>
+ <spirit:name>INPUT_MODE</spirit:name>
+ <spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.INPUT_MODE" spirit:choiceRef="choice_pairs_f669c2f5" spirit:order="7.8">frequency</spirit:value>
+ </spirit:parameter>
+ <spirit:parameter>
+ <spirit:name>INTERFACE_SELECTION</spirit:name>
+ <spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.INTERFACE_SELECTION" spirit:choiceRef="choice_pairs_8b28f1f7" spirit:order="11.1">Enable_AXI</spirit:value>
+ </spirit:parameter>
+ <spirit:parameter>
+ <spirit:name>AXI_DRP</spirit:name>
+ <spirit:displayName>Write DRP registers</spirit:displayName>
+ <spirit:value spirit:format="bool" spirit:resolve="user" spirit:id="PARAM_VALUE.AXI_DRP" spirit:order="11.12">false</spirit:value>
+ </spirit:parameter>
+ <spirit:parameter>
+ <spirit:name>PHASE_DUTY_CONFIG</spirit:name>
+ <spirit:displayName>Phase Duty Cycle Config</spirit:displayName>
+ <spirit:value spirit:format="bool" spirit:resolve="user" spirit:id="PARAM_VALUE.PHASE_DUTY_CONFIG" spirit:order="11.2">false</spirit:value>
+ </spirit:parameter>
+ </spirit:parameters>
+ <spirit:vendorExtensions>
+ <xilinx:coreExtensions>
+ <xilinx:displayName>Clocking Wizard</xilinx:displayName>
+ <xilinx:xpmLibraries>
+ <xilinx:xpmLibrary>XPM_CDC</xilinx:xpmLibrary>
+ </xilinx:xpmLibraries>
+ <xilinx:coreRevision>11</xilinx:coreRevision>
+ <xilinx:configElementInfos>
+ <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.S_AXI_LITE.ADDR_WIDTH" xilinx:valueSource="auto"/>
+ <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.S_AXI_LITE.ARUSER_WIDTH" xilinx:valueSource="constant"/>
+ <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.S_AXI_LITE.AWUSER_WIDTH" xilinx:valueSource="constant"/>
+ <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.S_AXI_LITE.BUSER_WIDTH" xilinx:valueSource="constant"/>
+ <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.S_AXI_LITE.DATA_WIDTH" xilinx:valueSource="auto"/>
+ <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.S_AXI_LITE.HAS_BRESP" xilinx:valueSource="auto"/>
+ <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.S_AXI_LITE.HAS_BURST" xilinx:valueSource="constant"/>
+ <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.S_AXI_LITE.HAS_CACHE" xilinx:valueSource="constant"/>
+ <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.S_AXI_LITE.HAS_LOCK" xilinx:valueSource="constant"/>
+ <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.S_AXI_LITE.HAS_PROT" xilinx:valueSource="constant"/>
+ <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.S_AXI_LITE.HAS_QOS" xilinx:valueSource="constant"/>
+ <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.S_AXI_LITE.HAS_REGION" xilinx:valueSource="constant"/>
+ <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.S_AXI_LITE.HAS_RRESP" xilinx:valueSource="auto"/>
+ <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.S_AXI_LITE.HAS_WSTRB" xilinx:valueSource="auto"/>
+ <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.S_AXI_LITE.ID_WIDTH" xilinx:valueSource="constant"/>
+ <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.S_AXI_LITE.PROTOCOL" xilinx:valueSource="constant"/>
+ <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.S_AXI_LITE.RUSER_WIDTH" xilinx:valueSource="constant"/>
+ <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.S_AXI_LITE.WUSER_WIDTH" xilinx:valueSource="constant"/>
+ <xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.CLKOUT1_JITTER" xilinx:valueSource="user"/>
+ <xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.CLKOUT1_PHASE_ERROR" xilinx:valueSource="user"/>
+ <xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.CLKOUT1_REQUESTED_OUT_FREQ" xilinx:valueSource="user"/>
+ <xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.MMCM_CLKFBOUT_MULT_F" xilinx:valueSource="user"/>
+ <xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.MMCM_CLKOUT0_DIVIDE_F" xilinx:valueSource="user"/>
+ <xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.RESET_PORT" xilinx:valueSource="user"/>
+ <xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.RESET_TYPE" xilinx:valueSource="user"/>
+ <xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.USE_LOCKED" xilinx:valueSource="user"/>
+ </xilinx:configElementInfos>
+ </xilinx:coreExtensions>
+ <xilinx:packagingInfo>
+ <xilinx:xilinxVersion>2022.2</xilinx:xilinxVersion>
+ <xilinx:checksum xilinx:scope="busInterfaces" xilinx:value="0d9e23d5"/>
+ <xilinx:checksum xilinx:scope="fileGroups" xilinx:value="e96d5789"/>
+ <xilinx:checksum xilinx:scope="ports" xilinx:value="4f3d3737"/>
+ <xilinx:checksum xilinx:scope="hdlParameters" xilinx:value="c11c59cd"/>
+ <xilinx:checksum xilinx:scope="parameters" xilinx:value="63dcade9"/>
+ </xilinx:packagingInfo>
+ </spirit:vendorExtensions>
+</spirit:component>
diff --git a/game.gen/sources_1/ip/clk_wiz_1/clk_wiz_1_board.xdc b/game.gen/sources_1/ip/clk_wiz_1/clk_wiz_1_board.xdc
new file mode 100644
index 0000000000000000000000000000000000000000..3422a8eba3c6e7f364935db84ab8bb8ad1af9318
--- /dev/null
+++ b/game.gen/sources_1/ip/clk_wiz_1/clk_wiz_1_board.xdc
@@ -0,0 +1,2 @@
+#--------------------Physical Constraints-----------------
+
diff --git a/game.gen/sources_1/ip/clk_wiz_1/clk_wiz_1_clk_wiz.v b/game.gen/sources_1/ip/clk_wiz_1/clk_wiz_1_clk_wiz.v
new file mode 100644
index 0000000000000000000000000000000000000000..da51acb2df25193f1b8ec792c0e30ccaf44721a3
--- /dev/null
+++ b/game.gen/sources_1/ip/clk_wiz_1/clk_wiz_1_clk_wiz.v
@@ -0,0 +1,202 @@
+
+// file: clk_wiz_1.v
+//
+// (c) Copyright 2008 - 2013 Xilinx, Inc. All rights reserved.
+//
+// This file contains confidential and proprietary information
+// of Xilinx, Inc. and is protected under U.S. and
+// international copyright and other intellectual property
+// laws.
+//
+// DISCLAIMER
+// This disclaimer is not a license and does not grant any
+// rights to the materials distributed herewith. Except as
+// otherwise provided in a valid license issued to you by
+// Xilinx, and to the maximum extent permitted by applicable
+// law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
+// WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
+// AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
+// BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
+// INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
+// (2) Xilinx shall not be liable (whether in contract or tort,
+// including negligence, or under any other theory of
+// liability) for any loss or damage of any kind or nature
+// related to, arising under or in connection with these
+// materials, including for any direct, or any indirect,
+// special, incidental, or consequential loss or damage
+// (including loss of data, profits, goodwill, or any type of
+// loss or damage suffered as a result of any action brought
+// by a third party) even if such damage or loss was
+// reasonably foreseeable or Xilinx had been advised of the
+// possibility of the same.
+//
+// CRITICAL APPLICATIONS
+// Xilinx products are not designed or intended to be fail-
+// safe, or for use in any application requiring fail-safe
+// performance, such as life-support or safety devices or
+// systems, Class III medical devices, nuclear facilities,
+// applications related to the deployment of airbags, or any
+// other applications that could lead to death, personal
+// injury, or severe property or environmental damage
+// (individually and collectively, "Critical
+// Applications"). Customer assumes the sole risk and
+// liability of any use of Xilinx products in Critical
+// Applications, subject only to applicable laws and
+// regulations governing limitations on product liability.
+//
+// THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
+// PART OF THIS FILE AT ALL TIMES.
+//
+//----------------------------------------------------------------------------
+// User entered comments
+//----------------------------------------------------------------------------
+// None
+//
+//----------------------------------------------------------------------------
+// Output Output Phase Duty Cycle Pk-to-Pk Phase
+// Clock Freq (MHz) (degrees) (%) Jitter (ps) Error (ps)
+//----------------------------------------------------------------------------
+// clk_out1__25.00000______0.000______50.0______181.828____104.359
+//
+//----------------------------------------------------------------------------
+// Input Clock Freq (MHz) Input Jitter (UI)
+//----------------------------------------------------------------------------
+// __primary_________100.000____________0.010
+
+`timescale 1ps/1ps
+
+module clk_wiz_1_clk_wiz
+
+ (// Clock in ports
+ // Clock out ports
+ output clk_out1,
+ // Status and control signals
+ input resetn,
+ input clk_in1
+ );
+ // Input buffering
+ //------------------------------------
+wire clk_in1_clk_wiz_1;
+wire clk_in2_clk_wiz_1;
+ IBUF clkin1_ibufg
+ (.O (clk_in1_clk_wiz_1),
+ .I (clk_in1));
+
+
+
+
+ // Clocking PRIMITIVE
+ //------------------------------------
+
+ // Instantiation of the MMCM PRIMITIVE
+ // * Unused inputs are tied off
+ // * Unused outputs are labeled unused
+
+ wire clk_out1_clk_wiz_1;
+ wire clk_out2_clk_wiz_1;
+ wire clk_out3_clk_wiz_1;
+ wire clk_out4_clk_wiz_1;
+ wire clk_out5_clk_wiz_1;
+ wire clk_out6_clk_wiz_1;
+ wire clk_out7_clk_wiz_1;
+
+ wire [15:0] do_unused;
+ wire drdy_unused;
+ wire psdone_unused;
+ wire locked_int;
+ wire clkfbout_clk_wiz_1;
+ wire clkfbout_buf_clk_wiz_1;
+ wire clkfboutb_unused;
+ wire clkout0b_unused;
+ wire clkout1_unused;
+ wire clkout1b_unused;
+ wire clkout2_unused;
+ wire clkout2b_unused;
+ wire clkout3_unused;
+ wire clkout3b_unused;
+ wire clkout4_unused;
+ wire clkout5_unused;
+ wire clkout6_unused;
+ wire clkfbstopped_unused;
+ wire clkinstopped_unused;
+ wire reset_high;
+
+ MMCME2_ADV
+ #(.BANDWIDTH ("OPTIMIZED"),
+ .CLKOUT4_CASCADE ("FALSE"),
+ .COMPENSATION ("ZHOLD"),
+ .STARTUP_WAIT ("FALSE"),
+ .DIVCLK_DIVIDE (1),
+ .CLKFBOUT_MULT_F (9.125),
+ .CLKFBOUT_PHASE (0.000),
+ .CLKFBOUT_USE_FINE_PS ("FALSE"),
+ .CLKOUT0_DIVIDE_F (36.500),
+ .CLKOUT0_PHASE (0.000),
+ .CLKOUT0_DUTY_CYCLE (0.500),
+ .CLKOUT0_USE_FINE_PS ("FALSE"),
+ .CLKIN1_PERIOD (10.000))
+ mmcm_adv_inst
+ // Output clocks
+ (
+ .CLKFBOUT (clkfbout_clk_wiz_1),
+ .CLKFBOUTB (clkfboutb_unused),
+ .CLKOUT0 (clk_out1_clk_wiz_1),
+ .CLKOUT0B (clkout0b_unused),
+ .CLKOUT1 (clkout1_unused),
+ .CLKOUT1B (clkout1b_unused),
+ .CLKOUT2 (clkout2_unused),
+ .CLKOUT2B (clkout2b_unused),
+ .CLKOUT3 (clkout3_unused),
+ .CLKOUT3B (clkout3b_unused),
+ .CLKOUT4 (clkout4_unused),
+ .CLKOUT5 (clkout5_unused),
+ .CLKOUT6 (clkout6_unused),
+ // Input clock control
+ .CLKFBIN (clkfbout_buf_clk_wiz_1),
+ .CLKIN1 (clk_in1_clk_wiz_1),
+ .CLKIN2 (1'b0),
+ // Tied to always select the primary input clock
+ .CLKINSEL (1'b1),
+ // Ports for dynamic reconfiguration
+ .DADDR (7'h0),
+ .DCLK (1'b0),
+ .DEN (1'b0),
+ .DI (16'h0),
+ .DO (do_unused),
+ .DRDY (drdy_unused),
+ .DWE (1'b0),
+ // Ports for dynamic phase shift
+ .PSCLK (1'b0),
+ .PSEN (1'b0),
+ .PSINCDEC (1'b0),
+ .PSDONE (psdone_unused),
+ // Other control and status signals
+ .LOCKED (locked_int),
+ .CLKINSTOPPED (clkinstopped_unused),
+ .CLKFBSTOPPED (clkfbstopped_unused),
+ .PWRDWN (1'b0),
+ .RST (reset_high));
+ assign reset_high = ~resetn;
+
+// Clock Monitor clock assigning
+//--------------------------------------
+ // Output buffering
+ //-----------------------------------
+
+ BUFG clkf_buf
+ (.O (clkfbout_buf_clk_wiz_1),
+ .I (clkfbout_clk_wiz_1));
+
+
+
+
+
+
+ BUFG clkout1_buf
+ (.O (clk_out1),
+ .I (clk_out1_clk_wiz_1));
+
+
+
+
+endmodule
diff --git a/game.gen/sources_1/ip/clk_wiz_1/clk_wiz_1_ooc.xdc b/game.gen/sources_1/ip/clk_wiz_1/clk_wiz_1_ooc.xdc
new file mode 100644
index 0000000000000000000000000000000000000000..a8593f0e9c89be4065f4287f7e971ce56327556b
--- /dev/null
+++ b/game.gen/sources_1/ip/clk_wiz_1/clk_wiz_1_ooc.xdc
@@ -0,0 +1,58 @@
+
+# file: clk_wiz_1_ooc.xdc
+#
+# (c) Copyright 2008 - 2013 Xilinx, Inc. All rights reserved.
+#
+# This file contains confidential and proprietary information
+# of Xilinx, Inc. and is protected under U.S. and
+# international copyright and other intellectual property
+# laws.
+#
+# DISCLAIMER
+# This disclaimer is not a license and does not grant any
+# rights to the materials distributed herewith. Except as
+# otherwise provided in a valid license issued to you by
+# Xilinx, and to the maximum extent permitted by applicable
+# law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
+# WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
+# AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
+# BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
+# INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
+# (2) Xilinx shall not be liable (whether in contract or tort,
+# including negligence, or under any other theory of
+# liability) for any loss or damage of any kind or nature
+# related to, arising under or in connection with these
+# materials, including for any direct, or any indirect,
+# special, incidental, or consequential loss or damage
+# (including loss of data, profits, goodwill, or any type of
+# loss or damage suffered as a result of any action brought
+# by a third party) even if such damage or loss was
+# reasonably foreseeable or Xilinx had been advised of the
+# possibility of the same.
+#
+# CRITICAL APPLICATIONS
+# Xilinx products are not designed or intended to be fail-
+# safe, or for use in any application requiring fail-safe
+# performance, such as life-support or safety devices or
+# systems, Class III medical devices, nuclear facilities,
+# applications related to the deployment of airbags, or any
+# other applications that could lead to death, personal
+# injury, or severe property or environmental damage
+# (individually and collectively, "Critical
+# Applications"). Customer assumes the sole risk and
+# liability of any use of Xilinx products in Critical
+# Applications, subject only to applicable laws and
+# regulations governing limitations on product liability.
+#
+# THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
+# PART OF THIS FILE AT ALL TIMES.
+#
+
+#################
+#DEFAULT CLOCK CONSTRAINTS
+
+############################################################
+# Clock Period Constraints #
+############################################################
+#create_clock -period 10.000 [get_ports clk_in1]
+
diff --git a/game.gen/sources_1/ip/clk_wiz_1/doc/clk_wiz_v6_0_changelog.txt b/game.gen/sources_1/ip/clk_wiz_1/doc/clk_wiz_v6_0_changelog.txt
new file mode 100755
index 0000000000000000000000000000000000000000..02aca2c449e08678c0925e1161b470a6259acc15
--- /dev/null
+++ b/game.gen/sources_1/ip/clk_wiz_1/doc/clk_wiz_v6_0_changelog.txt
@@ -0,0 +1,286 @@
+2022.2:
+ * Version 6.0 (Rev. 11)
+ * Bug Fix: CR Fixes
+ * Other: CR Fixes
+
+2022.1.2:
+ * Version 6.0 (Rev. 10)
+ * No changes
+
+2022.1.1:
+ * Version 6.0 (Rev. 10)
+ * No changes
+
+2022.1:
+ * Version 6.0 (Rev. 10)
+ * Bug Fix: CR Fixes
+ * Other: CR Fixes
+
+2021.2.2:
+ * Version 6.0 (Rev. 9)
+ * No changes
+
+2021.2.1:
+ * Version 6.0 (Rev. 9)
+ * No changes
+
+2021.2:
+ * Version 6.0 (Rev. 9)
+ * Bug Fix: CR Fixes
+ * Other: CR Fixes
+
+2021.1.1:
+ * Version 6.0 (Rev. 8)
+ * No changes
+
+2021.1:
+ * Version 6.0 (Rev. 8)
+ * Bug Fix: Internal GUI fixes
+ * Other: CR Fixes
+
+2020.3:
+ * Version 6.0 (Rev. 7)
+ * Bug Fix: Internal GUI fixes
+ * Other: CR Fixes
+
+2020.2.2:
+ * Version 6.0 (Rev. 6)
+ * No changes
+
+2020.2.1:
+ * Version 6.0 (Rev. 6)
+ * No changes
+
+2020.2:
+ * Version 6.0 (Rev. 6)
+ * Bug Fix: Internal GUI fixes
+ * Other: CR Fixes
+
+2020.1.1:
+ * Version 6.0 (Rev. 5)
+ * No changes
+
+2020.1:
+ * Version 6.0 (Rev. 5)
+ * Bug Fix: Internal GUI fixes
+ * Other: CR Fixes
+
+2019.2.2:
+ * Version 6.0 (Rev. 4)
+ * No changes
+
+2019.2.1:
+ * Version 6.0 (Rev. 4)
+ * No changes
+
+2019.2:
+ * Version 6.0 (Rev. 4)
+ * Bug Fix: Internal GUI fixes
+ * Other: CR Fixes
+
+2019.1.3:
+ * Version 6.0 (Rev. 3)
+ * No changes
+
+2019.1.2:
+ * Version 6.0 (Rev. 3)
+ * No changes
+
+2019.1.1:
+ * Version 6.0 (Rev. 3)
+ * No changes
+
+2019.1:
+ * Version 6.0 (Rev. 3)
+ * Bug Fix: Internal GUI fixes
+ * Other: New family support added
+
+2018.3.1:
+ * Version 6.0 (Rev. 2)
+ * No changes
+
+2018.3:
+ * Version 6.0 (Rev. 2)
+ * Bug Fix: Made input source independent for primary and secondary clock
+ * Other: New family support added
+
+2018.2:
+ * Version 6.0 (Rev. 1)
+ * Bug Fix: Removed vco freq check when Primitive is None
+ * Other: New family support added
+
+2018.1:
+ * Version 6.0
+ * Bug Fix: Bug fixes in Dynamic Reconfiguration feature and Write DRP feature
+ * Bug Fix: Bug fixes for connection issue for s_axi_aresetn pin in IPI
+ * Feature Enhancement: The default value of USE_PHASE_ALIGMENT is updated to false for UltraScale and UltraScale+ devices. Phase Alignment feature uses extra clock routes in UltraScale and UltraScale+ designs when MMCMs are used. These routing resources are wasted when user do not understand when phase alignment is really needed. Now, implementation tools can use these extra clock routing resources for high fanout signals.
+ * Feature Enhancement: A column "Max. freq of buffer" is added in the Output Clock table which shows the maximum frequency that the selected output buffer can support
+ * Other: DRCs added for invalid input values in Override mode
+
+2017.4:
+ * Version 5.4 (Rev. 3)
+ * Bug Fix: Internal GUI issues are fixed for COMPENSATION mode as INTERNAL
+ * Bug Fix: Fixed issue in dynamic reconfiguration of fractional values of M in MMCME3, MMCME4
+
+2017.3:
+ * Version 5.4 (Rev. 2)
+ * General: Internal GUI changes. No effect on the customer design. Added support for aspartan7 devices
+
+2017.2:
+ * Version 5.4 (Rev. 1)
+ * General: Internal GUI changes. No effect on the customer design.
+
+2017.1:
+ * Version 5.4
+ * Port Change: Minor version upgrade. CLR pins are added to the pin list when selected buffer is BUFGCEDIV for ultrascale and ultrascale plus devices.
+ * Other: Added support for new zynq ultrascale plus devices.
+
+2016.4:
+ * Version 5.3 (Rev. 3)
+ * Bug Fix: Internal GUI issues are fixed.
+
+2016.3:
+ * Version 5.3 (Rev. 2)
+ * Feature Enhancement: Added new option "Auto" under PRIMITIVE selection for ultrascale and above devices. This option allows the Wizard to instantiate appropriate primitive for the user inputs.
+ * Feature Enhancement: Added Matched Routing Option for better timing solutions.
+ * Feature Enhancement: Options 'Buffer' and 'Buffer_with_CE' are added to the buffer selection list.
+ * Other: Source HDL files are concatenated into a single file to speed up synthesis and simulation. No changes required by the user
+ * Other: Added support for Spartan7 devices.
+
+2016.2:
+ * Version 5.3 (Rev. 1)
+ * Internal register bit update, no effect on customer designs.
+
+2016.1:
+ * Version 5.3
+ * Added Clock Monitor Feature as part of clocking wizard
+ * DRP registers can be directly written through AXI without resource utilization
+ * Changes to HDL library management to support Vivado IP simulation library
+
+2015.4.2:
+ * Version 5.2 (Rev. 1)
+ * No changes
+
+2015.4.1:
+ * Version 5.2 (Rev. 1)
+ * No changes
+
+2015.4:
+ * Version 5.2 (Rev. 1)
+ * Internal device family change, no functional changes
+
+2015.3:
+ * Version 5.2
+ * IP revision number added to HDL module, library, and include file names, to support designs with both locked and upgraded IP instances
+ * Port Renaming tab is hidden in the GUI in IP Integrator as this feature is not supported
+ * Phase alignment feature is removed for ultrascale PLL as primitve has limited capabilities of supporting this feature
+ * When clocking wizard is targetted on a board part, the frequency values that gets propagated to primary and secondary clocks are displayed in floating number format
+ * Example design and simulation files are delivered in verilog only
+
+2015.2.1:
+ * Version 5.1 (Rev. 6)
+ * No changes
+
+2015.2:
+ * Version 5.1 (Rev. 6)
+ * No changes
+
+2015.1:
+ * Version 5.1 (Rev. 6)
+ * Updated mmcm_pll_filter_lookup and mmcm_pll_lock_lookup functions in the header file for 7-Series and UltraScale devices
+ * Supported devices and production status are now determined automatically, to simplify support for future devices
+
+2014.4.1:
+ * Version 5.1 (Rev. 5)
+ * No changes
+
+2014.4:
+ * Version 5.1 (Rev. 5)
+ * Internal device family change, no functional changes
+ * updates related to the source selection based on board interface for zed board
+
+2014.3:
+ * Version 5.1 (Rev. 4)
+ * Option added to enable dynamic phase and duty cycle for resource optimization in AXI4-Lite interface
+
+2014.2:
+ * Version 5.1 (Rev. 3)
+ * Updated for AXI4-Lite interface locked status register address and bit mapping to align with the pg065
+
+2014.1:
+ * Version 5.1 (Rev. 2)
+ * Updated to use inverted output CLKOUTB 0-3 of Clocking Primitive based on requested 180 phase w.r.t. previous clock
+ * Internal device family name change, no functional changes
+
+2013.4:
+ * Version 5.1 (Rev. 1)
+ * Added support for Ultrascale devices
+ * Updated Board Flow GUI to select the clock interfaces
+ * Fixed issue with Stub file parameter error for BUFR output driver
+
+2013.3:
+ * Version 5.1
+ * Added AXI4-Lite interface to dynamically reconfigure MMCM/PLL
+ * Improved safe clock logic to remove glitches on clock outputs for odd multiples of input clock frequencies
+ * Fixed precision issues between displayed and actual frequencies
+ * Added tool tips to GUI
+ * Added Jitter and Phase error values to IP properties
+ * Added support for Cadence IES and Synopsys VCS simulators
+ * Reduced warnings in synthesis and simulation
+ * Enhanced support for IP Integrator
+
+2013.2:
+ * Version 5.0 (Rev. 1)
+ * Fixed issue with clock constraints for multiple instances of clocking wizard
+ * Updated Life-Cycle status of devices
+
+2013.1:
+ * Version 5.0
+ * Lower case ports for Verilog
+ * Added Safe Clock Startup and Clock Sequencing
+
+(c) Copyright 2008 - 2022 Xilinx, Inc. All rights reserved.
+
+This file contains confidential and proprietary information
+of Xilinx, Inc. and is protected under U.S. and
+international copyright and other intellectual property
+laws.
+
+DISCLAIMER
+This disclaimer is not a license and does not grant any
+rights to the materials distributed herewith. Except as
+otherwise provided in a valid license issued to you by
+Xilinx, and to the maximum extent permitted by applicable
+law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
+WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
+AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
+BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
+INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
+(2) Xilinx shall not be liable (whether in contract or tort,
+including negligence, or under any other theory of
+liability) for any loss or damage of any kind or nature
+related to, arising under or in connection with these
+materials, including for any direct, or any indirect,
+special, incidental, or consequential loss or damage
+(including loss of data, profits, goodwill, or any type of
+loss or damage suffered as a result of any action brought
+by a third party) even if such damage or loss was
+reasonably foreseeable or Xilinx had been advised of the
+possibility of the same.
+
+CRITICAL APPLICATIONS
+Xilinx products are not designed or intended to be fail-
+safe, or for use in any application requiring fail-safe
+performance, such as life-support or safety devices or
+systems, Class III medical devices, nuclear facilities,
+applications related to the deployment of airbags, or any
+other applications that could lead to death, personal
+injury, or severe property or environmental damage
+(individually and collectively, "Critical
+Applications"). Customer assumes the sole risk and
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+Applications, subject only to applicable laws and
+regulations governing limitations on product liability.
+
+THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
+PART OF THIS FILE AT ALL TIMES.
diff --git a/game.gen/sources_1/ip/clk_wiz_1/mmcm_pll_drp_func_7s_mmcm.vh b/game.gen/sources_1/ip/clk_wiz_1/mmcm_pll_drp_func_7s_mmcm.vh
new file mode 100755
index 0000000000000000000000000000000000000000..481cd2d0f4bcd479fd5192a0d44df3da3a7f1e08
--- /dev/null
+++ b/game.gen/sources_1/ip/clk_wiz_1/mmcm_pll_drp_func_7s_mmcm.vh
@@ -0,0 +1,671 @@
+///////////////////////////////////////////////////////////////////////////////
+//
+// Company: Xilinx
+// Engineer: Jim Tatsukawa, Karl Kurbjun and Carl Ribbing
+// Date: 7/30/2014
+// Design Name: MMCME2 DRP
+// Module Name: mmcme2_drp_func.h
+// Version: 1.04
+// Target Devices: 7 Series || MMCM
+// Tool versions: 2014.3
+// Description: This header provides the functions necessary to
+// calculate the DRP register values for the V6 MMCM.
+//
+// Revision Notes: 3/12 - Updating lookup_low/lookup_high (CR)
+// 4/13 - Fractional divide function in mmcm_frac_count_calc function. CRS610807
+//
+// Disclaimer: XILINX IS PROVIDING THIS DESIGN, CODE, OR
+// INFORMATION "AS IS" SOLELY FOR USE IN DEVELOPING
+// PROGRAMS AND SOLUTIONS FOR XILINX DEVICES. BY
+// PROVIDING THIS DESIGN, CODE, OR INFORMATION AS
+// ONE POSSIBLE IMPLEMENTATION OF THIS FEATURE,
+// APPLICATION OR STANDARD, XILINX IS MAKING NO
+// REPRESENTATION THAT THIS IMPLEMENTATION IS FREE
+// FROM ANY CLAIMS OF INFRINGEMENT, AND YOU ARE
+// RESPONSIBLE FOR OBTAINING ANY RIGHTS YOU MAY
+// REQUIRE FOR YOUR IMPLEMENTATION. XILINX
+// EXPRESSLY DISCLAIMS ANY WARRANTY WHATSOEVER WITH
+// RESPECT TO THE ADEQUACY OF THE IMPLEMENTATION,
+// INCLUDING BUT NOT LIMITED TO ANY WARRANTIES OR
+// REPRESENTATIONS THAT THIS IMPLEMENTATION IS FREE
+// FROM CLAIMS OF INFRINGEMENT, IMPLIED WARRANTIES
+// OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
+// PURPOSE.
+//
+// (c) Copyright 2009-2010 Xilinx, Inc.
+// All rights reserved.
+//
+///////////////////////////////////////////////////////////////////////////////
+
+// These are user functions that should not be modified. Changes to the defines
+// or code within the functions may alter the accuracy of the calculations.
+
+// Define debug to provide extra messages durring elaboration
+//`define DEBUG 1
+
+// FRAC_PRECISION describes the width of the fractional portion of the fixed
+// point numbers. These should not be modified, they are for development
+// only
+`define FRAC_PRECISION 10
+// FIXED_WIDTH describes the total size for fixed point calculations(int+frac).
+// Warning: L.50 and below will not calculate properly with FIXED_WIDTHs
+// greater than 32
+`define FIXED_WIDTH 32
+
+// This function takes a fixed point number and rounds it to the nearest
+// fractional precision bit.
+function [`FIXED_WIDTH:1] round_frac
+ (
+ // Input is (FIXED_WIDTH-FRAC_PRECISION).FRAC_PRECISION fixed point number
+ input [`FIXED_WIDTH:1] decimal,
+
+ // This describes the precision of the fraction, for example a value
+ // of 1 would modify the fractional so that instead of being a .16
+ // fractional, it would be a .1 (rounded to the nearest 0.5 in turn)
+ input [`FIXED_WIDTH:1] precision
+ );
+
+ begin
+
+ `ifdef DEBUG
+ $display("round_frac - decimal: %h, precision: %h", decimal, precision);
+ `endif
+ // If the fractional precision bit is high then round up
+ if( decimal[(`FRAC_PRECISION-precision)] == 1'b1) begin
+ round_frac = decimal + (1'b1 << (`FRAC_PRECISION-precision));
+ end else begin
+ round_frac = decimal;
+ end
+ `ifdef DEBUG
+ $display("round_frac: %h", round_frac);
+ `endif
+ end
+endfunction
+
+// This function calculates high_time, low_time, w_edge, and no_count
+// of a non-fractional counter based on the divide and duty cycle
+//
+// NOTE: high_time and low_time are returned as integers between 0 and 63
+// inclusive. 64 should equal 6'b000000 (in other words it is okay to
+// ignore the overflow)
+function [13:0] mmcm_pll_divider
+ (
+ input [7:0] divide, // Max divide is 128
+ input [31:0] duty_cycle // Duty cycle is multiplied by 100,000
+ );
+
+ reg [`FIXED_WIDTH:1] duty_cycle_fix;
+
+ // High/Low time is initially calculated with a wider integer to prevent a
+ // calculation error when it overflows to 64.
+ reg [6:0] high_time;
+ reg [6:0] low_time;
+ reg w_edge;
+ reg no_count;
+
+ reg [`FIXED_WIDTH:1] temp;
+
+ begin
+ // Duty Cycle must be between 0 and 1,000
+ if(duty_cycle <=0 || duty_cycle >= 100000) begin
+`ifndef SYNTHESIS
+ $display("ERROR: duty_cycle: %d is invalid", duty_cycle);
+ `endif
+ $finish;
+ end
+
+ // Convert to FIXED_WIDTH-FRAC_PRECISION.FRAC_PRECISION fixed point
+ duty_cycle_fix = (duty_cycle << `FRAC_PRECISION) / 100_000;
+
+ `ifdef DEBUG
+ $display("duty_cycle_fix: %h", duty_cycle_fix);
+ `endif
+
+ // If the divide is 1 nothing needs to be set except the no_count bit.
+ // Other values are dummies
+ if(divide == 7'h01) begin
+ high_time = 7'h01;
+ w_edge = 1'b0;
+ low_time = 7'h01;
+ no_count = 1'b1;
+ end else begin
+ temp = round_frac(duty_cycle_fix*divide, 1);
+
+ // comes from above round_frac
+ high_time = temp[`FRAC_PRECISION+7:`FRAC_PRECISION+1];
+ // If the duty cycle * divide rounded is .5 or greater then this bit
+ // is set.
+ w_edge = temp[`FRAC_PRECISION]; // comes from round_frac
+
+ // If the high time comes out to 0, it needs to be set to at least 1
+ // and w_edge set to 0
+ if(high_time == 7'h00) begin
+ high_time = 7'h01;
+ w_edge = 1'b0;
+ end
+
+ if(high_time == divide) begin
+ high_time = divide - 1;
+ w_edge = 1'b1;
+ end
+
+ // Calculate low_time based on the divide setting and set no_count to
+ // 0 as it is only used when divide is 1.
+ low_time = divide - high_time;
+ no_count = 1'b0;
+ end
+
+ // Set the return value.
+ mmcm_pll_divider = {w_edge,no_count,high_time[5:0],low_time[5:0]};
+ end
+endfunction
+
+// This function calculates mx, delay_time, and phase_mux
+// of a non-fractional counter based on the divide and phase
+//
+// NOTE: The only valid value for the MX bits is 2'b00 to ensure the coarse mux
+// is used.
+function [10:0] mmcm_pll_phase
+ (
+ // divide must be an integer (use fractional if not)
+ // assumed that divide already checked to be valid
+ input [7:0] divide, // Max divide is 128
+
+ // Phase is given in degrees (-360,000 to 360,000)
+ input signed [31:0] phase
+ );
+
+ reg [`FIXED_WIDTH:1] phase_in_cycles;
+ reg [`FIXED_WIDTH:1] phase_fixed;
+ reg [1:0] mx;
+ reg [5:0] delay_time;
+ reg [2:0] phase_mux;
+
+ reg [`FIXED_WIDTH:1] temp;
+
+ begin
+`ifdef DEBUG
+ $display("mmcm_pll_phase-divide:%d,phase:%d",
+ divide, phase);
+`endif
+
+ if ((phase < -360000) || (phase > 360000)) begin
+`ifndef SYNTHESIS
+ $display("ERROR: phase of $phase is not between -360000 and 360000");
+ `endif
+ $finish;
+ end
+
+ // If phase is less than 0, convert it to a positive phase shift
+ // Convert to (FIXED_WIDTH-FRAC_PRECISION).FRAC_PRECISION fixed point
+ if(phase < 0) begin
+ phase_fixed = ( (phase + 360000) << `FRAC_PRECISION ) / 1000;
+ end else begin
+ phase_fixed = ( phase << `FRAC_PRECISION ) / 1000;
+ end
+
+ // Put phase in terms of decimal number of vco clock cycles
+ phase_in_cycles = ( phase_fixed * divide ) / 360;
+
+`ifdef DEBUG
+ $display("phase_in_cycles: %h", phase_in_cycles);
+`endif
+
+
+ temp = round_frac(phase_in_cycles, 3);
+
+ // set mx to 2'b00 that the phase mux from the VCO is enabled
+ mx = 2'b00;
+ phase_mux = temp[`FRAC_PRECISION:`FRAC_PRECISION-2];
+ delay_time = temp[`FRAC_PRECISION+6:`FRAC_PRECISION+1];
+
+ `ifdef DEBUG
+ $display("temp: %h", temp);
+ `endif
+
+ // Setup the return value
+ mmcm_pll_phase={mx, phase_mux, delay_time};
+ end
+endfunction
+
+// This function takes the divide value and outputs the necessary lock values
+function [39:0] mmcm_pll_lock_lookup
+ (
+ input [6:0] divide // Max divide is 64
+ );
+
+ reg [2559:0] lookup;
+
+ begin
+ lookup = {
+ // This table is composed of:
+ // LockRefDly_LockFBDly_LockCnt_LockSatHigh_UnlockCnt
+ 40'b00110_00110_1111101000_1111101001_0000000001,
+ 40'b00110_00110_1111101000_1111101001_0000000001,
+ 40'b01000_01000_1111101000_1111101001_0000000001,
+ 40'b01011_01011_1111101000_1111101001_0000000001,
+ 40'b01110_01110_1111101000_1111101001_0000000001,
+ 40'b10001_10001_1111101000_1111101001_0000000001,
+ 40'b10011_10011_1111101000_1111101001_0000000001,
+ 40'b10110_10110_1111101000_1111101001_0000000001,
+ 40'b11001_11001_1111101000_1111101001_0000000001,
+ 40'b11100_11100_1111101000_1111101001_0000000001,
+ 40'b11111_11111_1110000100_1111101001_0000000001,
+ 40'b11111_11111_1100111001_1111101001_0000000001,
+ 40'b11111_11111_1011101110_1111101001_0000000001,
+ 40'b11111_11111_1010111100_1111101001_0000000001,
+ 40'b11111_11111_1010001010_1111101001_0000000001,
+ 40'b11111_11111_1001110001_1111101001_0000000001,
+ 40'b11111_11111_1000111111_1111101001_0000000001,
+ 40'b11111_11111_1000100110_1111101001_0000000001,
+ 40'b11111_11111_1000001101_1111101001_0000000001,
+ 40'b11111_11111_0111110100_1111101001_0000000001,
+ 40'b11111_11111_0111011011_1111101001_0000000001,
+ 40'b11111_11111_0111000010_1111101001_0000000001,
+ 40'b11111_11111_0110101001_1111101001_0000000001,
+ 40'b11111_11111_0110010000_1111101001_0000000001,
+ 40'b11111_11111_0110010000_1111101001_0000000001,
+ 40'b11111_11111_0101110111_1111101001_0000000001,
+ 40'b11111_11111_0101011110_1111101001_0000000001,
+ 40'b11111_11111_0101011110_1111101001_0000000001,
+ 40'b11111_11111_0101000101_1111101001_0000000001,
+ 40'b11111_11111_0101000101_1111101001_0000000001,
+ 40'b11111_11111_0100101100_1111101001_0000000001,
+ 40'b11111_11111_0100101100_1111101001_0000000001,
+ 40'b11111_11111_0100101100_1111101001_0000000001,
+ 40'b11111_11111_0100010011_1111101001_0000000001,
+ 40'b11111_11111_0100010011_1111101001_0000000001,
+ 40'b11111_11111_0100010011_1111101001_0000000001,
+ 40'b11111_11111_0011111010_1111101001_0000000001,
+ 40'b11111_11111_0011111010_1111101001_0000000001,
+ 40'b11111_11111_0011111010_1111101001_0000000001,
+ 40'b11111_11111_0011111010_1111101001_0000000001,
+ 40'b11111_11111_0011111010_1111101001_0000000001,
+ 40'b11111_11111_0011111010_1111101001_0000000001,
+ 40'b11111_11111_0011111010_1111101001_0000000001,
+ 40'b11111_11111_0011111010_1111101001_0000000001,
+ 40'b11111_11111_0011111010_1111101001_0000000001,
+ 40'b11111_11111_0011111010_1111101001_0000000001,
+ 40'b11111_11111_0011111010_1111101001_0000000001,
+ 40'b11111_11111_0011111010_1111101001_0000000001,
+ 40'b11111_11111_0011111010_1111101001_0000000001,
+ 40'b11111_11111_0011111010_1111101001_0000000001,
+ 40'b11111_11111_0011111010_1111101001_0000000001,
+ 40'b11111_11111_0011111010_1111101001_0000000001,
+ 40'b11111_11111_0011111010_1111101001_0000000001,
+ 40'b11111_11111_0011111010_1111101001_0000000001,
+ 40'b11111_11111_0011111010_1111101001_0000000001,
+ 40'b11111_11111_0011111010_1111101001_0000000001,
+ 40'b11111_11111_0011111010_1111101001_0000000001,
+ 40'b11111_11111_0011111010_1111101001_0000000001,
+ 40'b11111_11111_0011111010_1111101001_0000000001,
+ 40'b11111_11111_0011111010_1111101001_0000000001,
+ 40'b11111_11111_0011111010_1111101001_0000000001,
+ 40'b11111_11111_0011111010_1111101001_0000000001,
+ 40'b11111_11111_0011111010_1111101001_0000000001,
+ 40'b11111_11111_0011111010_1111101001_0000000001
+ };
+
+ // Set lookup_entry with the explicit bits from lookup with a part select
+ mmcm_pll_lock_lookup = lookup[ ((64-divide)*40) +: 40];
+ `ifdef DEBUG
+ $display("lock_lookup: %b", mmcm_pll_lock_lookup);
+ `endif
+ end
+endfunction
+
+// This function takes the divide value and the bandwidth setting of the MMCM
+// and outputs the digital filter settings necessary.
+function [9:0] mmcm_pll_filter_lookup
+ (
+ input [6:0] divide, // Max divide is 64
+ input [8*9:0] BANDWIDTH
+ );
+
+ reg [639:0] lookup_low;
+ reg [639:0] lookup_high;
+
+ reg [9:0] lookup_entry;
+
+ begin
+ lookup_low = {
+ // CP_RES_LFHF
+ 10'b0010_1111_00,
+ 10'b0010_1111_00,
+ 10'b0010_1111_00,
+ 10'b0010_1111_00,
+ 10'b0010_0111_00,
+ 10'b0010_1011_00,
+ 10'b0010_1101_00,
+ 10'b0010_0011_00,
+ 10'b0010_0101_00,
+ 10'b0010_0101_00,
+ 10'b0010_1001_00,
+ 10'b0010_1110_00,
+ 10'b0010_1110_00,
+ 10'b0010_1110_00,
+ 10'b0010_1110_00,
+ 10'b0010_0001_00,
+ 10'b0010_0001_00,
+ 10'b0010_0001_00,
+ 10'b0010_0110_00,
+ 10'b0010_0110_00,
+ 10'b0010_0110_00,
+ 10'b0010_0110_00,
+ 10'b0010_0110_00,
+ 10'b0010_0110_00,
+ 10'b0010_0110_00,
+ 10'b0010_1010_00,
+ 10'b0010_1010_00,
+ 10'b0010_1010_00,
+ 10'b0010_1010_00,
+ 10'b0010_1010_00,
+ 10'b0010_1100_00,
+ 10'b0010_1100_00,
+ 10'b0010_1100_00,
+ 10'b0010_1100_00,
+ 10'b0010_1100_00,
+ 10'b0010_1100_00,
+ 10'b0010_1100_00,
+ 10'b0010_1100_00,
+ 10'b0010_1100_00,
+ 10'b0010_1100_00,
+ 10'b0010_1100_00,
+ 10'b0010_1100_00,
+ 10'b0010_1100_00,
+ 10'b0010_1100_00,
+ 10'b0010_1100_00,
+ 10'b0010_1100_00,
+ 10'b0010_1100_00,
+ 10'b0010_0010_00,
+ 10'b0010_0010_00,
+ 10'b0010_0010_00,
+ 10'b0010_0010_00,
+ 10'b0010_0010_00,
+ 10'b0010_0010_00,
+ 10'b0010_0010_00,
+ 10'b0010_0010_00,
+ 10'b0010_0010_00,
+ 10'b0010_0010_00,
+ 10'b0010_0010_00,
+ 10'b0010_0010_00,
+ 10'b0010_0010_00,
+ 10'b0010_0010_00,
+ 10'b0010_0010_00,
+ 10'b0010_0010_00,
+ 10'b0010_0010_00
+ };
+
+ lookup_high = {
+ // CP_RES_LFHF
+ 10'b0010_1111_00,
+ 10'b0100_1111_00,
+ 10'b0101_1011_00,
+ 10'b0111_0111_00,
+ 10'b1101_0111_00,
+ 10'b1110_1011_00,
+ 10'b1110_1101_00,
+ 10'b1111_0011_00,
+ 10'b1110_0101_00,
+ 10'b1111_0101_00,
+ 10'b1111_1001_00,
+ 10'b1101_0001_00,
+ 10'b1111_1001_00,
+ 10'b1111_1001_00,
+ 10'b1111_1001_00,
+ 10'b1111_1001_00,
+ 10'b1111_0101_00,
+ 10'b1111_0101_00,
+ 10'b1100_0001_00,
+ 10'b1100_0001_00,
+ 10'b1100_0001_00,
+ 10'b0101_1100_00,
+ 10'b0101_1100_00,
+ 10'b0101_1100_00,
+ 10'b0101_1100_00,
+ 10'b0011_0100_00,
+ 10'b0011_0100_00,
+ 10'b0011_0100_00,
+ 10'b0011_0100_00,
+ 10'b0011_0100_00,
+ 10'b0011_0100_00,
+ 10'b0011_0100_00,
+ 10'b0011_0100_00,
+ 10'b0011_0100_00,
+ 10'b0011_0100_00,
+ 10'b0011_0100_00,
+ 10'b0011_0100_00,
+ 10'b0011_0100_00,
+ 10'b0011_0100_00,
+ 10'b0011_0100_00,
+ 10'b0011_0100_00,
+ 10'b0010_1000_00,
+ 10'b0010_1000_00,
+ 10'b0010_1000_00,
+ 10'b0010_1000_00,
+ 10'b0010_1000_00,
+ 10'b0111_0001_00,
+ 10'b0111_0001_00,
+ 10'b0100_1100_00,
+ 10'b0100_1100_00,
+ 10'b0100_1100_00,
+ 10'b0100_1100_00,
+ 10'b0110_0001_00,
+ 10'b0110_0001_00,
+ 10'b0101_0110_00,
+ 10'b0101_0110_00,
+ 10'b0101_0110_00,
+ 10'b0010_0100_00,
+ 10'b0010_0100_00,
+ 10'b0010_0100_00,
+ 10'b0010_0100_00,
+ 10'b0100_1010_00,
+ 10'b0011_1100_00,
+ 10'b0011_1100_00
+ };
+
+ // Set lookup_entry with the explicit bits from lookup with a part select
+ if(BANDWIDTH == "LOW") begin
+ // Low Bandwidth
+ mmcm_pll_filter_lookup = lookup_low[ ((64-divide)*10) +: 10];
+ end else begin
+ // High or optimized bandwidth
+ mmcm_pll_filter_lookup = lookup_high[ ((64-divide)*10) +: 10];
+ end
+
+ `ifdef DEBUG
+ $display("filter_lookup: %b", mmcm_pll_filter_lookup);
+ `endif
+ end
+endfunction
+
+// This function takes in the divide, phase, and duty cycle
+// setting to calculate the upper and lower counter registers.
+function [37:0] mmcm_pll_count_calc
+ (
+ input [7:0] divide, // Max divide is 128
+ input signed [31:0] phase,
+ input [31:0] duty_cycle // Multiplied by 100,000
+ );
+
+ reg [13:0] div_calc;
+ reg [16:0] phase_calc;
+
+ begin
+ `ifdef DEBUG
+ $display("mmcm_pll_count_calc- divide:%h, phase:%d, duty_cycle:%d",
+ divide, phase, duty_cycle);
+ `endif
+
+ // w_edge[13], no_count[12], high_time[11:6], low_time[5:0]
+ div_calc = mmcm_pll_divider(divide, duty_cycle);
+ // mx[10:9], pm[8:6], dt[5:0]
+ phase_calc = mmcm_pll_phase(divide, phase);
+
+ // Return value is the upper and lower address of counter
+ // Upper address is:
+ // RESERVED [31:26]
+ // MX [25:24]
+ // EDGE [23]
+ // NOCOUNT [22]
+ // DELAY_TIME [21:16]
+ // Lower Address is:
+ // PHASE_MUX [15:13]
+ // RESERVED [12]
+ // HIGH_TIME [11:6]
+ // LOW_TIME [5:0]
+
+ `ifdef DEBUG
+ $display("div:%d dc:%d phase:%d ht:%d lt:%d ed:%d nc:%d mx:%d dt:%d pm:%d",
+ divide, duty_cycle, phase, div_calc[11:6], div_calc[5:0],
+ div_calc[13], div_calc[12],
+ phase_calc[16:15], phase_calc[5:0], phase_calc[14:12]);
+ `endif
+
+ mmcm_pll_count_calc =
+ {
+ // Upper Address
+ 6'h00, phase_calc[10:9], div_calc[13:12], phase_calc[5:0],
+ // Lower Address
+ phase_calc[8:6], 1'b0, div_calc[11:0]
+ };
+ end
+endfunction
+
+
+// This function takes in the divide, phase, and duty cycle
+// setting to calculate the upper and lower counter registers.
+// for fractional multiply/divide functions.
+//
+//
+function [37:0] mmcm_frac_count_calc
+ (
+ input [7:0] divide, // Max divide is 128
+ input signed [31:0] phase,
+ input [31:0] duty_cycle, // Multiplied by 1,000
+ input [9:0] frac // Multiplied by 1000
+ );
+
+ //Required for fractional divide calculations
+ reg [7:0] lt_frac;
+ reg [7:0] ht_frac;
+
+ reg /*[7:0]*/ wf_fall_frac;
+ reg /*[7:0]*/ wf_rise_frac;
+
+ reg [31:0] a;
+ reg [7:0] pm_rise_frac_filtered ;
+ reg [7:0] pm_fall_frac_filtered ;
+ reg [7:0] clkout0_divide_int;
+ reg [2:0] clkout0_divide_frac;
+ reg [7:0] even_part_high;
+ reg [7:0] even_part_low;
+
+ reg [7:0] odd;
+ reg [7:0] odd_and_frac;
+
+ reg [7:0] pm_fall;
+ reg [7:0] pm_rise;
+ reg [7:0] dt;
+ reg [7:0] dt_int;
+ reg [63:0] dt_calc;
+
+ reg [7:0] pm_rise_frac;
+ reg [7:0] pm_fall_frac;
+
+ reg [31:0] a_per_in_octets;
+ reg [31:0] a_phase_in_cycles;
+
+ parameter precision = 0.125;
+
+ reg [31:0] phase_fixed; // changed to 31:0 from 32:1 jt 5/2/11
+ reg [31: 0] phase_pos;
+ reg [31: 0] phase_vco;
+ reg [31:0] temp;// changed to 31:0 from 32:1 jt 5/2/11
+ reg [13:0] div_calc;
+ reg [16:0] phase_calc;
+
+ begin
+ `ifdef DEBUG
+ $display("mmcm_frac_count_calc- divide:%h, phase:%d, duty_cycle:%d",
+ divide, phase, duty_cycle);
+ `endif
+
+ //convert phase to fixed
+ if ((phase < -360000) || (phase > 360000)) begin
+`ifndef SYNTHESIS
+ $display("ERROR: phase of $phase is not between -360000 and 360000");
+ `endif
+ $finish;
+ end
+
+
+ // Return value is
+ // Transfer data
+ // RESERVED [37:36]
+ // FRAC_TIME [35:33]
+ // FRAC_WF_FALL [32]
+ // Upper address is:
+ // RESERVED [31:26]
+ // MX [25:24]
+ // EDGE [23]
+ // NOCOUNT [22]
+ // DELAY_TIME [21:16]
+ // Lower Address is:
+ // PHASE_MUX [15:13]
+ // RESERVED [12]
+ // HIGH_TIME [11:6]
+ // LOW_TIME [5:0]
+
+
+
+ clkout0_divide_frac = frac / 125;
+ clkout0_divide_int = divide;
+
+ even_part_high = clkout0_divide_int >> 1;//$rtoi(clkout0_divide_int / 2);
+ even_part_low = even_part_high;
+
+ odd = clkout0_divide_int - even_part_high - even_part_low;
+ odd_and_frac = (8*odd) + clkout0_divide_frac;
+
+ lt_frac = even_part_high - (odd_and_frac <= 9);//IF(odd_and_frac>9,even_part_high, even_part_high - 1)
+ ht_frac = even_part_low - (odd_and_frac <= 8);//IF(odd_and_frac>8,even_part_low, even_part_low- 1)
+
+ pm_fall = {odd[6:0],2'b00} + {6'h00, clkout0_divide_frac[2:1]}; // using >> instead of clkout0_divide_frac / 2
+ pm_rise = 0; //0
+
+ wf_fall_frac = ((odd_and_frac >=2) && (odd_and_frac <=9)) || ((clkout0_divide_frac == 1) && (clkout0_divide_int == 2));//CRS610807
+ wf_rise_frac = (odd_and_frac >=1) && (odd_and_frac <=8);//IF(odd_and_frac>=1,IF(odd_and_frac <= 8,1,0),0)
+
+
+
+ //Calculate phase in fractional cycles
+ a_per_in_octets = (8 * divide) + (frac / 125) ;
+ a_phase_in_cycles = (phase+10) * a_per_in_octets / 360000 ;//Adding 1 due to rounding errors
+ pm_rise_frac = (a_phase_in_cycles[7:0] ==8'h00)?8'h00:a_phase_in_cycles[7:0] - {a_phase_in_cycles[7:3],3'b000};
+
+ dt_calc = ((phase+10) * a_per_in_octets / 8 )/360000 ;//TRUNC(phase* divide / 360); //or_simply (a_per_in_octets / 8)
+ dt = dt_calc[7:0];
+
+ pm_rise_frac_filtered = (pm_rise_frac >=8) ? (pm_rise_frac ) - 8: pm_rise_frac ; //((phase_fixed * (divide + frac / 1000)) / 360) - {pm_rise_frac[7:3],3'b000};//$rtoi(clkout0_phase * clkout0_divide / 45);//a;
+
+ dt_int = dt + (& pm_rise_frac[7:4]); //IF(pm_rise_overwriting>7,dt+1,dt)
+ pm_fall_frac = pm_fall + pm_rise_frac;
+ pm_fall_frac_filtered = pm_fall + pm_rise_frac - {pm_fall_frac[7:3], 3'b000};
+
+ div_calc = mmcm_pll_divider(divide, duty_cycle); //Use to determine edge[7], no count[6]
+ phase_calc = mmcm_pll_phase(divide, phase);// returns{mx[1:0], phase_mux[2:0], delay_time[5:0]}
+
+ mmcm_frac_count_calc[37:0] =
+ { 2'b00, pm_fall_frac_filtered[2:0], wf_fall_frac,
+ 1'b0, clkout0_divide_frac[2:0], 1'b1, wf_rise_frac, phase_calc[10:9], div_calc[13:12], dt[5:0],
+ pm_rise_frac_filtered[2], pm_rise_frac_filtered[1], pm_rise_frac_filtered[0], 1'b0, ht_frac[5:0], lt_frac[5:0]
+ } ;
+
+ `ifdef DEBUG
+ $display("-%d.%d p%d>> :DADDR_9_15 frac30to28.frac_en.wf_r_frac.dt:%b%d%d_%b:DADDR_7_13 pm_f_frac_filtered_29to27.wf_f_frac_26:%b%d:DADDR_8_14.pm_r_frac_filt_15to13.ht_frac.lt_frac:%b%b%b:", divide, frac, phase, clkout0_divide_frac, 1, wf_rise_frac, dt, pm_fall_frac_filtered, wf_fall_frac, pm_rise_frac_filtered, ht_frac, lt_frac);
+ `endif
+
+ end
+endfunction
+
diff --git a/game.gen/sources_1/ip/clk_wiz_1/mmcm_pll_drp_func_7s_pll.vh b/game.gen/sources_1/ip/clk_wiz_1/mmcm_pll_drp_func_7s_pll.vh
new file mode 100755
index 0000000000000000000000000000000000000000..d34dbe728f2561b75d3502c80f5c2768979d6fb4
--- /dev/null
+++ b/game.gen/sources_1/ip/clk_wiz_1/mmcm_pll_drp_func_7s_pll.vh
@@ -0,0 +1,531 @@
+///////////////////////////////////////////////////////////////////////////////
+//
+// Company: Xilinx
+// Engineer: Jim Tatsukawa, Karl Kurbjun and Carl Ribbing
+// Date: 7/30/2014
+// Design Name: PLLE2 DRP
+// Module Name: plle2_drp_func.h
+// Version: 2.00
+// Target Devices: 7 Series || PLL
+// Tool versions: 2014.3
+// Description: This header provides the functions necessary to
+// calculate the DRP register values for the V6 PLL.
+// Updated for CR663854.
+//
+// Disclaimer: XILINX IS PROVIDING THIS DESIGN, CODE, OR
+// INFORMATION "AS IS" SOLELY FOR USE IN DEVELOPING
+// PROGRAMS AND SOLUTIONS FOR XILINX DEVICES. BY
+// PROVIDING THIS DESIGN, CODE, OR INFORMATION AS
+// ONE POSSIBLE IMPLEMENTATION OF THIS FEATURE,
+// APPLICATION OR STANDARD, XILINX IS MAKING NO
+// REPRESENTATION THAT THIS IMPLEMENTATION IS FREE
+// FROM ANY CLAIMS OF INFRINGEMENT, AND YOU ARE
+// RESPONSIBLE FOR OBTAINING ANY RIGHTS YOU MAY
+// REQUIRE FOR YOUR IMPLEMENTATION. XILINX
+// EXPRESSLY DISCLAIMS ANY WARRANTY WHATSOEVER WITH
+// RESPECT TO THE ADEQUACY OF THE IMPLEMENTATION,
+// INCLUDING BUT NOT LIMITED TO ANY WARRANTIES OR
+// REPRESENTATIONS THAT THIS IMPLEMENTATION IS FREE
+// FROM CLAIMS OF INFRINGEMENT, IMPLIED WARRANTIES
+// OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
+// PURPOSE.
+//
+// (c) Copyright 2009-2010 Xilinx, Inc.
+// All rights reserved.
+//
+///////////////////////////////////////////////////////////////////////////////
+
+// These are user functions that should not be modified. Changes to the defines
+// or code within the functions may alter the accuracy of the calculations.
+
+// Define debug to provide extra messages durring elaboration
+//`define DEBUG 1
+
+// FRAC_PRECISION describes the width of the fractional portion of the fixed
+// point numbers. These should not be modified, they are for development
+// only
+`define FRAC_PRECISION 10
+// FIXED_WIDTH describes the total size for fixed point calculations(int+frac).
+// Warning: L.50 and below will not calculate properly with FIXED_WIDTHs
+// greater than 32
+`define FIXED_WIDTH 32
+
+// This function takes a fixed point number and rounds it to the nearest
+// fractional precision bit.
+function [`FIXED_WIDTH:1] round_frac
+ (
+ // Input is (FIXED_WIDTH-FRAC_PRECISION).FRAC_PRECISION fixed point number
+ input [`FIXED_WIDTH:1] decimal,
+
+ // This describes the precision of the fraction, for example a value
+ // of 1 would modify the fractional so that instead of being a .16
+ // fractional, it would be a .1 (rounded to the nearest 0.5 in turn)
+ input [`FIXED_WIDTH:1] precision
+ );
+
+ begin
+
+`ifdef DEBUG
+ $display("round_frac - decimal: %h, precision: %h", decimal, precision);
+`endif
+ // If the fractional precision bit is high then round up
+ if( decimal[(`FRAC_PRECISION-precision)] == 1'b1) begin
+ round_frac = decimal + (1'b1 << (`FRAC_PRECISION-precision));
+ end else begin
+ round_frac = decimal;
+ end
+`ifdef DEBUG
+ $display("round_frac: %h", round_frac);
+`endif
+ end
+endfunction
+
+// This function calculates high_time, low_time, w_edge, and no_count
+// of a non-fractional counter based on the divide and duty cycle
+//
+// NOTE: high_time and low_time are returned as integers between 0 and 63
+// inclusive. 64 should equal 6'b000000 (in other words it is okay to
+// ignore the overflow)
+function [13:0] mmcm_pll_divider
+ (
+ input [7:0] divide, // Max divide is 128
+ input [31:0] duty_cycle // Duty cycle is multiplied by 100,000
+ );
+
+ reg [`FIXED_WIDTH:1] duty_cycle_fix;
+
+ // High/Low time is initially calculated with a wider integer to prevent a
+ // calculation error when it overflows to 64.
+ reg [6:0] high_time;
+ reg [6:0] low_time;
+ reg w_edge;
+ reg no_count;
+
+ reg [`FIXED_WIDTH:1] temp;
+
+ begin
+ // Duty Cycle must be between 0 and 1,000
+ if(duty_cycle <=0 || duty_cycle >= 100000) begin
+`ifndef SYNTHESIS
+ $display("ERROR: duty_cycle: %d is invalid", duty_cycle);
+ `endif
+ $finish;
+ end
+
+ // Convert to FIXED_WIDTH-FRAC_PRECISION.FRAC_PRECISION fixed point
+ duty_cycle_fix = (duty_cycle << `FRAC_PRECISION) / 100_000;
+
+`ifdef DEBUG
+ $display("duty_cycle_fix: %h", duty_cycle_fix);
+`endif
+
+ // If the divide is 1 nothing needs to be set except the no_count bit.
+ // Other values are dummies
+ if(divide == 7'h01) begin
+ high_time = 7'h01;
+ w_edge = 1'b0;
+ low_time = 7'h01;
+ no_count = 1'b1;
+ end else begin
+ temp = round_frac(duty_cycle_fix*divide, 1);
+
+ // comes from above round_frac
+ high_time = temp[`FRAC_PRECISION+7:`FRAC_PRECISION+1];
+ // If the duty cycle * divide rounded is .5 or greater then this bit
+ // is set.
+ w_edge = temp[`FRAC_PRECISION]; // comes from round_frac
+
+ // If the high time comes out to 0, it needs to be set to at least 1
+ // and w_edge set to 0
+ if(high_time == 7'h00) begin
+ high_time = 7'h01;
+ w_edge = 1'b0;
+ end
+
+ if(high_time == divide) begin
+ high_time = divide - 1;
+ w_edge = 1'b1;
+ end
+
+ // Calculate low_time based on the divide setting and set no_count to
+ // 0 as it is only used when divide is 1.
+ low_time = divide - high_time;
+ no_count = 1'b0;
+ end
+
+ // Set the return value.
+ mmcm_pll_divider = {w_edge,no_count,high_time[5:0],low_time[5:0]};
+ end
+endfunction
+
+// This function calculates mx, delay_time, and phase_mux
+// of a non-fractional counter based on the divide and phase
+//
+// NOTE: The only valid value for the MX bits is 2'b00 to ensure the coarse mux
+// is used.
+function [10:0] mmcm_pll_phase
+ (
+ // divide must be an integer (use fractional if not)
+ // assumed that divide already checked to be valid
+ input [7:0] divide, // Max divide is 128
+
+ // Phase is given in degrees (-360,000 to 360,000)
+ input signed [31:0] phase
+ );
+
+ reg [`FIXED_WIDTH:1] phase_in_cycles;
+ reg [`FIXED_WIDTH:1] phase_fixed;
+ reg [1:0] mx;
+ reg [5:0] delay_time;
+ reg [2:0] phase_mux;
+
+ reg [`FIXED_WIDTH:1] temp;
+
+ begin
+`ifdef DEBUG
+ $display("mmcm_pll_phase-divide:%d,phase:%d",
+ divide, phase);
+`endif
+
+ if ((phase < -360000) || (phase > 360000)) begin
+`ifndef SYNTHESIS
+ $display("ERROR: phase of $phase is not between -360000 and 360000");
+ `endif
+ $finish;
+ end
+
+ // If phase is less than 0, convert it to a positive phase shift
+ // Convert to (FIXED_WIDTH-FRAC_PRECISION).FRAC_PRECISION fixed point
+ if(phase < 0) begin
+ phase_fixed = ( (phase + 360000) << `FRAC_PRECISION ) / 1000;
+ end else begin
+ phase_fixed = ( phase << `FRAC_PRECISION ) / 1000;
+ end
+
+ // Put phase in terms of decimal number of vco clock cycles
+ phase_in_cycles = ( phase_fixed * divide ) / 360;
+
+`ifdef DEBUG
+ $display("phase_in_cycles: %h", phase_in_cycles);
+`endif
+
+
+ temp = round_frac(phase_in_cycles, 3);
+
+ // set mx to 2'b00 that the phase mux from the VCO is enabled
+ mx = 2'b00;
+ phase_mux = temp[`FRAC_PRECISION:`FRAC_PRECISION-2];
+ delay_time = temp[`FRAC_PRECISION+6:`FRAC_PRECISION+1];
+
+`ifdef DEBUG
+ $display("temp: %h", temp);
+`endif
+
+ // Setup the return value
+ mmcm_pll_phase={mx, phase_mux, delay_time};
+ end
+endfunction
+
+// This function takes the divide value and outputs the necessary lock values
+function [39:0] mmcm_pll_lock_lookup
+ (
+ input [6:0] divide // Max divide is 64
+ );
+
+ reg [2559:0] lookup;
+
+ begin
+ lookup = {
+ // This table is composed of:
+ // LockRefDly_LockFBDly_LockCnt_LockSatHigh_UnlockCnt
+ 40'b00110_00110_1111101000_1111101001_0000000001,
+ 40'b00110_00110_1111101000_1111101001_0000000001,
+ 40'b01000_01000_1111101000_1111101001_0000000001,
+ 40'b01011_01011_1111101000_1111101001_0000000001,
+ 40'b01110_01110_1111101000_1111101001_0000000001,
+ 40'b10001_10001_1111101000_1111101001_0000000001,
+ 40'b10011_10011_1111101000_1111101001_0000000001,
+ 40'b10110_10110_1111101000_1111101001_0000000001,
+ 40'b11001_11001_1111101000_1111101001_0000000001,
+ 40'b11100_11100_1111101000_1111101001_0000000001,
+ 40'b11111_11111_1110000100_1111101001_0000000001,
+ 40'b11111_11111_1100111001_1111101001_0000000001,
+ 40'b11111_11111_1011101110_1111101001_0000000001,
+ 40'b11111_11111_1010111100_1111101001_0000000001,
+ 40'b11111_11111_1010001010_1111101001_0000000001,
+ 40'b11111_11111_1001110001_1111101001_0000000001,
+ 40'b11111_11111_1000111111_1111101001_0000000001,
+ 40'b11111_11111_1000100110_1111101001_0000000001,
+ 40'b11111_11111_1000001101_1111101001_0000000001,
+ 40'b11111_11111_0111110100_1111101001_0000000001,
+ 40'b11111_11111_0111011011_1111101001_0000000001,
+ 40'b11111_11111_0111000010_1111101001_0000000001,
+ 40'b11111_11111_0110101001_1111101001_0000000001,
+ 40'b11111_11111_0110010000_1111101001_0000000001,
+ 40'b11111_11111_0110010000_1111101001_0000000001,
+ 40'b11111_11111_0101110111_1111101001_0000000001,
+ 40'b11111_11111_0101011110_1111101001_0000000001,
+ 40'b11111_11111_0101011110_1111101001_0000000001,
+ 40'b11111_11111_0101000101_1111101001_0000000001,
+ 40'b11111_11111_0101000101_1111101001_0000000001,
+ 40'b11111_11111_0100101100_1111101001_0000000001,
+ 40'b11111_11111_0100101100_1111101001_0000000001,
+ 40'b11111_11111_0100101100_1111101001_0000000001,
+ 40'b11111_11111_0100010011_1111101001_0000000001,
+ 40'b11111_11111_0100010011_1111101001_0000000001,
+ 40'b11111_11111_0100010011_1111101001_0000000001,
+ 40'b11111_11111_0011111010_1111101001_0000000001,
+ 40'b11111_11111_0011111010_1111101001_0000000001,
+ 40'b11111_11111_0011111010_1111101001_0000000001,
+ 40'b11111_11111_0011111010_1111101001_0000000001,
+ 40'b11111_11111_0011111010_1111101001_0000000001,
+ 40'b11111_11111_0011111010_1111101001_0000000001,
+ 40'b11111_11111_0011111010_1111101001_0000000001,
+ 40'b11111_11111_0011111010_1111101001_0000000001,
+ 40'b11111_11111_0011111010_1111101001_0000000001,
+ 40'b11111_11111_0011111010_1111101001_0000000001,
+ 40'b11111_11111_0011111010_1111101001_0000000001,
+ 40'b11111_11111_0011111010_1111101001_0000000001,
+ 40'b11111_11111_0011111010_1111101001_0000000001,
+ 40'b11111_11111_0011111010_1111101001_0000000001,
+ 40'b11111_11111_0011111010_1111101001_0000000001,
+ 40'b11111_11111_0011111010_1111101001_0000000001,
+ 40'b11111_11111_0011111010_1111101001_0000000001,
+ 40'b11111_11111_0011111010_1111101001_0000000001,
+ 40'b11111_11111_0011111010_1111101001_0000000001,
+ 40'b11111_11111_0011111010_1111101001_0000000001,
+ 40'b11111_11111_0011111010_1111101001_0000000001,
+ 40'b11111_11111_0011111010_1111101001_0000000001,
+ 40'b11111_11111_0011111010_1111101001_0000000001,
+ 40'b11111_11111_0011111010_1111101001_0000000001,
+ 40'b11111_11111_0011111010_1111101001_0000000001,
+ 40'b11111_11111_0011111010_1111101001_0000000001,
+ 40'b11111_11111_0011111010_1111101001_0000000001,
+ 40'b11111_11111_0011111010_1111101001_0000000001
+ };
+
+ // Set lookup_entry with the explicit bits from lookup with a part select
+ mmcm_pll_lock_lookup = lookup[ ((64-divide)*40) +: 40];
+ `ifdef DEBUG
+ $display("lock_lookup: %b", mmcm_pll_lock_lookup);
+ `endif
+ end
+endfunction
+
+// This function takes the divide value and the bandwidth setting of the PLL
+// and outputs the digital filter settings necessary.
+function [9:0] mmcm_pll_filter_lookup
+ (
+ input [6:0] divide, // Max divide is 64
+ input [8*9:0] BANDWIDTH
+ );
+
+ reg [639:0] lookup_low;
+ reg [639:0] lookup_high;
+
+ reg [9:0] lookup_entry;
+
+ begin
+ lookup_low = {
+ // CP_RES_LFHF
+ 10'b0010_1111_00,
+ 10'b0010_1111_00,
+ 10'b0010_0111_00,
+ 10'b0010_1101_00,
+ 10'b0010_0101_00,
+ 10'b0010_0101_00,
+ 10'b0010_1001_00,
+ 10'b0010_1110_00,
+ 10'b0010_1110_00,
+ 10'b0010_0001_00,
+ 10'b0010_0001_00,
+ 10'b0010_0110_00,
+ 10'b0010_0110_00,
+ 10'b0010_0110_00,
+ 10'b0010_0110_00,
+ 10'b0010_1010_00,
+ 10'b0010_1010_00,
+ 10'b0010_1010_00,
+ 10'b0010_1010_00,
+ 10'b0010_1100_00,
+ 10'b0010_1100_00,
+ 10'b0010_1100_00,
+ 10'b0010_1100_00,
+ 10'b0010_1100_00,
+ 10'b0010_1100_00,
+ 10'b0010_1100_00,
+ 10'b0010_1100_00,
+ 10'b0010_1100_00,
+ 10'b0010_1100_00,
+ 10'b0010_1100_00,
+ 10'b0010_0010_00,
+ 10'b0010_0010_00,
+ 10'b0010_0010_00,
+ 10'b0010_0010_00,
+ 10'b0010_0010_00,
+ 10'b0010_0010_00,
+ 10'b0010_0010_00,
+ 10'b0010_0010_00,
+ 10'b0010_0010_00,
+ 10'b0010_0010_00,
+ 10'b0011_1100_00,
+ 10'b0011_1100_00,
+ 10'b0011_1100_00,
+ 10'b0011_1100_00,
+ 10'b0011_1100_00,
+ 10'b0011_1100_00,
+ 10'b0011_1100_00,
+ 10'b0010_0100_00,
+ 10'b0010_0100_00,
+ 10'b0010_0100_00,
+ 10'b0010_0100_00,
+ 10'b0010_0100_00,
+ 10'b0010_0100_00,
+ 10'b0010_0100_00,
+ 10'b0010_0100_00,
+ 10'b0010_0100_00,
+ 10'b0010_0100_00,
+ 10'b0010_0100_00,
+ 10'b0010_0100_00,
+ 10'b0010_0100_00,
+ 10'b0010_0100_00,
+ 10'b0010_0100_00,
+ 10'b0010_0100_00,
+ 10'b0010_0100_00
+ };
+
+ lookup_high = {
+ // CP_RES_LFHF
+ 10'b0011_0111_00,
+ 10'b0011_0111_00,
+ 10'b0101_1111_00,
+ 10'b0111_1111_00,
+ 10'b0111_1011_00,
+ 10'b1101_0111_00,
+ 10'b1110_1011_00,
+ 10'b1110_1101_00,
+ 10'b1111_1101_00,
+ 10'b1111_0111_00,
+ 10'b1111_1011_00,
+ 10'b1111_1101_00,
+ 10'b1111_0011_00,
+ 10'b1110_0101_00,
+ 10'b1111_0101_00,
+ 10'b1111_0101_00,
+ 10'b1111_0101_00,
+ 10'b1111_0101_00,
+ 10'b0111_0110_00,
+ 10'b0111_0110_00,
+ 10'b0111_0110_00,
+ 10'b0111_0110_00,
+ 10'b0101_1100_00,
+ 10'b0101_1100_00,
+ 10'b0101_1100_00,
+ 10'b1100_0001_00,
+ 10'b1100_0001_00,
+ 10'b1100_0001_00,
+ 10'b1100_0001_00,
+ 10'b1100_0001_00,
+ 10'b1100_0001_00,
+ 10'b1100_0001_00,
+ 10'b1100_0001_00,
+ 10'b0100_0010_00,
+ 10'b0100_0010_00,
+ 10'b0100_0010_00,
+ 10'b0010_1000_00,
+ 10'b0010_1000_00,
+ 10'b0010_1000_00,
+ 10'b0011_0100_00,
+ 10'b0010_1000_00,
+ 10'b0010_1000_00,
+ 10'b0010_1000_00,
+ 10'b0010_1000_00,
+ 10'b0010_1000_00,
+ 10'b0010_1000_00,
+ 10'b0010_1000_00,
+ 10'b0010_1000_00,
+ 10'b0010_1000_00,
+ 10'b0010_1000_00,
+ 10'b0010_1000_00,
+ 10'b0010_1000_00,
+ 10'b0010_1000_00,
+ 10'b0100_1100_00,
+ 10'b0100_1100_00,
+ 10'b0100_1100_00,
+ 10'b0100_1100_00,
+ 10'b0100_1100_00,
+ 10'b0100_1100_00,
+ 10'b0100_1100_00,
+ 10'b0010_0100_00,
+ 10'b0010_0100_00,
+ 10'b0010_0100_00,
+ 10'b0010_0100_00
+ };
+
+ // Set lookup_entry with the explicit bits from lookup with a part select
+ if(BANDWIDTH == "LOW") begin
+ // Low Bandwidth
+ mmcm_pll_filter_lookup = lookup_low[ ((64-divide)*10) +: 10];
+ end else begin
+ // High or optimized bandwidth
+ mmcm_pll_filter_lookup = lookup_high[ ((64-divide)*10) +: 10];
+ end
+
+ `ifdef DEBUG
+ $display("filter_lookup: %b", mmcm_pll_filter_lookup);
+ `endif
+ end
+endfunction
+
+// This function takes in the divide, phase, and duty cycle
+// setting to calculate the upper and lower counter registers.
+function [37:0] mmcm_pll_count_calc
+ (
+ input [7:0] divide, // Max divide is 128
+ input signed [31:0] phase,
+ input [31:0] duty_cycle // Multiplied by 100,000
+ );
+
+ reg [13:0] div_calc;
+ reg [16:0] phase_calc;
+
+ begin
+ `ifdef DEBUG
+ $display("mmcm_pll_count_calc- divide:%h, phase:%d, duty_cycle:%d",
+ divide, phase, duty_cycle);
+`endif
+
+ // w_edge[13], no_count[12], high_time[11:6], low_time[5:0]
+ div_calc = mmcm_pll_divider(divide, duty_cycle);
+ // mx[10:9], pm[8:6], dt[5:0]
+ phase_calc = mmcm_pll_phase(divide, phase);
+
+ // Return value is the upper and lower address of counter
+ // Upper address is:
+ // RESERVED [31:26]
+ // MX [25:24]
+ // EDGE [23]
+ // NOCOUNT [22]
+ // DELAY_TIME [21:16]
+ // Lower Address is:
+ // PHASE_MUX [15:13]
+ // RESERVED [12]
+ // HIGH_TIME [11:6]
+ // LOW_TIME [5:0]
+
+`ifdef DEBUG
+ $display("div:%d dc:%d phase:%d ht:%d lt:%d ed:%d nc:%d mx:%d dt:%d pm:%d",
+ divide, duty_cycle, phase, div_calc[11:6], div_calc[5:0],
+ div_calc[13], div_calc[12],
+ phase_calc[16:15], phase_calc[5:0], phase_calc[14:12]);
+`endif
+
+ mmcm_pll_count_calc =
+ {
+ // Upper Address
+ 6'h00, phase_calc[10:9], div_calc[13:12], phase_calc[5:0],
+ // Lower Address
+ phase_calc[8:6], 1'b0, div_calc[11:0]
+ };
+ end
+endfunction
diff --git a/game.gen/sources_1/ip/clk_wiz_1/mmcm_pll_drp_func_us_mmcm.vh b/game.gen/sources_1/ip/clk_wiz_1/mmcm_pll_drp_func_us_mmcm.vh
new file mode 100755
index 0000000000000000000000000000000000000000..811d4338c6a31e6d63f2f3723d50fb55197e4acb
--- /dev/null
+++ b/game.gen/sources_1/ip/clk_wiz_1/mmcm_pll_drp_func_us_mmcm.vh
@@ -0,0 +1,671 @@
+///////////////////////////////////////////////////////////////////////////////
+//
+// Company: Xilinx
+// Engineer: Jim Tatsukawa
+// Date: 7/30/2014
+// Design Name: MMCME2 DRP
+// Module Name: mmcme2_drp_func.h
+// Version: 1.04
+// Target Devices: UltraScale Architecture || MMCM
+// Tool versions: 2014.3
+// Description: This header provides the functions necessary to
+// calculate the DRP register values for the V6 MMCM.
+//
+// Revision Notes: 3/22 - Updating lookup_low/lookup_high (CR)
+// 4/13 - Fractional divide function in mmcm_frac_count_calc function. CRS610807
+//
+// Disclaimer: XILINX IS PROVIDING THIS DESIGN, CODE, OR
+// INFORMATION "AS IS" SOLELY FOR USE IN DEVELOPING
+// PROGRAMS AND SOLUTIONS FOR XILINX DEVICES. BY
+// PROVIDING THIS DESIGN, CODE, OR INFORMATION AS
+// ONE POSSIBLE IMPLEMENTATION OF THIS FEATURE,
+// APPLICATION OR STANDARD, XILINX IS MAKING NO
+// REPRESENTATION THAT THIS IMPLEMENTATION IS FREE
+// FROM ANY CLAIMS OF INFRINGEMENT, AND YOU ARE
+// RESPONSIBLE FOR OBTAINING ANY RIGHTS YOU MAY
+// REQUIRE FOR YOUR IMPLEMENTATION. XILINX
+// EXPRESSLY DISCLAIMS ANY WARRANTY WHATSOEVER WITH
+// RESPECT TO THE ADEQUACY OF THE IMPLEMENTATION,
+// INCLUDING BUT NOT LIMITED TO ANY WARRANTIES OR
+// REPRESENTATIONS THAT THIS IMPLEMENTATION IS FREE
+// FROM CLAIMS OF INFRINGEMENT, IMPLIED WARRANTIES
+// OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
+// PURPOSE.
+//
+// (c) Copyright 2009-2010 Xilinx, Inc.
+// All rights reserved.
+//
+///////////////////////////////////////////////////////////////////////////////
+
+// These are user functions that should not be modified. Changes to the defines
+// or code within the functions may alter the accuracy of the calculations.
+
+// Define debug to provide extra messages durring elaboration
+//`define DEBUG 1
+
+// FRAC_PRECISION describes the width of the fractional portion of the fixed
+// point numbers. These should not be modified, they are for development
+// only
+`define FRAC_PRECISION 10
+// FIXED_WIDTH describes the total size for fixed point calculations(int+frac).
+// Warning: L.50 and below will not calculate properly with FIXED_WIDTHs
+// greater than 32
+`define FIXED_WIDTH 32
+
+// This function takes a fixed point number and rounds it to the nearest
+// fractional precision bit.
+function [`FIXED_WIDTH:1] round_frac
+ (
+ // Input is (FIXED_WIDTH-FRAC_PRECISION).FRAC_PRECISION fixed point number
+ input [`FIXED_WIDTH:1] decimal,
+
+ // This describes the precision of the fraction, for example a value
+ // of 1 would modify the fractional so that instead of being a .16
+ // fractional, it would be a .1 (rounded to the nearest 0.5 in turn)
+ input [`FIXED_WIDTH:1] precision
+ );
+
+ begin
+
+ `ifdef DEBUG
+ $display("round_frac - decimal: %h, precision: %h", decimal, precision);
+ `endif
+ // If the fractional precision bit is high then round up
+ if( decimal[(`FRAC_PRECISION-precision)] == 1'b1) begin
+ round_frac = decimal + (1'b1 << (`FRAC_PRECISION-precision));
+ end else begin
+ round_frac = decimal;
+ end
+ `ifdef DEBUG
+ $display("round_frac: %h", round_frac);
+ `endif
+ end
+endfunction
+
+// This function calculates high_time, low_time, w_edge, and no_count
+// of a non-fractional counter based on the divide and duty cycle
+//
+// NOTE: high_time and low_time are returned as integers between 0 and 63
+// inclusive. 64 should equal 6'b000000 (in other words it is okay to
+// ignore the overflow)
+function [13:0] mmcm_pll_divider
+ (
+ input [7:0] divide, // Max divide is 128
+ input [31:0] duty_cycle // Duty cycle is multiplied by 100,000
+ );
+
+ reg [`FIXED_WIDTH:1] duty_cycle_fix;
+
+ // High/Low time is initially calculated with a wider integer to prevent a
+ // calculation error when it overflows to 64.
+ reg [6:0] high_time;
+ reg [6:0] low_time;
+ reg w_edge;
+ reg no_count;
+
+ reg [`FIXED_WIDTH:1] temp;
+
+ begin
+ // Duty Cycle must be between 0 and 1,000
+ if(duty_cycle <=0 || duty_cycle >= 100000) begin
+`ifndef SYNTHESIS
+ $display("ERROR: duty_cycle: %d is invalid", duty_cycle);
+ `endif
+ $finish;
+ end
+
+ // Convert to FIXED_WIDTH-FRAC_PRECISION.FRAC_PRECISION fixed point
+ duty_cycle_fix = (duty_cycle << `FRAC_PRECISION) / 100_000;
+
+ `ifdef DEBUG
+ $display("duty_cycle_fix: %h", duty_cycle_fix);
+ `endif
+
+ // If the divide is 1 nothing needs to be set except the no_count bit.
+ // Other values are dummies
+ if(divide == 7'h01) begin
+ high_time = 7'h01;
+ w_edge = 1'b0;
+ low_time = 7'h01;
+ no_count = 1'b1;
+ end else begin
+ temp = round_frac(duty_cycle_fix*divide, 1);
+
+ // comes from above round_frac
+ high_time = temp[`FRAC_PRECISION+7:`FRAC_PRECISION+1];
+ // If the duty cycle * divide rounded is .5 or greater then this bit
+ // is set.
+ w_edge = temp[`FRAC_PRECISION]; // comes from round_frac
+
+ // If the high time comes out to 0, it needs to be set to at least 1
+ // and w_edge set to 0
+ if(high_time == 7'h00) begin
+ high_time = 7'h01;
+ w_edge = 1'b0;
+ end
+
+ if(high_time == divide) begin
+ high_time = divide - 1;
+ w_edge = 1'b1;
+ end
+
+ // Calculate low_time based on the divide setting and set no_count to
+ // 0 as it is only used when divide is 1.
+ low_time = divide - high_time;
+ no_count = 1'b0;
+ end
+
+ // Set the return value.
+ mmcm_pll_divider = {w_edge,no_count,high_time[5:0],low_time[5:0]};
+ end
+endfunction
+
+// This function calculates mx, delay_time, and phase_mux
+// of a non-fractional counter based on the divide and phase
+//
+// NOTE: The only valid value for the MX bits is 2'b00 to ensure the coarse mux
+// is used.
+function [10:0] mmcm_pll_phase
+ (
+ // divide must be an integer (use fractional if not)
+ // assumed that divide already checked to be valid
+ input [7:0] divide, // Max divide is 128
+
+ // Phase is given in degrees (-360,000 to 360,000)
+ input signed [31:0] phase
+ );
+
+ reg [`FIXED_WIDTH:1] phase_in_cycles;
+ reg [`FIXED_WIDTH:1] phase_fixed;
+ reg [1:0] mx;
+ reg [5:0] delay_time;
+ reg [2:0] phase_mux;
+
+ reg [`FIXED_WIDTH:1] temp;
+
+ begin
+`ifdef DEBUG
+ $display("mmcm_pll_phase-divide:%d,phase:%d",
+ divide, phase);
+`endif
+
+ if ((phase < -360000) || (phase > 360000)) begin
+`ifndef SYNTHESIS
+ $display("ERROR: phase of $phase is not between -360000 and 360000");
+ `endif
+ $finish;
+ end
+
+ // If phase is less than 0, convert it to a positive phase shift
+ // Convert to (FIXED_WIDTH-FRAC_PRECISION).FRAC_PRECISION fixed point
+ if(phase < 0) begin
+ phase_fixed = ( (phase + 360000) << `FRAC_PRECISION ) / 1000;
+ end else begin
+ phase_fixed = ( phase << `FRAC_PRECISION ) / 1000;
+ end
+
+ // Put phase in terms of decimal number of vco clock cycles
+ phase_in_cycles = ( phase_fixed * divide ) / 360;
+
+`ifdef DEBUG
+ $display("phase_in_cycles: %h", phase_in_cycles);
+`endif
+
+
+ temp = round_frac(phase_in_cycles, 3);
+
+ // set mx to 2'b00 that the phase mux from the VCO is enabled
+ mx = 2'b00;
+ phase_mux = temp[`FRAC_PRECISION:`FRAC_PRECISION-2];
+ delay_time = temp[`FRAC_PRECISION+6:`FRAC_PRECISION+1];
+
+ `ifdef DEBUG
+ $display("temp: %h", temp);
+ `endif
+
+ // Setup the return value
+ mmcm_pll_phase={mx, phase_mux, delay_time};
+ end
+endfunction
+
+// This function takes the divide value and outputs the necessary lock values
+function [39:0] mmcm_pll_lock_lookup
+ (
+ input [6:0] divide // Max divide is 64
+ );
+
+ reg [2559:0] lookup;
+
+ begin
+ lookup = {
+ // This table is composed of:
+ // LockRefDly_LockFBDly_LockCnt_LockSatHigh_UnlockCnt
+ 40'b00110_00110_1111101000_1111101001_0000000001,
+ 40'b00110_00110_1111101000_1111101001_0000000001,
+ 40'b01000_01000_1111101000_1111101001_0000000001,
+ 40'b01011_01011_1111101000_1111101001_0000000001,
+ 40'b01110_01110_1111101000_1111101001_0000000001,
+ 40'b10001_10001_1111101000_1111101001_0000000001,
+ 40'b10011_10011_1111101000_1111101001_0000000001,
+ 40'b10110_10110_1111101000_1111101001_0000000001,
+ 40'b11001_11001_1111101000_1111101001_0000000001,
+ 40'b11100_11100_1111101000_1111101001_0000000001,
+ 40'b11111_11111_1110000100_1111101001_0000000001,
+ 40'b11111_11111_1100111001_1111101001_0000000001,
+ 40'b11111_11111_1011101110_1111101001_0000000001,
+ 40'b11111_11111_1010111100_1111101001_0000000001,
+ 40'b11111_11111_1010001010_1111101001_0000000001,
+ 40'b11111_11111_1001110001_1111101001_0000000001,
+ 40'b11111_11111_1000111111_1111101001_0000000001,
+ 40'b11111_11111_1000100110_1111101001_0000000001,
+ 40'b11111_11111_1000001101_1111101001_0000000001,
+ 40'b11111_11111_0111110100_1111101001_0000000001,
+ 40'b11111_11111_0111011011_1111101001_0000000001,
+ 40'b11111_11111_0111000010_1111101001_0000000001,
+ 40'b11111_11111_0110101001_1111101001_0000000001,
+ 40'b11111_11111_0110010000_1111101001_0000000001,
+ 40'b11111_11111_0110010000_1111101001_0000000001,
+ 40'b11111_11111_0101110111_1111101001_0000000001,
+ 40'b11111_11111_0101011110_1111101001_0000000001,
+ 40'b11111_11111_0101011110_1111101001_0000000001,
+ 40'b11111_11111_0101000101_1111101001_0000000001,
+ 40'b11111_11111_0101000101_1111101001_0000000001,
+ 40'b11111_11111_0100101100_1111101001_0000000001,
+ 40'b11111_11111_0100101100_1111101001_0000000001,
+ 40'b11111_11111_0100101100_1111101001_0000000001,
+ 40'b11111_11111_0100010011_1111101001_0000000001,
+ 40'b11111_11111_0100010011_1111101001_0000000001,
+ 40'b11111_11111_0100010011_1111101001_0000000001,
+ 40'b11111_11111_0011111010_1111101001_0000000001,
+ 40'b11111_11111_0011111010_1111101001_0000000001,
+ 40'b11111_11111_0011111010_1111101001_0000000001,
+ 40'b11111_11111_0011111010_1111101001_0000000001,
+ 40'b11111_11111_0011111010_1111101001_0000000001,
+ 40'b11111_11111_0011111010_1111101001_0000000001,
+ 40'b11111_11111_0011111010_1111101001_0000000001,
+ 40'b11111_11111_0011111010_1111101001_0000000001,
+ 40'b11111_11111_0011111010_1111101001_0000000001,
+ 40'b11111_11111_0011111010_1111101001_0000000001,
+ 40'b11111_11111_0011111010_1111101001_0000000001,
+ 40'b11111_11111_0011111010_1111101001_0000000001,
+ 40'b11111_11111_0011111010_1111101001_0000000001,
+ 40'b11111_11111_0011111010_1111101001_0000000001,
+ 40'b11111_11111_0011111010_1111101001_0000000001,
+ 40'b11111_11111_0011111010_1111101001_0000000001,
+ 40'b11111_11111_0011111010_1111101001_0000000001,
+ 40'b11111_11111_0011111010_1111101001_0000000001,
+ 40'b11111_11111_0011111010_1111101001_0000000001,
+ 40'b11111_11111_0011111010_1111101001_0000000001,
+ 40'b11111_11111_0011111010_1111101001_0000000001,
+ 40'b11111_11111_0011111010_1111101001_0000000001,
+ 40'b11111_11111_0011111010_1111101001_0000000001,
+ 40'b11111_11111_0011111010_1111101001_0000000001,
+ 40'b11111_11111_0011111010_1111101001_0000000001,
+ 40'b11111_11111_0011111010_1111101001_0000000001,
+ 40'b11111_11111_0011111010_1111101001_0000000001,
+ 40'b11111_11111_0011111010_1111101001_0000000001
+ };
+
+ // Set lookup_entry with the explicit bits from lookup with a part select
+ mmcm_pll_lock_lookup = lookup[ ((64-divide)*40) +: 40];
+ `ifdef DEBUG
+ $display("lock_lookup: %b", mmcm_pll_lock_lookup);
+ `endif
+ end
+endfunction
+
+// This function takes the divide value and the bandwidth setting of the MMCM
+// and outputs the digital filter settings necessary.
+function [9:0] mmcm_pll_filter_lookup
+ (
+ input [6:0] divide, // Max divide is 64
+ input [8*9:0] BANDWIDTH
+ );
+
+ reg [639:0] lookup_low;
+ reg [639:0] lookup_high;
+
+ reg [9:0] lookup_entry;
+
+ begin
+ lookup_low = {
+ // CP_RES_LFHF
+ 10'b0010_1111_11,
+ 10'b0010_1111_11,
+ 10'b0010_1111_11,
+ 10'b0010_1111_11,
+ 10'b0010_1111_11,
+ 10'b0010_1111_11,
+ 10'b0010_0111_11,
+ 10'b0010_0111_11,
+ 10'b0010_0111_11,
+ 10'b0010_1101_11,
+ 10'b0010_1101_11,
+ 10'b0010_1101_11,
+ 10'b0010_0011_11,
+ 10'b0010_0101_11,
+ 10'b0010_0101_11,
+ 10'b0010_0101_11,
+ 10'b0010_1001_11,
+ 10'b0010_1001_11,
+ 10'b0010_1110_11,
+ 10'b0010_1110_11,
+ 10'b0010_1110_11,
+ 10'b0010_1110_11,
+ 10'b0010_1110_11,
+ 10'b0010_1110_11,
+ 10'b0010_0001_11,
+ 10'b0010_0001_11,
+ 10'b0010_0001_11,
+ 10'b0010_0001_11,
+ 10'b0010_0001_11,
+ 10'b0010_0110_11,
+ 10'b0010_0110_11,
+ 10'b0010_0110_11,
+ 10'b0010_0110_11,
+ 10'b0010_0110_11,
+ 10'b0010_0110_11,
+ 10'b0010_0110_11,
+ 10'b0010_0110_11,
+ 10'b0010_0110_11,
+ 10'b0010_0110_11,
+ 10'b0010_1010_11,
+ 10'b0010_1010_11,
+ 10'b0010_1010_11,
+ 10'b0010_1010_11,
+ 10'b0010_1010_11,
+ 10'b0010_1010_11,
+ 10'b0010_1010_11,
+ 10'b0010_1010_11,
+ 10'b0010_1100_11,
+ 10'b0010_1100_11,
+ 10'b0010_1100_11,
+ 10'b0010_1100_11,
+ 10'b0010_1100_11,
+ 10'b0010_1100_11,
+ 10'b0010_1100_11,
+ 10'b0010_1100_11,
+ 10'b0010_1100_11,
+ 10'b0010_1100_11,
+ 10'b0010_1100_11,
+ 10'b0010_1100_11,
+ 10'b0010_1100_11,
+ 10'b0010_1100_11,
+ 10'b0010_1100_11,
+ 10'b0010_1100_11,
+ 10'b0010_1100_11
+ };
+
+ lookup_high = {
+ // CP_RES_LFHF
+ 10'b0010_1111_11,
+ 10'b0010_1111_11,
+ 10'b0010_1011_11,
+ 10'b0011_1111_11,
+ 10'b0100_1111_11,
+ 10'b0100_1111_11,
+ 10'b0101_1111_11,
+ 10'b0110_1111_11,
+ 10'b0111_1111_11,
+ 10'b0111_1111_11,
+ 10'b1100_1111_11,
+ 10'b1101_1111_11,
+ 10'b1110_1111_11,
+ 10'b1111_1111_11,
+ 10'b1111_1111_11,
+ 10'b1110_0111_11,
+ 10'b1110_1011_11,
+ 10'b1111_0111_11,
+ 10'b1111_1011_11,
+ 10'b1111_1011_11,
+ 10'b1110_1101_11,
+ 10'b1111_1101_11,
+ 10'b1111_1101_11,
+ 10'b1111_0011_11,
+ 10'b1111_0011_11,
+ 10'b1111_0011_11,
+ 10'b1110_0101_11,
+ 10'b1110_0101_11,
+ 10'b1110_0101_11,
+ 10'b1111_0101_11,
+ 10'b1111_0101_11,
+ 10'b1111_0101_11,
+ 10'b1111_1001_11,
+ 10'b1111_1001_11,
+ 10'b1111_1001_11,
+ 10'b1111_1001_11,
+ 10'b1111_1001_11,
+ 10'b1110_1110_11,
+ 10'b1110_1110_11,
+ 10'b1110_1110_11,
+ 10'b1110_1110_11,
+ 10'b1111_1110_11,
+ 10'b1111_1110_11,
+ 10'b1111_1110_11,
+ 10'b1111_1110_11,
+ 10'b1111_1110_11,
+ 10'b1111_1110_11,
+ 10'b1111_1110_11,
+ 10'b1110_0001_11,
+ 10'b1110_0001_11,
+ 10'b1110_0001_11,
+ 10'b1110_0001_11,
+ 10'b1110_0001_11,
+ 10'b1100_0110_11,
+ 10'b1100_0110_11,
+ 10'b1100_0110_11,
+ 10'b1100_0110_11,
+ 10'b1100_0110_11,
+ 10'b1100_0110_11,
+ 10'b1100_0110_11,
+ 10'b1100_1010_11,
+ 10'b1100_1010_11,
+ 10'b1100_1010_11,
+ 10'b1100_1010_11
+ };
+
+ // Set lookup_entry with the explicit bits from lookup with a part select
+ if(BANDWIDTH == "LOW") begin
+ // Low Bandwidth
+ mmcm_pll_filter_lookup = lookup_low[ ((64-divide)*10) +: 10];
+ end else begin
+ // High or optimized bandwidth
+ mmcm_pll_filter_lookup = lookup_high[ ((64-divide)*10) +: 10];
+ end
+
+ `ifdef DEBUG
+ $display("filter_lookup: %b", mmcm_pll_filter_lookup);
+ `endif
+ end
+endfunction
+
+// This function takes in the divide, phase, and duty cycle
+// setting to calculate the upper and lower counter registers.
+function [37:0] mmcm_pll_count_calc
+ (
+ input [7:0] divide, // Max divide is 128
+ input signed [31:0] phase,
+ input [31:0] duty_cycle // Multiplied by 100,000
+ );
+
+ reg [13:0] div_calc;
+ reg [16:0] phase_calc;
+
+ begin
+ `ifdef DEBUG
+ $display("mmcm_pll_count_calc- divide:%h, phase:%d, duty_cycle:%d",
+ divide, phase, duty_cycle);
+ `endif
+
+ // w_edge[13], no_count[12], high_time[11:6], low_time[5:0]
+ div_calc = mmcm_pll_divider(divide, duty_cycle);
+ // mx[10:9], pm[8:6], dt[5:0]
+ phase_calc = mmcm_pll_phase(divide, phase);
+
+ // Return value is the upper and lower address of counter
+ // Upper address is:
+ // RESERVED [31:26]
+ // MX [25:24]
+ // EDGE [23]
+ // NOCOUNT [22]
+ // DELAY_TIME [21:16]
+ // Lower Address is:
+ // PHASE_MUX [15:13]
+ // RESERVED [12]
+ // HIGH_TIME [11:6]
+ // LOW_TIME [5:0]
+
+ `ifdef DEBUG
+ $display("div:%d dc:%d phase:%d ht:%d lt:%d ed:%d nc:%d mx:%d dt:%d pm:%d",
+ divide, duty_cycle, phase, div_calc[11:6], div_calc[5:0],
+ div_calc[13], div_calc[12],
+ phase_calc[16:15], phase_calc[5:0], phase_calc[14:12]);
+ `endif
+
+ mmcm_pll_count_calc =
+ {
+ // Upper Address
+ 6'h00, phase_calc[10:9], div_calc[13:12], phase_calc[5:0],
+ // Lower Address
+ phase_calc[8:6], 1'b0, div_calc[11:0]
+ };
+ end
+endfunction
+
+
+// This function takes in the divide, phase, and duty cycle
+// setting to calculate the upper and lower counter registers.
+// for fractional multiply/divide functions.
+//
+//
+function [37:0] mmcm_frac_count_calc
+ (
+ input [7:0] divide, // Max divide is 128
+ input signed [31:0] phase,
+ input [31:0] duty_cycle, // Multiplied by 1,000
+ input [9:0] frac // Multiplied by 1000
+ );
+
+ //Required for fractional divide calculations
+ reg [7:0] lt_frac;
+ reg [7:0] ht_frac;
+
+ reg /*[7:0]*/ wf_fall_frac;
+ reg /*[7:0]*/ wf_rise_frac;
+
+ reg [31:0] a;
+ reg [7:0] pm_rise_frac_filtered ;
+ reg [7:0] pm_fall_frac_filtered ;
+ reg [7:0] clkout0_divide_int;
+ reg [2:0] clkout0_divide_frac;
+ reg [7:0] even_part_high;
+ reg [7:0] even_part_low;
+
+ reg [7:0] odd;
+ reg [7:0] odd_and_frac;
+
+ reg [7:0] pm_fall;
+ reg [7:0] pm_rise;
+ reg [7:0] dt;
+ reg [7:0] dt_int;
+ reg [63:0] dt_calc;
+
+ reg [7:0] pm_rise_frac;
+ reg [7:0] pm_fall_frac;
+
+ reg [31:0] a_per_in_octets;
+ reg [31:0] a_phase_in_cycles;
+
+ parameter precision = 0.125;
+
+ reg [31:0] phase_fixed; // changed to 31:0 from 32:1 jt 5/2/11
+ reg [31: 0] phase_pos;
+ reg [31: 0] phase_vco;
+ reg [31:0] temp;// changed to 31:0 from 32:1 jt 5/2/11
+ reg [13:0] div_calc;
+ reg [16:0] phase_calc;
+
+ begin
+ `ifdef DEBUG
+ $display("mmcm_frac_count_calc- divide:%h, phase:%d, duty_cycle:%d",
+ divide, phase, duty_cycle);
+ `endif
+
+ //convert phase to fixed
+ if ((phase < -360000) || (phase > 360000)) begin
+`ifndef SYNTHESIS
+ $display("ERROR: phase of $phase is not between -360000 and 360000");
+ `endif
+ $finish;
+ end
+
+
+ // Return value is
+ // Transfer data
+ // RESERVED [37:36]
+ // FRAC_TIME [35:33]
+ // FRAC_WF_FALL [32]
+ // Upper address is:
+ // RESERVED [31:26]
+ // MX [25:24]
+ // EDGE [23]
+ // NOCOUNT [22]
+ // DELAY_TIME [21:16]
+ // Lower Address is:
+ // PHASE_MUX [15:13]
+ // RESERVED [12]
+ // HIGH_TIME [11:6]
+ // LOW_TIME [5:0]
+
+
+
+ clkout0_divide_frac = frac / 125;
+ clkout0_divide_int = divide;
+
+ even_part_high = clkout0_divide_int >> 1;//$rtoi(clkout0_divide_int / 2);
+ even_part_low = even_part_high;
+
+ odd = clkout0_divide_int - even_part_high - even_part_low;
+ odd_and_frac = (8*odd) + clkout0_divide_frac;
+
+ lt_frac = even_part_high - (odd_and_frac <= 9);//IF(odd_and_frac>9,even_part_high, even_part_high - 1)
+ ht_frac = even_part_low - (odd_and_frac <= 8);//IF(odd_and_frac>8,even_part_low, even_part_low- 1)
+
+ pm_fall = {odd[6:0],2'b00} + {6'h00, clkout0_divide_frac[2:1]}; // using >> instead of clkout0_divide_frac / 2
+ pm_rise = 0; //0
+
+ wf_fall_frac = ((odd_and_frac >=2) && (odd_and_frac <=9)) || ((clkout0_divide_frac == 1) && (clkout0_divide_int == 2));//CRS610807
+ wf_rise_frac = (odd_and_frac >=1) && (odd_and_frac <=8);//IF(odd_and_frac>=1,IF(odd_and_frac <= 8,1,0),0)
+
+
+
+ //Calculate phase in fractional cycles
+ a_per_in_octets = (8 * divide) + (frac / 125) ;
+ a_phase_in_cycles = (phase+10) * a_per_in_octets / 360000 ;//Adding 1 due to rounding errors
+ pm_rise_frac = (a_phase_in_cycles[7:0] ==8'h00)?8'h00:a_phase_in_cycles[7:0] - {a_phase_in_cycles[7:3],3'b000};
+
+ dt_calc = ((phase+10) * a_per_in_octets / 8 )/360000 ;//TRUNC(phase* divide / 360); //or_simply (a_per_in_octets / 8)
+ dt = dt_calc[7:0];
+
+ pm_rise_frac_filtered = (pm_rise_frac >=8) ? (pm_rise_frac ) - 8: pm_rise_frac ; //((phase_fixed * (divide + frac / 1000)) / 360) - {pm_rise_frac[7:3],3'b000};//$rtoi(clkout0_phase * clkout0_divide / 45);//a;
+
+ dt_int = dt + (& pm_rise_frac[7:4]); //IF(pm_rise_overwriting>7,dt+1,dt)
+ pm_fall_frac = pm_fall + pm_rise_frac;
+ pm_fall_frac_filtered = pm_fall + pm_rise_frac - {pm_fall_frac[7:3], 3'b000};
+
+ div_calc = mmcm_pll_divider(divide, duty_cycle); //Use to determine edge[7], no count[6]
+ phase_calc = mmcm_pll_phase(divide, phase);// returns{mx[1:0], phase_mux[2:0], delay_time[5:0]}
+
+ mmcm_frac_count_calc[37:0] =
+ { 2'b00, pm_fall_frac_filtered[2:0], wf_fall_frac,
+ 1'b0, clkout0_divide_frac[2:0], 1'b1, wf_rise_frac, phase_calc[10:9], div_calc[13:12], dt[5:0],
+ pm_rise_frac_filtered[2], pm_rise_frac_filtered[1], pm_rise_frac_filtered[0], 1'b0, ht_frac[5:0], lt_frac[5:0]
+ } ;
+
+ `ifdef DEBUG
+ $display("-%d.%d p%d>> :DADDR_9_15 frac30to28.frac_en.wf_r_frac.dt:%b%d%d_%b:DADDR_7_13 pm_f_frac_filtered_29to27.wf_f_frac_26:%b%d:DADDR_8_14.pm_r_frac_filt_15to13.ht_frac.lt_frac:%b%b%b:", divide, frac, phase, clkout0_divide_frac, 1, wf_rise_frac, dt, pm_fall_frac_filtered, wf_fall_frac, pm_rise_frac_filtered, ht_frac, lt_frac);
+ `endif
+
+ end
+endfunction
+
diff --git a/game.gen/sources_1/ip/clk_wiz_1/mmcm_pll_drp_func_us_pll.vh b/game.gen/sources_1/ip/clk_wiz_1/mmcm_pll_drp_func_us_pll.vh
new file mode 100755
index 0000000000000000000000000000000000000000..9439f2359ee141fd7306d4bf77f61ac6c416465f
--- /dev/null
+++ b/game.gen/sources_1/ip/clk_wiz_1/mmcm_pll_drp_func_us_pll.vh
@@ -0,0 +1,530 @@
+///////////////////////////////////////////////////////////////////////////////
+//
+// Company: Xilinx
+// Engineer: Jim Tatsukawa
+// Date: 6/15/2015
+// Design Name: PLLE3 DRP
+// Module Name: plle3_drp_func.h
+// Version: 1.10
+// Target Devices: UltraScale Architecture
+// Tool versions: 2015.1
+// Description: This header provides the functions necessary to
+// calculate the DRP register values for the V6 PLL.
+//
+// Revision Notes: 8/11 - PLLE3 updated for PLLE3 file 4564419
+// Revision Notes: 6/15 - pll_filter_lookup fixed for max M of 19
+// PM_Rise bits have been removed for PLLE3
+//
+// Disclaimer: XILINX IS PROVIDING THIS DESIGN, CODE, OR
+// INFORMATION "AS IS" SOLELY FOR USE IN DEVELOPING
+// PROGRAMS AND SOLUTIONS FOR XILINX DEVICES. BY
+// PROVIDING THIS DESIGN, CODE, OR INFORMATION AS
+// ONE POSSIBLE IMPLEMENTATION OF THIS FEATURE,
+// APPLICATION OR STANDARD, XILINX IS MAKING NO
+// REPRESENTATION THAT THIS IMPLEMENTATION IS FREE
+// FROM ANY CLAIMS OF INFRINGEMENT, AND YOU ARE
+// RESPONSIBLE FOR OBTAINING ANY RIGHTS YOU MAY
+// REQUIRE FOR YOUR IMPLEMENTATION. XILINX
+// EXPRESSLY DISCLAIMS ANY WARRANTY WHATSOEVER WITH
+// RESPECT TO THE ADEQUACY OF THE IMPLEMENTATION,
+// INCLUDING BUT NOT LIMITED TO ANY WARRANTIES OR
+// REPRESENTATIONS THAT THIS IMPLEMENTATION IS FREE
+// FROM CLAIMS OF INFRINGEMENT, IMPLIED WARRANTIES
+// OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
+// PURPOSE.
+//
+// (c) Copyright 2009-2010 Xilinx, Inc.
+// All rights reserved.
+//
+///////////////////////////////////////////////////////////////////////////////
+
+// These are user functions that should not be modified. Changes to the defines
+// or code within the functions may alter the accuracy of the calculations.
+
+// Define debug to provide extra messages durring elaboration
+//`define DEBUG 1
+
+// FRAC_PRECISION describes the width of the fractional portion of the fixed
+// point numbers. These should not be modified, they are for development
+// only
+`define FRAC_PRECISION 10
+// FIXED_WIDTH describes the total size for fixed point calculations(int+frac).
+// Warning: L.50 and below will not calculate properly with FIXED_WIDTHs
+// greater than 32
+`define FIXED_WIDTH 32
+
+// This function takes a fixed point number and rounds it to the nearest
+// fractional precision bit.
+function [`FIXED_WIDTH:1] round_frac
+ (
+ // Input is (FIXED_WIDTH-FRAC_PRECISION).FRAC_PRECISION fixed point number
+ input [`FIXED_WIDTH:1] decimal,
+
+ // This describes the precision of the fraction, for example a value
+ // of 1 would modify the fractional so that instead of being a .16
+ // fractional, it would be a .1 (rounded to the nearest 0.5 in turn)
+ input [`FIXED_WIDTH:1] precision
+ );
+
+ begin
+
+ `ifdef DEBUG
+ $display("round_frac - decimal: %h, precision: %h", decimal, precision);
+ `endif
+ // If the fractional precision bit is high then round up
+ if( decimal[(`FRAC_PRECISION-precision)] == 1'b1) begin
+ round_frac = decimal + (1'b1 << (`FRAC_PRECISION-precision));
+ end else begin
+ round_frac = decimal;
+ end
+ `ifdef DEBUG
+ $display("round_frac: %h", round_frac);
+ `endif
+ end
+endfunction
+
+// This function calculates high_time, low_time, w_edge, and no_count
+// of a non-fractional counter based on the divide and duty cycle
+//
+// NOTE: high_time and low_time are returned as integers between 0 and 63
+// inclusive. 64 should equal 6'b000000 (in other words it is okay to
+// ignore the overflow)
+function [13:0] mmcm_pll_divider
+ (
+ input [7:0] divide, // Max divide is 128
+ input [31:0] duty_cycle // Duty cycle is multiplied by 100,000
+ );
+
+ reg [`FIXED_WIDTH:1] duty_cycle_fix;
+
+ // High/Low time is initially calculated with a wider integer to prevent a
+ // calculation error when it overflows to 64.
+ reg [6:0] high_time;
+ reg [6:0] low_time;
+ reg w_edge;
+ reg no_count;
+
+ reg [`FIXED_WIDTH:1] temp;
+
+ begin
+ // Duty Cycle must be between 0 and 1,000
+ if(duty_cycle <=0 || duty_cycle >= 100000) begin
+`ifndef SYNTHESIS
+ $display("ERROR: duty_cycle: %d is invalid", duty_cycle);
+ `endif
+ $finish;
+ end
+
+ // Convert to FIXED_WIDTH-FRAC_PRECISION.FRAC_PRECISION fixed point
+ duty_cycle_fix = (duty_cycle << `FRAC_PRECISION) / 100_000;
+
+ `ifdef DEBUG
+ $display("duty_cycle_fix: %h", duty_cycle_fix);
+ `endif
+
+ // If the divide is 1 nothing needs to be set except the no_count bit.
+ // Other values are dummies
+ if(divide == 7'h01) begin
+ high_time = 7'h01;
+ w_edge = 1'b0;
+ low_time = 7'h01;
+ no_count = 1'b1;
+ end else begin
+ temp = round_frac(duty_cycle_fix*divide, 1);
+
+ // comes from above round_frac
+ high_time = temp[`FRAC_PRECISION+7:`FRAC_PRECISION+1];
+ // If the duty cycle * divide rounded is .5 or greater then this bit
+ // is set.
+ w_edge = temp[`FRAC_PRECISION]; // comes from round_frac
+
+ // If the high time comes out to 0, it needs to be set to at least 1
+ // and w_edge set to 0
+ if(high_time == 7'h00) begin
+ high_time = 7'h01;
+ w_edge = 1'b0;
+ end
+
+ if(high_time == divide) begin
+ high_time = divide - 1;
+ w_edge = 1'b1;
+ end
+
+ // Calculate low_time based on the divide setting and set no_count to
+ // 0 as it is only used when divide is 1.
+ low_time = divide - high_time;
+ no_count = 1'b0;
+ end
+
+ // Set the return value.
+ mmcm_pll_divider = {w_edge,no_count,high_time[5:0],low_time[5:0]};
+ end
+endfunction
+
+// This function calculates mx, delay_time, and phase_mux
+// of a non-fractional counter based on the divide and phase
+//
+// NOTE: The only valid value for the MX bits is 2'b00 to ensure the coarse mux
+// is used.
+function [10:0] mmcm_pll_phase
+ (
+ // divide must be an integer (use fractional if not)
+ // assumed that divide already checked to be valid
+ input [7:0] divide, // Max divide is 128
+
+ // Phase is given in degrees (-360,000 to 360,000)
+ input signed [31:0] phase
+ );
+
+ reg [`FIXED_WIDTH:1] phase_in_cycles;
+ reg [`FIXED_WIDTH:1] phase_fixed;
+ reg [1:0] mx;
+ reg [5:0] delay_time;
+ reg [2:0] phase_mux;
+
+ reg [`FIXED_WIDTH:1] temp;
+
+ begin
+`ifdef DEBUG
+ $display("mmcm_pll_phase-divide:%d,phase:%d",
+ divide, phase);
+`endif
+
+ if ((phase < -360000) || (phase > 360000)) begin
+`ifndef SYNTHESIS
+ $display("ERROR: phase of $phase is not between -360000 and 360000");
+ `endif
+ $finish;
+ end
+
+ // If phase is less than 0, convert it to a positive phase shift
+ // Convert to (FIXED_WIDTH-FRAC_PRECISION).FRAC_PRECISION fixed point
+ if(phase < 0) begin
+ phase_fixed = ( (phase + 360000) << `FRAC_PRECISION ) / 1000;
+ end else begin
+ phase_fixed = ( phase << `FRAC_PRECISION ) / 1000;
+ end
+
+ // Put phase in terms of decimal number of vco clock cycles
+ phase_in_cycles = ( phase_fixed * divide ) / 360;
+
+`ifdef DEBUG
+ $display("phase_in_cycles: %h", phase_in_cycles);
+`endif
+
+
+ temp = round_frac(phase_in_cycles, 3);
+
+ // set mx to 2'b00 that the phase mux from the VCO is enabled
+ mx = 2'b00;
+ phase_mux = temp[`FRAC_PRECISION:`FRAC_PRECISION-2];
+ delay_time = temp[`FRAC_PRECISION+6:`FRAC_PRECISION+1];
+
+ `ifdef DEBUG
+ $display("temp: %h", temp);
+ `endif
+
+ // Setup the return value
+ mmcm_pll_phase={mx, phase_mux, delay_time};
+ end
+endfunction
+
+// This function takes the divide value and outputs the necessary lock values
+function [39:0] mmcm_pll_lock_lookup
+ (
+ input [6:0] divide // Max divide is 64
+ );
+
+ reg [759:0] lookup;
+
+ begin
+ lookup = {
+ // This table is composed of:
+ // LockRefDly_LockFBDly_LockCnt_LockSatHigh_UnlockCnt
+ 40'b00110_00110_1111101000_1111101001_0000000001, //1
+ 40'b00110_00110_1111101000_1111101001_0000000001, //2
+ 40'b01000_01000_1111101000_1111101001_0000000001, //3
+ 40'b01011_01011_1111101000_1111101001_0000000001, //4
+ 40'b01110_01110_1111101000_1111101001_0000000001, //5
+ 40'b10001_10001_1111101000_1111101001_0000000001, //6
+ 40'b10011_10011_1111101000_1111101001_0000000001, //7
+ 40'b10110_10110_1111101000_1111101001_0000000001, //8
+ 40'b11001_11001_1111101000_1111101001_0000000001, //9
+ 40'b11100_11100_1111101000_1111101001_0000000001, //10
+ 40'b11111_11111_1110000100_1111101001_0000000001, //11
+ 40'b11111_11111_1100111001_1111101001_0000000001, //12
+ 40'b11111_11111_1011101110_1111101001_0000000001, //13
+ 40'b11111_11111_1010111100_1111101001_0000000001, //14
+ 40'b11111_11111_1010001010_1111101001_0000000001, //15
+ 40'b11111_11111_1001110001_1111101001_0000000001, //16
+ 40'b11111_11111_1000111111_1111101001_0000000001, //17
+ 40'b11111_11111_1000100110_1111101001_0000000001, //18
+ 40'b11111_11111_1000001101_1111101001_0000000001 //19
+
+ };
+
+ // Set lookup_entry with the explicit bits from lookup with a part select
+ mmcm_pll_lock_lookup = lookup[ ((19-divide)*40) +: 40];
+ `ifdef DEBUG
+ $display("lock_lookup: %b", mmcm_pll_lock_lookup);
+ `endif
+ end
+endfunction
+
+// This function takes the divide value and the bandwidth setting of the PLL
+// and outputs the digital filter settings necessary. Removing bandwidth setting for PLLE3.
+function [9:0] mmcm_pll_filter_lookup
+ (
+ input [6:0] divide // Max divide is 19
+ );
+
+ reg [639:0] lookup;
+ reg [9:0] lookup_entry;
+
+ begin
+
+ lookup = {
+ // CP_RES_LFHF
+ 10'b0010_1111_01, //1
+ 10'b0010_0011_11, //2
+ 10'b0011_0011_11, //3
+ 10'b0010_0001_11, //4
+ 10'b0010_0110_11, //5
+ 10'b0010_1010_11, //6
+ 10'b0010_1010_11, //7
+ 10'b0011_0110_11, //8
+ 10'b0010_1100_11, //9
+ 10'b0010_1100_11, //10
+ 10'b0010_1100_11, //11
+ 10'b0010_0010_11, //12
+ 10'b0011_1100_11, //13
+ 10'b0011_1100_11, //14
+ 10'b0011_1100_11, //15
+ 10'b0011_1100_11, //16
+ 10'b0011_0010_11, //17
+ 10'b0011_0010_11, //18
+ 10'b0011_0010_11 //19
+ };
+
+ mmcm_pll_filter_lookup = lookup [ ((19-divide)*10) +: 10];
+
+ `ifdef DEBUG
+ $display("filter_lookup: %b", mmcm_pll_filter_lookup);
+ `endif
+ end
+endfunction
+
+// This function set the CLKOUTPHY divide settings to match
+// the desired CLKOUTPHY_MODE setting. To create VCO_X2, then
+// the CLKOUTPHY will be set to 2'b00 since the VCO is internally
+// doubled and 2'b00 will represent divide by 1. Similarly "VCO" // will need to divide the doubled clock VCO clock frequency by // 2 therefore 2'b01 will match a divide by 2.And VCO_HALF will // need to divide the doubled VCO by 4, therefore 2'b10
+function [9:0] mmcm_pll_clkoutphy_calc
+ (
+ input [8*9:0] CLKOUTPHY_MODE
+ );
+
+ if(CLKOUTPHY_MODE == "VCO_X2") begin
+ mmcm_pll_clkoutphy_calc= 2'b00;
+ end else if(CLKOUTPHY_MODE == "VCO") begin
+ mmcm_pll_clkoutphy_calc= 2'b01;
+ end else if(CLKOUTPHY_MODE == "CLKIN") begin
+ mmcm_pll_clkoutphy_calc= 2'b11;
+ end else begin // Assume "VCO_HALF"
+ mmcm_pll_clkoutphy_calc= 2'b10;
+ end
+
+endfunction
+
+
+// This function takes in the divide, phase, and duty cycle
+// setting to calculate the upper and lower counter registers.
+function [37:0] mmcm_pll_count_calc
+ (
+ input [7:0] divide, // Max divide is 128
+ input signed [31:0] phase,
+ input [31:0] duty_cycle // Multiplied by 100,000
+ );
+
+ reg [13:0] div_calc;
+ reg [16:0] phase_calc;
+
+ begin
+ `ifdef DEBUG
+ $display("mmcm_pll_count_calc- divide:%h, phase:%d, duty_cycle:%d",
+ divide, phase, duty_cycle);
+ `endif
+
+ // w_edge[13], no_count[12], high_time[11:6], low_time[5:0]
+ div_calc = mmcm_pll_divider(divide, duty_cycle);
+ // mx[10:9], pm[8:6], dt[5:0]
+ phase_calc = mmcm_pll_phase(divide, phase);
+
+ // Return value is the upper and lower address of counter
+ // Upper address is:
+ // RESERVED [31:26]
+ // MX [25:24]
+ // EDGE [23]
+ // NOCOUNT [22]
+ // DELAY_TIME [21:16]
+ // Lower Address is:
+ // PHASE_MUX [15:13]
+ // RESERVED [12]
+ // HIGH_TIME [11:6]
+ // LOW_TIME [5:0]
+
+ `ifdef DEBUG
+ $display("div:%d dc:%d phase:%d ht:%d lt:%d ed:%d nc:%d mx:%d dt:%d pm:%d",
+ divide, duty_cycle, phase, div_calc[11:6], div_calc[5:0],
+ div_calc[13], div_calc[12],
+ phase_calc[16:15], phase_calc[5:0], 3'b000);//Removed PM_Rise bits
+ `endif
+
+ mmcm_pll_count_calc =
+ {
+ // Upper Address
+ 6'h00, phase_calc[10:9], div_calc[13:12], phase_calc[5:0],
+ // Lower Address
+ phase_calc[8:6], 1'b0, div_calc[11:0]
+ };
+ end
+endfunction
+
+
+// This function takes in the divide, phase, and duty cycle
+// setting to calculate the upper and lower counter registers.
+// for fractional multiply/divide functions.
+//
+//
+function [37:0] mmcm_pll_frac_count_calc
+ (
+ input [7:0] divide, // Max divide is 128
+ input signed [31:0] phase,
+ input [31:0] duty_cycle, // Multiplied by 1,000
+ input [9:0] frac // Multiplied by 1000
+ );
+
+ //Required for fractional divide calculations
+ reg [7:0] lt_frac;
+ reg [7:0] ht_frac;
+
+ reg /*[7:0]*/ wf_fall_frac;
+ reg /*[7:0]*/ wf_rise_frac;
+
+ reg [31:0] a;
+ reg [7:0] pm_rise_frac_filtered ;
+ reg [7:0] pm_fall_frac_filtered ;
+ reg [7:0] clkout0_divide_int;
+ reg [2:0] clkout0_divide_frac;
+ reg [7:0] even_part_high;
+ reg [7:0] even_part_low;
+
+ reg [7:0] odd;
+ reg [7:0] odd_and_frac;
+
+ reg [7:0] pm_fall;
+ reg [7:0] pm_rise;
+ reg [7:0] dt;
+ reg [7:0] dt_int;
+ reg [63:0] dt_calc;
+
+ reg [7:0] pm_rise_frac;
+ reg [7:0] pm_fall_frac;
+
+ reg [31:0] a_per_in_octets;
+ reg [31:0] a_phase_in_cycles;
+
+ parameter precision = 0.125;
+
+ reg [31:0] phase_fixed; // changed to 31:0 from 32:1 jt 5/2/11
+ reg [31: 0] phase_pos;
+ reg [31: 0] phase_vco;
+ reg [31:0] temp;// changed to 31:0 from 32:1 jt 5/2/11
+ reg [13:0] div_calc;
+ reg [16:0] phase_calc;
+
+ begin
+ `ifdef DEBUG
+ $display("mmcm_pll_frac_count_calc- divide:%h, phase:%d, duty_cycle:%d",
+ divide, phase, duty_cycle);
+ `endif
+
+ //convert phase to fixed
+ if ((phase < -360000) || (phase > 360000)) begin
+`ifndef SYNTHESIS
+ $display("ERROR: phase of $phase is not between -360000 and 360000");
+ `endif
+ $finish;
+ end
+
+
+ // Return value is
+ // Transfer data
+ // RESERVED [37:36]
+ // FRAC_TIME [35:33]
+ // FRAC_WF_FALL [32]
+ // Upper address is:
+ // RESERVED [31:26]
+ // MX [25:24]
+ // EDGE [23]
+ // NOCOUNT [22]
+ // DELAY_TIME [21:16]
+ // Lower Address is:
+ // PHASE_MUX [15:13]
+ // RESERVED [12]
+ // HIGH_TIME [11:6]
+ // LOW_TIME [5:0]
+
+
+
+ clkout0_divide_frac = frac / 125;
+ clkout0_divide_int = divide;
+
+ even_part_high = clkout0_divide_int >> 1;//$rtoi(clkout0_divide_int / 2);
+ even_part_low = even_part_high;
+
+ odd = clkout0_divide_int - even_part_high - even_part_low;
+ odd_and_frac = (8*odd) + clkout0_divide_frac;
+
+ lt_frac = even_part_high - (odd_and_frac <= 9);//IF(odd_and_frac>9,even_part_high, even_part_high - 1)
+ ht_frac = even_part_low - (odd_and_frac <= 8);//IF(odd_and_frac>8,even_part_low, even_part_low- 1)
+
+ pm_fall = {odd[6:0],2'b00} + {6'h00, clkout0_divide_frac[2:1]}; // using >> instead of clkout0_divide_frac / 2
+ pm_rise = 0; //0
+
+ wf_fall_frac = (odd_and_frac >=2) && (odd_and_frac <=9);//IF(odd_and_frac>=2,IF(odd_and_frac <= 9,1,0),0)
+ wf_rise_frac = (odd_and_frac >=1) && (odd_and_frac <=8);//IF(odd_and_frac>=1,IF(odd_and_frac <= 8,1,0),0)
+
+
+
+ //Calculate phase in fractional cycles
+ a_per_in_octets = (8 * divide) + (frac / 125) ;
+ a_phase_in_cycles = (phase+10) * a_per_in_octets / 360000 ;//Adding 1 due to rounding errors
+ pm_rise_frac = (a_phase_in_cycles[7:0] ==8'h00)?8'h00:a_phase_in_cycles[7:0] - {a_phase_in_cycles[7:3],3'b000};
+
+ dt_calc = ((phase+10) * a_per_in_octets / 8 )/360000 ;//TRUNC(phase* divide / 360); //or_simply (a_per_in_octets / 8)
+ dt = dt_calc[7:0];
+
+ pm_rise_frac_filtered = (pm_rise_frac >=8) ? (pm_rise_frac ) - 8: pm_rise_frac ; //((phase_fixed * (divide + frac / 1000)) / 360) - {pm_rise_frac[7:3],3'b000};//$rtoi(clkout0_phase * clkout0_divide / 45);//a;
+
+ dt_int = dt + (& pm_rise_frac[7:4]); //IF(pm_rise_overwriting>7,dt+1,dt)
+ pm_fall_frac = pm_fall + pm_rise_frac;
+ pm_fall_frac_filtered = pm_fall + pm_rise_frac - {pm_fall_frac[7:3], 3'b000};
+
+ div_calc = mmcm_pll_divider(divide, duty_cycle); //Use to determine edge[7], no count[6]
+ phase_calc = mmcm_pll_phase(divide, phase);// returns{mx[1:0], phase_mux[2:0], delay_time[5:0]}
+
+ mmcm_pll_frac_count_calc[37:0] =
+ { 2'b00, pm_fall_frac_filtered[2:0], wf_fall_frac,
+ 1'b0, clkout0_divide_frac[2:0], 1'b1, wf_rise_frac, phase_calc[10:9], div_calc[13:12], dt[5:0],
+ 3'b000, 1'b0, ht_frac[5:0], lt_frac[5:0] //Removed PM_Rise bits
+// pm_rise_frac_filtered[2], pm_rise_frac_filtered[1], pm_rise_frac_filtered[0], 1'b0, ht_frac[5:0], lt_frac[5:0]
+ } ;
+
+ `ifdef DEBUG
+ $display("-%d.%d p%d>> :DADDR_9_15 frac30to28.frac_en.wf_r_frac.dt:%b%d%d_%b:DADDR_7_13 pm_f_frac_filtered_29to27.wf_f_frac_26:%b%d:DADDR_8_14.pm_r_frac_filt_15to13.ht_frac.lt_frac:%b%b%b:", divide, frac, phase, clkout0_divide_frac, 1, wf_rise_frac, dt, pm_fall_frac_filtered, wf_fall_frac, 3'b000, ht_frac, lt_frac);
+ `endif
+
+ end
+endfunction
+
+
diff --git a/game.gen/sources_1/ip/clk_wiz_1/mmcm_pll_drp_func_us_plus_mmcm.vh b/game.gen/sources_1/ip/clk_wiz_1/mmcm_pll_drp_func_us_plus_mmcm.vh
new file mode 100755
index 0000000000000000000000000000000000000000..ebf87be0b41af231c503eefb0859dbe93dbe8cd4
--- /dev/null
+++ b/game.gen/sources_1/ip/clk_wiz_1/mmcm_pll_drp_func_us_plus_mmcm.vh
@@ -0,0 +1,861 @@
+///////////////////////////////////////////////////////////////////////////////
+//
+// Company: Xilinx
+// Engineer: Jim Tatsukawa. Updated by Ralf Krueger
+// Date: 7/30/2014
+// Design Name: MMCME4 DRP
+// Module Name: mmcme4_drp_func.h
+// Version: 1.31
+// Target Devices: UltraScale Plus Architecture
+// Tool versions: 2017.1
+// Description: This header provides the functions necessary to
+// calculate the DRP register values for UltraScal+ MMCM.
+//
+// Revision Notes: 3/22 - Updating lookup_low/lookup_high (CR)
+// 4/13 - Fractional divide function in mmcm_frac_count_calc function
+// 2/28/17 - Updated for Ultrascale Plus
+//
+// Disclaimer: XILINX IS PROVIDING THIS DESIGN, CODE, OR
+// INFORMATION "AS IS" SOLELY FOR USE IN DEVELOPING
+// PROGRAMS AND SOLUTIONS FOR XILINX DEVICES. BY
+// PROVIDING THIS DESIGN, CODE, OR INFORMATION AS
+// ONE POSSIBLE IMPLEMENTATION OF THIS FEATURE,
+// APPLICATION OR STANDARD, XILINX IS MAKING NO
+// REPRESENTATION THAT THIS IMPLEMENTATION IS FREE
+// FROM ANY CLAIMS OF INFRINGEMENT, AND YOU ARE
+// RESPONSIBLE FOR OBTAINING ANY RIGHTS YOU MAY
+// REQUIRE FOR YOUR IMPLEMENTATION. XILINX
+// EXPRESSLY DISCLAIMS ANY WARRANTY WHATSOEVER WITH
+// RESPECT TO THE ADEQUACY OF THE IMPLEMENTATION,
+// INCLUDING BUT NOT LIMITED TO ANY WARRANTIES OR
+// REPRESENTATIONS THAT THIS IMPLEMENTATION IS FREE
+// FROM CLAIMS OF INFRINGEMENT, IMPLIED WARRANTIES
+// OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
+// PURPOSE.
+//
+// (c) Copyright 2009-2017 Xilinx, Inc.
+// All rights reserved.
+//
+///////////////////////////////////////////////////////////////////////////////
+
+// These are user functions that should not be modified. Changes to the defines
+// or code within the functions may alter the accuracy of the calculations.
+
+// Define debug to provide extra messages during elaboration
+//`define DEBUG 1
+
+// FRAC_PRECISION describes the width of the fractional portion of the fixed
+// point numbers. These should not be modified, they are for development only
+`define FRAC_PRECISION 10
+// FIXED_WIDTH describes the total size for fixed point calculations(int+frac).
+// Warning: L.50 and below will not calculate properly with FIXED_WIDTHs
+// greater than 32
+`define FIXED_WIDTH 32
+
+// This function takes a fixed point number and rounds it to the nearest
+// fractional precision bit.
+function [`FIXED_WIDTH:1] round_frac
+ (
+ // Input is (FIXED_WIDTH-FRAC_PRECISION).FRAC_PRECISION fixed point number
+ input [`FIXED_WIDTH:1] decimal,
+
+ // This describes the precision of the fraction, for example a value
+ // of 1 would modify the fractional so that instead of being a .16
+ // fractional, it would be a .1 (rounded to the nearest 0.5 in turn)
+ input [`FIXED_WIDTH:1] precision
+ );
+
+ begin
+
+ `ifdef DEBUG
+ $display("round_frac - decimal: %h, precision: %h", decimal, precision);
+ `endif
+ // If the fractional precision bit is high then round up
+ if( decimal[(`FRAC_PRECISION-precision)] == 1'b1) begin
+ round_frac = decimal + (1'b1 << (`FRAC_PRECISION-precision));
+ end else begin
+ round_frac = decimal;
+ end
+ `ifdef DEBUG
+ $display("round_frac: %h", round_frac);
+ `endif
+ end
+endfunction
+
+// This function calculates high_time, low_time, w_edge, and no_count
+// of a non-fractional counter based on the divide and duty cycle
+//
+// NOTE: high_time and low_time are returned as integers between 0 and 63
+// inclusive. 64 should equal 6'b000000 (in other words it is okay to
+// ignore the overflow)
+function [13:0] mmcm_pll_divider
+ (
+ input [7:0] divide, // Max divide is 128
+ input [31:0] duty_cycle // Duty cycle is multiplied by 100,000
+ );
+
+ reg [`FIXED_WIDTH:1] duty_cycle_fix;
+
+ // High/Low time is initially calculated with a wider integer to prevent a
+ // calculation error when it overflows to 64.
+ reg [6:0] high_time;
+ reg [6:0] low_time;
+ reg w_edge;
+ reg no_count;
+
+ reg [`FIXED_WIDTH:1] temp;
+
+ begin
+ // Duty Cycle must be between 0 and 1,000
+ if(duty_cycle <=0 || duty_cycle >= 100000) begin
+`ifndef SYNTHESIS
+ $display("ERROR: duty_cycle: %d is invalid", duty_cycle);
+ `endif
+ $finish;
+ end
+
+ // Convert to FIXED_WIDTH-FRAC_PRECISION.FRAC_PRECISION fixed point
+ duty_cycle_fix = (duty_cycle << `FRAC_PRECISION) / 100_000;
+
+ `ifdef DEBUG
+ $display("duty_cycle_fix: %h", duty_cycle_fix);
+ `endif
+
+ // If the divide is 1 nothing needs to be set except the no_count bit.
+ // Other values are dummies
+ if(divide == 7'h01) begin
+ high_time = 7'h01;
+ w_edge = 1'b0;
+ low_time = 7'h01;
+ no_count = 1'b1;
+ end else begin
+ temp = round_frac(duty_cycle_fix*divide, 1);
+
+ // comes from above round_frac
+ high_time = temp[`FRAC_PRECISION+7:`FRAC_PRECISION+1];
+ // If the duty cycle * divide rounded is .5 or greater then this bit
+ // is set.
+ w_edge = temp[`FRAC_PRECISION]; // comes from round_frac
+
+ // If the high time comes out to 0, it needs to be set to at least 1
+ // and w_edge set to 0
+ if(high_time == 7'h00) begin
+ high_time = 7'h01;
+ w_edge = 1'b0;
+ end
+
+ if(high_time == divide) begin
+ high_time = divide - 1;
+ w_edge = 1'b1;
+ end
+
+ // Calculate low_time based on the divide setting and set no_count to
+ // 0 as it is only used when divide is 1.
+ low_time = divide - high_time;
+ no_count = 1'b0;
+ end
+
+ // Set the return value.
+ mmcm_pll_divider = {w_edge,no_count,high_time[5:0],low_time[5:0]};
+ end
+endfunction
+
+// This function calculates mx, delay_time, and phase_mux
+// of a non-fractional counter based on the divide and phase
+//
+// NOTE: The only valid value for the MX bits is 2'b00 to ensure the coarse mux
+// is used.
+function [10:0] mmcm_pll_phase
+ (
+ // divide must be an integer (use fractional if not)
+ // assumed that divide already checked to be valid
+ input [7:0] divide, // Max divide is 128
+
+ // Phase is given in degrees (-360,000 to 360,000)
+ input signed [31:0] phase
+ );
+
+ reg [`FIXED_WIDTH:1] phase_in_cycles;
+ reg [`FIXED_WIDTH:1] phase_fixed;
+ reg [1:0] mx;
+ reg [5:0] delay_time;
+ reg [2:0] phase_mux;
+
+ reg [`FIXED_WIDTH:1] temp;
+
+ begin
+`ifdef DEBUG
+ $display("mmcm_phase-divide:%d,phase:%d", divide, phase);
+`endif
+
+ if ((phase < -360000) || (phase > 360000)) begin
+`ifndef SYNTHESIS
+ $display("ERROR: phase of $phase is not between -360000 and 360000");
+ `endif
+ $finish;
+ end
+
+ // If phase is less than 0, convert it to a positive phase shift
+ // Convert to (FIXED_WIDTH-FRAC_PRECISION).FRAC_PRECISION fixed point
+ if(phase < 0) begin
+ phase_fixed = ( (phase + 360000) << `FRAC_PRECISION ) / 1000;
+ end else begin
+ phase_fixed = ( phase << `FRAC_PRECISION ) / 1000;
+ end
+
+ // Put phase in terms of decimal number of vco clock cycles
+ phase_in_cycles = ( phase_fixed * divide ) / 360;
+
+`ifdef DEBUG
+ $display("phase_in_cycles: %h", phase_in_cycles);
+`endif
+
+ temp = round_frac(phase_in_cycles, 3);
+
+ // set mx to 2'b00 that the phase mux from the VCO is enabled
+ mx = 2'b00;
+ phase_mux = temp[`FRAC_PRECISION:`FRAC_PRECISION-2];
+ delay_time = temp[`FRAC_PRECISION+6:`FRAC_PRECISION+1];
+
+ `ifdef DEBUG
+ $display("temp: %h", temp);
+ `endif
+
+ // Setup the return value
+ mmcm_pll_phase={mx, phase_mux, delay_time};
+ end
+endfunction
+
+// This function takes the divide value and outputs the necessary lock values
+function [39:0] mmcm_pll_lock_lookup
+ (
+ input [7:0] divide // Max M divide is 128 in UltrascalePlus
+ );
+
+ reg [5119:0] lookup;
+
+ begin
+ lookup = {
+ // This table is composed of:
+ // LockRefDly_LockFBDly_LockCnt_LockSatHigh_UnlockCnt
+ 40'b00110_00110_1111101000_1111101001_0000000001, // M=1 (not allowed)
+ 40'b00110_00110_1111101000_1111101001_0000000001, // M=2
+ 40'b01000_01000_1111101000_1111101001_0000000001, // M=3
+ 40'b01011_01011_1111101000_1111101001_0000000001, // M=4
+ 40'b01110_01110_1111101000_1111101001_0000000001, // M=5
+ 40'b10001_10001_1111101000_1111101001_0000000001, // M=6
+ 40'b10011_10011_1111101000_1111101001_0000000001, // M=7
+ 40'b10110_10110_1111101000_1111101001_0000000001,
+ 40'b11001_11001_1111101000_1111101001_0000000001,
+ 40'b11100_11100_1111101000_1111101001_0000000001,
+ 40'b11111_11111_1110000100_1111101001_0000000001,
+ 40'b11111_11111_1100111001_1111101001_0000000001,
+ 40'b11111_11111_1011101110_1111101001_0000000001,
+ 40'b11111_11111_1010111100_1111101001_0000000001,
+ 40'b11111_11111_1010001010_1111101001_0000000001,
+ 40'b11111_11111_1001110001_1111101001_0000000001,
+ 40'b11111_11111_1000111111_1111101001_0000000001,
+ 40'b11111_11111_1000100110_1111101001_0000000001,
+ 40'b11111_11111_1000001101_1111101001_0000000001,
+ 40'b11111_11111_0111110100_1111101001_0000000001,
+ 40'b11111_11111_0111011011_1111101001_0000000001,
+ 40'b11111_11111_0111000010_1111101001_0000000001,
+ 40'b11111_11111_0110101001_1111101001_0000000001,
+ 40'b11111_11111_0110010000_1111101001_0000000001,
+ 40'b11111_11111_0110010000_1111101001_0000000001,
+ 40'b11111_11111_0101110111_1111101001_0000000001,
+ 40'b11111_11111_0101011110_1111101001_0000000001,
+ 40'b11111_11111_0101011110_1111101001_0000000001,
+ 40'b11111_11111_0101000101_1111101001_0000000001,
+ 40'b11111_11111_0101000101_1111101001_0000000001,
+ 40'b11111_11111_0100101100_1111101001_0000000001,
+ 40'b11111_11111_0100101100_1111101001_0000000001,
+ 40'b11111_11111_0100101100_1111101001_0000000001,
+ 40'b11111_11111_0100010011_1111101001_0000000001,
+ 40'b11111_11111_0100010011_1111101001_0000000001,
+ 40'b11111_11111_0100010011_1111101001_0000000001,
+ 40'b11111_11111_0011111010_1111101001_0000000001,
+ 40'b11111_11111_0011111010_1111101001_0000000001,
+ 40'b11111_11111_0011111010_1111101001_0000000001,
+ 40'b11111_11111_0011111010_1111101001_0000000001,
+ 40'b11111_11111_0011111010_1111101001_0000000001,
+ 40'b11111_11111_0011111010_1111101001_0000000001,
+ 40'b11111_11111_0011111010_1111101001_0000000001,
+ 40'b11111_11111_0011111010_1111101001_0000000001,
+ 40'b11111_11111_0011111010_1111101001_0000000001,
+ 40'b11111_11111_0011111010_1111101001_0000000001,
+ 40'b11111_11111_0011111010_1111101001_0000000001,
+ 40'b11111_11111_0011111010_1111101001_0000000001,
+ 40'b11111_11111_0011111010_1111101001_0000000001,
+ 40'b11111_11111_0011111010_1111101001_0000000001,
+ 40'b11111_11111_0011111010_1111101001_0000000001,
+ 40'b11111_11111_0011111010_1111101001_0000000001,
+ 40'b11111_11111_0011111010_1111101001_0000000001,
+ 40'b11111_11111_0011111010_1111101001_0000000001,
+ 40'b11111_11111_0011111010_1111101001_0000000001,
+ 40'b11111_11111_0011111010_1111101001_0000000001,
+ 40'b11111_11111_0011111010_1111101001_0000000001,
+ 40'b11111_11111_0011111010_1111101001_0000000001,
+ 40'b11111_11111_0011111010_1111101001_0000000001,
+ 40'b11111_11111_0011111010_1111101001_0000000001,
+ 40'b11111_11111_0011111010_1111101001_0000000001,
+ 40'b11111_11111_0011111010_1111101001_0000000001,
+ 40'b11111_11111_0011111010_1111101001_0000000001,
+ 40'b11111_11111_0011111010_1111101001_0000000001,
+ 40'b11111_11111_0011111010_1111101001_0000000001,
+ 40'b11111_11111_0011111010_1111101001_0000000001,
+ 40'b11111_11111_0011111010_1111101001_0000000001,
+ 40'b11111_11111_0011111010_1111101001_0000000001,
+ 40'b11111_11111_0011111010_1111101001_0000000001,
+ 40'b11111_11111_0011111010_1111101001_0000000001,
+ 40'b11111_11111_0011111010_1111101001_0000000001,
+ 40'b11111_11111_0011111010_1111101001_0000000001,
+ 40'b11111_11111_0011111010_1111101001_0000000001,
+ 40'b11111_11111_0011111010_1111101001_0000000001,
+ 40'b11111_11111_0011111010_1111101001_0000000001,
+ 40'b11111_11111_0011111010_1111101001_0000000001,
+ 40'b11111_11111_0011111010_1111101001_0000000001,
+ 40'b11111_11111_0011111010_1111101001_0000000001,
+ 40'b11111_11111_0011111010_1111101001_0000000001,
+ 40'b11111_11111_0011111010_1111101001_0000000001,
+ 40'b11111_11111_0011111010_1111101001_0000000001,
+ 40'b11111_11111_0011111010_1111101001_0000000001,
+ 40'b11111_11111_0011111010_1111101001_0000000001,
+ 40'b11111_11111_0011111010_1111101001_0000000001,
+ 40'b11111_11111_0011111010_1111101001_0000000001,
+ 40'b11111_11111_0011111010_1111101001_0000000001,
+ 40'b11111_11111_0011111010_1111101001_0000000001,
+ 40'b11111_11111_0011111010_1111101001_0000000001,
+ 40'b11111_11111_0011111010_1111101001_0000000001,
+ 40'b11111_11111_0011111010_1111101001_0000000001,
+ 40'b11111_11111_0011111010_1111101001_0000000001,
+ 40'b11111_11111_0011111010_1111101001_0000000001,
+ 40'b11111_11111_0011111010_1111101001_0000000001,
+ 40'b11111_11111_0011111010_1111101001_0000000001,
+ 40'b11111_11111_0011111010_1111101001_0000000001,
+ 40'b11111_11111_0011111010_1111101001_0000000001,
+ 40'b11111_11111_0011111010_1111101001_0000000001,
+ 40'b11111_11111_0011111010_1111101001_0000000001,
+ 40'b11111_11111_0011111010_1111101001_0000000001,
+ 40'b11111_11111_0011111010_1111101001_0000000001,
+ 40'b11111_11111_0011111010_1111101001_0000000001,
+ 40'b11111_11111_0011111010_1111101001_0000000001,
+ 40'b11111_11111_0011111010_1111101001_0000000001,
+ 40'b11111_11111_0011111010_1111101001_0000000001,
+ 40'b11111_11111_0011111010_1111101001_0000000001,
+ 40'b11111_11111_0011111010_1111101001_0000000001,
+ 40'b11111_11111_0011111010_1111101001_0000000001,
+ 40'b11111_11111_0011111010_1111101001_0000000001,
+ 40'b11111_11111_0011111010_1111101001_0000000001,
+ 40'b11111_11111_0011111010_1111101001_0000000001,
+ 40'b11111_11111_0011111010_1111101001_0000000001,
+ 40'b11111_11111_0011111010_1111101001_0000000001,
+ 40'b11111_11111_0011111010_1111101001_0000000001,
+ 40'b11111_11111_0011111010_1111101001_0000000001,
+ 40'b11111_11111_0011111010_1111101001_0000000001,
+ 40'b11111_11111_0011111010_1111101001_0000000001,
+ 40'b11111_11111_0011111010_1111101001_0000000001,
+ 40'b11111_11111_0011111010_1111101001_0000000001,
+ 40'b11111_11111_0011111010_1111101001_0000000001,
+ 40'b11111_11111_0011111010_1111101001_0000000001,
+ 40'b11111_11111_0011111010_1111101001_0000000001,
+ 40'b11111_11111_0011111010_1111101001_0000000001,
+ 40'b11111_11111_0011111010_1111101001_0000000001,
+ 40'b11111_11111_0011111010_1111101001_0000000001,
+ 40'b11111_11111_0011111010_1111101001_0000000001,
+ 40'b11111_11111_0011111010_1111101001_0000000001,
+ 40'b11111_11111_0011111010_1111101001_0000000001, // M=127
+ 40'b11111_11111_0011111010_1111101001_0000000001 // M=128
+ };
+
+ // Set lookup_entry with the explicit bits from lookup with a part select
+ mmcm_pll_lock_lookup = lookup[ ((128-divide)*40) +: 40];
+ `ifdef DEBUG
+ $display("lock_lookup: %b", mmcm_pll_lock_lookup);
+ `endif
+ end
+endfunction
+
+// This function takes the divide value and the bandwidth setting of the MMCM
+// and outputs the digital filter settings necessary.
+function [9:0] mmcm_pll_filter_lookup
+ (
+ input [7:0] divide, // input [7:0] divide // Max M divide is 128 in UltraScalePlus
+ input [8*9:0] BANDWIDTH
+ );
+
+ reg [1279:0] lookup_low;
+ reg [1279:0] lookup_high;
+
+ reg [9:0] lookup_entry;
+
+ begin
+ lookup_low = {
+ // CP_RES_LFHF
+ 10'b0011_1111_11, // M=1 - not legal
+ 10'b0011_1111_11, // M=2
+ 10'b0011_1101_11, // M=3
+ 10'b0011_0101_11, // M=4
+ 10'b0011_1001_11, // M=5
+ 10'b0011_1110_11, // M=6
+ 10'b0011_1110_11, // M=7
+ 10'b0011_0001_11,
+ 10'b0011_0110_11,
+ 10'b0011_0110_11,
+ 10'b0011_0110_11,
+ 10'b0011_1010_11,
+ 10'b0011_1010_11,
+ 10'b0011_1010_11,
+ 10'b0100_0110_11,
+ 10'b0011_1100_11,
+ 10'b1110_0110_11,
+ 10'b1111_0110_11,
+ 10'b1110_1010_11,
+ 10'b1110_1010_11,
+ 10'b1111_1010_11,
+ 10'b1111_1010_11,
+ 10'b1111_1010_11,
+ 10'b1111_1010_11,
+ 10'b1111_1010_11,
+ 10'b1101_1100_11,
+ 10'b1101_1100_11,
+ 10'b1101_1100_11,
+ 10'b1110_1100_11,
+ 10'b1110_1100_11,
+ 10'b1110_1100_11,
+ 10'b1111_1100_11,
+ 10'b1111_1100_11,
+ 10'b1111_1100_11,
+ 10'b1111_1100_11,
+ 10'b1111_1100_11,
+ 10'b1111_1100_11,
+ 10'b1110_0010_11,
+ 10'b1110_0010_11,
+ 10'b1110_0010_11,
+ 10'b1110_0010_11,
+ 10'b1111_0010_11,
+ 10'b1111_0010_11,
+ 10'b1111_0010_11,
+ 10'b1111_0010_11,
+ 10'b1111_0010_11,
+ 10'b1111_0010_11,
+ 10'b1111_0010_11,
+ 10'b1111_0010_11,
+ 10'b1111_0010_11,
+ 10'b1111_0010_11,
+ 10'b1111_0010_11,
+ 10'b1111_0010_11,
+ 10'b1111_0010_11,
+ 10'b1111_0010_11,
+ 10'b1111_0010_11,
+ 10'b1111_0010_11,
+ 10'b1111_0010_11,
+ 10'b1111_0010_11,
+ 10'b1111_0010_11,
+ 10'b1111_0010_11,
+ 10'b1111_0010_11,
+ 10'b1100_0100_11,
+ 10'b1100_0100_11,
+ 10'b1100_0100_11,
+ 10'b1100_0100_11,
+ 10'b1100_0100_11,
+ 10'b1100_0100_11,
+ 10'b1100_0100_11,
+ 10'b1100_0100_11,
+ 10'b1101_0100_11,
+ 10'b1101_0100_11,
+ 10'b1101_0100_11,
+ 10'b1101_0100_11,
+ 10'b1101_0100_11,
+ 10'b1101_0100_11,
+ 10'b1101_0100_11,
+ 10'b1110_0100_11,
+ 10'b1110_0100_11,
+ 10'b1110_0100_11,
+ 10'b1110_0100_11,
+ 10'b1110_0100_11,
+ 10'b1110_0100_11,
+ 10'b1110_0100_11,
+ 10'b1110_0100_11,
+ 10'b1111_0100_11,
+ 10'b1111_0100_11,
+ 10'b1111_0100_11,
+ 10'b1111_0100_11,
+ 10'b1111_0100_11,
+ 10'b1111_0100_11,
+ 10'b1111_0100_11,
+ 10'b1111_0100_11,
+ 10'b1111_0100_11,
+ 10'b1111_0100_11,
+ 10'b1111_0100_11,
+ 10'b1111_0100_11,
+ 10'b1111_0100_11,
+ 10'b1111_0100_11,
+ 10'b1111_0100_11,
+ 10'b1111_0100_11,
+ 10'b1111_0100_11,
+ 10'b1111_0100_11,
+ 10'b1111_0100_11,
+ 10'b1111_0100_11,
+ 10'b1111_0100_11,
+ 10'b1111_0100_11,
+ 10'b1111_0100_11,
+ 10'b1111_0100_11,
+ 10'b1111_0100_11,
+ 10'b1111_0100_11,
+ 10'b1111_0100_11,
+ 10'b1111_0100_11,
+ 10'b1111_0100_11,
+ 10'b1111_0100_11,
+ 10'b1111_0100_11,
+ 10'b1111_0100_11,
+ 10'b1111_0100_11,
+ 10'b1111_0100_11,
+ 10'b1101_1000_11,
+ 10'b1101_1000_11,
+ 10'b1101_1000_11,
+ 10'b1101_1000_11,
+ 10'b1101_1000_11,
+ 10'b1101_1000_11,
+ 10'b1101_1000_11,
+ 10'b1101_1000_11, // M=127
+ 10'b1101_1000_11 // M=128
+};
+
+ lookup_high = {
+ // CP_RES_LFHF
+ 10'b0111_1111_11, // M=1 - not legal
+ 10'b0111_1111_11, // M=2
+ 10'b1110_1111_11, // M=3
+ 10'b1111_1111_11, // M=4
+ 10'b1111_1011_11, // M=5
+ 10'b1111_1101_11, // M=6
+ 10'b1111_0011_11, // M=7
+ 10'b1110_0101_11,
+ 10'b1111_1001_11,
+ 10'b1111_1001_11,
+ 10'b1110_1110_11,
+ 10'b1111_1110_11,
+ 10'b1111_0001_11,
+ 10'b1111_0001_11,
+ 10'b1111_0001_11,
+ 10'b1110_0110_11,
+ 10'b1110_0110_11,
+ 10'b1111_0110_11,
+ 10'b1110_1010_11,
+ 10'b1110_1010_11,
+ 10'b1111_1010_11,
+ 10'b1111_1010_11,
+ 10'b1111_1010_11,
+ 10'b1111_1010_11,
+ 10'b1111_1010_11,
+ 10'b1101_1100_11,
+ 10'b1101_1100_11,
+ 10'b1101_1100_11,
+ 10'b1110_1100_11,
+ 10'b1110_1100_11,
+ 10'b1110_1100_11,
+ 10'b1111_1100_11,
+ 10'b1111_1100_11,
+ 10'b1111_1100_11,
+ 10'b1111_1100_11,
+ 10'b1111_1100_11,
+ 10'b1111_1100_11,
+ 10'b1110_0010_11,
+ 10'b1110_0010_11,
+ 10'b1110_0010_11,
+ 10'b1110_0010_11,
+ 10'b1111_0010_11,
+ 10'b1111_0010_11,
+ 10'b1111_0010_11,
+ 10'b1111_0010_11,
+ 10'b1111_0010_11,
+ 10'b1111_0010_11,
+ 10'b1111_0010_11,
+ 10'b1111_0010_11,
+ 10'b1111_0010_11,
+ 10'b1111_0010_11,
+ 10'b1111_0010_11,
+ 10'b1111_0010_11,
+ 10'b1111_0010_11,
+ 10'b1111_0010_11,
+ 10'b1111_0010_11,
+ 10'b1111_0010_11,
+ 10'b1111_0010_11,
+ 10'b1111_0010_11,
+ 10'b1111_0010_11,
+ 10'b1111_0010_11,
+ 10'b1111_0010_11,
+ 10'b1100_0100_11,
+ 10'b1100_0100_11,
+ 10'b1100_0100_11,
+ 10'b1100_0100_11,
+ 10'b1100_0100_11,
+ 10'b1100_0100_11,
+ 10'b1100_0100_11,
+ 10'b1100_0100_11,
+ 10'b1101_0100_11,
+ 10'b1101_0100_11,
+ 10'b1101_0100_11,
+ 10'b1101_0100_11,
+ 10'b1101_0100_11,
+ 10'b1101_0100_11,
+ 10'b1101_0100_11,
+ 10'b1110_0100_11,
+ 10'b1110_0100_11,
+ 10'b1110_0100_11,
+ 10'b1110_0100_11,
+ 10'b1110_0100_11,
+ 10'b1110_0100_11,
+ 10'b1110_0100_11,
+ 10'b1110_0100_11,
+ 10'b1111_0100_11,
+ 10'b1111_0100_11,
+ 10'b1111_0100_11,
+ 10'b1111_0100_11,
+ 10'b1111_0100_11,
+ 10'b1111_0100_11,
+ 10'b1111_0100_11,
+ 10'b1111_0100_11,
+ 10'b1111_0100_11,
+ 10'b1111_0100_11,
+ 10'b1111_0100_11,
+ 10'b1111_0100_11,
+ 10'b1111_0100_11,
+ 10'b1111_0100_11,
+ 10'b1111_0100_11,
+ 10'b1111_0100_11,
+ 10'b1111_0100_11,
+ 10'b1111_0100_11,
+ 10'b1111_0100_11,
+ 10'b1111_0100_11,
+ 10'b1111_0100_11,
+ 10'b1111_0100_11,
+ 10'b1111_0100_11,
+ 10'b1111_0100_11,
+ 10'b1111_0100_11,
+ 10'b1111_0100_11,
+ 10'b1111_0100_11,
+ 10'b1111_0100_11,
+ 10'b1111_0100_11,
+ 10'b1111_0100_11,
+ 10'b1111_0100_11,
+ 10'b1111_0100_11,
+ 10'b1111_0100_11,
+ 10'b1111_0100_11,
+ 10'b1101_1000_11,
+ 10'b1101_1000_11,
+ 10'b1101_1000_11,
+ 10'b1101_1000_11,
+ 10'b1101_1000_11,
+ 10'b1101_1000_11,
+ 10'b1101_1000_11,
+ 10'b1101_1000_11,
+ 10'b1101_1000_11 // M=128
+};
+
+ // Set lookup_entry with the explicit bits from lookup with a part select
+ if(BANDWIDTH == "LOW") begin
+ // Low Bandwidth
+ mmcm_pll_filter_lookup = lookup_low[ ((128-divide)*10) +: 10];
+ end else begin
+ // High or optimized bandwidth
+ mmcm_pll_filter_lookup = lookup_high[ ((128-divide)*10) +: 10];
+ end
+
+ `ifdef DEBUG
+ $display("filter_lookup: %b", mmcm_pll_filter_lookup);
+ `endif
+ end
+endfunction
+
+// This function takes in the divide, phase, and duty cycle
+// setting to calculate the upper and lower counter registers.
+function [37:0] mmcm_pll_count_calc
+ (
+ input [7:0] divide, // Max divide is 128
+ input signed [31:0] phase,
+ input [31:0] duty_cycle // Multiplied by 100,000
+ );
+
+ reg [13:0] div_calc;
+ reg [16:0] phase_calc;
+
+ begin
+ `ifdef DEBUG
+ $display("mmcm_pll_count_calc- divide:%h, phase:%d, duty_cycle:%d",
+ divide, phase, duty_cycle);
+ `endif
+
+ // w_edge[13], no_count[12], high_time[11:6], low_time[5:0]
+ div_calc = mmcm_pll_divider(divide, duty_cycle);
+ // mx[10:9], pm[8:6], dt[5:0]
+ phase_calc = mmcm_pll_phase(divide, phase);
+
+ // Return value is the upper and lower address of counter
+ // Upper address is:
+ // RESERVED [31:26]
+ // MX [25:24]
+ // EDGE [23]
+ // NOCOUNT [22]
+ // DELAY_TIME [21:16]
+ // Lower Address is:
+ // PHASE_MUX [15:13]
+ // RESERVED [12]
+ // HIGH_TIME [11:6]
+ // LOW_TIME [5:0]
+
+ `ifdef DEBUG
+ $display("div:%d dc:%d phase:%d ht:%d lt:%d ed:%d nc:%d mx:%d dt:%d pm:%d",
+ divide, duty_cycle, phase, div_calc[11:6], div_calc[5:0],
+ div_calc[13], div_calc[12],
+ phase_calc[16:15], phase_calc[5:0], phase_calc[14:12]);
+ `endif
+
+ mmcm_pll_count_calc =
+ {
+ // Upper Address
+ 6'h00, phase_calc[10:9], div_calc[13:12], phase_calc[5:0],
+ // Lower Address
+ phase_calc[8:6], 1'b0, div_calc[11:0]
+ };
+ end
+endfunction
+
+
+// This function takes in the divide, phase, and duty cycle
+// setting to calculate the upper and lower counter registers.
+// for fractional multiply/divide functions.
+//
+//
+function [37:0] mmcm_frac_count_calc
+ (
+ input [7:0] divide, // Max divide is 128
+ input signed [31:0] phase,
+ input [31:0] duty_cycle, // Multiplied by 100,000. Not programmable in fractional
+ input [9:0] frac // Multiplied by 1000
+ );
+
+ //Required for fractional divide calculations
+ reg [7:0] lt_frac;
+ reg [7:0] ht_frac;
+
+ reg /*[7:0]*/ wf_fall_frac;
+ reg /*[7:0]*/ wf_rise_frac;
+
+ reg [31:0] a;
+ reg [7:0] pm_rise_frac_filtered ;
+ reg [7:0] pm_fall_frac_filtered ;
+ reg [7:0] clkout0_divide_int;
+ reg [2:0] clkout0_divide_frac;
+ reg [7:0] even_part_high;
+ reg [7:0] even_part_low;
+
+ reg [7:0] odd;
+ reg [7:0] odd_and_frac;
+
+ reg [7:0] pm_fall;
+ reg [7:0] pm_rise;
+ reg [7:0] dt;
+ reg [7:0] dt_int;
+ reg [63:0] dt_calc;
+
+ reg [7:0] pm_rise_frac;
+ reg [7:0] pm_fall_frac;
+
+ reg [31:0] a_per_in_octets;
+ reg [31:0] a_phase_in_cycles;
+
+ parameter precision = 0.125;
+
+ reg [31:0] phase_fixed; // changed to 31:0 from 32:1 jt 5/2/11
+ reg [31: 0] phase_pos;
+ reg [31: 0] phase_vco;
+ reg [31:0] temp;// changed to 31:0 from 32:1 jt 5/2/11
+ reg [13:0] div_calc;
+ reg [16:0] phase_calc;
+
+ begin
+ `ifdef DEBUG
+ $display("mmcm_frac_count_calc- divide:%h, phase:%d, duty_cycle:%d",
+ divide, phase, duty_cycle);
+ `endif
+
+ //convert phase to fixed
+ if ((phase < -360000) || (phase > 360000)) begin
+`ifndef SYNTHESIS
+ $display("ERROR: phase of $phase is not between -360000 and 360000");
+ `endif
+ $finish;
+ end
+
+
+ // Return value is
+ // Transfer data
+ // RESERVED [37:36]
+ // FRAC_TIME [35:33]
+ // FRAC_WF_FALL [32]
+ // Upper address is:
+ // RESERVED [31:26]
+ // MX [25:24]
+ // EDGE [23]
+ // NOCOUNT [22]
+ // DELAY_TIME [21:16]
+ // Lower Address is:
+ // PHASE_MUX [15:13]
+ // RESERVED [12]
+ // HIGH_TIME [11:6]
+ // LOW_TIME [5:0]
+
+
+
+ clkout0_divide_frac = frac / 125;
+ clkout0_divide_int = divide;
+
+ even_part_high = clkout0_divide_int >> 1;//$rtoi(clkout0_divide_int / 2);
+ even_part_low = even_part_high;
+
+ odd = clkout0_divide_int - even_part_high - even_part_low;
+ odd_and_frac = (8*odd) + clkout0_divide_frac;
+
+ lt_frac = even_part_high - (odd_and_frac <= 9);//IF(odd_and_frac>9,even_part_high, even_part_high - 1)
+ ht_frac = even_part_low - (odd_and_frac <= 8);//IF(odd_and_frac>8,even_part_low, even_part_low- 1)
+
+ pm_fall = {odd[6:0],2'b00} + {6'h00, clkout0_divide_frac[2:1]}; // using >> instead of clkout0_divide_frac / 2
+ pm_rise = 0; //0
+
+ wf_fall_frac = ((odd_and_frac >=2) && (odd_and_frac <=9)) || (clkout0_divide_int == 2 && clkout0_divide_frac == 1); //IF(odd_and_frac>=2,IF(odd_and_frac <= 9,1,0),0)
+ wf_rise_frac = (odd_and_frac >=1) && (odd_and_frac <=8); //IF(odd_and_frac>=1,IF(odd_and_frac <= 8,1,0),0)
+
+
+
+ //Calculate phase in fractional cycles
+ a_per_in_octets = (8 * divide) + (frac / 125) ;
+ a_phase_in_cycles = (phase+10) * a_per_in_octets / 360000 ;//Adding 1 due to rounding errors
+ pm_rise_frac = (a_phase_in_cycles[7:0] ==8'h00)?8'h00:a_phase_in_cycles[7:0] - {a_phase_in_cycles[7:3],3'b000};
+
+ dt_calc = ((phase+10) * a_per_in_octets / 8 )/360000 ;//TRUNC(phase* divide / 360); //or_simply (a_per_in_octets / 8)
+ dt = dt_calc[7:0];
+
+ pm_rise_frac_filtered = (pm_rise_frac >=8) ? (pm_rise_frac ) - 8: pm_rise_frac ; //((phase_fixed * (divide + frac / 1000)) / 360) - {pm_rise_frac[7:3],3'b000};//$rtoi(clkout0_phase * clkout0_divide / 45);//a;
+
+ dt_int = dt + (& pm_rise_frac[7:4]); //IF(pm_rise_overwriting>7,dt+1,dt)
+ pm_fall_frac = pm_fall + pm_rise_frac;
+ pm_fall_frac_filtered = pm_fall + pm_rise_frac - {pm_fall_frac[7:3], 3'b000};
+
+ div_calc = mmcm_pll_divider(divide, duty_cycle); //Use to determine edge[7], no count[6]
+ phase_calc = mmcm_pll_phase(divide, phase);// returns{mx[1:0], phase_mux[2:0], delay_time[5:0]}
+
+ mmcm_frac_count_calc[37:0] =
+ { 2'b00, pm_fall_frac_filtered[2:0], wf_fall_frac,
+ 1'b0, clkout0_divide_frac[2:0], 1'b1, wf_rise_frac, phase_calc[10:9], 2'b00, dt[5:0],
+ pm_rise_frac_filtered[2], pm_rise_frac_filtered[1], pm_rise_frac_filtered[0], 1'b0, ht_frac[5:0], lt_frac[5:0]
+ } ;
+
+ `ifdef DEBUG
+ $display("-%d.%d p%d>> :DADDR_9_15 frac30to28.frac_en.wf_r_frac.dt:%b%d%d_%b:DADDR_7_13 pm_f_frac_filtered_29to27.wf_f_frac_26:%b%d:DADDR_8_14.pm_r_frac_filt_15to13.ht_frac.lt_frac:%b%b%b:", divide, frac, phase, clkout0_divide_frac, 1, wf_rise_frac, dt, pm_fall_frac_filtered, wf_fall_frac, pm_rise_frac_filtered, ht_frac, lt_frac);
+ `endif
+
+ end
+endfunction
+
diff --git a/game.gen/sources_1/ip/clk_wiz_1/mmcm_pll_drp_func_us_plus_pll.vh b/game.gen/sources_1/ip/clk_wiz_1/mmcm_pll_drp_func_us_plus_pll.vh
new file mode 100755
index 0000000000000000000000000000000000000000..1d2dc690993b37ed296d61be5c6c2aaad1de90c1
--- /dev/null
+++ b/game.gen/sources_1/ip/clk_wiz_1/mmcm_pll_drp_func_us_plus_pll.vh
@@ -0,0 +1,536 @@
+///////////////////////////////////////////////////////////////////////////////
+//
+// Company: Xilinx
+// Engineer: Jim Tatsukawa, Ralf Krueger, updated for Ultrascale+
+// Date: 6/15/2015
+// Design Name: PLLE4 DRP
+// Module Name: plle4_drp_func.h
+// Version: 2.0
+// Target Devices: UltraScale+ Architecture
+// Tool versions: 2017.1
+// Description: This header provides the functions necessary to
+// calculate the DRP register values for the V6 PLL.
+//
+// Revision Notes: 8/11 - PLLE3 updated for PLLE3 file 4564419
+// Revision Notes: 6/15 - pll_filter_lookup fixed for max M of 19
+// M_Rise bits have been removed for PLLE3
+// Revision Notes: 2/28/17 - pll_filter_lookup and CPRES updated for
+// Ultrascale+ and for max M of 21
+//
+// Disclaimer: XILINX IS PROVIDING THIS DESIGN, CODE, OR
+// INFORMATION "AS IS" SOLELY FOR USE IN DEVELOPING
+// PROGRAMS AND SOLUTIONS FOR XILINX DEVICES. BY
+// PROVIDING THIS DESIGN, CODE, OR INFORMATION AS
+// ONE POSSIBLE IMPLEMENTATION OF THIS FEATURE,
+// APPLICATION OR STANDARD, XILINX IS MAKING NO
+// REPRESENTATION THAT THIS IMPLEMENTATION IS FREE
+// FROM ANY CLAIMS OF INFRINGEMENT, AND YOU ARE
+// RESPONSIBLE FOR OBTAINING ANY RIGHTS YOU MAY
+// REQUIRE FOR YOUR IMPLEMENTATION. XILINX
+// EXPRESSLY DISCLAIMS ANY WARRANTY WHATSOEVER WITH
+// RESPECT TO THE ADEQUACY OF THE IMPLEMENTATION,
+// INCLUDING BUT NOT LIMITED TO ANY WARRANTIES OR
+// REPRESENTATIONS THAT THIS IMPLEMENTATION IS FREE
+// FROM CLAIMS OF INFRINGEMENT, IMPLIED WARRANTIES
+// OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
+// PURPOSE.
+//
+// (c) Copyright 2009-2017 Xilinx, Inc.
+// All rights reserved.
+//
+///////////////////////////////////////////////////////////////////////////////
+
+// These are user functions that should not be modified. Changes to the defines
+// or code within the functions may alter the accuracy of the calculations.
+
+// Define debug to provide extra messages durring elaboration
+//`define DEBUG 1
+
+// FRAC_PRECISION describes the width of the fractional portion of the fixed
+// point numbers. These should not be modified, they are for development
+// only
+`define FRAC_PRECISION 10
+// FIXED_WIDTH describes the total size for fixed point calculations(int+frac).
+// Warning: L.50 and below will not calculate properly with FIXED_WIDTHs
+// greater than 32
+`define FIXED_WIDTH 32
+
+// This function takes a fixed point number and rounds it to the nearest
+// fractional precision bit.
+function [`FIXED_WIDTH:1] round_frac
+ (
+ // Input is (FIXED_WIDTH-FRAC_PRECISION).FRAC_PRECISION fixed point number
+ input [`FIXED_WIDTH:1] decimal,
+
+ // This describes the precision of the fraction, for example a value
+ // of 1 would modify the fractional so that instead of being a .16
+ // fractional, it would be a .1 (rounded to the nearest 0.5 in turn)
+ input [`FIXED_WIDTH:1] precision
+ );
+
+ begin
+
+ `ifdef DEBUG
+ $display("round_frac - decimal: %h, precision: %h", decimal, precision);
+ `endif
+ // If the fractional precision bit is high then round up
+ if( decimal[(`FRAC_PRECISION-precision)] == 1'b1) begin
+ round_frac = decimal + (1'b1 << (`FRAC_PRECISION-precision));
+ end else begin
+ round_frac = decimal;
+ end
+ `ifdef DEBUG
+ $display("round_frac: %h", round_frac);
+ `endif
+ end
+endfunction
+
+// This function calculates high_time, low_time, w_edge, and no_count
+// of a non-fractional counter based on the divide and duty cycle
+//
+// NOTE: high_time and low_time are returned as integers between 0 and 63
+// inclusive. 64 should equal 6'b000000 (in other words it is okay to
+// ignore the overflow)
+function [13:0] mmcm_pll_divider
+ (
+ input [7:0] divide, // Max divide is 128
+ input [31:0] duty_cycle // Duty cycle is multiplied by 100,000
+ );
+
+ reg [`FIXED_WIDTH:1] duty_cycle_fix;
+
+ // High/Low time is initially calculated with a wider integer to prevent a
+ // calculation error when it overflows to 64.
+ reg [6:0] high_time;
+ reg [6:0] low_time;
+ reg w_edge;
+ reg no_count;
+
+ reg [`FIXED_WIDTH:1] temp;
+
+ begin
+ // Duty Cycle must be between 0 and 1,000
+ if(duty_cycle <=0 || duty_cycle >= 100000) begin
+`ifndef SYNTHESIS
+ $display("ERROR: duty_cycle: %d is invalid", duty_cycle);
+ `endif
+ $finish;
+ end
+
+ // Convert to FIXED_WIDTH-FRAC_PRECISION.FRAC_PRECISION fixed point
+ duty_cycle_fix = (duty_cycle << `FRAC_PRECISION) / 100_000;
+
+ `ifdef DEBUG
+ $display("duty_cycle_fix: %h", duty_cycle_fix);
+ `endif
+
+ // If the divide is 1 nothing needs to be set except the no_count bit.
+ // Other values are dummies
+ if(divide == 7'h01) begin
+ high_time = 7'h01;
+ w_edge = 1'b0;
+ low_time = 7'h01;
+ no_count = 1'b1;
+ end else begin
+ temp = round_frac(duty_cycle_fix*divide, 1);
+
+ // comes from above round_frac
+ high_time = temp[`FRAC_PRECISION+7:`FRAC_PRECISION+1];
+ // If the duty cycle * divide rounded is .5 or greater then this bit
+ // is set.
+ w_edge = temp[`FRAC_PRECISION]; // comes from round_frac
+
+ // If the high time comes out to 0, it needs to be set to at least 1
+ // and w_edge set to 0
+ if(high_time == 7'h00) begin
+ high_time = 7'h01;
+ w_edge = 1'b0;
+ end
+
+ if(high_time == divide) begin
+ high_time = divide - 1;
+ w_edge = 1'b1;
+ end
+
+ // Calculate low_time based on the divide setting and set no_count to
+ // 0 as it is only used when divide is 1.
+ low_time = divide - high_time;
+ no_count = 1'b0;
+ end
+
+ // Set the return value.
+ mmcm_pll_divider = {w_edge,no_count,high_time[5:0],low_time[5:0]};
+ end
+endfunction
+
+// This function calculates mx, delay_time, and phase_mux
+// of a non-fractional counter based on the divide and phase
+//
+// NOTE: The only valid value for the MX bits is 2'b00 to ensure the coarse mux
+// is used.
+function [10:0] mmcm_pll_phase
+ (
+ // divide must be an integer (use fractional if not)
+ // assumed that divide already checked to be valid
+ input [7:0] divide, // Max divide is 128
+
+ // Phase is given in degrees (-360,000 to 360,000)
+ input signed [31:0] phase
+ );
+
+ reg [`FIXED_WIDTH:1] phase_in_cycles;
+ reg [`FIXED_WIDTH:1] phase_fixed;
+ reg [1:0] mx;
+ reg [5:0] delay_time;
+ reg [2:0] phase_mux;
+
+ reg [`FIXED_WIDTH:1] temp;
+
+ begin
+`ifdef DEBUG
+ $display("pll_phase-divide:%d,phase:%d",
+ divide, phase);
+`endif
+
+ if ((phase < -360000) || (phase > 360000)) begin
+`ifndef SYNTHESIS
+ $display("ERROR: phase of $phase is not between -360000 and 360000");
+`endif
+ $finish;
+ end
+
+ // If phase is less than 0, convert it to a positive phase shift
+ // Convert to (FIXED_WIDTH-FRAC_PRECISION).FRAC_PRECISION fixed point
+ if(phase < 0) begin
+ phase_fixed = ( (phase + 360000) << `FRAC_PRECISION ) / 1000;
+ end else begin
+ phase_fixed = ( phase << `FRAC_PRECISION ) / 1000;
+ end
+
+ // Put phase in terms of decimal number of vco clock cycles
+ phase_in_cycles = ( phase_fixed * divide ) / 360;
+
+`ifdef DEBUG
+ $display("phase_in_cycles: %h", phase_in_cycles);
+`endif
+
+
+ temp = round_frac(phase_in_cycles, 3);
+
+ // set mx to 2'b00 that the phase mux from the VCO is enabled
+ mx = 2'b00;
+ phase_mux = temp[`FRAC_PRECISION:`FRAC_PRECISION-2];
+ delay_time = temp[`FRAC_PRECISION+6:`FRAC_PRECISION+1];
+
+ `ifdef DEBUG
+ $display("temp: %h", temp);
+ `endif
+
+ // Setup the return value
+ mmcm_pll_phase={mx, phase_mux, delay_time};
+ end
+endfunction
+
+// This function takes the divide value and outputs the necessary lock values
+function [39:0] mmcm_pll_lock_lookup
+ (
+ input [6:0] divide // Max divide is 21
+ );
+
+ reg [839:0] lookup;
+
+ begin
+ lookup = {
+ // This table is composed of:
+ // LockRefDly_LockFBDly_LockCnt_LockSatHigh_UnlockCnt
+ 40'b00110_00110_1111101000_1111101001_0000000001, //1 illegal in Ultrascale+
+ 40'b00110_00110_1111101000_1111101001_0000000001, //2
+ 40'b01000_01000_1111101000_1111101001_0000000001, //3
+ 40'b01011_01011_1111101000_1111101001_0000000001, //4
+ 40'b01110_01110_1111101000_1111101001_0000000001, //5
+ 40'b10001_10001_1111101000_1111101001_0000000001, //6
+ 40'b10011_10011_1111101000_1111101001_0000000001, //7
+ 40'b10110_10110_1111101000_1111101001_0000000001, //8
+ 40'b11001_11001_1111101000_1111101001_0000000001, //9
+ 40'b11100_11100_1111101000_1111101001_0000000001, //10
+ 40'b11111_11111_1110000100_1111101001_0000000001, //11
+ 40'b11111_11111_1100111001_1111101001_0000000001, //12
+ 40'b11111_11111_1011101110_1111101001_0000000001, //13
+ 40'b11111_11111_1010111100_1111101001_0000000001, //14
+ 40'b11111_11111_1010001010_1111101001_0000000001, //15
+ 40'b11111_11111_1001110001_1111101001_0000000001, //16
+ 40'b11111_11111_1000111111_1111101001_0000000001, //17
+ 40'b11111_11111_1000100110_1111101001_0000000001, //18
+ 40'b11111_11111_1000001101_1111101001_0000000001, //19
+ 40'b11111_11111_0111110100_1111101001_0000000001, //20
+ 40'b11111_11111_0111011011_1111101001_0000000001 //21
+ };
+
+ // Set lookup_entry with the explicit bits from lookup with a part select
+ mmcm_pll_lock_lookup = lookup[ ((21-divide)*40) +: 40];
+ `ifdef DEBUG
+ $display("lock_lookup: %b", pll_lock_lookup);
+ `endif
+ end
+endfunction
+
+// This function takes the divide value and the bandwidth setting of the PLL
+// and outputs the digital filter settings necessary. Removing bandwidth setting for PLLE3.
+function [9:0] mmcm_pll_filter_lookup
+ (
+ input [6:0] divide // Max divide is 21
+ );
+
+ reg [209:0] lookup;
+ reg [9:0] lookup_entry;
+
+ begin
+
+ lookup = {
+ // CP_RES_LFHF
+ 10'b0011_0111_11, //1 not legal in Ultrascale+
+ 10'b0011_0111_11, //2
+ 10'b0011_0011_11, //3
+ 10'b0011_1001_11, //4
+ 10'b0011_0001_11, //5
+ 10'b0100_1110_11, //6
+ 10'b0011_0110_11, //7
+ 10'b0011_1010_11, //8
+ 10'b0111_1001_11, //9
+ 10'b0111_1001_11, //10
+ 10'b0101_0110_11, //11
+ 10'b1100_0101_11, //12
+ 10'b0101_1010_11, //13
+ 10'b0110_0110_11, //14
+ 10'b0110_1010_11, //15
+ 10'b0111_0110_11, //16
+ 10'b1111_0101_11, //17
+ 10'b1100_0110_11, //18
+ 10'b1110_0001_11, //19
+ 10'b1101_0110_11, //20
+ 10'b1111_0001_11 //21
+ };
+
+ mmcm_pll_filter_lookup = lookup [ ((21-divide)*10) +: 10];
+
+ `ifdef DEBUG
+ $display("filter_lookup: %b", pll_filter_lookup);
+ `endif
+ end
+endfunction
+
+// This function set the CLKOUTPHY divide settings to match
+// the desired CLKOUTPHY_MODE setting. To create VCO_X2, then
+// the CLKOUTPHY will be set to 2'b00 since the VCO is internally
+// doubled and 2'b00 will represent divide by 1. Similarly "VCO"
+// will need to divide the doubled clock VCO clock frequency by
+// 2 therefore 2'b01 will match a divide by 2.And VCO_HALF will
+// need to divide the doubled VCO by 4, therefore 2'b10
+function [9:0] mmcm_pll_clkoutphy_calc
+ (
+ input [8*9:0] CLKOUTPHY_MODE
+ );
+
+ if(CLKOUTPHY_MODE == "VCO_X2") begin
+ mmcm_pll_clkoutphy_calc= 2'b00;
+ end else if(CLKOUTPHY_MODE == "VCO") begin
+ mmcm_pll_clkoutphy_calc= 2'b01;
+ end else if(CLKOUTPHY_MODE == "CLKIN") begin
+ mmcm_pll_clkoutphy_calc= 2'b11;
+ end else begin // Assume "VCO_HALF"
+ mmcm_pll_clkoutphy_calc= 2'b10;
+ end
+
+endfunction
+
+
+// This function takes in the divide, phase, and duty cycle
+// setting to calculate the upper and lower counter registers.
+function [37:0] mmcm_pll_count_calc
+ (
+ input [7:0] divide, // Max divide is 128
+ input signed [31:0] phase,
+ input [31:0] duty_cycle // Multiplied by 100,000
+ );
+
+ reg [13:0] div_calc;
+ reg [16:0] phase_calc;
+
+ begin
+ `ifdef DEBUG
+ $display("pll_count_calc- divide:%h, phase:%d, duty_cycle:%d",
+ divide, phase, duty_cycle);
+ `endif
+
+ // w_edge[13], no_count[12], high_time[11:6], low_time[5:0]
+ div_calc = mmcm_pll_divider(divide, duty_cycle);
+ // mx[10:9], pm[8:6], dt[5:0]
+ phase_calc = mmcm_pll_phase(divide, phase);
+
+ // Return value is the upper and lower address of counter
+ // Upper address is:
+ // RESERVED [31:26]
+ // MX [25:24]
+ // EDGE [23]
+ // NOCOUNT [22]
+ // DELAY_TIME [21:16]
+ // Lower Address is:
+ // PHASE_MUX [15:13]
+ // RESERVED [12]
+ // HIGH_TIME [11:6]
+ // LOW_TIME [5:0]
+
+ `ifdef DEBUG
+ $display("div:%d dc:%d phase:%d ht:%d lt:%d ed:%d nc:%d mx:%d dt:%d pm:%d",
+ divide, duty_cycle, phase, div_calc[11:6], div_calc[5:0],
+ div_calc[13], div_calc[12],
+ phase_calc[16:15], phase_calc[5:0], 3'b000); //Removed PM_Rise bits
+ `endif
+
+ mmcm_pll_count_calc =
+ {
+ // Upper Address
+ 6'h00, phase_calc[10:9], div_calc[13:12], phase_calc[5:0],
+ // Lower Address
+ phase_calc[8:6], 1'b0, div_calc[11:0]
+ };
+ end
+endfunction
+
+
+// This function takes in the divide, phase, and duty cycle
+// setting to calculate the upper and lower counter registers.
+// for fractional multiply/divide functions.
+//
+//
+function [37:0] mmcm_pll_frac_count_calc
+ (
+ input [7:0] divide, // Max divide is 128
+ input signed [31:0] phase,
+ input [31:0] duty_cycle, // Multiplied by 1,000
+ input [9:0] frac // Multiplied by 1000
+ );
+
+ //Required for fractional divide calculations
+ reg [7:0] lt_frac;
+ reg [7:0] ht_frac;
+
+ reg /*[7:0]*/ wf_fall_frac;
+ reg /*[7:0]*/ wf_rise_frac;
+
+ reg [31:0] a;
+ reg [7:0] pm_rise_frac_filtered ;
+ reg [7:0] pm_fall_frac_filtered ;
+ reg [7:0] clkout0_divide_int;
+ reg [2:0] clkout0_divide_frac;
+ reg [7:0] even_part_high;
+ reg [7:0] even_part_low;
+
+ reg [7:0] odd;
+ reg [7:0] odd_and_frac;
+
+ reg [7:0] pm_fall;
+ reg [7:0] pm_rise;
+ reg [7:0] dt;
+ reg [7:0] dt_int;
+ reg [63:0] dt_calc;
+
+ reg [7:0] pm_rise_frac;
+ reg [7:0] pm_fall_frac;
+
+ reg [31:0] a_per_in_octets;
+ reg [31:0] a_phase_in_cycles;
+
+ parameter precision = 0.125;
+
+ reg [31:0] phase_fixed; // changed to 31:0 from 32:1 jt 5/2/11
+ reg [31: 0] phase_pos;
+ reg [31: 0] phase_vco;
+ reg [31:0] temp;// changed to 31:0 from 32:1 jt 5/2/11
+ reg [13:0] div_calc;
+ reg [16:0] phase_calc;
+
+ begin
+ `ifdef DEBUG
+ $display("pll_frac_count_calc- divide:%h, phase:%d, duty_cycle:%d",
+ divide, phase, duty_cycle);
+ `endif
+
+ //convert phase to fixed
+ if ((phase < -360000) || (phase > 360000)) begin
+`ifndef SYNTHESIS
+ $display("ERROR: phase of $phase is not between -360000 and 360000");
+ `endif
+ $finish;
+ end
+
+
+ // Return value is
+ // Transfer data
+ // RESERVED [37:36]
+ // FRAC_TIME [35:33]
+ // FRAC_WF_FALL [32]
+ // Upper address is:
+ // RESERVED [31:26]
+ // MX [25:24]
+ // EDGE [23]
+ // NOCOUNT [22]
+ // DELAY_TIME [21:16]
+ // Lower Address is:
+ // PHASE_MUX [15:13]
+ // RESERVED [12]
+ // HIGH_TIME [11:6]
+ // LOW_TIME [5:0]
+
+
+
+ clkout0_divide_frac = frac / 125;
+ clkout0_divide_int = divide;
+
+ even_part_high = clkout0_divide_int >> 1;//$rtoi(clkout0_divide_int / 2);
+ even_part_low = even_part_high;
+
+ odd = clkout0_divide_int - even_part_high - even_part_low;
+ odd_and_frac = (8*odd) + clkout0_divide_frac;
+
+ lt_frac = even_part_high - (odd_and_frac <= 9);//IF(odd_and_frac>9,even_part_high, even_part_high - 1)
+ ht_frac = even_part_low - (odd_and_frac <= 8);//IF(odd_and_frac>8,even_part_low, even_part_low- 1)
+
+ pm_fall = {odd[6:0],2'b00} + {6'h00, clkout0_divide_frac[2:1]}; // using >> instead of clkout0_divide_frac / 2
+ pm_rise = 0; //0
+
+ wf_fall_frac = (odd_and_frac >=2) && (odd_and_frac <=9);//IF(odd_and_frac>=2,IF(odd_and_frac <= 9,1,0),0)
+ wf_rise_frac = (odd_and_frac >=1) && (odd_and_frac <=8);//IF(odd_and_frac>=1,IF(odd_and_frac <= 8,1,0),0)
+
+
+
+ //Calculate phase in fractional cycles
+ a_per_in_octets = (8 * divide) + (frac / 125) ;
+ a_phase_in_cycles = (phase+10) * a_per_in_octets / 360000 ;//Adding 1 due to rounding errors
+ pm_rise_frac = (a_phase_in_cycles[7:0] ==8'h00)?8'h00:a_phase_in_cycles[7:0] - {a_phase_in_cycles[7:3],3'b000};
+
+ dt_calc = ((phase+10) * a_per_in_octets / 8 )/360000 ;//TRUNC(phase* divide / 360); //or_simply (a_per_in_octets / 8)
+ dt = dt_calc[7:0];
+
+ pm_rise_frac_filtered = (pm_rise_frac >=8) ? (pm_rise_frac ) - 8: pm_rise_frac ; //((phase_fixed * (divide + frac / 1000)) / 360) - {pm_rise_frac[7:3],3'b000};//$rtoi(clkout0_phase * clkout0_divide / 45);//a;
+
+ dt_int = dt + (& pm_rise_frac[7:4]); //IF(pm_rise_overwriting>7,dt+1,dt)
+ pm_fall_frac = pm_fall + pm_rise_frac;
+ pm_fall_frac_filtered = pm_fall + pm_rise_frac - {pm_fall_frac[7:3], 3'b000};
+
+ div_calc = mmcm_pll_divider(divide, duty_cycle); //Use to determine edge[7], no count[6]
+ phase_calc = mmcm_pll_phase(divide, phase);// returns{mx[1:0], phase_mux[2:0], delay_time[5:0]}
+
+ mmcm_pll_frac_count_calc[37:0] =
+ { 2'b00, pm_fall_frac_filtered[2:0], wf_fall_frac,
+ 1'b0, clkout0_divide_frac[2:0], 1'b1, wf_rise_frac, phase_calc[10:9], div_calc[13:12], dt[5:0],
+ 3'b000, 1'b0, ht_frac[5:0], lt_frac[5:0] //Removed PM_Rise bits
+ } ;
+
+ `ifdef DEBUG
+ $display("-%d.%d p%d>> :DADDR_9_15 frac30to28.frac_en.wf_r_frac.dt:%b%d%d_%b:DADDR_7_13 pm_f_frac_filtered_29to27.wf_f_frac_26:%b%d:DADDR_8_14.pm_r_frac_filt_15to13.ht_frac.lt_frac:%b%b%b:", divide, frac, phase, clkout0_divide_frac, 1, wf_rise_frac, dt, pm_fall_frac_filtered, wf_fall_frac, 3'b000, ht_frac, lt_frac);
+ `endif
+
+ end
+endfunction
+
diff --git a/game.hw/game.lpr b/game.hw/game.lpr
new file mode 100644
index 0000000000000000000000000000000000000000..d56332c2dae048fc60e846f7d2ae7c72df494694
--- /dev/null
+++ b/game.hw/game.lpr
@@ -0,0 +1,8 @@
+<?xml version="1.0" encoding="UTF-8"?>
+<!-- Product Version: Vivado v2022.2 (64-bit) -->
+<!-- -->
+<!-- Copyright 1986-2022 Xilinx, Inc. All Rights Reserved. -->
+
+<labtools version="1" minor="0">
+ <HWSession Dir="hw_1" File="hw.xml"/>
+</labtools>
diff --git a/game.hw/hw_1/hw.xml b/game.hw/hw_1/hw.xml
new file mode 100644
index 0000000000000000000000000000000000000000..2e0f599bf353f2226bdff72d1739e2e8bb44b66e
--- /dev/null
+++ b/game.hw/hw_1/hw.xml
@@ -0,0 +1,17 @@
+<?xml version="1.0" encoding="UTF-8"?>
+<!-- Product Version: Vivado v2022.2 (64-bit) -->
+<!-- -->
+<!-- Copyright 1986-2022 Xilinx, Inc. All Rights Reserved. -->
+
+<hwsession version="1" minor="2">
+ <device name="xc7a100t_0" gui_info=""/>
+ <ObjectList object_type="hw_device" gui_info="">
+ <Object name="xc7a100t_0" gui_info="">
+ <Properties Property="FULL_PROBES.FILE" value=""/>
+ <Properties Property="PROBES.FILE" value=""/>
+ <Properties Property="PROGRAM.HW_BITSTREAM" value="$_project_name_.runs/impl_1/TopModule.bit"/>
+ <Properties Property="SLR.COUNT" value="1"/>
+ </Object>
+ </ObjectList>
+ <probeset name="hw project" active="false"/>
+</hwsession>
diff --git a/game.ip_user_files/README.txt b/game.ip_user_files/README.txt
new file mode 100644
index 0000000000000000000000000000000000000000..023052cab505345c50834e560e42db8c25daf798
--- /dev/null
+++ b/game.ip_user_files/README.txt
@@ -0,0 +1 @@
+The files in this directory structure are automatically generated and managed by Vivado. Editing these files is not recommended.
diff --git a/game.ip_user_files/ip/clk_wiz_0/clk_wiz_0.vho b/game.ip_user_files/ip/clk_wiz_0/clk_wiz_0.vho
new file mode 100755
index 0000000000000000000000000000000000000000..0fa97dbfe9fd121047d190f4c2b038836ac332a6
--- /dev/null
+++ b/game.ip_user_files/ip/clk_wiz_0/clk_wiz_0.vho
@@ -0,0 +1,92 @@
+
+--
+-- (c) Copyright 2008 - 2013 Xilinx, Inc. All rights reserved.
+--
+-- This file contains confidential and proprietary information
+-- of Xilinx, Inc. and is protected under U.S. and
+-- international copyright and other intellectual property
+-- laws.
+--
+-- DISCLAIMER
+-- This disclaimer is not a license and does not grant any
+-- rights to the materials distributed herewith. Except as
+-- otherwise provided in a valid license issued to you by
+-- Xilinx, and to the maximum extent permitted by applicable
+-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
+-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
+-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
+-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
+-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
+-- (2) Xilinx shall not be liable (whether in contract or tort,
+-- including negligence, or under any other theory of
+-- liability) for any loss or damage of any kind or nature
+-- related to, arising under or in connection with these
+-- materials, including for any direct, or any indirect,
+-- special, incidental, or consequential loss or damage
+-- (including loss of data, profits, goodwill, or any type of
+-- loss or damage suffered as a result of any action brought
+-- by a third party) even if such damage or loss was
+-- reasonably foreseeable or Xilinx had been advised of the
+-- possibility of the same.
+--
+-- CRITICAL APPLICATIONS
+-- Xilinx products are not designed or intended to be fail-
+-- safe, or for use in any application requiring fail-safe
+-- performance, such as life-support or safety devices or
+-- systems, Class III medical devices, nuclear facilities,
+-- applications related to the deployment of airbags, or any
+-- other applications that could lead to death, personal
+-- injury, or severe property or environmental damage
+-- (individually and collectively, "Critical
+-- Applications"). Customer assumes the sole risk and
+-- liability of any use of Xilinx products in Critical
+-- Applications, subject only to applicable laws and
+-- regulations governing limitations on product liability.
+--
+-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
+-- PART OF THIS FILE AT ALL TIMES.
+--
+------------------------------------------------------------------------------
+-- User entered comments
+------------------------------------------------------------------------------
+-- None
+--
+------------------------------------------------------------------------------
+-- Output Output Phase Duty Cycle Pk-to-Pk Phase
+-- Clock Freq (MHz) (degrees) (%) Jitter (ps) Error (ps)
+------------------------------------------------------------------------------
+-- clk_out1__25.00000______0.000______50.0______181.828____104.359
+--
+------------------------------------------------------------------------------
+-- Input Clock Freq (MHz) Input Jitter (UI)
+------------------------------------------------------------------------------
+-- __primary_________100.000____________0.010
+
+
+-- The following code must appear in the VHDL architecture header:
+------------- Begin Cut here for COMPONENT Declaration ------ COMP_TAG
+component clk_wiz_0
+port
+ (-- Clock in ports
+ -- Clock out ports
+ clk_out1 : out std_logic;
+ -- Status and control signals
+ resetn : in std_logic;
+ clk_in1 : in std_logic
+ );
+end component;
+
+-- COMP_TAG_END ------ End COMPONENT Declaration ------------
+-- The following code must appear in the VHDL architecture
+-- body. Substitute your own instance name and net names.
+------------- Begin Cut here for INSTANTIATION Template ----- INST_TAG
+your_instance_name : clk_wiz_0
+ port map (
+ -- Clock out ports
+ clk_out1 => clk_out1,
+ -- Status and control signals
+ resetn => resetn,
+ -- Clock in ports
+ clk_in1 => clk_in1
+ );
+-- INST_TAG_END ------ End INSTANTIATION Template ------------
diff --git a/game.ip_user_files/ip/clk_wiz_1/clk_wiz_1.vho b/game.ip_user_files/ip/clk_wiz_1/clk_wiz_1.vho
new file mode 100755
index 0000000000000000000000000000000000000000..3bdc63cb4f58ddaab9569b66043511a372c9830b
--- /dev/null
+++ b/game.ip_user_files/ip/clk_wiz_1/clk_wiz_1.vho
@@ -0,0 +1,92 @@
+
+--
+-- (c) Copyright 2008 - 2013 Xilinx, Inc. All rights reserved.
+--
+-- This file contains confidential and proprietary information
+-- of Xilinx, Inc. and is protected under U.S. and
+-- international copyright and other intellectual property
+-- laws.
+--
+-- DISCLAIMER
+-- This disclaimer is not a license and does not grant any
+-- rights to the materials distributed herewith. Except as
+-- otherwise provided in a valid license issued to you by
+-- Xilinx, and to the maximum extent permitted by applicable
+-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
+-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
+-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
+-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
+-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
+-- (2) Xilinx shall not be liable (whether in contract or tort,
+-- including negligence, or under any other theory of
+-- liability) for any loss or damage of any kind or nature
+-- related to, arising under or in connection with these
+-- materials, including for any direct, or any indirect,
+-- special, incidental, or consequential loss or damage
+-- (including loss of data, profits, goodwill, or any type of
+-- loss or damage suffered as a result of any action brought
+-- by a third party) even if such damage or loss was
+-- reasonably foreseeable or Xilinx had been advised of the
+-- possibility of the same.
+--
+-- CRITICAL APPLICATIONS
+-- Xilinx products are not designed or intended to be fail-
+-- safe, or for use in any application requiring fail-safe
+-- performance, such as life-support or safety devices or
+-- systems, Class III medical devices, nuclear facilities,
+-- applications related to the deployment of airbags, or any
+-- other applications that could lead to death, personal
+-- injury, or severe property or environmental damage
+-- (individually and collectively, "Critical
+-- Applications"). Customer assumes the sole risk and
+-- liability of any use of Xilinx products in Critical
+-- Applications, subject only to applicable laws and
+-- regulations governing limitations on product liability.
+--
+-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
+-- PART OF THIS FILE AT ALL TIMES.
+--
+------------------------------------------------------------------------------
+-- User entered comments
+------------------------------------------------------------------------------
+-- None
+--
+------------------------------------------------------------------------------
+-- Output Output Phase Duty Cycle Pk-to-Pk Phase
+-- Clock Freq (MHz) (degrees) (%) Jitter (ps) Error (ps)
+------------------------------------------------------------------------------
+-- clk_out1__25.00000______0.000______50.0______181.828____104.359
+--
+------------------------------------------------------------------------------
+-- Input Clock Freq (MHz) Input Jitter (UI)
+------------------------------------------------------------------------------
+-- __primary_________100.000____________0.010
+
+
+-- The following code must appear in the VHDL architecture header:
+------------- Begin Cut here for COMPONENT Declaration ------ COMP_TAG
+component clk_wiz_1
+port
+ (-- Clock in ports
+ -- Clock out ports
+ clk_out1 : out std_logic;
+ -- Status and control signals
+ resetn : in std_logic;
+ clk_in1 : in std_logic
+ );
+end component;
+
+-- COMP_TAG_END ------ End COMPONENT Declaration ------------
+-- The following code must appear in the VHDL architecture
+-- body. Substitute your own instance name and net names.
+------------- Begin Cut here for INSTANTIATION Template ----- INST_TAG
+your_instance_name : clk_wiz_1
+ port map (
+ -- Clock out ports
+ clk_out1 => clk_out1,
+ -- Status and control signals
+ resetn => resetn,
+ -- Clock in ports
+ clk_in1 => clk_in1
+ );
+-- INST_TAG_END ------ End INSTANTIATION Template ------------
diff --git a/game.ip_user_files/sim_scripts/clk_wiz_0/activehdl/README.txt b/game.ip_user_files/sim_scripts/clk_wiz_0/activehdl/README.txt
new file mode 100644
index 0000000000000000000000000000000000000000..193e9e2b2252650fd85b3c628bc718694820608b
--- /dev/null
+++ b/game.ip_user_files/sim_scripts/clk_wiz_0/activehdl/README.txt
@@ -0,0 +1,49 @@
+################################################################################
+# Vivado (TM) v2022.2 (64-bit)
+#
+# README.txt: Please read the sections below to understand the steps required to
+# run the exported script and information about the source files.
+#
+# Generated by export_simulation on Mon Feb 27 10:47:03 CET 2023
+#
+################################################################################
+
+1. How to run the generated simulation script:-
+
+From the shell prompt in the current directory, issue the following command:-
+
+./clk_wiz_0.sh
+
+This command will launch the 'compile', 'elaborate' and 'simulate' functions
+implemented in the script file for the 3-step flow. These functions are called
+from the main 'run' function in the script file.
+
+The 'run' function first executes the 'setup' function, the purpose of which is to
+create simulator specific setup files, create design library mappings and library
+directories and copy 'glbl.v' from the Vivado software install location into the
+current directory.
+
+The 'setup' function is also used for removing the simulator generated data in
+order to reset the current directory to the original state when export_simulation
+was launched from Vivado. This generated data can be removed by specifying the
+'-reset_run' switch to the './clk_wiz_0.sh' script.
+
+./clk_wiz_0.sh -reset_run
+
+To keep the generated data from the previous run but regenerate the setup files and
+library directories, use the '-noclean_files' switch.
+
+./clk_wiz_0.sh -noclean_files
+
+For more information on the script, please type './clk_wiz_0.sh -help'.
+
+2. Additional design information files:-
+
+export_simulation generates following additional file that can be used for fetching
+the design files information or for integrating with external custom scripts.
+
+Name : file_info.txt
+Purpose: This file contains detail design file information based on the compile order
+ when export_simulation was executed from Vivado. The file contains information
+ about the file type, name, whether it is part of the IP, associated library
+ and the file path information.
diff --git a/game.ip_user_files/sim_scripts/clk_wiz_0/activehdl/clk_wiz_0.sh b/game.ip_user_files/sim_scripts/clk_wiz_0/activehdl/clk_wiz_0.sh
new file mode 100755
index 0000000000000000000000000000000000000000..872bb571f4bb223a8bddb4dcc11f61e3b2cc1108
--- /dev/null
+++ b/game.ip_user_files/sim_scripts/clk_wiz_0/activehdl/clk_wiz_0.sh
@@ -0,0 +1,149 @@
+#!/bin/bash -f
+#*********************************************************************************************************
+# Vivado (TM) v2022.2 (64-bit)
+#
+# Filename : clk_wiz_0.sh
+# Simulator : Aldec Active-HDL Simulator
+# Description : Simulation script for compiling, elaborating and verifying the project source files.
+# The script will automatically create the design libraries sub-directories in the run
+# directory, add the library logical mappings in the simulator setup file, create default
+# 'do/prj' file, execute compilation, elaboration and simulation steps.
+#
+# Generated by Vivado on Mon Feb 27 10:47:03 CET 2023
+# SW Build 3671981 on Fri Oct 14 04:59:54 MDT 2022
+#
+# Tool Version Limit: 2022.10
+#
+# usage: clk_wiz_0.sh [-help]
+# usage: clk_wiz_0.sh [-lib_map_path]
+# usage: clk_wiz_0.sh [-noclean_files]
+# usage: clk_wiz_0.sh [-reset_run]
+#
+# Prerequisite:- To compile and run simulation, you must compile the Xilinx simulation libraries using the
+# 'compile_simlib' TCL command. For more information about this command, run 'compile_simlib -help' in the
+# Vivado Tcl Shell. Once the libraries have been compiled successfully, specify the -lib_map_path switch
+# that points to these libraries and rerun export_simulation. For more information about this switch please
+# type 'export_simulation -help' in the Tcl shell.
+#
+# You can also point to the simulation libraries by either replacing the <SPECIFY_COMPILED_LIB_PATH> in this
+# script with the compiled library directory path or specify this path with the '-lib_map_path' switch when
+# executing this script. Please type 'clk_wiz_0.sh -help' for more information.
+#
+# Additional references - 'Xilinx Vivado Design Suite User Guide:Logic simulation (UG900)'
+#
+#*********************************************************************************************************
+
+# Script info
+echo -e "clk_wiz_0.sh - Script generated by export_simulation (Vivado v2022.2 (64-bit)-id)\n"
+
+# Main steps
+run()
+{
+ check_args $# $1
+ setup $1 $2
+ compile
+ simulate
+}
+
+# RUN_STEP: <compile>
+compile()
+{
+ source compile.do 2>&1 | tee -a compile.log
+}
+
+# RUN_STEP: <simulate>
+simulate()
+{
+ runvsimsa -l simulate.log -do "do {simulate.do}"
+}
+
+# STEP: setup
+setup()
+{
+ case $1 in
+ "-lib_map_path" )
+ if [[ ($2 == "") ]]; then
+ echo -e "ERROR: Simulation library directory path not specified (type \"./clk_wiz_0.sh -help\" for more information)\n"
+ exit 1
+ fi
+ map_setup_file $2
+ ;;
+ "-reset_run" )
+ reset_run
+ echo -e "INFO: Simulation run files deleted.\n"
+ exit 0
+ ;;
+ "-noclean_files" )
+ # do not remove previous data
+ ;;
+ * )
+ map_setup_file $2
+ esac
+
+ # Add any setup/initialization commands here:-
+
+ # <user specific commands>
+
+}
+
+# Map library.cfg file
+map_setup_file()
+{
+ file="library.cfg"
+ lib_map_path=""
+ if [[ ($1 != "") ]]; then
+ lib_map_path="$1"
+ fi
+ if [[ ($lib_map_path != "") ]]; then
+ src_file="$lib_map_path/$file"
+ if [[ -e $src_file ]]; then
+ vmap -link $lib_map_path
+ fi
+ fi
+}
+
+# Delete generated data from the previous run
+reset_run()
+{
+ files_to_remove=(compile.log elaboration.log simulate.log dataset.asdb work activehdl)
+ for (( i=0; i<${#files_to_remove[*]}; i++ )); do
+ file="${files_to_remove[i]}"
+ if [[ -e $file ]]; then
+ rm -rf $file
+ fi
+ done
+}
+
+# Check command line arguments
+check_args()
+{
+ if [[ ($1 == 1 ) && ($2 != "-lib_map_path" && $2 != "-noclean_files" && $2 != "-reset_run" && $2 != "-help" && $2 != "-h") ]]; then
+ echo -e "ERROR: Unknown option specified '$2' (type \"./clk_wiz_0.sh -help\" for more information)\n"
+ exit 1
+ fi
+
+ if [[ ($2 == "-help" || $2 == "-h") ]]; then
+ usage
+ fi
+}
+
+# Script usage
+usage()
+{
+ msg="Usage: clk_wiz_0.sh [-help]\n\
+Usage: clk_wiz_0.sh [-lib_map_path]\n\
+Usage: clk_wiz_0.sh [-reset_run]\n\
+Usage: clk_wiz_0.sh [-noclean_files]\n\n\
+[-help] -- Print help information for this script\n\n\
+[-lib_map_path <path>] -- Compiled simulation library directory path. The simulation library is compiled\n\
+using the compile_simlib tcl command. Please see 'compile_simlib -help' for more information.\n\n\
+[-reset_run] -- Recreate simulator setup files and library mappings for a clean run. The generated files\n\
+from the previous run will be removed. If you don't want to remove the simulator generated files, use the\n\
+-noclean_files switch.\n\n\
+[-noclean_files] -- Reset previous run, but do not remove simulator generated files from the previous run.\n\n"
+ echo -e $msg
+ exit 1
+}
+
+# Launch script
+run $1 $2
diff --git a/game.ip_user_files/sim_scripts/clk_wiz_0/activehdl/clk_wiz_0.udo b/game.ip_user_files/sim_scripts/clk_wiz_0/activehdl/clk_wiz_0.udo
new file mode 100644
index 0000000000000000000000000000000000000000..e69de29bb2d1d6434b8b29ae775ad8c2e48c5391
diff --git a/game.ip_user_files/sim_scripts/clk_wiz_0/activehdl/compile.do b/game.ip_user_files/sim_scripts/clk_wiz_0/activehdl/compile.do
new file mode 100644
index 0000000000000000000000000000000000000000..a67ebc42497d02f7795d8838e2cc4d071cd7f92c
--- /dev/null
+++ b/game.ip_user_files/sim_scripts/clk_wiz_0/activehdl/compile.do
@@ -0,0 +1,22 @@
+vlib work
+vlib activehdl
+
+vlib activehdl/xpm
+vlib activehdl/xil_defaultlib
+
+vmap xpm activehdl/xpm
+vmap xil_defaultlib activehdl/xil_defaultlib
+
+vlog -work xpm -sv2k12 "+incdir+../../../../game.gen/sources_1/ip/clk_wiz_0" \
+"/opt/Xilinx/Vivado/2022.2/data/ip/xpm/xpm_cdc/hdl/xpm_cdc.sv" \
+
+vcom -work xpm -93 \
+"/opt/Xilinx/Vivado/2022.2/data/ip/xpm/xpm_VCOMP.vhd" \
+
+vcom -work xil_defaultlib -93 \
+"../../../../game.gen/sources_1/ip/clk_wiz_0/clk_wiz_0_sim_netlist.vhdl" \
+
+
+vlog -work xil_defaultlib \
+"glbl.v"
+
diff --git a/game.ip_user_files/sim_scripts/clk_wiz_0/activehdl/file_info.txt b/game.ip_user_files/sim_scripts/clk_wiz_0/activehdl/file_info.txt
new file mode 100644
index 0000000000000000000000000000000000000000..275a6e12cd472264cee1afb10355af4b66b5d48f
--- /dev/null
+++ b/game.ip_user_files/sim_scripts/clk_wiz_0/activehdl/file_info.txt
@@ -0,0 +1,4 @@
+xpm_cdc.sv,systemverilog,xpm,../../../opt/Xilinx/Vivado/2022.2/data/ip/xpm/xpm_cdc/hdl/xpm_cdc.sv,incdir="../../../../game.gen/sources_1/ip/clk_wiz_0"
+xpm_VCOMP.vhd,vhdl,xpm,../../../opt/Xilinx/Vivado/2022.2/data/ip/xpm/xpm_VCOMP.vhd,incdir="../../../../game.gen/sources_1/ip/clk_wiz_0"
+clk_wiz_0_sim_netlist.vhdl,vhdl,xil_defaultlib,../../../../game.gen/sources_1/ip/clk_wiz_0/clk_wiz_0_sim_netlist.vhdl,incdir="../../../../game.gen/sources_1/ip/clk_wiz_0"
+glbl.v,Verilog,xil_defaultlib,glbl.v
diff --git a/game.ip_user_files/sim_scripts/clk_wiz_0/activehdl/glbl.v b/game.ip_user_files/sim_scripts/clk_wiz_0/activehdl/glbl.v
new file mode 100644
index 0000000000000000000000000000000000000000..ed3b249ceef65a0d1b42790def9ee8179363679c
--- /dev/null
+++ b/game.ip_user_files/sim_scripts/clk_wiz_0/activehdl/glbl.v
@@ -0,0 +1,84 @@
+// $Header: /devl/xcs/repo/env/Databases/CAEInterfaces/verunilibs/data/glbl.v,v 1.14 2010/10/28 20:44:00 fphillip Exp $
+`ifndef GLBL
+`define GLBL
+`timescale 1 ps / 1 ps
+
+module glbl ();
+
+ parameter ROC_WIDTH = 100000;
+ parameter TOC_WIDTH = 0;
+ parameter GRES_WIDTH = 10000;
+ parameter GRES_START = 10000;
+
+//-------- STARTUP Globals --------------
+ wire GSR;
+ wire GTS;
+ wire GWE;
+ wire PRLD;
+ wire GRESTORE;
+ tri1 p_up_tmp;
+ tri (weak1, strong0) PLL_LOCKG = p_up_tmp;
+
+ wire PROGB_GLBL;
+ wire CCLKO_GLBL;
+ wire FCSBO_GLBL;
+ wire [3:0] DO_GLBL;
+ wire [3:0] DI_GLBL;
+
+ reg GSR_int;
+ reg GTS_int;
+ reg PRLD_int;
+ reg GRESTORE_int;
+
+//-------- JTAG Globals --------------
+ wire JTAG_TDO_GLBL;
+ wire JTAG_TCK_GLBL;
+ wire JTAG_TDI_GLBL;
+ wire JTAG_TMS_GLBL;
+ wire JTAG_TRST_GLBL;
+
+ reg JTAG_CAPTURE_GLBL;
+ reg JTAG_RESET_GLBL;
+ reg JTAG_SHIFT_GLBL;
+ reg JTAG_UPDATE_GLBL;
+ reg JTAG_RUNTEST_GLBL;
+
+ reg JTAG_SEL1_GLBL = 0;
+ reg JTAG_SEL2_GLBL = 0 ;
+ reg JTAG_SEL3_GLBL = 0;
+ reg JTAG_SEL4_GLBL = 0;
+
+ reg JTAG_USER_TDO1_GLBL = 1'bz;
+ reg JTAG_USER_TDO2_GLBL = 1'bz;
+ reg JTAG_USER_TDO3_GLBL = 1'bz;
+ reg JTAG_USER_TDO4_GLBL = 1'bz;
+
+ assign (strong1, weak0) GSR = GSR_int;
+ assign (strong1, weak0) GTS = GTS_int;
+ assign (weak1, weak0) PRLD = PRLD_int;
+ assign (strong1, weak0) GRESTORE = GRESTORE_int;
+
+ initial begin
+ GSR_int = 1'b1;
+ PRLD_int = 1'b1;
+ #(ROC_WIDTH)
+ GSR_int = 1'b0;
+ PRLD_int = 1'b0;
+ end
+
+ initial begin
+ GTS_int = 1'b1;
+ #(TOC_WIDTH)
+ GTS_int = 1'b0;
+ end
+
+ initial begin
+ GRESTORE_int = 1'b0;
+ #(GRES_START);
+ GRESTORE_int = 1'b1;
+ #(GRES_WIDTH);
+ GRESTORE_int = 1'b0;
+ end
+
+endmodule
+`endif
diff --git a/game.ip_user_files/sim_scripts/clk_wiz_0/activehdl/simulate.do b/game.ip_user_files/sim_scripts/clk_wiz_0/activehdl/simulate.do
new file mode 100644
index 0000000000000000000000000000000000000000..cb21d1138bb40e4b086bd6a322e0321940a5d624
--- /dev/null
+++ b/game.ip_user_files/sim_scripts/clk_wiz_0/activehdl/simulate.do
@@ -0,0 +1,20 @@
+onbreak {quit -force}
+onerror {quit -force}
+
+asim +access +r +m+clk_wiz_0 -L xpm -L xil_defaultlib -L unisims_ver -L unimacro_ver -L secureip -O5 xil_defaultlib.clk_wiz_0 xil_defaultlib.glbl
+
+set NumericStdNoWarnings 1
+set StdArithNoWarnings 1
+
+do {wave.do}
+
+view wave
+view structure
+
+do {clk_wiz_0.udo}
+
+run
+
+endsim
+
+quit -force
diff --git a/game.ip_user_files/sim_scripts/clk_wiz_0/activehdl/wave.do b/game.ip_user_files/sim_scripts/clk_wiz_0/activehdl/wave.do
new file mode 100644
index 0000000000000000000000000000000000000000..70157b0cf36569bda8275f1a9640c41911f8d5f7
--- /dev/null
+++ b/game.ip_user_files/sim_scripts/clk_wiz_0/activehdl/wave.do
@@ -0,0 +1,2 @@
+add wave *
+add wave /glbl/GSR
diff --git a/game.ip_user_files/sim_scripts/clk_wiz_0/modelsim/README.txt b/game.ip_user_files/sim_scripts/clk_wiz_0/modelsim/README.txt
new file mode 100644
index 0000000000000000000000000000000000000000..193e9e2b2252650fd85b3c628bc718694820608b
--- /dev/null
+++ b/game.ip_user_files/sim_scripts/clk_wiz_0/modelsim/README.txt
@@ -0,0 +1,49 @@
+################################################################################
+# Vivado (TM) v2022.2 (64-bit)
+#
+# README.txt: Please read the sections below to understand the steps required to
+# run the exported script and information about the source files.
+#
+# Generated by export_simulation on Mon Feb 27 10:47:03 CET 2023
+#
+################################################################################
+
+1. How to run the generated simulation script:-
+
+From the shell prompt in the current directory, issue the following command:-
+
+./clk_wiz_0.sh
+
+This command will launch the 'compile', 'elaborate' and 'simulate' functions
+implemented in the script file for the 3-step flow. These functions are called
+from the main 'run' function in the script file.
+
+The 'run' function first executes the 'setup' function, the purpose of which is to
+create simulator specific setup files, create design library mappings and library
+directories and copy 'glbl.v' from the Vivado software install location into the
+current directory.
+
+The 'setup' function is also used for removing the simulator generated data in
+order to reset the current directory to the original state when export_simulation
+was launched from Vivado. This generated data can be removed by specifying the
+'-reset_run' switch to the './clk_wiz_0.sh' script.
+
+./clk_wiz_0.sh -reset_run
+
+To keep the generated data from the previous run but regenerate the setup files and
+library directories, use the '-noclean_files' switch.
+
+./clk_wiz_0.sh -noclean_files
+
+For more information on the script, please type './clk_wiz_0.sh -help'.
+
+2. Additional design information files:-
+
+export_simulation generates following additional file that can be used for fetching
+the design files information or for integrating with external custom scripts.
+
+Name : file_info.txt
+Purpose: This file contains detail design file information based on the compile order
+ when export_simulation was executed from Vivado. The file contains information
+ about the file type, name, whether it is part of the IP, associated library
+ and the file path information.
diff --git a/game.ip_user_files/sim_scripts/clk_wiz_0/modelsim/clk_wiz_0.sh b/game.ip_user_files/sim_scripts/clk_wiz_0/modelsim/clk_wiz_0.sh
new file mode 100755
index 0000000000000000000000000000000000000000..22c6747e468fcefd8b647cd8f936a6c400958c5b
--- /dev/null
+++ b/game.ip_user_files/sim_scripts/clk_wiz_0/modelsim/clk_wiz_0.sh
@@ -0,0 +1,165 @@
+#!/bin/bash -f
+#*********************************************************************************************************
+# Vivado (TM) v2022.2 (64-bit)
+#
+# Filename : clk_wiz_0.sh
+# Simulator : Mentor Graphics ModelSim Simulator
+# Description : Simulation script for compiling, elaborating and verifying the project source files.
+# The script will automatically create the design libraries sub-directories in the run
+# directory, add the library logical mappings in the simulator setup file, create default
+# 'do/prj' file, execute compilation, elaboration and simulation steps.
+#
+# Generated by Vivado on Mon Feb 27 10:47:03 CET 2023
+# SW Build 3671981 on Fri Oct 14 04:59:54 MDT 2022
+#
+# Tool Version Limit: 2022.10
+#
+# usage: clk_wiz_0.sh [-help]
+# usage: clk_wiz_0.sh [-lib_map_path]
+# usage: clk_wiz_0.sh [-noclean_files]
+# usage: clk_wiz_0.sh [-reset_run]
+#
+# Prerequisite:- To compile and run simulation, you must compile the Xilinx simulation libraries using the
+# 'compile_simlib' TCL command. For more information about this command, run 'compile_simlib -help' in the
+# Vivado Tcl Shell. Once the libraries have been compiled successfully, specify the -lib_map_path switch
+# that points to these libraries and rerun export_simulation. For more information about this switch please
+# type 'export_simulation -help' in the Tcl shell.
+#
+# You can also point to the simulation libraries by either replacing the <SPECIFY_COMPILED_LIB_PATH> in this
+# script with the compiled library directory path or specify this path with the '-lib_map_path' switch when
+# executing this script. Please type 'clk_wiz_0.sh -help' for more information.
+#
+# Additional references - 'Xilinx Vivado Design Suite User Guide:Logic simulation (UG900)'
+#
+#*********************************************************************************************************
+
+# Script info
+echo -e "clk_wiz_0.sh - Script generated by export_simulation (Vivado v2022.2 (64-bit)-id)\n"
+
+# Main steps
+run()
+{
+ check_args $# $1
+ setup $1 $2
+ compile
+ simulate
+}
+
+# RUN_STEP: <compile>
+compile()
+{
+ source compile.do 2>&1 | tee -a compile.log
+}
+
+# RUN_STEP: <simulate>
+simulate()
+{
+ vsim -64 -c -do "do {simulate.do}" -l simulate.log
+}
+
+# STEP: setup
+setup()
+{
+ case $1 in
+ "-lib_map_path" )
+ if [[ ($2 == "") ]]; then
+ echo -e "ERROR: Simulation library directory path not specified (type \"./clk_wiz_0.sh -help\" for more information)\n"
+ exit 1
+ fi
+ copy_setup_file $2
+ ;;
+ "-reset_run" )
+ reset_run
+ echo -e "INFO: Simulation run files deleted.\n"
+ exit 0
+ ;;
+ "-noclean_files" )
+ # do not remove previous data
+ ;;
+ * )
+ copy_setup_file $2
+ esac
+
+ create_lib_dir
+
+ # Add any setup/initialization commands here:-
+
+ # <user specific commands>
+
+}
+
+# Copy modelsim.ini file
+copy_setup_file()
+{
+ file="modelsim.ini"
+ lib_map_path="<SPECIFY_COMPILED_LIB_PATH>"
+ if [[ ($1 != "" && -e $1) ]]; then
+ lib_map_path="$1"
+ else
+ echo -e "ERROR: Compiled simulation library directory path not specified or does not exist (type "./top.sh -help" for more information)\n"
+ fi
+ if [[ ($lib_map_path != "") ]]; then
+ src_file="$lib_map_path/$file"
+ cp $src_file .
+ fi
+}
+
+# Create design library directory
+create_lib_dir()
+{
+ lib_dir="modelsim_lib"
+ if [[ -e $lib_dir ]]; then
+ rm -rf $lib_dir
+ fi
+
+ mkdir $lib_dir
+
+}
+
+# Delete generated data from the previous run
+reset_run()
+{
+ files_to_remove=(compile.log elaborate.log simulate.log vsim.wlf modelsim_lib)
+ for (( i=0; i<${#files_to_remove[*]}; i++ )); do
+ file="${files_to_remove[i]}"
+ if [[ -e $file ]]; then
+ rm -rf $file
+ fi
+ done
+
+ create_lib_dir
+}
+
+# Check command line arguments
+check_args()
+{
+ if [[ ($1 == 1 ) && ($2 != "-lib_map_path" && $2 != "-noclean_files" && $2 != "-reset_run" && $2 != "-help" && $2 != "-h") ]]; then
+ echo -e "ERROR: Unknown option specified '$2' (type \"./clk_wiz_0.sh -help\" for more information)\n"
+ exit 1
+ fi
+
+ if [[ ($2 == "-help" || $2 == "-h") ]]; then
+ usage
+ fi
+}
+
+# Script usage
+usage()
+{
+ msg="Usage: clk_wiz_0.sh [-help]\n\
+Usage: clk_wiz_0.sh [-lib_map_path]\n\
+Usage: clk_wiz_0.sh [-reset_run]\n\
+Usage: clk_wiz_0.sh [-noclean_files]\n\n\
+[-help] -- Print help information for this script\n\n\
+[-lib_map_path <path>] -- Compiled simulation library directory path. The simulation library is compiled\n\
+using the compile_simlib tcl command. Please see 'compile_simlib -help' for more information.\n\n\
+[-reset_run] -- Recreate simulator setup files and library mappings for a clean run. The generated files\n\
+from the previous run will be removed. If you don't want to remove the simulator generated files, use the\n\
+-noclean_files switch.\n\n\
+[-noclean_files] -- Reset previous run, but do not remove simulator generated files from the previous run.\n\n"
+ echo -e $msg
+ exit 1
+}
+
+# Launch script
+run $1 $2
diff --git a/game.ip_user_files/sim_scripts/clk_wiz_0/modelsim/clk_wiz_0.udo b/game.ip_user_files/sim_scripts/clk_wiz_0/modelsim/clk_wiz_0.udo
new file mode 100644
index 0000000000000000000000000000000000000000..e69de29bb2d1d6434b8b29ae775ad8c2e48c5391
diff --git a/game.ip_user_files/sim_scripts/clk_wiz_0/modelsim/compile.do b/game.ip_user_files/sim_scripts/clk_wiz_0/modelsim/compile.do
new file mode 100644
index 0000000000000000000000000000000000000000..04856688980a68eb324ece0483faba853f436552
--- /dev/null
+++ b/game.ip_user_files/sim_scripts/clk_wiz_0/modelsim/compile.do
@@ -0,0 +1,22 @@
+vlib modelsim_lib/work
+vlib modelsim_lib/msim
+
+vlib modelsim_lib/msim/xpm
+vlib modelsim_lib/msim/xil_defaultlib
+
+vmap xpm modelsim_lib/msim/xpm
+vmap xil_defaultlib modelsim_lib/msim/xil_defaultlib
+
+vlog -work xpm -64 -incr -mfcu -sv "+incdir+../../../../game.gen/sources_1/ip/clk_wiz_0" \
+"/opt/Xilinx/Vivado/2022.2/data/ip/xpm/xpm_cdc/hdl/xpm_cdc.sv" \
+
+vcom -work xpm -64 -93 \
+"/opt/Xilinx/Vivado/2022.2/data/ip/xpm/xpm_VCOMP.vhd" \
+
+vcom -work xil_defaultlib -64 -93 \
+"../../../../game.gen/sources_1/ip/clk_wiz_0/clk_wiz_0_sim_netlist.vhdl" \
+
+
+vlog -work xil_defaultlib \
+"glbl.v"
+
diff --git a/game.ip_user_files/sim_scripts/clk_wiz_0/modelsim/file_info.txt b/game.ip_user_files/sim_scripts/clk_wiz_0/modelsim/file_info.txt
new file mode 100644
index 0000000000000000000000000000000000000000..275a6e12cd472264cee1afb10355af4b66b5d48f
--- /dev/null
+++ b/game.ip_user_files/sim_scripts/clk_wiz_0/modelsim/file_info.txt
@@ -0,0 +1,4 @@
+xpm_cdc.sv,systemverilog,xpm,../../../opt/Xilinx/Vivado/2022.2/data/ip/xpm/xpm_cdc/hdl/xpm_cdc.sv,incdir="../../../../game.gen/sources_1/ip/clk_wiz_0"
+xpm_VCOMP.vhd,vhdl,xpm,../../../opt/Xilinx/Vivado/2022.2/data/ip/xpm/xpm_VCOMP.vhd,incdir="../../../../game.gen/sources_1/ip/clk_wiz_0"
+clk_wiz_0_sim_netlist.vhdl,vhdl,xil_defaultlib,../../../../game.gen/sources_1/ip/clk_wiz_0/clk_wiz_0_sim_netlist.vhdl,incdir="../../../../game.gen/sources_1/ip/clk_wiz_0"
+glbl.v,Verilog,xil_defaultlib,glbl.v
diff --git a/game.ip_user_files/sim_scripts/clk_wiz_0/modelsim/glbl.v b/game.ip_user_files/sim_scripts/clk_wiz_0/modelsim/glbl.v
new file mode 100644
index 0000000000000000000000000000000000000000..ed3b249ceef65a0d1b42790def9ee8179363679c
--- /dev/null
+++ b/game.ip_user_files/sim_scripts/clk_wiz_0/modelsim/glbl.v
@@ -0,0 +1,84 @@
+// $Header: /devl/xcs/repo/env/Databases/CAEInterfaces/verunilibs/data/glbl.v,v 1.14 2010/10/28 20:44:00 fphillip Exp $
+`ifndef GLBL
+`define GLBL
+`timescale 1 ps / 1 ps
+
+module glbl ();
+
+ parameter ROC_WIDTH = 100000;
+ parameter TOC_WIDTH = 0;
+ parameter GRES_WIDTH = 10000;
+ parameter GRES_START = 10000;
+
+//-------- STARTUP Globals --------------
+ wire GSR;
+ wire GTS;
+ wire GWE;
+ wire PRLD;
+ wire GRESTORE;
+ tri1 p_up_tmp;
+ tri (weak1, strong0) PLL_LOCKG = p_up_tmp;
+
+ wire PROGB_GLBL;
+ wire CCLKO_GLBL;
+ wire FCSBO_GLBL;
+ wire [3:0] DO_GLBL;
+ wire [3:0] DI_GLBL;
+
+ reg GSR_int;
+ reg GTS_int;
+ reg PRLD_int;
+ reg GRESTORE_int;
+
+//-------- JTAG Globals --------------
+ wire JTAG_TDO_GLBL;
+ wire JTAG_TCK_GLBL;
+ wire JTAG_TDI_GLBL;
+ wire JTAG_TMS_GLBL;
+ wire JTAG_TRST_GLBL;
+
+ reg JTAG_CAPTURE_GLBL;
+ reg JTAG_RESET_GLBL;
+ reg JTAG_SHIFT_GLBL;
+ reg JTAG_UPDATE_GLBL;
+ reg JTAG_RUNTEST_GLBL;
+
+ reg JTAG_SEL1_GLBL = 0;
+ reg JTAG_SEL2_GLBL = 0 ;
+ reg JTAG_SEL3_GLBL = 0;
+ reg JTAG_SEL4_GLBL = 0;
+
+ reg JTAG_USER_TDO1_GLBL = 1'bz;
+ reg JTAG_USER_TDO2_GLBL = 1'bz;
+ reg JTAG_USER_TDO3_GLBL = 1'bz;
+ reg JTAG_USER_TDO4_GLBL = 1'bz;
+
+ assign (strong1, weak0) GSR = GSR_int;
+ assign (strong1, weak0) GTS = GTS_int;
+ assign (weak1, weak0) PRLD = PRLD_int;
+ assign (strong1, weak0) GRESTORE = GRESTORE_int;
+
+ initial begin
+ GSR_int = 1'b1;
+ PRLD_int = 1'b1;
+ #(ROC_WIDTH)
+ GSR_int = 1'b0;
+ PRLD_int = 1'b0;
+ end
+
+ initial begin
+ GTS_int = 1'b1;
+ #(TOC_WIDTH)
+ GTS_int = 1'b0;
+ end
+
+ initial begin
+ GRESTORE_int = 1'b0;
+ #(GRES_START);
+ GRESTORE_int = 1'b1;
+ #(GRES_WIDTH);
+ GRESTORE_int = 1'b0;
+ end
+
+endmodule
+`endif
diff --git a/game.ip_user_files/sim_scripts/clk_wiz_0/modelsim/simulate.do b/game.ip_user_files/sim_scripts/clk_wiz_0/modelsim/simulate.do
new file mode 100644
index 0000000000000000000000000000000000000000..68a9ae762e5be488be759d2a9ba70cb512b52372
--- /dev/null
+++ b/game.ip_user_files/sim_scripts/clk_wiz_0/modelsim/simulate.do
@@ -0,0 +1,19 @@
+onbreak {quit -f}
+onerror {quit -f}
+
+vsim -voptargs="+acc " -L xpm -L xil_defaultlib -L unisims_ver -L unimacro_ver -L secureip -lib xil_defaultlib xil_defaultlib.clk_wiz_0 xil_defaultlib.glbl
+
+set NumericStdNoWarnings 1
+set StdArithNoWarnings 1
+
+do {wave.do}
+
+view wave
+view structure
+view signals
+
+do {clk_wiz_0.udo}
+
+run 1000ns
+
+quit -force
diff --git a/game.ip_user_files/sim_scripts/clk_wiz_0/modelsim/wave.do b/game.ip_user_files/sim_scripts/clk_wiz_0/modelsim/wave.do
new file mode 100644
index 0000000000000000000000000000000000000000..70157b0cf36569bda8275f1a9640c41911f8d5f7
--- /dev/null
+++ b/game.ip_user_files/sim_scripts/clk_wiz_0/modelsim/wave.do
@@ -0,0 +1,2 @@
+add wave *
+add wave /glbl/GSR
diff --git a/game.ip_user_files/sim_scripts/clk_wiz_0/questa/README.txt b/game.ip_user_files/sim_scripts/clk_wiz_0/questa/README.txt
new file mode 100644
index 0000000000000000000000000000000000000000..193e9e2b2252650fd85b3c628bc718694820608b
--- /dev/null
+++ b/game.ip_user_files/sim_scripts/clk_wiz_0/questa/README.txt
@@ -0,0 +1,49 @@
+################################################################################
+# Vivado (TM) v2022.2 (64-bit)
+#
+# README.txt: Please read the sections below to understand the steps required to
+# run the exported script and information about the source files.
+#
+# Generated by export_simulation on Mon Feb 27 10:47:03 CET 2023
+#
+################################################################################
+
+1. How to run the generated simulation script:-
+
+From the shell prompt in the current directory, issue the following command:-
+
+./clk_wiz_0.sh
+
+This command will launch the 'compile', 'elaborate' and 'simulate' functions
+implemented in the script file for the 3-step flow. These functions are called
+from the main 'run' function in the script file.
+
+The 'run' function first executes the 'setup' function, the purpose of which is to
+create simulator specific setup files, create design library mappings and library
+directories and copy 'glbl.v' from the Vivado software install location into the
+current directory.
+
+The 'setup' function is also used for removing the simulator generated data in
+order to reset the current directory to the original state when export_simulation
+was launched from Vivado. This generated data can be removed by specifying the
+'-reset_run' switch to the './clk_wiz_0.sh' script.
+
+./clk_wiz_0.sh -reset_run
+
+To keep the generated data from the previous run but regenerate the setup files and
+library directories, use the '-noclean_files' switch.
+
+./clk_wiz_0.sh -noclean_files
+
+For more information on the script, please type './clk_wiz_0.sh -help'.
+
+2. Additional design information files:-
+
+export_simulation generates following additional file that can be used for fetching
+the design files information or for integrating with external custom scripts.
+
+Name : file_info.txt
+Purpose: This file contains detail design file information based on the compile order
+ when export_simulation was executed from Vivado. The file contains information
+ about the file type, name, whether it is part of the IP, associated library
+ and the file path information.
diff --git a/game.ip_user_files/sim_scripts/clk_wiz_0/questa/clk_wiz_0.sh b/game.ip_user_files/sim_scripts/clk_wiz_0/questa/clk_wiz_0.sh
new file mode 100755
index 0000000000000000000000000000000000000000..d85db81d8e76cb483ba07c4b076442215f1086a5
--- /dev/null
+++ b/game.ip_user_files/sim_scripts/clk_wiz_0/questa/clk_wiz_0.sh
@@ -0,0 +1,172 @@
+#!/bin/bash -f
+#*********************************************************************************************************
+# Vivado (TM) v2022.2 (64-bit)
+#
+# Filename : clk_wiz_0.sh
+# Simulator : Mentor Graphics Questa Advanced Simulator
+# Description : Simulation script for compiling, elaborating and verifying the project source files.
+# The script will automatically create the design libraries sub-directories in the run
+# directory, add the library logical mappings in the simulator setup file, create default
+# 'do/prj' file, execute compilation, elaboration and simulation steps.
+#
+# Generated by Vivado on Mon Feb 27 10:47:03 CET 2023
+# SW Build 3671981 on Fri Oct 14 04:59:54 MDT 2022
+#
+# Tool Version Limit: 2022.10
+#
+# usage: clk_wiz_0.sh [-help]
+# usage: clk_wiz_0.sh [-lib_map_path]
+# usage: clk_wiz_0.sh [-noclean_files]
+# usage: clk_wiz_0.sh [-reset_run]
+#
+# Prerequisite:- To compile and run simulation, you must compile the Xilinx simulation libraries using the
+# 'compile_simlib' TCL command. For more information about this command, run 'compile_simlib -help' in the
+# Vivado Tcl Shell. Once the libraries have been compiled successfully, specify the -lib_map_path switch
+# that points to these libraries and rerun export_simulation. For more information about this switch please
+# type 'export_simulation -help' in the Tcl shell.
+#
+# You can also point to the simulation libraries by either replacing the <SPECIFY_COMPILED_LIB_PATH> in this
+# script with the compiled library directory path or specify this path with the '-lib_map_path' switch when
+# executing this script. Please type 'clk_wiz_0.sh -help' for more information.
+#
+# Additional references - 'Xilinx Vivado Design Suite User Guide:Logic simulation (UG900)'
+#
+#*********************************************************************************************************
+
+# Script info
+echo -e "clk_wiz_0.sh - Script generated by export_simulation (Vivado v2022.2 (64-bit)-id)\n"
+
+# Main steps
+run()
+{
+ check_args $# $1
+ setup $1 $2
+ compile
+ elaborate
+ simulate
+}
+
+# RUN_STEP: <compile>
+compile()
+{
+ source compile.do 2>&1 | tee -a compile.log
+}
+
+# RUN_STEP: <elaborate>
+elaborate()
+{
+ source elaborate.do 2>&1 | tee elaborate.log
+}
+
+# RUN_STEP: <simulate>
+simulate()
+{
+ vsim -64 -c -do "do {simulate.do}" -l simulate.log
+}
+
+# STEP: setup
+setup()
+{
+ case $1 in
+ "-lib_map_path" )
+ if [[ ($2 == "") ]]; then
+ echo -e "ERROR: Simulation library directory path not specified (type \"./clk_wiz_0.sh -help\" for more information)\n"
+ exit 1
+ fi
+ copy_setup_file $2
+ ;;
+ "-reset_run" )
+ reset_run
+ echo -e "INFO: Simulation run files deleted.\n"
+ exit 0
+ ;;
+ "-noclean_files" )
+ # do not remove previous data
+ ;;
+ * )
+ copy_setup_file $2
+ esac
+
+ create_lib_dir
+
+ # Add any setup/initialization commands here:-
+
+ # <user specific commands>
+
+}
+
+# Copy modelsim.ini file
+copy_setup_file()
+{
+ file="modelsim.ini"
+ lib_map_path="<SPECIFY_COMPILED_LIB_PATH>"
+ if [[ ($1 != "" && -e $1) ]]; then
+ lib_map_path="$1"
+ else
+ echo -e "ERROR: Compiled simulation library directory path not specified or does not exist (type "./top.sh -help" for more information)\n"
+ fi
+ if [[ ($lib_map_path != "") ]]; then
+ src_file="$lib_map_path/$file"
+ cp $src_file .
+ fi
+}
+
+# Create design library directory
+create_lib_dir()
+{
+ lib_dir="questa_lib"
+ if [[ -e $lib_dir ]]; then
+ rm -rf $lib_dir
+ fi
+
+ mkdir $lib_dir
+
+}
+
+# Delete generated data from the previous run
+reset_run()
+{
+ files_to_remove=(compile.log elaborate.log simulate.log vsim.wlf questa_lib)
+ for (( i=0; i<${#files_to_remove[*]}; i++ )); do
+ file="${files_to_remove[i]}"
+ if [[ -e $file ]]; then
+ rm -rf $file
+ fi
+ done
+
+ create_lib_dir
+}
+
+# Check command line arguments
+check_args()
+{
+ if [[ ($1 == 1 ) && ($2 != "-lib_map_path" && $2 != "-noclean_files" && $2 != "-reset_run" && $2 != "-help" && $2 != "-h") ]]; then
+ echo -e "ERROR: Unknown option specified '$2' (type \"./clk_wiz_0.sh -help\" for more information)\n"
+ exit 1
+ fi
+
+ if [[ ($2 == "-help" || $2 == "-h") ]]; then
+ usage
+ fi
+}
+
+# Script usage
+usage()
+{
+ msg="Usage: clk_wiz_0.sh [-help]\n\
+Usage: clk_wiz_0.sh [-lib_map_path]\n\
+Usage: clk_wiz_0.sh [-reset_run]\n\
+Usage: clk_wiz_0.sh [-noclean_files]\n\n\
+[-help] -- Print help information for this script\n\n\
+[-lib_map_path <path>] -- Compiled simulation library directory path. The simulation library is compiled\n\
+using the compile_simlib tcl command. Please see 'compile_simlib -help' for more information.\n\n\
+[-reset_run] -- Recreate simulator setup files and library mappings for a clean run. The generated files\n\
+from the previous run will be removed. If you don't want to remove the simulator generated files, use the\n\
+-noclean_files switch.\n\n\
+[-noclean_files] -- Reset previous run, but do not remove simulator generated files from the previous run.\n\n"
+ echo -e $msg
+ exit 1
+}
+
+# Launch script
+run $1 $2
diff --git a/game.ip_user_files/sim_scripts/clk_wiz_0/questa/clk_wiz_0.udo b/game.ip_user_files/sim_scripts/clk_wiz_0/questa/clk_wiz_0.udo
new file mode 100644
index 0000000000000000000000000000000000000000..e69de29bb2d1d6434b8b29ae775ad8c2e48c5391
diff --git a/game.ip_user_files/sim_scripts/clk_wiz_0/questa/compile.do b/game.ip_user_files/sim_scripts/clk_wiz_0/questa/compile.do
new file mode 100644
index 0000000000000000000000000000000000000000..a07c691b0b6cf9dc83434da302694e002bf45014
--- /dev/null
+++ b/game.ip_user_files/sim_scripts/clk_wiz_0/questa/compile.do
@@ -0,0 +1,22 @@
+vlib questa_lib/work
+vlib questa_lib/msim
+
+vlib questa_lib/msim/xpm
+vlib questa_lib/msim/xil_defaultlib
+
+vmap xpm questa_lib/msim/xpm
+vmap xil_defaultlib questa_lib/msim/xil_defaultlib
+
+vlog -work xpm -64 -incr -mfcu -sv "+incdir+../../../../game.gen/sources_1/ip/clk_wiz_0" \
+"/opt/Xilinx/Vivado/2022.2/data/ip/xpm/xpm_cdc/hdl/xpm_cdc.sv" \
+
+vcom -work xpm -64 -93 \
+"/opt/Xilinx/Vivado/2022.2/data/ip/xpm/xpm_VCOMP.vhd" \
+
+vcom -work xil_defaultlib -64 -93 \
+"../../../../game.gen/sources_1/ip/clk_wiz_0/clk_wiz_0_sim_netlist.vhdl" \
+
+
+vlog -work xil_defaultlib \
+"glbl.v"
+
diff --git a/game.ip_user_files/sim_scripts/clk_wiz_0/questa/elaborate.do b/game.ip_user_files/sim_scripts/clk_wiz_0/questa/elaborate.do
new file mode 100644
index 0000000000000000000000000000000000000000..8a0f445ccc74276ce5ed36a90dcb0578ffcd865c
--- /dev/null
+++ b/game.ip_user_files/sim_scripts/clk_wiz_0/questa/elaborate.do
@@ -0,0 +1 @@
+vopt -64 +acc=npr -l elaborate.log -L xil_defaultlib -L xpm -L unisims_ver -L unimacro_ver -L secureip -work xil_defaultlib xil_defaultlib.clk_wiz_0 xil_defaultlib.glbl -o clk_wiz_0_opt
diff --git a/game.ip_user_files/sim_scripts/clk_wiz_0/questa/file_info.txt b/game.ip_user_files/sim_scripts/clk_wiz_0/questa/file_info.txt
new file mode 100644
index 0000000000000000000000000000000000000000..275a6e12cd472264cee1afb10355af4b66b5d48f
--- /dev/null
+++ b/game.ip_user_files/sim_scripts/clk_wiz_0/questa/file_info.txt
@@ -0,0 +1,4 @@
+xpm_cdc.sv,systemverilog,xpm,../../../opt/Xilinx/Vivado/2022.2/data/ip/xpm/xpm_cdc/hdl/xpm_cdc.sv,incdir="../../../../game.gen/sources_1/ip/clk_wiz_0"
+xpm_VCOMP.vhd,vhdl,xpm,../../../opt/Xilinx/Vivado/2022.2/data/ip/xpm/xpm_VCOMP.vhd,incdir="../../../../game.gen/sources_1/ip/clk_wiz_0"
+clk_wiz_0_sim_netlist.vhdl,vhdl,xil_defaultlib,../../../../game.gen/sources_1/ip/clk_wiz_0/clk_wiz_0_sim_netlist.vhdl,incdir="../../../../game.gen/sources_1/ip/clk_wiz_0"
+glbl.v,Verilog,xil_defaultlib,glbl.v
diff --git a/game.ip_user_files/sim_scripts/clk_wiz_0/questa/glbl.v b/game.ip_user_files/sim_scripts/clk_wiz_0/questa/glbl.v
new file mode 100644
index 0000000000000000000000000000000000000000..ed3b249ceef65a0d1b42790def9ee8179363679c
--- /dev/null
+++ b/game.ip_user_files/sim_scripts/clk_wiz_0/questa/glbl.v
@@ -0,0 +1,84 @@
+// $Header: /devl/xcs/repo/env/Databases/CAEInterfaces/verunilibs/data/glbl.v,v 1.14 2010/10/28 20:44:00 fphillip Exp $
+`ifndef GLBL
+`define GLBL
+`timescale 1 ps / 1 ps
+
+module glbl ();
+
+ parameter ROC_WIDTH = 100000;
+ parameter TOC_WIDTH = 0;
+ parameter GRES_WIDTH = 10000;
+ parameter GRES_START = 10000;
+
+//-------- STARTUP Globals --------------
+ wire GSR;
+ wire GTS;
+ wire GWE;
+ wire PRLD;
+ wire GRESTORE;
+ tri1 p_up_tmp;
+ tri (weak1, strong0) PLL_LOCKG = p_up_tmp;
+
+ wire PROGB_GLBL;
+ wire CCLKO_GLBL;
+ wire FCSBO_GLBL;
+ wire [3:0] DO_GLBL;
+ wire [3:0] DI_GLBL;
+
+ reg GSR_int;
+ reg GTS_int;
+ reg PRLD_int;
+ reg GRESTORE_int;
+
+//-------- JTAG Globals --------------
+ wire JTAG_TDO_GLBL;
+ wire JTAG_TCK_GLBL;
+ wire JTAG_TDI_GLBL;
+ wire JTAG_TMS_GLBL;
+ wire JTAG_TRST_GLBL;
+
+ reg JTAG_CAPTURE_GLBL;
+ reg JTAG_RESET_GLBL;
+ reg JTAG_SHIFT_GLBL;
+ reg JTAG_UPDATE_GLBL;
+ reg JTAG_RUNTEST_GLBL;
+
+ reg JTAG_SEL1_GLBL = 0;
+ reg JTAG_SEL2_GLBL = 0 ;
+ reg JTAG_SEL3_GLBL = 0;
+ reg JTAG_SEL4_GLBL = 0;
+
+ reg JTAG_USER_TDO1_GLBL = 1'bz;
+ reg JTAG_USER_TDO2_GLBL = 1'bz;
+ reg JTAG_USER_TDO3_GLBL = 1'bz;
+ reg JTAG_USER_TDO4_GLBL = 1'bz;
+
+ assign (strong1, weak0) GSR = GSR_int;
+ assign (strong1, weak0) GTS = GTS_int;
+ assign (weak1, weak0) PRLD = PRLD_int;
+ assign (strong1, weak0) GRESTORE = GRESTORE_int;
+
+ initial begin
+ GSR_int = 1'b1;
+ PRLD_int = 1'b1;
+ #(ROC_WIDTH)
+ GSR_int = 1'b0;
+ PRLD_int = 1'b0;
+ end
+
+ initial begin
+ GTS_int = 1'b1;
+ #(TOC_WIDTH)
+ GTS_int = 1'b0;
+ end
+
+ initial begin
+ GRESTORE_int = 1'b0;
+ #(GRES_START);
+ GRESTORE_int = 1'b1;
+ #(GRES_WIDTH);
+ GRESTORE_int = 1'b0;
+ end
+
+endmodule
+`endif
diff --git a/game.ip_user_files/sim_scripts/clk_wiz_0/questa/simulate.do b/game.ip_user_files/sim_scripts/clk_wiz_0/questa/simulate.do
new file mode 100644
index 0000000000000000000000000000000000000000..81ab20f2c1e6fb2a82acf793792f3d55ea2f8ded
--- /dev/null
+++ b/game.ip_user_files/sim_scripts/clk_wiz_0/questa/simulate.do
@@ -0,0 +1,19 @@
+onbreak {quit -f}
+onerror {quit -f}
+
+vsim -lib xil_defaultlib clk_wiz_0_opt
+
+set NumericStdNoWarnings 1
+set StdArithNoWarnings 1
+
+do {wave.do}
+
+view wave
+view structure
+view signals
+
+do {clk_wiz_0.udo}
+
+run 1000ns
+
+quit -force
diff --git a/game.ip_user_files/sim_scripts/clk_wiz_0/questa/wave.do b/game.ip_user_files/sim_scripts/clk_wiz_0/questa/wave.do
new file mode 100644
index 0000000000000000000000000000000000000000..70157b0cf36569bda8275f1a9640c41911f8d5f7
--- /dev/null
+++ b/game.ip_user_files/sim_scripts/clk_wiz_0/questa/wave.do
@@ -0,0 +1,2 @@
+add wave *
+add wave /glbl/GSR
diff --git a/game.ip_user_files/sim_scripts/clk_wiz_0/riviera/README.txt b/game.ip_user_files/sim_scripts/clk_wiz_0/riviera/README.txt
new file mode 100644
index 0000000000000000000000000000000000000000..193e9e2b2252650fd85b3c628bc718694820608b
--- /dev/null
+++ b/game.ip_user_files/sim_scripts/clk_wiz_0/riviera/README.txt
@@ -0,0 +1,49 @@
+################################################################################
+# Vivado (TM) v2022.2 (64-bit)
+#
+# README.txt: Please read the sections below to understand the steps required to
+# run the exported script and information about the source files.
+#
+# Generated by export_simulation on Mon Feb 27 10:47:03 CET 2023
+#
+################################################################################
+
+1. How to run the generated simulation script:-
+
+From the shell prompt in the current directory, issue the following command:-
+
+./clk_wiz_0.sh
+
+This command will launch the 'compile', 'elaborate' and 'simulate' functions
+implemented in the script file for the 3-step flow. These functions are called
+from the main 'run' function in the script file.
+
+The 'run' function first executes the 'setup' function, the purpose of which is to
+create simulator specific setup files, create design library mappings and library
+directories and copy 'glbl.v' from the Vivado software install location into the
+current directory.
+
+The 'setup' function is also used for removing the simulator generated data in
+order to reset the current directory to the original state when export_simulation
+was launched from Vivado. This generated data can be removed by specifying the
+'-reset_run' switch to the './clk_wiz_0.sh' script.
+
+./clk_wiz_0.sh -reset_run
+
+To keep the generated data from the previous run but regenerate the setup files and
+library directories, use the '-noclean_files' switch.
+
+./clk_wiz_0.sh -noclean_files
+
+For more information on the script, please type './clk_wiz_0.sh -help'.
+
+2. Additional design information files:-
+
+export_simulation generates following additional file that can be used for fetching
+the design files information or for integrating with external custom scripts.
+
+Name : file_info.txt
+Purpose: This file contains detail design file information based on the compile order
+ when export_simulation was executed from Vivado. The file contains information
+ about the file type, name, whether it is part of the IP, associated library
+ and the file path information.
diff --git a/game.ip_user_files/sim_scripts/clk_wiz_0/riviera/clk_wiz_0.sh b/game.ip_user_files/sim_scripts/clk_wiz_0/riviera/clk_wiz_0.sh
new file mode 100755
index 0000000000000000000000000000000000000000..056e8195fa85bb6f5bb2b4337604319e8e8052eb
--- /dev/null
+++ b/game.ip_user_files/sim_scripts/clk_wiz_0/riviera/clk_wiz_0.sh
@@ -0,0 +1,151 @@
+#!/bin/bash -f
+#*********************************************************************************************************
+# Vivado (TM) v2022.2 (64-bit)
+#
+# Filename : clk_wiz_0.sh
+# Simulator : Aldec Riviera-PRO Simulator
+# Description : Simulation script for compiling, elaborating and verifying the project source files.
+# The script will automatically create the design libraries sub-directories in the run
+# directory, add the library logical mappings in the simulator setup file, create default
+# 'do/prj' file, execute compilation, elaboration and simulation steps.
+#
+# Generated by Vivado on Mon Feb 27 10:47:03 CET 2023
+# SW Build 3671981 on Fri Oct 14 04:59:54 MDT 2022
+#
+# Tool Version Limit: 2022.10
+#
+# usage: clk_wiz_0.sh [-help]
+# usage: clk_wiz_0.sh [-lib_map_path]
+# usage: clk_wiz_0.sh [-noclean_files]
+# usage: clk_wiz_0.sh [-reset_run]
+#
+# Prerequisite:- To compile and run simulation, you must compile the Xilinx simulation libraries using the
+# 'compile_simlib' TCL command. For more information about this command, run 'compile_simlib -help' in the
+# Vivado Tcl Shell. Once the libraries have been compiled successfully, specify the -lib_map_path switch
+# that points to these libraries and rerun export_simulation. For more information about this switch please
+# type 'export_simulation -help' in the Tcl shell.
+#
+# You can also point to the simulation libraries by either replacing the <SPECIFY_COMPILED_LIB_PATH> in this
+# script with the compiled library directory path or specify this path with the '-lib_map_path' switch when
+# executing this script. Please type 'clk_wiz_0.sh -help' for more information.
+#
+# Additional references - 'Xilinx Vivado Design Suite User Guide:Logic simulation (UG900)'
+#
+#*********************************************************************************************************
+
+# Script info
+echo -e "clk_wiz_0.sh - Script generated by export_simulation (Vivado v2022.2 (64-bit)-id)\n"
+
+# Main steps
+run()
+{
+ check_args $# $1
+ setup $1 $2
+ compile
+ simulate
+}
+
+# RUN_STEP: <compile>
+compile()
+{
+ source compile.do 2>&1 | tee -a compile.log
+}
+
+# RUN_STEP: <simulate>
+simulate()
+{
+ runvsimsa -l simulate.log -do "do {simulate.do}"
+}
+
+# STEP: setup
+setup()
+{
+ case $1 in
+ "-lib_map_path" )
+ if [[ ($2 == "") ]]; then
+ echo -e "ERROR: Simulation library directory path not specified (type \"./clk_wiz_0.sh -help\" for more information)\n"
+ exit 1
+ fi
+ map_setup_file $2
+ ;;
+ "-reset_run" )
+ reset_run
+ echo -e "INFO: Simulation run files deleted.\n"
+ exit 0
+ ;;
+ "-noclean_files" )
+ # do not remove previous data
+ ;;
+ * )
+ map_setup_file $2
+ esac
+
+ # Add any setup/initialization commands here:-
+
+ # <user specific commands>
+
+}
+
+# Map library.cfg file
+map_setup_file()
+{
+ file="library.cfg"
+ lib_map_path="<SPECIFY_COMPILED_LIB_PATH>"
+ if [[ ($1 != "" && -e $1) ]]; then
+ lib_map_path="$1"
+ else
+ echo -e "ERROR: Compiled simulation library directory path not specified or does not exist (type "./top.sh -help" for more information)\n"
+ fi
+ if [[ ($lib_map_path != "") ]]; then
+ src_file="$lib_map_path/$file"
+ if [[ -e $src_file ]]; then
+ vmap -link $lib_map_path
+ fi
+ fi
+}
+
+# Delete generated data from the previous run
+reset_run()
+{
+ files_to_remove=(compile.log elaboration.log simulate.log dataset.asdb work riviera)
+ for (( i=0; i<${#files_to_remove[*]}; i++ )); do
+ file="${files_to_remove[i]}"
+ if [[ -e $file ]]; then
+ rm -rf $file
+ fi
+ done
+}
+
+# Check command line arguments
+check_args()
+{
+ if [[ ($1 == 1 ) && ($2 != "-lib_map_path" && $2 != "-noclean_files" && $2 != "-reset_run" && $2 != "-help" && $2 != "-h") ]]; then
+ echo -e "ERROR: Unknown option specified '$2' (type \"./clk_wiz_0.sh -help\" for more information)\n"
+ exit 1
+ fi
+
+ if [[ ($2 == "-help" || $2 == "-h") ]]; then
+ usage
+ fi
+}
+
+# Script usage
+usage()
+{
+ msg="Usage: clk_wiz_0.sh [-help]\n\
+Usage: clk_wiz_0.sh [-lib_map_path]\n\
+Usage: clk_wiz_0.sh [-reset_run]\n\
+Usage: clk_wiz_0.sh [-noclean_files]\n\n\
+[-help] -- Print help information for this script\n\n\
+[-lib_map_path <path>] -- Compiled simulation library directory path. The simulation library is compiled\n\
+using the compile_simlib tcl command. Please see 'compile_simlib -help' for more information.\n\n\
+[-reset_run] -- Recreate simulator setup files and library mappings for a clean run. The generated files\n\
+from the previous run will be removed. If you don't want to remove the simulator generated files, use the\n\
+-noclean_files switch.\n\n\
+[-noclean_files] -- Reset previous run, but do not remove simulator generated files from the previous run.\n\n"
+ echo -e $msg
+ exit 1
+}
+
+# Launch script
+run $1 $2
diff --git a/game.ip_user_files/sim_scripts/clk_wiz_0/riviera/clk_wiz_0.udo b/game.ip_user_files/sim_scripts/clk_wiz_0/riviera/clk_wiz_0.udo
new file mode 100644
index 0000000000000000000000000000000000000000..e69de29bb2d1d6434b8b29ae775ad8c2e48c5391
diff --git a/game.ip_user_files/sim_scripts/clk_wiz_0/riviera/compile.do b/game.ip_user_files/sim_scripts/clk_wiz_0/riviera/compile.do
new file mode 100644
index 0000000000000000000000000000000000000000..667a7d5404b15ba52a3595e75a7bac1ad8fdc0e9
--- /dev/null
+++ b/game.ip_user_files/sim_scripts/clk_wiz_0/riviera/compile.do
@@ -0,0 +1,22 @@
+vlib work
+vlib riviera
+
+vlib riviera/xpm
+vlib riviera/xil_defaultlib
+
+vmap xpm riviera/xpm
+vmap xil_defaultlib riviera/xil_defaultlib
+
+vlog -work xpm -sv2k12 "+incdir+../../../../game.gen/sources_1/ip/clk_wiz_0" \
+"/opt/Xilinx/Vivado/2022.2/data/ip/xpm/xpm_cdc/hdl/xpm_cdc.sv" \
+
+vcom -work xpm -93 \
+"/opt/Xilinx/Vivado/2022.2/data/ip/xpm/xpm_VCOMP.vhd" \
+
+vcom -work xil_defaultlib -93 \
+"../../../../game.gen/sources_1/ip/clk_wiz_0/clk_wiz_0_sim_netlist.vhdl" \
+
+
+vlog -work xil_defaultlib \
+"glbl.v"
+
diff --git a/game.ip_user_files/sim_scripts/clk_wiz_0/riviera/file_info.txt b/game.ip_user_files/sim_scripts/clk_wiz_0/riviera/file_info.txt
new file mode 100644
index 0000000000000000000000000000000000000000..275a6e12cd472264cee1afb10355af4b66b5d48f
--- /dev/null
+++ b/game.ip_user_files/sim_scripts/clk_wiz_0/riviera/file_info.txt
@@ -0,0 +1,4 @@
+xpm_cdc.sv,systemverilog,xpm,../../../opt/Xilinx/Vivado/2022.2/data/ip/xpm/xpm_cdc/hdl/xpm_cdc.sv,incdir="../../../../game.gen/sources_1/ip/clk_wiz_0"
+xpm_VCOMP.vhd,vhdl,xpm,../../../opt/Xilinx/Vivado/2022.2/data/ip/xpm/xpm_VCOMP.vhd,incdir="../../../../game.gen/sources_1/ip/clk_wiz_0"
+clk_wiz_0_sim_netlist.vhdl,vhdl,xil_defaultlib,../../../../game.gen/sources_1/ip/clk_wiz_0/clk_wiz_0_sim_netlist.vhdl,incdir="../../../../game.gen/sources_1/ip/clk_wiz_0"
+glbl.v,Verilog,xil_defaultlib,glbl.v
diff --git a/game.ip_user_files/sim_scripts/clk_wiz_0/riviera/glbl.v b/game.ip_user_files/sim_scripts/clk_wiz_0/riviera/glbl.v
new file mode 100644
index 0000000000000000000000000000000000000000..ed3b249ceef65a0d1b42790def9ee8179363679c
--- /dev/null
+++ b/game.ip_user_files/sim_scripts/clk_wiz_0/riviera/glbl.v
@@ -0,0 +1,84 @@
+// $Header: /devl/xcs/repo/env/Databases/CAEInterfaces/verunilibs/data/glbl.v,v 1.14 2010/10/28 20:44:00 fphillip Exp $
+`ifndef GLBL
+`define GLBL
+`timescale 1 ps / 1 ps
+
+module glbl ();
+
+ parameter ROC_WIDTH = 100000;
+ parameter TOC_WIDTH = 0;
+ parameter GRES_WIDTH = 10000;
+ parameter GRES_START = 10000;
+
+//-------- STARTUP Globals --------------
+ wire GSR;
+ wire GTS;
+ wire GWE;
+ wire PRLD;
+ wire GRESTORE;
+ tri1 p_up_tmp;
+ tri (weak1, strong0) PLL_LOCKG = p_up_tmp;
+
+ wire PROGB_GLBL;
+ wire CCLKO_GLBL;
+ wire FCSBO_GLBL;
+ wire [3:0] DO_GLBL;
+ wire [3:0] DI_GLBL;
+
+ reg GSR_int;
+ reg GTS_int;
+ reg PRLD_int;
+ reg GRESTORE_int;
+
+//-------- JTAG Globals --------------
+ wire JTAG_TDO_GLBL;
+ wire JTAG_TCK_GLBL;
+ wire JTAG_TDI_GLBL;
+ wire JTAG_TMS_GLBL;
+ wire JTAG_TRST_GLBL;
+
+ reg JTAG_CAPTURE_GLBL;
+ reg JTAG_RESET_GLBL;
+ reg JTAG_SHIFT_GLBL;
+ reg JTAG_UPDATE_GLBL;
+ reg JTAG_RUNTEST_GLBL;
+
+ reg JTAG_SEL1_GLBL = 0;
+ reg JTAG_SEL2_GLBL = 0 ;
+ reg JTAG_SEL3_GLBL = 0;
+ reg JTAG_SEL4_GLBL = 0;
+
+ reg JTAG_USER_TDO1_GLBL = 1'bz;
+ reg JTAG_USER_TDO2_GLBL = 1'bz;
+ reg JTAG_USER_TDO3_GLBL = 1'bz;
+ reg JTAG_USER_TDO4_GLBL = 1'bz;
+
+ assign (strong1, weak0) GSR = GSR_int;
+ assign (strong1, weak0) GTS = GTS_int;
+ assign (weak1, weak0) PRLD = PRLD_int;
+ assign (strong1, weak0) GRESTORE = GRESTORE_int;
+
+ initial begin
+ GSR_int = 1'b1;
+ PRLD_int = 1'b1;
+ #(ROC_WIDTH)
+ GSR_int = 1'b0;
+ PRLD_int = 1'b0;
+ end
+
+ initial begin
+ GTS_int = 1'b1;
+ #(TOC_WIDTH)
+ GTS_int = 1'b0;
+ end
+
+ initial begin
+ GRESTORE_int = 1'b0;
+ #(GRES_START);
+ GRESTORE_int = 1'b1;
+ #(GRES_WIDTH);
+ GRESTORE_int = 1'b0;
+ end
+
+endmodule
+`endif
diff --git a/game.ip_user_files/sim_scripts/clk_wiz_0/riviera/simulate.do b/game.ip_user_files/sim_scripts/clk_wiz_0/riviera/simulate.do
new file mode 100644
index 0000000000000000000000000000000000000000..05f355ee1ee0371e43b72503378cec0926ab7611
--- /dev/null
+++ b/game.ip_user_files/sim_scripts/clk_wiz_0/riviera/simulate.do
@@ -0,0 +1,20 @@
+onbreak {quit -force}
+onerror {quit -force}
+
+asim +access +r +m+clk_wiz_0 -L xpm -L xil_defaultlib -L unisims_ver -L unimacro_ver -L secureip -O5 xil_defaultlib.clk_wiz_0 xil_defaultlib.glbl
+
+set NumericStdNoWarnings 1
+set StdArithNoWarnings 1
+
+do {wave.do}
+
+view wave
+view structure
+
+do {clk_wiz_0.udo}
+
+run 1000ns
+
+endsim
+
+quit -force
diff --git a/game.ip_user_files/sim_scripts/clk_wiz_0/riviera/wave.do b/game.ip_user_files/sim_scripts/clk_wiz_0/riviera/wave.do
new file mode 100644
index 0000000000000000000000000000000000000000..70157b0cf36569bda8275f1a9640c41911f8d5f7
--- /dev/null
+++ b/game.ip_user_files/sim_scripts/clk_wiz_0/riviera/wave.do
@@ -0,0 +1,2 @@
+add wave *
+add wave /glbl/GSR
diff --git a/game.ip_user_files/sim_scripts/clk_wiz_0/vcs/README.txt b/game.ip_user_files/sim_scripts/clk_wiz_0/vcs/README.txt
new file mode 100644
index 0000000000000000000000000000000000000000..193e9e2b2252650fd85b3c628bc718694820608b
--- /dev/null
+++ b/game.ip_user_files/sim_scripts/clk_wiz_0/vcs/README.txt
@@ -0,0 +1,49 @@
+################################################################################
+# Vivado (TM) v2022.2 (64-bit)
+#
+# README.txt: Please read the sections below to understand the steps required to
+# run the exported script and information about the source files.
+#
+# Generated by export_simulation on Mon Feb 27 10:47:03 CET 2023
+#
+################################################################################
+
+1. How to run the generated simulation script:-
+
+From the shell prompt in the current directory, issue the following command:-
+
+./clk_wiz_0.sh
+
+This command will launch the 'compile', 'elaborate' and 'simulate' functions
+implemented in the script file for the 3-step flow. These functions are called
+from the main 'run' function in the script file.
+
+The 'run' function first executes the 'setup' function, the purpose of which is to
+create simulator specific setup files, create design library mappings and library
+directories and copy 'glbl.v' from the Vivado software install location into the
+current directory.
+
+The 'setup' function is also used for removing the simulator generated data in
+order to reset the current directory to the original state when export_simulation
+was launched from Vivado. This generated data can be removed by specifying the
+'-reset_run' switch to the './clk_wiz_0.sh' script.
+
+./clk_wiz_0.sh -reset_run
+
+To keep the generated data from the previous run but regenerate the setup files and
+library directories, use the '-noclean_files' switch.
+
+./clk_wiz_0.sh -noclean_files
+
+For more information on the script, please type './clk_wiz_0.sh -help'.
+
+2. Additional design information files:-
+
+export_simulation generates following additional file that can be used for fetching
+the design files information or for integrating with external custom scripts.
+
+Name : file_info.txt
+Purpose: This file contains detail design file information based on the compile order
+ when export_simulation was executed from Vivado. The file contains information
+ about the file type, name, whether it is part of the IP, associated library
+ and the file path information.
diff --git a/game.ip_user_files/sim_scripts/clk_wiz_0/vcs/clk_wiz_0.sh b/game.ip_user_files/sim_scripts/clk_wiz_0/vcs/clk_wiz_0.sh
new file mode 100755
index 0000000000000000000000000000000000000000..7f76b9a2dfdd40824ed70206d3f97cf521dcef52
--- /dev/null
+++ b/game.ip_user_files/sim_scripts/clk_wiz_0/vcs/clk_wiz_0.sh
@@ -0,0 +1,234 @@
+#!/bin/bash -f
+#*********************************************************************************************************
+# Vivado (TM) v2022.2 (64-bit)
+#
+# Filename : clk_wiz_0.sh
+# Simulator : Synopsys Verilog Compiler Simulator
+# Description : Simulation script for compiling, elaborating and verifying the project source files.
+# The script will automatically create the design libraries sub-directories in the run
+# directory, add the library logical mappings in the simulator setup file, create default
+# 'do/prj' file, execute compilation, elaboration and simulation steps.
+#
+# Generated by Vivado on Mon Feb 27 10:47:03 CET 2023
+# SW Build 3671981 on Fri Oct 14 04:59:54 MDT 2022
+#
+# Tool Version Limit: 2022.10
+#
+# usage: clk_wiz_0.sh [-help]
+# usage: clk_wiz_0.sh [-lib_map_path]
+# usage: clk_wiz_0.sh [-noclean_files]
+# usage: clk_wiz_0.sh [-reset_run]
+#
+# Prerequisite:- To compile and run simulation, you must compile the Xilinx simulation libraries using the
+# 'compile_simlib' TCL command. For more information about this command, run 'compile_simlib -help' in the
+# Vivado Tcl Shell. Once the libraries have been compiled successfully, specify the -lib_map_path switch
+# that points to these libraries and rerun export_simulation. For more information about this switch please
+# type 'export_simulation -help' in the Tcl shell.
+#
+# You can also point to the simulation libraries by either replacing the <SPECIFY_COMPILED_LIB_PATH> in this
+# script with the compiled library directory path or specify this path with the '-lib_map_path' switch when
+# executing this script. Please type 'clk_wiz_0.sh -help' for more information.
+#
+# Additional references - 'Xilinx Vivado Design Suite User Guide:Logic simulation (UG900)'
+#
+#*********************************************************************************************************
+
+# Directory path for design sources and include directories (if any) wrt this path
+ref_dir="."
+
+# Override directory with 'export_sim_ref_dir' env path value if set in the shell
+if [[ (! -z "$export_sim_ref_dir") && ($export_sim_ref_dir != "") ]]; then
+ ref_dir="$export_sim_ref_dir"
+fi
+
+# Set vlogan compile options
+vlogan_opts="-full64 "
+
+# Set vhdlan compile options
+vhdlan_opts="-full64 "
+
+# Set vcs elaboration options
+vcs_elab_opts="-full64 -debug_acc+pp+dmptf -t ps -licqueue -l elaborate.log "
+
+# Set vcs simulation options
+vcs_sim_opts="-ucli -licqueue -l simulate.log "
+
+# Design libraries
+design_libs=(xpm xil_defaultlib)
+
+# Simulation root library directory
+sim_lib_dir="vcs_lib"
+
+# Script info
+echo -e "clk_wiz_0.sh - Script generated by export_simulation (Vivado v2022.2 (64-bit)-id)\n"
+
+# Main steps
+run()
+{
+ check_args $# $1
+ setup $1 $2
+ compile
+ elaborate
+ simulate
+}
+
+# RUN_STEP: <compile>
+compile()
+{
+ vlogan -work xpm $vlogan_opts -sverilog +incdir+"$ref_dir/../../../../game.gen/sources_1/ip/clk_wiz_0" \
+ "/opt/Xilinx/Vivado/2022.2/data/ip/xpm/xpm_cdc/hdl/xpm_cdc.sv" \
+ 2>&1 | tee -a vlogan.log
+
+ vhdlan -work xpm $vhdlan_opts \
+ "/opt/Xilinx/Vivado/2022.2/data/ip/xpm/xpm_VCOMP.vhd" \
+ 2>&1 | tee -a vhdlan.log
+
+ vhdlan -work xil_defaultlib $vhdlan_opts \
+ "$ref_dir/../../../../game.gen/sources_1/ip/clk_wiz_0/clk_wiz_0_sim_netlist.vhdl" \
+ 2>&1 | tee -a vhdlan.log
+
+
+ vlogan -work xil_defaultlib $vlogan_opts +v2k \
+ glbl.v \
+ 2>&1 | tee -a vlogan.log
+}
+
+# RUN_STEP: <elaborate>
+elaborate()
+{
+ vcs $vcs_elab_opts xil_defaultlib.clk_wiz_0 xil_defaultlib.glbl -o clk_wiz_0_simv
+}
+
+# RUN_STEP: <simulate>
+simulate()
+{
+ ./clk_wiz_0_simv $vcs_sim_opts -do simulate.do
+}
+
+# STEP: setup
+setup()
+{
+ case $1 in
+ "-lib_map_path" )
+ if [[ ($2 == "") ]]; then
+ echo -e "ERROR: Simulation library directory path not specified (type \"./clk_wiz_0.sh -help\" for more information)\n"
+ exit 1
+ fi
+ create_lib_mappings $2
+ ;;
+ "-reset_run" )
+ reset_run
+ echo -e "INFO: Simulation run files deleted.\n"
+ exit 0
+ ;;
+ "-noclean_files" )
+ # do not remove previous data
+ ;;
+ * )
+ create_lib_mappings $2
+ esac
+
+ create_lib_dir
+
+ # Add any setup/initialization commands here:-
+
+ # <user specific commands>
+
+}
+
+# Define design library mappings
+create_lib_mappings()
+{
+ file="synopsys_sim.setup"
+ if [[ -e $file ]]; then
+ if [[ ($1 == "") ]]; then
+ return
+ else
+ rm -rf $file
+ fi
+ fi
+
+ touch $file
+
+ lib_map_path="<SPECIFY_COMPILED_LIB_PATH>"
+ if [[ ($1 != "" && -e $1) ]]; then
+ lib_map_path="$1"
+ else
+ echo -e "ERROR: Compiled simulation library directory path not specified or does not exist (type "./top.sh -help" for more information)\n"
+ fi
+
+ for (( i=0; i<${#design_libs[*]}; i++ )); do
+ lib="${design_libs[i]}"
+ mapping="$lib:$sim_lib_dir/$lib"
+ echo $mapping >> $file
+ done
+
+ if [[ ($lib_map_path != "") ]]; then
+ incl_ref="OTHERS=$lib_map_path/synopsys_sim.setup"
+ echo $incl_ref >> $file
+ fi
+}
+
+# Create design library directory paths
+create_lib_dir()
+{
+ if [[ -e $sim_lib_dir ]]; then
+ rm -rf $sim_lib_dir
+ fi
+
+ for (( i=0; i<${#design_libs[*]}; i++ )); do
+ lib="${design_libs[i]}"
+ lib_dir="$sim_lib_dir/$lib"
+ if [[ ! -e $lib_dir ]]; then
+ mkdir -p $lib_dir
+ fi
+ done
+}
+
+# Delete generated data from the previous run
+reset_run()
+{
+ files_to_remove=(ucli.key clk_wiz_0_simv vlogan.log vhdlan.log compile.log elaborate.log simulate.log .vlogansetup.env .vlogansetup.args .vcs_lib_lock scirocco_command.log 64 AN.DB csrc clk_wiz_0_simv.daidir)
+ for (( i=0; i<${#files_to_remove[*]}; i++ )); do
+ file="${files_to_remove[i]}"
+ if [[ -e $file ]]; then
+ rm -rf $file
+ fi
+ done
+
+ create_lib_dir
+}
+
+# Check command line arguments
+check_args()
+{
+ if [[ ($1 == 1 ) && ($2 != "-lib_map_path" && $2 != "-noclean_files" && $2 != "-reset_run" && $2 != "-help" && $2 != "-h") ]]; then
+ echo -e "ERROR: Unknown option specified '$2' (type \"./clk_wiz_0.sh -help\" for more information)\n"
+ exit 1
+ fi
+
+ if [[ ($2 == "-help" || $2 == "-h") ]]; then
+ usage
+ fi
+}
+
+# Script usage
+usage()
+{
+ msg="Usage: clk_wiz_0.sh [-help]\n\
+Usage: clk_wiz_0.sh [-lib_map_path]\n\
+Usage: clk_wiz_0.sh [-reset_run]\n\
+Usage: clk_wiz_0.sh [-noclean_files]\n\n\
+[-help] -- Print help information for this script\n\n\
+[-lib_map_path <path>] -- Compiled simulation library directory path. The simulation library is compiled\n\
+using the compile_simlib tcl command. Please see 'compile_simlib -help' for more information.\n\n\
+[-reset_run] -- Recreate simulator setup files and library mappings for a clean run. The generated files\n\
+from the previous run will be removed. If you don't want to remove the simulator generated files, use the\n\
+-noclean_files switch.\n\n\
+[-noclean_files] -- Reset previous run, but do not remove simulator generated files from the previous run.\n\n"
+ echo -e $msg
+ exit 1
+}
+
+# Launch script
+run $1 $2
diff --git a/game.ip_user_files/sim_scripts/clk_wiz_0/vcs/file_info.txt b/game.ip_user_files/sim_scripts/clk_wiz_0/vcs/file_info.txt
new file mode 100644
index 0000000000000000000000000000000000000000..275a6e12cd472264cee1afb10355af4b66b5d48f
--- /dev/null
+++ b/game.ip_user_files/sim_scripts/clk_wiz_0/vcs/file_info.txt
@@ -0,0 +1,4 @@
+xpm_cdc.sv,systemverilog,xpm,../../../opt/Xilinx/Vivado/2022.2/data/ip/xpm/xpm_cdc/hdl/xpm_cdc.sv,incdir="../../../../game.gen/sources_1/ip/clk_wiz_0"
+xpm_VCOMP.vhd,vhdl,xpm,../../../opt/Xilinx/Vivado/2022.2/data/ip/xpm/xpm_VCOMP.vhd,incdir="../../../../game.gen/sources_1/ip/clk_wiz_0"
+clk_wiz_0_sim_netlist.vhdl,vhdl,xil_defaultlib,../../../../game.gen/sources_1/ip/clk_wiz_0/clk_wiz_0_sim_netlist.vhdl,incdir="../../../../game.gen/sources_1/ip/clk_wiz_0"
+glbl.v,Verilog,xil_defaultlib,glbl.v
diff --git a/game.ip_user_files/sim_scripts/clk_wiz_0/vcs/glbl.v b/game.ip_user_files/sim_scripts/clk_wiz_0/vcs/glbl.v
new file mode 100644
index 0000000000000000000000000000000000000000..ed3b249ceef65a0d1b42790def9ee8179363679c
--- /dev/null
+++ b/game.ip_user_files/sim_scripts/clk_wiz_0/vcs/glbl.v
@@ -0,0 +1,84 @@
+// $Header: /devl/xcs/repo/env/Databases/CAEInterfaces/verunilibs/data/glbl.v,v 1.14 2010/10/28 20:44:00 fphillip Exp $
+`ifndef GLBL
+`define GLBL
+`timescale 1 ps / 1 ps
+
+module glbl ();
+
+ parameter ROC_WIDTH = 100000;
+ parameter TOC_WIDTH = 0;
+ parameter GRES_WIDTH = 10000;
+ parameter GRES_START = 10000;
+
+//-------- STARTUP Globals --------------
+ wire GSR;
+ wire GTS;
+ wire GWE;
+ wire PRLD;
+ wire GRESTORE;
+ tri1 p_up_tmp;
+ tri (weak1, strong0) PLL_LOCKG = p_up_tmp;
+
+ wire PROGB_GLBL;
+ wire CCLKO_GLBL;
+ wire FCSBO_GLBL;
+ wire [3:0] DO_GLBL;
+ wire [3:0] DI_GLBL;
+
+ reg GSR_int;
+ reg GTS_int;
+ reg PRLD_int;
+ reg GRESTORE_int;
+
+//-------- JTAG Globals --------------
+ wire JTAG_TDO_GLBL;
+ wire JTAG_TCK_GLBL;
+ wire JTAG_TDI_GLBL;
+ wire JTAG_TMS_GLBL;
+ wire JTAG_TRST_GLBL;
+
+ reg JTAG_CAPTURE_GLBL;
+ reg JTAG_RESET_GLBL;
+ reg JTAG_SHIFT_GLBL;
+ reg JTAG_UPDATE_GLBL;
+ reg JTAG_RUNTEST_GLBL;
+
+ reg JTAG_SEL1_GLBL = 0;
+ reg JTAG_SEL2_GLBL = 0 ;
+ reg JTAG_SEL3_GLBL = 0;
+ reg JTAG_SEL4_GLBL = 0;
+
+ reg JTAG_USER_TDO1_GLBL = 1'bz;
+ reg JTAG_USER_TDO2_GLBL = 1'bz;
+ reg JTAG_USER_TDO3_GLBL = 1'bz;
+ reg JTAG_USER_TDO4_GLBL = 1'bz;
+
+ assign (strong1, weak0) GSR = GSR_int;
+ assign (strong1, weak0) GTS = GTS_int;
+ assign (weak1, weak0) PRLD = PRLD_int;
+ assign (strong1, weak0) GRESTORE = GRESTORE_int;
+
+ initial begin
+ GSR_int = 1'b1;
+ PRLD_int = 1'b1;
+ #(ROC_WIDTH)
+ GSR_int = 1'b0;
+ PRLD_int = 1'b0;
+ end
+
+ initial begin
+ GTS_int = 1'b1;
+ #(TOC_WIDTH)
+ GTS_int = 1'b0;
+ end
+
+ initial begin
+ GRESTORE_int = 1'b0;
+ #(GRES_START);
+ GRESTORE_int = 1'b1;
+ #(GRES_WIDTH);
+ GRESTORE_int = 1'b0;
+ end
+
+endmodule
+`endif
diff --git a/game.ip_user_files/sim_scripts/clk_wiz_0/vcs/simulate.do b/game.ip_user_files/sim_scripts/clk_wiz_0/vcs/simulate.do
new file mode 100644
index 0000000000000000000000000000000000000000..b77c6f13cc6afd61d4290ba7e26ed1b021638b31
--- /dev/null
+++ b/game.ip_user_files/sim_scripts/clk_wiz_0/vcs/simulate.do
@@ -0,0 +1,2 @@
+run 1000ns
+quit
diff --git a/game.ip_user_files/sim_scripts/clk_wiz_0/xcelium/README.txt b/game.ip_user_files/sim_scripts/clk_wiz_0/xcelium/README.txt
new file mode 100644
index 0000000000000000000000000000000000000000..0a8c1671f7323c30112c930a7cb5f6bc7f0c5677
--- /dev/null
+++ b/game.ip_user_files/sim_scripts/clk_wiz_0/xcelium/README.txt
@@ -0,0 +1,48 @@
+################################################################################
+# Vivado (TM) v2022.2 (64-bit)
+#
+# README.txt: Please read the sections below to understand the steps required to
+# run the exported script and information about the source files.
+#
+# Generated by export_simulation on Mon Feb 27 10:47:03 CET 2023
+#
+################################################################################
+
+1. How to run the generated simulation script:-
+
+From the shell prompt in the current directory, issue the following command:-
+
+./clk_wiz_0.sh
+
+This command will launch the 'execute' function for the single-step flow. This
+function is called from the main 'run' function in the script file.
+
+The 'run' function first executes the 'setup' function, the purpose of which is to
+create simulator specific setup files, create design library mappings and library
+directories and copy 'glbl.v' from the Vivado software install location into the
+current directory.
+
+The 'setup' function is also used for removing the simulator generated data in
+order to reset the current directory to the original state when export_simulation
+was launched from Vivado. This generated data can be removed by specifying the
+'-reset_run' switch to the './clk_wiz_0.sh' script.
+
+./clk_wiz_0.sh -reset_run
+
+To keep the generated data from the previous run but regenerate the setup files and
+library directories, use the '-noclean_files' switch.
+
+./clk_wiz_0.sh -noclean_files
+
+For more information on the script, please type './clk_wiz_0.sh -help'.
+
+2. Additional design information files:-
+
+export_simulation generates following additional file that can be used for fetching
+the design files information or for integrating with external custom scripts.
+
+Name : file_info.txt
+Purpose: This file contains detail design file information based on the compile order
+ when export_simulation was executed from Vivado. The file contains information
+ about the file type, name, whether it is part of the IP, associated library
+ and the file path information.
diff --git a/game.ip_user_files/sim_scripts/clk_wiz_0/xcelium/clk_wiz_0.sh b/game.ip_user_files/sim_scripts/clk_wiz_0/xcelium/clk_wiz_0.sh
new file mode 100755
index 0000000000000000000000000000000000000000..b91f01299a2280e1460ebd7a596667f7438b49a4
--- /dev/null
+++ b/game.ip_user_files/sim_scripts/clk_wiz_0/xcelium/clk_wiz_0.sh
@@ -0,0 +1,176 @@
+#!/bin/bash -f
+#*********************************************************************************************************
+# Vivado (TM) v2022.2 (64-bit)
+#
+# Filename : clk_wiz_0.sh
+# Simulator : Cadence Xcelium Parallel Simulator
+# Description : Simulation script for compiling, elaborating and verifying the project source files.
+# The script will automatically create the design libraries sub-directories in the run
+# directory, add the library logical mappings in the simulator setup file, create default
+# 'do/prj' file, execute compilation, elaboration and simulation steps.
+#
+# Generated by Vivado on Mon Feb 27 10:47:03 CET 2023
+# SW Build 3671981 on Fri Oct 14 04:59:54 MDT 2022
+#
+# Tool Version Limit: 2022.10
+#
+# usage: clk_wiz_0.sh [-help]
+# usage: clk_wiz_0.sh [-lib_map_path]
+# usage: clk_wiz_0.sh [-noclean_files]
+# usage: clk_wiz_0.sh [-reset_run]
+#
+# Prerequisite:- To compile and run simulation, you must compile the Xilinx simulation libraries using the
+# 'compile_simlib' TCL command. For more information about this command, run 'compile_simlib -help' in the
+# Vivado Tcl Shell. Once the libraries have been compiled successfully, specify the -lib_map_path switch
+# that points to these libraries and rerun export_simulation. For more information about this switch please
+# type 'export_simulation -help' in the Tcl shell.
+#
+# You can also point to the simulation libraries by either replacing the <SPECIFY_COMPILED_LIB_PATH> in this
+# script with the compiled library directory path or specify this path with the '-lib_map_path' switch when
+# executing this script. Please type 'clk_wiz_0.sh -help' for more information.
+#
+# Additional references - 'Xilinx Vivado Design Suite User Guide:Logic simulation (UG900)'
+#
+#*********************************************************************************************************
+
+# Directory path for design sources and include directories (if any) wrt this path
+ref_dir="."
+
+# Override directory with 'export_sim_ref_dir' env path value if set in the shell
+if [[ (! -z "$export_sim_ref_dir") && ($export_sim_ref_dir != "") ]]; then
+ ref_dir="$export_sim_ref_dir"
+fi
+
+# Set the compiled library directory path
+ref_lib_dir="."
+
+# Set xrun options
+xrun_opts="-64bit -v93 -relax -access +rwc -namemap_mixgen "
+
+# Design libraries
+design_libs=(simprims_ver xpm xil_defaultlib)
+
+# Simulation root library directory
+sim_lib_dir="xcelium_lib"
+
+# Script info
+echo -e "clk_wiz_0.sh - Script generated by export_simulation (Vivado v2022.2 (64-bit)-id)\n"
+
+# Main steps
+run()
+{
+ check_args $# $1
+ setup $1 $2
+ execute
+}
+
+# RUN_STEP: <execute>
+execute()
+{
+ xrun $xrun_opts \
+ -reflib "$ref_lib_dir/unisim:unisim" \
+ -reflib "$ref_lib_dir/unisims_ver:unisims_ver" \
+ -reflib "$ref_lib_dir/secureip:secureip" \
+ -reflib "$ref_lib_dir/unimacro:unimacro" \
+ -reflib "$ref_lib_dir/unimacro_ver:unimacro_ver" \
+ -top xil_defaultlib.clk_wiz_0 \
+ -f run.f \
+ -top glbl \
+ +incdir+"../../../../game.gen/sources_1/ip/clk_wiz_0" \
+ -input simulate.do
+}
+
+# STEP: setup
+setup()
+{
+ case $1 in
+ "-lib_map_path" )
+ if [[ ($2 == "") ]]; then
+ echo -e "ERROR: Simulation library directory path not specified (type \"./clk_wiz_0.sh -help\" for more information)\n"
+ exit 1
+ else
+ ref_lib_dir=$2
+ fi
+ ;;
+ "-reset_run" )
+ reset_run
+ echo -e "INFO: Simulation run files deleted.\n"
+ exit 0
+ ;;
+ "-noclean_files" )
+ # do not remove previous data
+ ;;
+ * )
+ esac
+
+ create_lib_dir
+
+ # Add any setup/initialization commands here:-
+
+ # <user specific commands>
+
+}
+
+# Create design library directory paths
+create_lib_dir()
+{
+ if [[ -e $sim_lib_dir ]]; then
+ rm -rf $sim_lib_dir
+ fi
+
+ for (( i=0; i<${#design_libs[*]}; i++ )); do
+ lib="${design_libs[i]}"
+ lib_dir="$sim_lib_dir/$lib"
+ if [[ ! -e $lib_dir ]]; then
+ mkdir -p $lib_dir
+ fi
+ done
+}
+
+# Delete generated data from the previous run
+reset_run()
+{
+ files_to_remove=(xmsim.key xrun.key xrun.log waves.shm xrun.history .simvision xcelium.d xcelium)
+ for (( i=0; i<${#files_to_remove[*]}; i++ )); do
+ file="${files_to_remove[i]}"
+ if [[ -e $file ]]; then
+ rm -rf $file
+ fi
+ done
+
+ create_lib_dir
+}
+
+# Check command line arguments
+check_args()
+{
+ if [[ ($1 == 1 ) && ($2 != "-lib_map_path" && $2 != "-noclean_files" && $2 != "-reset_run" && $2 != "-help" && $2 != "-h") ]]; then
+ echo -e "ERROR: Unknown option specified '$2' (type \"./clk_wiz_0.sh -help\" for more information)\n"
+ exit 1
+ fi
+
+ if [[ ($2 == "-help" || $2 == "-h") ]]; then
+ usage
+ fi
+}
+
+# Script usage
+usage()
+{
+ msg="Usage: clk_wiz_0.sh [-help]\n\
+Usage: clk_wiz_0.sh [-lib_map_path]\n\
+Usage: clk_wiz_0.sh [-reset_run]\n\
+Usage: clk_wiz_0.sh [-noclean_files]\n\n\
+[-help] -- Print help information for this script\n\n\
+[-lib_map_path <path>] -- Compiled simulation library directory path. The simulation library is compiled\n\
+using the compile_simlib tcl command. Please see 'compile_simlib -help' for more information.\n\n\
+[-reset_run] -- Recreate simulator setup files and library mappings for a clean run. The generated files\n\
+from the previous run will be removed. If you don't want to remove the simulator generated files, use the\n\
+-noclean_files switch.\n\n\
+[-noclean_files] -- Reset previous run, but do not remove simulator generated files from the previous run.\n\n"
+ echo -e $msg
+ exit 1
+}
+
+# Launch script
+run $1 $2
diff --git a/game.ip_user_files/sim_scripts/clk_wiz_0/xcelium/file_info.txt b/game.ip_user_files/sim_scripts/clk_wiz_0/xcelium/file_info.txt
new file mode 100644
index 0000000000000000000000000000000000000000..275a6e12cd472264cee1afb10355af4b66b5d48f
--- /dev/null
+++ b/game.ip_user_files/sim_scripts/clk_wiz_0/xcelium/file_info.txt
@@ -0,0 +1,4 @@
+xpm_cdc.sv,systemverilog,xpm,../../../opt/Xilinx/Vivado/2022.2/data/ip/xpm/xpm_cdc/hdl/xpm_cdc.sv,incdir="../../../../game.gen/sources_1/ip/clk_wiz_0"
+xpm_VCOMP.vhd,vhdl,xpm,../../../opt/Xilinx/Vivado/2022.2/data/ip/xpm/xpm_VCOMP.vhd,incdir="../../../../game.gen/sources_1/ip/clk_wiz_0"
+clk_wiz_0_sim_netlist.vhdl,vhdl,xil_defaultlib,../../../../game.gen/sources_1/ip/clk_wiz_0/clk_wiz_0_sim_netlist.vhdl,incdir="../../../../game.gen/sources_1/ip/clk_wiz_0"
+glbl.v,Verilog,xil_defaultlib,glbl.v
diff --git a/game.ip_user_files/sim_scripts/clk_wiz_0/xcelium/glbl.v b/game.ip_user_files/sim_scripts/clk_wiz_0/xcelium/glbl.v
new file mode 100644
index 0000000000000000000000000000000000000000..ed3b249ceef65a0d1b42790def9ee8179363679c
--- /dev/null
+++ b/game.ip_user_files/sim_scripts/clk_wiz_0/xcelium/glbl.v
@@ -0,0 +1,84 @@
+// $Header: /devl/xcs/repo/env/Databases/CAEInterfaces/verunilibs/data/glbl.v,v 1.14 2010/10/28 20:44:00 fphillip Exp $
+`ifndef GLBL
+`define GLBL
+`timescale 1 ps / 1 ps
+
+module glbl ();
+
+ parameter ROC_WIDTH = 100000;
+ parameter TOC_WIDTH = 0;
+ parameter GRES_WIDTH = 10000;
+ parameter GRES_START = 10000;
+
+//-------- STARTUP Globals --------------
+ wire GSR;
+ wire GTS;
+ wire GWE;
+ wire PRLD;
+ wire GRESTORE;
+ tri1 p_up_tmp;
+ tri (weak1, strong0) PLL_LOCKG = p_up_tmp;
+
+ wire PROGB_GLBL;
+ wire CCLKO_GLBL;
+ wire FCSBO_GLBL;
+ wire [3:0] DO_GLBL;
+ wire [3:0] DI_GLBL;
+
+ reg GSR_int;
+ reg GTS_int;
+ reg PRLD_int;
+ reg GRESTORE_int;
+
+//-------- JTAG Globals --------------
+ wire JTAG_TDO_GLBL;
+ wire JTAG_TCK_GLBL;
+ wire JTAG_TDI_GLBL;
+ wire JTAG_TMS_GLBL;
+ wire JTAG_TRST_GLBL;
+
+ reg JTAG_CAPTURE_GLBL;
+ reg JTAG_RESET_GLBL;
+ reg JTAG_SHIFT_GLBL;
+ reg JTAG_UPDATE_GLBL;
+ reg JTAG_RUNTEST_GLBL;
+
+ reg JTAG_SEL1_GLBL = 0;
+ reg JTAG_SEL2_GLBL = 0 ;
+ reg JTAG_SEL3_GLBL = 0;
+ reg JTAG_SEL4_GLBL = 0;
+
+ reg JTAG_USER_TDO1_GLBL = 1'bz;
+ reg JTAG_USER_TDO2_GLBL = 1'bz;
+ reg JTAG_USER_TDO3_GLBL = 1'bz;
+ reg JTAG_USER_TDO4_GLBL = 1'bz;
+
+ assign (strong1, weak0) GSR = GSR_int;
+ assign (strong1, weak0) GTS = GTS_int;
+ assign (weak1, weak0) PRLD = PRLD_int;
+ assign (strong1, weak0) GRESTORE = GRESTORE_int;
+
+ initial begin
+ GSR_int = 1'b1;
+ PRLD_int = 1'b1;
+ #(ROC_WIDTH)
+ GSR_int = 1'b0;
+ PRLD_int = 1'b0;
+ end
+
+ initial begin
+ GTS_int = 1'b1;
+ #(TOC_WIDTH)
+ GTS_int = 1'b0;
+ end
+
+ initial begin
+ GRESTORE_int = 1'b0;
+ #(GRES_START);
+ GRESTORE_int = 1'b1;
+ #(GRES_WIDTH);
+ GRESTORE_int = 1'b0;
+ end
+
+endmodule
+`endif
diff --git a/game.ip_user_files/sim_scripts/clk_wiz_0/xcelium/run.f b/game.ip_user_files/sim_scripts/clk_wiz_0/xcelium/run.f
new file mode 100644
index 0000000000000000000000000000000000000000..f953cff60c2928490762a890a07f1feebb28eb7a
--- /dev/null
+++ b/game.ip_user_files/sim_scripts/clk_wiz_0/xcelium/run.f
@@ -0,0 +1,13 @@
+-makelib xcelium_lib/xpm -sv \
+ "/opt/Xilinx/Vivado/2022.2/data/ip/xpm/xpm_cdc/hdl/xpm_cdc.sv" \
+-endlib
+-makelib xcelium_lib/xpm \
+ "/opt/Xilinx/Vivado/2022.2/data/ip/xpm/xpm_VCOMP.vhd" \
+-endlib
+-makelib xcelium_lib/xil_defaultlib \
+ "../../../../game.gen/sources_1/ip/clk_wiz_0/clk_wiz_0_sim_netlist.vhdl" \
+-endlib
+-makelib xcelium_lib/xil_defaultlib \
+ glbl.v
+-endlib
+
diff --git a/game.ip_user_files/sim_scripts/clk_wiz_0/xcelium/simulate.do b/game.ip_user_files/sim_scripts/clk_wiz_0/xcelium/simulate.do
new file mode 100644
index 0000000000000000000000000000000000000000..fb6d1f776970ca90fb0a9d24505e9f1691a90d27
--- /dev/null
+++ b/game.ip_user_files/sim_scripts/clk_wiz_0/xcelium/simulate.do
@@ -0,0 +1,2 @@
+run 1000ns
+exit
diff --git a/game.ip_user_files/sim_scripts/clk_wiz_0/xsim/README.txt b/game.ip_user_files/sim_scripts/clk_wiz_0/xsim/README.txt
new file mode 100644
index 0000000000000000000000000000000000000000..193e9e2b2252650fd85b3c628bc718694820608b
--- /dev/null
+++ b/game.ip_user_files/sim_scripts/clk_wiz_0/xsim/README.txt
@@ -0,0 +1,49 @@
+################################################################################
+# Vivado (TM) v2022.2 (64-bit)
+#
+# README.txt: Please read the sections below to understand the steps required to
+# run the exported script and information about the source files.
+#
+# Generated by export_simulation on Mon Feb 27 10:47:03 CET 2023
+#
+################################################################################
+
+1. How to run the generated simulation script:-
+
+From the shell prompt in the current directory, issue the following command:-
+
+./clk_wiz_0.sh
+
+This command will launch the 'compile', 'elaborate' and 'simulate' functions
+implemented in the script file for the 3-step flow. These functions are called
+from the main 'run' function in the script file.
+
+The 'run' function first executes the 'setup' function, the purpose of which is to
+create simulator specific setup files, create design library mappings and library
+directories and copy 'glbl.v' from the Vivado software install location into the
+current directory.
+
+The 'setup' function is also used for removing the simulator generated data in
+order to reset the current directory to the original state when export_simulation
+was launched from Vivado. This generated data can be removed by specifying the
+'-reset_run' switch to the './clk_wiz_0.sh' script.
+
+./clk_wiz_0.sh -reset_run
+
+To keep the generated data from the previous run but regenerate the setup files and
+library directories, use the '-noclean_files' switch.
+
+./clk_wiz_0.sh -noclean_files
+
+For more information on the script, please type './clk_wiz_0.sh -help'.
+
+2. Additional design information files:-
+
+export_simulation generates following additional file that can be used for fetching
+the design files information or for integrating with external custom scripts.
+
+Name : file_info.txt
+Purpose: This file contains detail design file information based on the compile order
+ when export_simulation was executed from Vivado. The file contains information
+ about the file type, name, whether it is part of the IP, associated library
+ and the file path information.
diff --git a/game.ip_user_files/sim_scripts/clk_wiz_0/xsim/clk_wiz_0.sh b/game.ip_user_files/sim_scripts/clk_wiz_0/xsim/clk_wiz_0.sh
new file mode 100755
index 0000000000000000000000000000000000000000..659543d98d0ac61d2a116aceb0043ce18dd6dd65
--- /dev/null
+++ b/game.ip_user_files/sim_scripts/clk_wiz_0/xsim/clk_wiz_0.sh
@@ -0,0 +1,219 @@
+#!/bin/bash -f
+#*********************************************************************************************************
+# Vivado (TM) v2022.2 (64-bit)
+#
+# Filename : clk_wiz_0.sh
+# Simulator : Xilinx Vivado Simulator
+# Description : Simulation script for compiling, elaborating and verifying the project source files.
+# The script will automatically create the design libraries sub-directories in the run
+# directory, add the library logical mappings in the simulator setup file, create default
+# 'do/prj' file, execute compilation, elaboration and simulation steps.
+#
+# Generated by Vivado on Mon Feb 27 10:47:03 CET 2023
+# SW Build 3671981 on Fri Oct 14 04:59:54 MDT 2022
+#
+# Tool Version Limit: 2022.10
+#
+# usage: clk_wiz_0.sh [-help]
+# usage: clk_wiz_0.sh [-lib_map_path]
+# usage: clk_wiz_0.sh [-noclean_files]
+# usage: clk_wiz_0.sh [-reset_run]
+#
+#*********************************************************************************************************
+
+# Set xvlog options
+xvlog_opts="--incr --relax "
+
+# Set xvlog options
+xvhdl_opts="--incr --relax "
+
+# Script info
+echo -e "clk_wiz_0.sh - Script generated by export_simulation (Vivado v2022.2 (64-bit)-id)\n"
+
+# Main steps
+run()
+{
+ check_args $# $1
+ setup $1 $2
+ compile
+ elaborate
+ simulate
+}
+
+# RUN_STEP: <compile>
+compile()
+{
+ xvlog $xvlog_opts -prj vlog.prj 2>&1 | tee compile.log
+ xvhdl $xvhdl_opts -prj vhdl.prj 2>&1 | tee compile.log
+}
+
+# RUN_STEP: <elaborate>
+elaborate()
+{
+ xelab --incr --debug typical --relax --mt auto -L xil_defaultlib -L unisims_ver -L unimacro_ver -L secureip -L xpm --snapshot clk_wiz_0 xil_defaultlib.clk_wiz_0 xil_defaultlib.glbl -log elaborate.log
+}
+
+# RUN_STEP: <simulate>
+simulate()
+{
+ xsim clk_wiz_0 -key {Behavioral:sim_1:Functional:clk_wiz_0} -tclbatch cmd.tcl -log simulate.log
+}
+
+# STEP: setup
+setup()
+{
+ case $1 in
+ "-lib_map_path" )
+ if [[ ($2 == "") ]]; then
+ echo -e "ERROR: Simulation library directory path not specified (type \"./clk_wiz_0.sh -help\" for more information)\n"
+ exit 1
+ fi
+ copy_setup_file $2
+ ;;
+ "-reset_run" )
+ reset_run
+ echo -e "INFO: Simulation run files deleted.\n"
+ exit 0
+ ;;
+ "-noclean_files" )
+ # do not remove previous data
+ ;;
+ * )
+ copy_setup_file $2
+ esac
+
+ # Add any setup/initialization commands here:-
+
+ # <user specific commands>
+
+}
+
+# Copy xsim.ini file
+copy_setup_file()
+{
+ file="xsim.ini"
+ lib_map_path="/opt/Xilinx/Vivado/2022.2/data/xsim"
+ if [[ ($1 != "") ]]; then
+ lib_map_path="$1"
+ fi
+ if [[ ($lib_map_path != "") ]]; then
+ src_file="$lib_map_path/$file"
+ if [[ -e $src_file ]]; then
+ cp $src_file .
+ fi
+
+ # Map local design libraries to xsim.ini
+ map_local_libs
+
+ fi
+}
+
+# Map local design libraries
+map_local_libs()
+{
+ updated_mappings=()
+ local_mappings=()
+
+ # Local design libraries
+ local_libs=()
+
+ if [[ 0 == ${#local_libs[@]} ]]; then
+ return
+ fi
+
+ file="xsim.ini"
+ file_backup="xsim.ini.bak"
+
+ if [[ -e $file ]]; then
+ rm -f $file_backup
+
+ # Create a backup copy of the xsim.ini file
+ cp $file $file_backup
+
+ # Read libraries from backup file and search in local library collection
+ while read -r line
+ do
+ IN=$line
+
+ # Split mapping entry with '=' delimiter to fetch library name and mapping
+ read lib_name mapping <<<$(IFS="="; echo $IN)
+
+ # If local library found, then construct the local mapping and add to local mapping collection
+ if `echo ${local_libs[@]} | grep -wq $lib_name` ; then
+ line="$lib_name=xsim.dir/$lib_name"
+ local_mappings+=("$lib_name")
+ fi
+
+ # Add to updated library mapping collection
+ updated_mappings+=("$line")
+ done < "$file_backup"
+
+ # Append local libraries not found originally from xsim.ini
+ for (( i=0; i<${#local_libs[*]}; i++ )); do
+ lib_name="${local_libs[i]}"
+ if `echo ${local_mappings[@]} | grep -wvq $lib_name` ; then
+ line="$lib_name=xsim.dir/$lib_name"
+ updated_mappings+=("$line")
+ fi
+ done
+
+ # Write updated mappings in xsim.ini
+ rm -f $file
+ for (( i=0; i<${#updated_mappings[*]}; i++ )); do
+ lib_name="${updated_mappings[i]}"
+ echo $lib_name >> $file
+ done
+ else
+ for (( i=0; i<${#local_libs[*]}; i++ )); do
+ lib_name="${local_libs[i]}"
+ mapping="$lib_name=xsim.dir/$lib_name"
+ echo $mapping >> $file
+ done
+ fi
+}
+
+# Delete generated data from the previous run
+reset_run()
+{
+ files_to_remove=(xelab.pb xsim.jou xvhdl.log xvlog.log compile.log elaborate.log simulate.log xelab.log xsim.log run.log xvhdl.pb xvlog.pb clk_wiz_0.wdb xsim.dir)
+ for (( i=0; i<${#files_to_remove[*]}; i++ )); do
+ file="${files_to_remove[i]}"
+ if [[ -e $file ]]; then
+ rm -rf $file
+ fi
+ done
+}
+
+# Check command line arguments
+check_args()
+{
+ if [[ ($1 == 1 ) && ($2 != "-lib_map_path" && $2 != "-noclean_files" && $2 != "-reset_run" && $2 != "-help" && $2 != "-h") ]]; then
+ echo -e "ERROR: Unknown option specified '$2' (type \"./clk_wiz_0.sh -help\" for more information)\n"
+ exit 1
+ fi
+
+ if [[ ($2 == "-help" || $2 == "-h") ]]; then
+ usage
+ fi
+}
+
+# Script usage
+usage()
+{
+ msg="Usage: clk_wiz_0.sh [-help]\n\
+Usage: clk_wiz_0.sh [-lib_map_path]\n\
+Usage: clk_wiz_0.sh [-reset_run]\n\
+Usage: clk_wiz_0.sh [-noclean_files]\n\n\
+[-help] -- Print help information for this script\n\n\
+[-lib_map_path <path>] -- Compiled simulation library directory path. The simulation library is compiled\n\
+using the compile_simlib tcl command. Please see 'compile_simlib -help' for more information.\n\n\
+[-reset_run] -- Recreate simulator setup files and library mappings for a clean run. The generated files\n\
+from the previous run will be removed. If you don't want to remove the simulator generated files, use the\n\
+-noclean_files switch.\n\n\
+[-noclean_files] -- Reset previous run, but do not remove simulator generated files from the previous run.\n\n"
+ echo -e $msg
+ exit 1
+}
+
+# Launch script
+run $1 $2
diff --git a/game.ip_user_files/sim_scripts/clk_wiz_0/xsim/cmd.tcl b/game.ip_user_files/sim_scripts/clk_wiz_0/xsim/cmd.tcl
new file mode 100644
index 0000000000000000000000000000000000000000..6ac0dc83b46834457d1ece6c095d2b62c68473cb
--- /dev/null
+++ b/game.ip_user_files/sim_scripts/clk_wiz_0/xsim/cmd.tcl
@@ -0,0 +1,12 @@
+set curr_wave [current_wave_config]
+if { [string length $curr_wave] == 0 } {
+ if { [llength [get_objects]] > 0} {
+ add_wave /
+ set_property needs_save false [current_wave_config]
+ } else {
+ send_msg_id Add_Wave-1 WARNING "No top level signals found. Simulator will start without a wave window. If you want to open a wave window go to 'File->New Waveform Configuration' or type 'create_wave_config' in the TCL console."
+ }
+}
+
+run 1000ns
+quit
diff --git a/game.ip_user_files/sim_scripts/clk_wiz_0/xsim/file_info.txt b/game.ip_user_files/sim_scripts/clk_wiz_0/xsim/file_info.txt
new file mode 100644
index 0000000000000000000000000000000000000000..35382c856dd399eb287cef33a7b9d1a0c6596ee5
--- /dev/null
+++ b/game.ip_user_files/sim_scripts/clk_wiz_0/xsim/file_info.txt
@@ -0,0 +1,2 @@
+clk_wiz_0_sim_netlist.vhdl,vhdl,xil_defaultlib,../../../../game.gen/sources_1/ip/clk_wiz_0/clk_wiz_0_sim_netlist.vhdl,incdir="../../../../game.gen/sources_1/ip/clk_wiz_0"
+glbl.v,Verilog,xil_defaultlib,glbl.v
diff --git a/game.ip_user_files/sim_scripts/clk_wiz_0/xsim/glbl.v b/game.ip_user_files/sim_scripts/clk_wiz_0/xsim/glbl.v
new file mode 100644
index 0000000000000000000000000000000000000000..ed3b249ceef65a0d1b42790def9ee8179363679c
--- /dev/null
+++ b/game.ip_user_files/sim_scripts/clk_wiz_0/xsim/glbl.v
@@ -0,0 +1,84 @@
+// $Header: /devl/xcs/repo/env/Databases/CAEInterfaces/verunilibs/data/glbl.v,v 1.14 2010/10/28 20:44:00 fphillip Exp $
+`ifndef GLBL
+`define GLBL
+`timescale 1 ps / 1 ps
+
+module glbl ();
+
+ parameter ROC_WIDTH = 100000;
+ parameter TOC_WIDTH = 0;
+ parameter GRES_WIDTH = 10000;
+ parameter GRES_START = 10000;
+
+//-------- STARTUP Globals --------------
+ wire GSR;
+ wire GTS;
+ wire GWE;
+ wire PRLD;
+ wire GRESTORE;
+ tri1 p_up_tmp;
+ tri (weak1, strong0) PLL_LOCKG = p_up_tmp;
+
+ wire PROGB_GLBL;
+ wire CCLKO_GLBL;
+ wire FCSBO_GLBL;
+ wire [3:0] DO_GLBL;
+ wire [3:0] DI_GLBL;
+
+ reg GSR_int;
+ reg GTS_int;
+ reg PRLD_int;
+ reg GRESTORE_int;
+
+//-------- JTAG Globals --------------
+ wire JTAG_TDO_GLBL;
+ wire JTAG_TCK_GLBL;
+ wire JTAG_TDI_GLBL;
+ wire JTAG_TMS_GLBL;
+ wire JTAG_TRST_GLBL;
+
+ reg JTAG_CAPTURE_GLBL;
+ reg JTAG_RESET_GLBL;
+ reg JTAG_SHIFT_GLBL;
+ reg JTAG_UPDATE_GLBL;
+ reg JTAG_RUNTEST_GLBL;
+
+ reg JTAG_SEL1_GLBL = 0;
+ reg JTAG_SEL2_GLBL = 0 ;
+ reg JTAG_SEL3_GLBL = 0;
+ reg JTAG_SEL4_GLBL = 0;
+
+ reg JTAG_USER_TDO1_GLBL = 1'bz;
+ reg JTAG_USER_TDO2_GLBL = 1'bz;
+ reg JTAG_USER_TDO3_GLBL = 1'bz;
+ reg JTAG_USER_TDO4_GLBL = 1'bz;
+
+ assign (strong1, weak0) GSR = GSR_int;
+ assign (strong1, weak0) GTS = GTS_int;
+ assign (weak1, weak0) PRLD = PRLD_int;
+ assign (strong1, weak0) GRESTORE = GRESTORE_int;
+
+ initial begin
+ GSR_int = 1'b1;
+ PRLD_int = 1'b1;
+ #(ROC_WIDTH)
+ GSR_int = 1'b0;
+ PRLD_int = 1'b0;
+ end
+
+ initial begin
+ GTS_int = 1'b1;
+ #(TOC_WIDTH)
+ GTS_int = 1'b0;
+ end
+
+ initial begin
+ GRESTORE_int = 1'b0;
+ #(GRES_START);
+ GRESTORE_int = 1'b1;
+ #(GRES_WIDTH);
+ GRESTORE_int = 1'b0;
+ end
+
+endmodule
+`endif
diff --git a/game.ip_user_files/sim_scripts/clk_wiz_0/xsim/vhdl.prj b/game.ip_user_files/sim_scripts/clk_wiz_0/xsim/vhdl.prj
new file mode 100644
index 0000000000000000000000000000000000000000..deb08011e2c99d1c2c0f53009c3b756188ca1409
--- /dev/null
+++ b/game.ip_user_files/sim_scripts/clk_wiz_0/xsim/vhdl.prj
@@ -0,0 +1,4 @@
+vhdl xil_defaultlib \
+"../../../../game.gen/sources_1/ip/clk_wiz_0/clk_wiz_0_sim_netlist.vhdl" \
+
+nosort
diff --git a/game.ip_user_files/sim_scripts/clk_wiz_0/xsim/vlog.prj b/game.ip_user_files/sim_scripts/clk_wiz_0/xsim/vlog.prj
new file mode 100644
index 0000000000000000000000000000000000000000..35119d5b2db522be9bd7062493da65564389b07e
--- /dev/null
+++ b/game.ip_user_files/sim_scripts/clk_wiz_0/xsim/vlog.prj
@@ -0,0 +1,4 @@
+
+verilog xil_defaultlib "glbl.v"
+
+nosort
diff --git a/game.ip_user_files/sim_scripts/clk_wiz_1/activehdl/README.txt b/game.ip_user_files/sim_scripts/clk_wiz_1/activehdl/README.txt
new file mode 100644
index 0000000000000000000000000000000000000000..5895c5dd4ec54313cde5d4a854b86a0eb2180232
--- /dev/null
+++ b/game.ip_user_files/sim_scripts/clk_wiz_1/activehdl/README.txt
@@ -0,0 +1,49 @@
+################################################################################
+# Vivado (TM) v2022.2 (64-bit)
+#
+# README.txt: Please read the sections below to understand the steps required to
+# run the exported script and information about the source files.
+#
+# Generated by export_simulation on Mon Feb 27 12:44:43 CET 2023
+#
+################################################################################
+
+1. How to run the generated simulation script:-
+
+From the shell prompt in the current directory, issue the following command:-
+
+./clk_wiz_1.sh
+
+This command will launch the 'compile', 'elaborate' and 'simulate' functions
+implemented in the script file for the 3-step flow. These functions are called
+from the main 'run' function in the script file.
+
+The 'run' function first executes the 'setup' function, the purpose of which is to
+create simulator specific setup files, create design library mappings and library
+directories and copy 'glbl.v' from the Vivado software install location into the
+current directory.
+
+The 'setup' function is also used for removing the simulator generated data in
+order to reset the current directory to the original state when export_simulation
+was launched from Vivado. This generated data can be removed by specifying the
+'-reset_run' switch to the './clk_wiz_1.sh' script.
+
+./clk_wiz_1.sh -reset_run
+
+To keep the generated data from the previous run but regenerate the setup files and
+library directories, use the '-noclean_files' switch.
+
+./clk_wiz_1.sh -noclean_files
+
+For more information on the script, please type './clk_wiz_1.sh -help'.
+
+2. Additional design information files:-
+
+export_simulation generates following additional file that can be used for fetching
+the design files information or for integrating with external custom scripts.
+
+Name : file_info.txt
+Purpose: This file contains detail design file information based on the compile order
+ when export_simulation was executed from Vivado. The file contains information
+ about the file type, name, whether it is part of the IP, associated library
+ and the file path information.
diff --git a/game.ip_user_files/sim_scripts/clk_wiz_1/activehdl/clk_wiz_1.sh b/game.ip_user_files/sim_scripts/clk_wiz_1/activehdl/clk_wiz_1.sh
new file mode 100755
index 0000000000000000000000000000000000000000..4976e1f16352651deabebd97bdb0ac6fc4f53ac8
--- /dev/null
+++ b/game.ip_user_files/sim_scripts/clk_wiz_1/activehdl/clk_wiz_1.sh
@@ -0,0 +1,149 @@
+#!/bin/bash -f
+#*********************************************************************************************************
+# Vivado (TM) v2022.2 (64-bit)
+#
+# Filename : clk_wiz_1.sh
+# Simulator : Aldec Active-HDL Simulator
+# Description : Simulation script for compiling, elaborating and verifying the project source files.
+# The script will automatically create the design libraries sub-directories in the run
+# directory, add the library logical mappings in the simulator setup file, create default
+# 'do/prj' file, execute compilation, elaboration and simulation steps.
+#
+# Generated by Vivado on Mon Feb 27 12:44:43 CET 2023
+# SW Build 3671981 on Fri Oct 14 04:59:54 MDT 2022
+#
+# Tool Version Limit: 2022.10
+#
+# usage: clk_wiz_1.sh [-help]
+# usage: clk_wiz_1.sh [-lib_map_path]
+# usage: clk_wiz_1.sh [-noclean_files]
+# usage: clk_wiz_1.sh [-reset_run]
+#
+# Prerequisite:- To compile and run simulation, you must compile the Xilinx simulation libraries using the
+# 'compile_simlib' TCL command. For more information about this command, run 'compile_simlib -help' in the
+# Vivado Tcl Shell. Once the libraries have been compiled successfully, specify the -lib_map_path switch
+# that points to these libraries and rerun export_simulation. For more information about this switch please
+# type 'export_simulation -help' in the Tcl shell.
+#
+# You can also point to the simulation libraries by either replacing the <SPECIFY_COMPILED_LIB_PATH> in this
+# script with the compiled library directory path or specify this path with the '-lib_map_path' switch when
+# executing this script. Please type 'clk_wiz_1.sh -help' for more information.
+#
+# Additional references - 'Xilinx Vivado Design Suite User Guide:Logic simulation (UG900)'
+#
+#*********************************************************************************************************
+
+# Script info
+echo -e "clk_wiz_1.sh - Script generated by export_simulation (Vivado v2022.2 (64-bit)-id)\n"
+
+# Main steps
+run()
+{
+ check_args $# $1
+ setup $1 $2
+ compile
+ simulate
+}
+
+# RUN_STEP: <compile>
+compile()
+{
+ source compile.do 2>&1 | tee -a compile.log
+}
+
+# RUN_STEP: <simulate>
+simulate()
+{
+ runvsimsa -l simulate.log -do "do {simulate.do}"
+}
+
+# STEP: setup
+setup()
+{
+ case $1 in
+ "-lib_map_path" )
+ if [[ ($2 == "") ]]; then
+ echo -e "ERROR: Simulation library directory path not specified (type \"./clk_wiz_1.sh -help\" for more information)\n"
+ exit 1
+ fi
+ map_setup_file $2
+ ;;
+ "-reset_run" )
+ reset_run
+ echo -e "INFO: Simulation run files deleted.\n"
+ exit 0
+ ;;
+ "-noclean_files" )
+ # do not remove previous data
+ ;;
+ * )
+ map_setup_file $2
+ esac
+
+ # Add any setup/initialization commands here:-
+
+ # <user specific commands>
+
+}
+
+# Map library.cfg file
+map_setup_file()
+{
+ file="library.cfg"
+ lib_map_path=""
+ if [[ ($1 != "") ]]; then
+ lib_map_path="$1"
+ fi
+ if [[ ($lib_map_path != "") ]]; then
+ src_file="$lib_map_path/$file"
+ if [[ -e $src_file ]]; then
+ vmap -link $lib_map_path
+ fi
+ fi
+}
+
+# Delete generated data from the previous run
+reset_run()
+{
+ files_to_remove=(compile.log elaboration.log simulate.log dataset.asdb work activehdl)
+ for (( i=0; i<${#files_to_remove[*]}; i++ )); do
+ file="${files_to_remove[i]}"
+ if [[ -e $file ]]; then
+ rm -rf $file
+ fi
+ done
+}
+
+# Check command line arguments
+check_args()
+{
+ if [[ ($1 == 1 ) && ($2 != "-lib_map_path" && $2 != "-noclean_files" && $2 != "-reset_run" && $2 != "-help" && $2 != "-h") ]]; then
+ echo -e "ERROR: Unknown option specified '$2' (type \"./clk_wiz_1.sh -help\" for more information)\n"
+ exit 1
+ fi
+
+ if [[ ($2 == "-help" || $2 == "-h") ]]; then
+ usage
+ fi
+}
+
+# Script usage
+usage()
+{
+ msg="Usage: clk_wiz_1.sh [-help]\n\
+Usage: clk_wiz_1.sh [-lib_map_path]\n\
+Usage: clk_wiz_1.sh [-reset_run]\n\
+Usage: clk_wiz_1.sh [-noclean_files]\n\n\
+[-help] -- Print help information for this script\n\n\
+[-lib_map_path <path>] -- Compiled simulation library directory path. The simulation library is compiled\n\
+using the compile_simlib tcl command. Please see 'compile_simlib -help' for more information.\n\n\
+[-reset_run] -- Recreate simulator setup files and library mappings for a clean run. The generated files\n\
+from the previous run will be removed. If you don't want to remove the simulator generated files, use the\n\
+-noclean_files switch.\n\n\
+[-noclean_files] -- Reset previous run, but do not remove simulator generated files from the previous run.\n\n"
+ echo -e $msg
+ exit 1
+}
+
+# Launch script
+run $1 $2
diff --git a/game.ip_user_files/sim_scripts/clk_wiz_1/activehdl/clk_wiz_1.udo b/game.ip_user_files/sim_scripts/clk_wiz_1/activehdl/clk_wiz_1.udo
new file mode 100644
index 0000000000000000000000000000000000000000..e69de29bb2d1d6434b8b29ae775ad8c2e48c5391
diff --git a/game.ip_user_files/sim_scripts/clk_wiz_1/activehdl/compile.do b/game.ip_user_files/sim_scripts/clk_wiz_1/activehdl/compile.do
new file mode 100644
index 0000000000000000000000000000000000000000..edb56795268644513702ad71a190a2d604050a49
--- /dev/null
+++ b/game.ip_user_files/sim_scripts/clk_wiz_1/activehdl/compile.do
@@ -0,0 +1,19 @@
+vlib work
+vlib activehdl
+
+vlib activehdl/xpm
+vlib activehdl/xil_defaultlib
+
+vmap xpm activehdl/xpm
+vmap xil_defaultlib activehdl/xil_defaultlib
+
+vlog -work xpm -sv2k12 "+incdir+../../../../game.gen/sources_1/ip/clk_wiz_1" \
+"/opt/Xilinx/Vivado/2022.2/data/ip/xpm/xpm_cdc/hdl/xpm_cdc.sv" \
+
+vcom -work xpm -93 \
+"/opt/Xilinx/Vivado/2022.2/data/ip/xpm/xpm_VCOMP.vhd" \
+
+
+vlog -work xil_defaultlib \
+"glbl.v"
+
diff --git a/game.ip_user_files/sim_scripts/clk_wiz_1/activehdl/file_info.txt b/game.ip_user_files/sim_scripts/clk_wiz_1/activehdl/file_info.txt
new file mode 100644
index 0000000000000000000000000000000000000000..1ead46294a6b3acba3055d40c9e081ce12d0e9c1
--- /dev/null
+++ b/game.ip_user_files/sim_scripts/clk_wiz_1/activehdl/file_info.txt
@@ -0,0 +1,3 @@
+xpm_cdc.sv,systemverilog,xpm,../../../opt/Xilinx/Vivado/2022.2/data/ip/xpm/xpm_cdc/hdl/xpm_cdc.sv,incdir="../../../../game.gen/sources_1/ip/clk_wiz_1"
+xpm_VCOMP.vhd,vhdl,xpm,../../../opt/Xilinx/Vivado/2022.2/data/ip/xpm/xpm_VCOMP.vhd,incdir="../../../../game.gen/sources_1/ip/clk_wiz_1"
+glbl.v,Verilog,xil_defaultlib,glbl.v
diff --git a/game.ip_user_files/sim_scripts/clk_wiz_1/activehdl/glbl.v b/game.ip_user_files/sim_scripts/clk_wiz_1/activehdl/glbl.v
new file mode 100644
index 0000000000000000000000000000000000000000..ed3b249ceef65a0d1b42790def9ee8179363679c
--- /dev/null
+++ b/game.ip_user_files/sim_scripts/clk_wiz_1/activehdl/glbl.v
@@ -0,0 +1,84 @@
+// $Header: /devl/xcs/repo/env/Databases/CAEInterfaces/verunilibs/data/glbl.v,v 1.14 2010/10/28 20:44:00 fphillip Exp $
+`ifndef GLBL
+`define GLBL
+`timescale 1 ps / 1 ps
+
+module glbl ();
+
+ parameter ROC_WIDTH = 100000;
+ parameter TOC_WIDTH = 0;
+ parameter GRES_WIDTH = 10000;
+ parameter GRES_START = 10000;
+
+//-------- STARTUP Globals --------------
+ wire GSR;
+ wire GTS;
+ wire GWE;
+ wire PRLD;
+ wire GRESTORE;
+ tri1 p_up_tmp;
+ tri (weak1, strong0) PLL_LOCKG = p_up_tmp;
+
+ wire PROGB_GLBL;
+ wire CCLKO_GLBL;
+ wire FCSBO_GLBL;
+ wire [3:0] DO_GLBL;
+ wire [3:0] DI_GLBL;
+
+ reg GSR_int;
+ reg GTS_int;
+ reg PRLD_int;
+ reg GRESTORE_int;
+
+//-------- JTAG Globals --------------
+ wire JTAG_TDO_GLBL;
+ wire JTAG_TCK_GLBL;
+ wire JTAG_TDI_GLBL;
+ wire JTAG_TMS_GLBL;
+ wire JTAG_TRST_GLBL;
+
+ reg JTAG_CAPTURE_GLBL;
+ reg JTAG_RESET_GLBL;
+ reg JTAG_SHIFT_GLBL;
+ reg JTAG_UPDATE_GLBL;
+ reg JTAG_RUNTEST_GLBL;
+
+ reg JTAG_SEL1_GLBL = 0;
+ reg JTAG_SEL2_GLBL = 0 ;
+ reg JTAG_SEL3_GLBL = 0;
+ reg JTAG_SEL4_GLBL = 0;
+
+ reg JTAG_USER_TDO1_GLBL = 1'bz;
+ reg JTAG_USER_TDO2_GLBL = 1'bz;
+ reg JTAG_USER_TDO3_GLBL = 1'bz;
+ reg JTAG_USER_TDO4_GLBL = 1'bz;
+
+ assign (strong1, weak0) GSR = GSR_int;
+ assign (strong1, weak0) GTS = GTS_int;
+ assign (weak1, weak0) PRLD = PRLD_int;
+ assign (strong1, weak0) GRESTORE = GRESTORE_int;
+
+ initial begin
+ GSR_int = 1'b1;
+ PRLD_int = 1'b1;
+ #(ROC_WIDTH)
+ GSR_int = 1'b0;
+ PRLD_int = 1'b0;
+ end
+
+ initial begin
+ GTS_int = 1'b1;
+ #(TOC_WIDTH)
+ GTS_int = 1'b0;
+ end
+
+ initial begin
+ GRESTORE_int = 1'b0;
+ #(GRES_START);
+ GRESTORE_int = 1'b1;
+ #(GRES_WIDTH);
+ GRESTORE_int = 1'b0;
+ end
+
+endmodule
+`endif
diff --git a/game.ip_user_files/sim_scripts/clk_wiz_1/activehdl/simulate.do b/game.ip_user_files/sim_scripts/clk_wiz_1/activehdl/simulate.do
new file mode 100644
index 0000000000000000000000000000000000000000..7cf3fb71c44ba33194c09bbf3a69f1060c40c8b8
--- /dev/null
+++ b/game.ip_user_files/sim_scripts/clk_wiz_1/activehdl/simulate.do
@@ -0,0 +1,20 @@
+onbreak {quit -force}
+onerror {quit -force}
+
+asim +access +r +m+clk_wiz_1 -L xpm -L unisims_ver -L unimacro_ver -L secureip -O5 xil_defaultlib.clk_wiz_1 xil_defaultlib.glbl
+
+set NumericStdNoWarnings 1
+set StdArithNoWarnings 1
+
+do {wave.do}
+
+view wave
+view structure
+
+do {clk_wiz_1.udo}
+
+run
+
+endsim
+
+quit -force
diff --git a/game.ip_user_files/sim_scripts/clk_wiz_1/activehdl/wave.do b/game.ip_user_files/sim_scripts/clk_wiz_1/activehdl/wave.do
new file mode 100644
index 0000000000000000000000000000000000000000..70157b0cf36569bda8275f1a9640c41911f8d5f7
--- /dev/null
+++ b/game.ip_user_files/sim_scripts/clk_wiz_1/activehdl/wave.do
@@ -0,0 +1,2 @@
+add wave *
+add wave /glbl/GSR
diff --git a/game.ip_user_files/sim_scripts/clk_wiz_1/modelsim/README.txt b/game.ip_user_files/sim_scripts/clk_wiz_1/modelsim/README.txt
new file mode 100644
index 0000000000000000000000000000000000000000..5895c5dd4ec54313cde5d4a854b86a0eb2180232
--- /dev/null
+++ b/game.ip_user_files/sim_scripts/clk_wiz_1/modelsim/README.txt
@@ -0,0 +1,49 @@
+################################################################################
+# Vivado (TM) v2022.2 (64-bit)
+#
+# README.txt: Please read the sections below to understand the steps required to
+# run the exported script and information about the source files.
+#
+# Generated by export_simulation on Mon Feb 27 12:44:43 CET 2023
+#
+################################################################################
+
+1. How to run the generated simulation script:-
+
+From the shell prompt in the current directory, issue the following command:-
+
+./clk_wiz_1.sh
+
+This command will launch the 'compile', 'elaborate' and 'simulate' functions
+implemented in the script file for the 3-step flow. These functions are called
+from the main 'run' function in the script file.
+
+The 'run' function first executes the 'setup' function, the purpose of which is to
+create simulator specific setup files, create design library mappings and library
+directories and copy 'glbl.v' from the Vivado software install location into the
+current directory.
+
+The 'setup' function is also used for removing the simulator generated data in
+order to reset the current directory to the original state when export_simulation
+was launched from Vivado. This generated data can be removed by specifying the
+'-reset_run' switch to the './clk_wiz_1.sh' script.
+
+./clk_wiz_1.sh -reset_run
+
+To keep the generated data from the previous run but regenerate the setup files and
+library directories, use the '-noclean_files' switch.
+
+./clk_wiz_1.sh -noclean_files
+
+For more information on the script, please type './clk_wiz_1.sh -help'.
+
+2. Additional design information files:-
+
+export_simulation generates following additional file that can be used for fetching
+the design files information or for integrating with external custom scripts.
+
+Name : file_info.txt
+Purpose: This file contains detail design file information based on the compile order
+ when export_simulation was executed from Vivado. The file contains information
+ about the file type, name, whether it is part of the IP, associated library
+ and the file path information.
diff --git a/game.ip_user_files/sim_scripts/clk_wiz_1/modelsim/clk_wiz_1.sh b/game.ip_user_files/sim_scripts/clk_wiz_1/modelsim/clk_wiz_1.sh
new file mode 100755
index 0000000000000000000000000000000000000000..16f24431f30acf577e2553e145f6d46dbb0c363c
--- /dev/null
+++ b/game.ip_user_files/sim_scripts/clk_wiz_1/modelsim/clk_wiz_1.sh
@@ -0,0 +1,165 @@
+#!/bin/bash -f
+#*********************************************************************************************************
+# Vivado (TM) v2022.2 (64-bit)
+#
+# Filename : clk_wiz_1.sh
+# Simulator : Mentor Graphics ModelSim Simulator
+# Description : Simulation script for compiling, elaborating and verifying the project source files.
+# The script will automatically create the design libraries sub-directories in the run
+# directory, add the library logical mappings in the simulator setup file, create default
+# 'do/prj' file, execute compilation, elaboration and simulation steps.
+#
+# Generated by Vivado on Mon Feb 27 12:44:43 CET 2023
+# SW Build 3671981 on Fri Oct 14 04:59:54 MDT 2022
+#
+# Tool Version Limit: 2022.10
+#
+# usage: clk_wiz_1.sh [-help]
+# usage: clk_wiz_1.sh [-lib_map_path]
+# usage: clk_wiz_1.sh [-noclean_files]
+# usage: clk_wiz_1.sh [-reset_run]
+#
+# Prerequisite:- To compile and run simulation, you must compile the Xilinx simulation libraries using the
+# 'compile_simlib' TCL command. For more information about this command, run 'compile_simlib -help' in the
+# Vivado Tcl Shell. Once the libraries have been compiled successfully, specify the -lib_map_path switch
+# that points to these libraries and rerun export_simulation. For more information about this switch please
+# type 'export_simulation -help' in the Tcl shell.
+#
+# You can also point to the simulation libraries by either replacing the <SPECIFY_COMPILED_LIB_PATH> in this
+# script with the compiled library directory path or specify this path with the '-lib_map_path' switch when
+# executing this script. Please type 'clk_wiz_1.sh -help' for more information.
+#
+# Additional references - 'Xilinx Vivado Design Suite User Guide:Logic simulation (UG900)'
+#
+#*********************************************************************************************************
+
+# Script info
+echo -e "clk_wiz_1.sh - Script generated by export_simulation (Vivado v2022.2 (64-bit)-id)\n"
+
+# Main steps
+run()
+{
+ check_args $# $1
+ setup $1 $2
+ compile
+ simulate
+}
+
+# RUN_STEP: <compile>
+compile()
+{
+ source compile.do 2>&1 | tee -a compile.log
+}
+
+# RUN_STEP: <simulate>
+simulate()
+{
+ vsim -64 -c -do "do {simulate.do}" -l simulate.log
+}
+
+# STEP: setup
+setup()
+{
+ case $1 in
+ "-lib_map_path" )
+ if [[ ($2 == "") ]]; then
+ echo -e "ERROR: Simulation library directory path not specified (type \"./clk_wiz_1.sh -help\" for more information)\n"
+ exit 1
+ fi
+ copy_setup_file $2
+ ;;
+ "-reset_run" )
+ reset_run
+ echo -e "INFO: Simulation run files deleted.\n"
+ exit 0
+ ;;
+ "-noclean_files" )
+ # do not remove previous data
+ ;;
+ * )
+ copy_setup_file $2
+ esac
+
+ create_lib_dir
+
+ # Add any setup/initialization commands here:-
+
+ # <user specific commands>
+
+}
+
+# Copy modelsim.ini file
+copy_setup_file()
+{
+ file="modelsim.ini"
+ lib_map_path="<SPECIFY_COMPILED_LIB_PATH>"
+ if [[ ($1 != "" && -e $1) ]]; then
+ lib_map_path="$1"
+ else
+ echo -e "ERROR: Compiled simulation library directory path not specified or does not exist (type "./top.sh -help" for more information)\n"
+ fi
+ if [[ ($lib_map_path != "") ]]; then
+ src_file="$lib_map_path/$file"
+ cp $src_file .
+ fi
+}
+
+# Create design library directory
+create_lib_dir()
+{
+ lib_dir="modelsim_lib"
+ if [[ -e $lib_dir ]]; then
+ rm -rf $lib_dir
+ fi
+
+ mkdir $lib_dir
+
+}
+
+# Delete generated data from the previous run
+reset_run()
+{
+ files_to_remove=(compile.log elaborate.log simulate.log vsim.wlf modelsim_lib)
+ for (( i=0; i<${#files_to_remove[*]}; i++ )); do
+ file="${files_to_remove[i]}"
+ if [[ -e $file ]]; then
+ rm -rf $file
+ fi
+ done
+
+ create_lib_dir
+}
+
+# Check command line arguments
+check_args()
+{
+ if [[ ($1 == 1 ) && ($2 != "-lib_map_path" && $2 != "-noclean_files" && $2 != "-reset_run" && $2 != "-help" && $2 != "-h") ]]; then
+ echo -e "ERROR: Unknown option specified '$2' (type \"./clk_wiz_1.sh -help\" for more information)\n"
+ exit 1
+ fi
+
+ if [[ ($2 == "-help" || $2 == "-h") ]]; then
+ usage
+ fi
+}
+
+# Script usage
+usage()
+{
+ msg="Usage: clk_wiz_1.sh [-help]\n\
+Usage: clk_wiz_1.sh [-lib_map_path]\n\
+Usage: clk_wiz_1.sh [-reset_run]\n\
+Usage: clk_wiz_1.sh [-noclean_files]\n\n\
+[-help] -- Print help information for this script\n\n\
+[-lib_map_path <path>] -- Compiled simulation library directory path. The simulation library is compiled\n\
+using the compile_simlib tcl command. Please see 'compile_simlib -help' for more information.\n\n\
+[-reset_run] -- Recreate simulator setup files and library mappings for a clean run. The generated files\n\
+from the previous run will be removed. If you don't want to remove the simulator generated files, use the\n\
+-noclean_files switch.\n\n\
+[-noclean_files] -- Reset previous run, but do not remove simulator generated files from the previous run.\n\n"
+ echo -e $msg
+ exit 1
+}
+
+# Launch script
+run $1 $2
diff --git a/game.ip_user_files/sim_scripts/clk_wiz_1/modelsim/clk_wiz_1.udo b/game.ip_user_files/sim_scripts/clk_wiz_1/modelsim/clk_wiz_1.udo
new file mode 100644
index 0000000000000000000000000000000000000000..e69de29bb2d1d6434b8b29ae775ad8c2e48c5391
diff --git a/game.ip_user_files/sim_scripts/clk_wiz_1/modelsim/compile.do b/game.ip_user_files/sim_scripts/clk_wiz_1/modelsim/compile.do
new file mode 100644
index 0000000000000000000000000000000000000000..12bf40cdc65fa69448077584e6cd98753d7298f3
--- /dev/null
+++ b/game.ip_user_files/sim_scripts/clk_wiz_1/modelsim/compile.do
@@ -0,0 +1,19 @@
+vlib modelsim_lib/work
+vlib modelsim_lib/msim
+
+vlib modelsim_lib/msim/xpm
+vlib modelsim_lib/msim/xil_defaultlib
+
+vmap xpm modelsim_lib/msim/xpm
+vmap xil_defaultlib modelsim_lib/msim/xil_defaultlib
+
+vlog -work xpm -64 -incr -mfcu -sv "+incdir+../../../../game.gen/sources_1/ip/clk_wiz_1" \
+"/opt/Xilinx/Vivado/2022.2/data/ip/xpm/xpm_cdc/hdl/xpm_cdc.sv" \
+
+vcom -work xpm -64 -93 \
+"/opt/Xilinx/Vivado/2022.2/data/ip/xpm/xpm_VCOMP.vhd" \
+
+
+vlog -work xil_defaultlib \
+"glbl.v"
+
diff --git a/game.ip_user_files/sim_scripts/clk_wiz_1/modelsim/file_info.txt b/game.ip_user_files/sim_scripts/clk_wiz_1/modelsim/file_info.txt
new file mode 100644
index 0000000000000000000000000000000000000000..1ead46294a6b3acba3055d40c9e081ce12d0e9c1
--- /dev/null
+++ b/game.ip_user_files/sim_scripts/clk_wiz_1/modelsim/file_info.txt
@@ -0,0 +1,3 @@
+xpm_cdc.sv,systemverilog,xpm,../../../opt/Xilinx/Vivado/2022.2/data/ip/xpm/xpm_cdc/hdl/xpm_cdc.sv,incdir="../../../../game.gen/sources_1/ip/clk_wiz_1"
+xpm_VCOMP.vhd,vhdl,xpm,../../../opt/Xilinx/Vivado/2022.2/data/ip/xpm/xpm_VCOMP.vhd,incdir="../../../../game.gen/sources_1/ip/clk_wiz_1"
+glbl.v,Verilog,xil_defaultlib,glbl.v
diff --git a/game.ip_user_files/sim_scripts/clk_wiz_1/modelsim/glbl.v b/game.ip_user_files/sim_scripts/clk_wiz_1/modelsim/glbl.v
new file mode 100644
index 0000000000000000000000000000000000000000..ed3b249ceef65a0d1b42790def9ee8179363679c
--- /dev/null
+++ b/game.ip_user_files/sim_scripts/clk_wiz_1/modelsim/glbl.v
@@ -0,0 +1,84 @@
+// $Header: /devl/xcs/repo/env/Databases/CAEInterfaces/verunilibs/data/glbl.v,v 1.14 2010/10/28 20:44:00 fphillip Exp $
+`ifndef GLBL
+`define GLBL
+`timescale 1 ps / 1 ps
+
+module glbl ();
+
+ parameter ROC_WIDTH = 100000;
+ parameter TOC_WIDTH = 0;
+ parameter GRES_WIDTH = 10000;
+ parameter GRES_START = 10000;
+
+//-------- STARTUP Globals --------------
+ wire GSR;
+ wire GTS;
+ wire GWE;
+ wire PRLD;
+ wire GRESTORE;
+ tri1 p_up_tmp;
+ tri (weak1, strong0) PLL_LOCKG = p_up_tmp;
+
+ wire PROGB_GLBL;
+ wire CCLKO_GLBL;
+ wire FCSBO_GLBL;
+ wire [3:0] DO_GLBL;
+ wire [3:0] DI_GLBL;
+
+ reg GSR_int;
+ reg GTS_int;
+ reg PRLD_int;
+ reg GRESTORE_int;
+
+//-------- JTAG Globals --------------
+ wire JTAG_TDO_GLBL;
+ wire JTAG_TCK_GLBL;
+ wire JTAG_TDI_GLBL;
+ wire JTAG_TMS_GLBL;
+ wire JTAG_TRST_GLBL;
+
+ reg JTAG_CAPTURE_GLBL;
+ reg JTAG_RESET_GLBL;
+ reg JTAG_SHIFT_GLBL;
+ reg JTAG_UPDATE_GLBL;
+ reg JTAG_RUNTEST_GLBL;
+
+ reg JTAG_SEL1_GLBL = 0;
+ reg JTAG_SEL2_GLBL = 0 ;
+ reg JTAG_SEL3_GLBL = 0;
+ reg JTAG_SEL4_GLBL = 0;
+
+ reg JTAG_USER_TDO1_GLBL = 1'bz;
+ reg JTAG_USER_TDO2_GLBL = 1'bz;
+ reg JTAG_USER_TDO3_GLBL = 1'bz;
+ reg JTAG_USER_TDO4_GLBL = 1'bz;
+
+ assign (strong1, weak0) GSR = GSR_int;
+ assign (strong1, weak0) GTS = GTS_int;
+ assign (weak1, weak0) PRLD = PRLD_int;
+ assign (strong1, weak0) GRESTORE = GRESTORE_int;
+
+ initial begin
+ GSR_int = 1'b1;
+ PRLD_int = 1'b1;
+ #(ROC_WIDTH)
+ GSR_int = 1'b0;
+ PRLD_int = 1'b0;
+ end
+
+ initial begin
+ GTS_int = 1'b1;
+ #(TOC_WIDTH)
+ GTS_int = 1'b0;
+ end
+
+ initial begin
+ GRESTORE_int = 1'b0;
+ #(GRES_START);
+ GRESTORE_int = 1'b1;
+ #(GRES_WIDTH);
+ GRESTORE_int = 1'b0;
+ end
+
+endmodule
+`endif
diff --git a/game.ip_user_files/sim_scripts/clk_wiz_1/modelsim/simulate.do b/game.ip_user_files/sim_scripts/clk_wiz_1/modelsim/simulate.do
new file mode 100644
index 0000000000000000000000000000000000000000..62ddccef1be43ced1a86ea6e2cb1de365cdfb5df
--- /dev/null
+++ b/game.ip_user_files/sim_scripts/clk_wiz_1/modelsim/simulate.do
@@ -0,0 +1,19 @@
+onbreak {quit -f}
+onerror {quit -f}
+
+vsim -voptargs="+acc " -L xpm -L unisims_ver -L unimacro_ver -L secureip -lib xil_defaultlib xil_defaultlib.clk_wiz_1 xil_defaultlib.glbl
+
+set NumericStdNoWarnings 1
+set StdArithNoWarnings 1
+
+do {wave.do}
+
+view wave
+view structure
+view signals
+
+do {clk_wiz_1.udo}
+
+run 1000ns
+
+quit -force
diff --git a/game.ip_user_files/sim_scripts/clk_wiz_1/modelsim/wave.do b/game.ip_user_files/sim_scripts/clk_wiz_1/modelsim/wave.do
new file mode 100644
index 0000000000000000000000000000000000000000..70157b0cf36569bda8275f1a9640c41911f8d5f7
--- /dev/null
+++ b/game.ip_user_files/sim_scripts/clk_wiz_1/modelsim/wave.do
@@ -0,0 +1,2 @@
+add wave *
+add wave /glbl/GSR
diff --git a/game.ip_user_files/sim_scripts/clk_wiz_1/questa/README.txt b/game.ip_user_files/sim_scripts/clk_wiz_1/questa/README.txt
new file mode 100644
index 0000000000000000000000000000000000000000..5895c5dd4ec54313cde5d4a854b86a0eb2180232
--- /dev/null
+++ b/game.ip_user_files/sim_scripts/clk_wiz_1/questa/README.txt
@@ -0,0 +1,49 @@
+################################################################################
+# Vivado (TM) v2022.2 (64-bit)
+#
+# README.txt: Please read the sections below to understand the steps required to
+# run the exported script and information about the source files.
+#
+# Generated by export_simulation on Mon Feb 27 12:44:43 CET 2023
+#
+################################################################################
+
+1. How to run the generated simulation script:-
+
+From the shell prompt in the current directory, issue the following command:-
+
+./clk_wiz_1.sh
+
+This command will launch the 'compile', 'elaborate' and 'simulate' functions
+implemented in the script file for the 3-step flow. These functions are called
+from the main 'run' function in the script file.
+
+The 'run' function first executes the 'setup' function, the purpose of which is to
+create simulator specific setup files, create design library mappings and library
+directories and copy 'glbl.v' from the Vivado software install location into the
+current directory.
+
+The 'setup' function is also used for removing the simulator generated data in
+order to reset the current directory to the original state when export_simulation
+was launched from Vivado. This generated data can be removed by specifying the
+'-reset_run' switch to the './clk_wiz_1.sh' script.
+
+./clk_wiz_1.sh -reset_run
+
+To keep the generated data from the previous run but regenerate the setup files and
+library directories, use the '-noclean_files' switch.
+
+./clk_wiz_1.sh -noclean_files
+
+For more information on the script, please type './clk_wiz_1.sh -help'.
+
+2. Additional design information files:-
+
+export_simulation generates following additional file that can be used for fetching
+the design files information or for integrating with external custom scripts.
+
+Name : file_info.txt
+Purpose: This file contains detail design file information based on the compile order
+ when export_simulation was executed from Vivado. The file contains information
+ about the file type, name, whether it is part of the IP, associated library
+ and the file path information.
diff --git a/game.ip_user_files/sim_scripts/clk_wiz_1/questa/clk_wiz_1.sh b/game.ip_user_files/sim_scripts/clk_wiz_1/questa/clk_wiz_1.sh
new file mode 100755
index 0000000000000000000000000000000000000000..0768a3ddf63e91c00dc8210958fe51497b5c0b41
--- /dev/null
+++ b/game.ip_user_files/sim_scripts/clk_wiz_1/questa/clk_wiz_1.sh
@@ -0,0 +1,172 @@
+#!/bin/bash -f
+#*********************************************************************************************************
+# Vivado (TM) v2022.2 (64-bit)
+#
+# Filename : clk_wiz_1.sh
+# Simulator : Mentor Graphics Questa Advanced Simulator
+# Description : Simulation script for compiling, elaborating and verifying the project source files.
+# The script will automatically create the design libraries sub-directories in the run
+# directory, add the library logical mappings in the simulator setup file, create default
+# 'do/prj' file, execute compilation, elaboration and simulation steps.
+#
+# Generated by Vivado on Mon Feb 27 12:44:43 CET 2023
+# SW Build 3671981 on Fri Oct 14 04:59:54 MDT 2022
+#
+# Tool Version Limit: 2022.10
+#
+# usage: clk_wiz_1.sh [-help]
+# usage: clk_wiz_1.sh [-lib_map_path]
+# usage: clk_wiz_1.sh [-noclean_files]
+# usage: clk_wiz_1.sh [-reset_run]
+#
+# Prerequisite:- To compile and run simulation, you must compile the Xilinx simulation libraries using the
+# 'compile_simlib' TCL command. For more information about this command, run 'compile_simlib -help' in the
+# Vivado Tcl Shell. Once the libraries have been compiled successfully, specify the -lib_map_path switch
+# that points to these libraries and rerun export_simulation. For more information about this switch please
+# type 'export_simulation -help' in the Tcl shell.
+#
+# You can also point to the simulation libraries by either replacing the <SPECIFY_COMPILED_LIB_PATH> in this
+# script with the compiled library directory path or specify this path with the '-lib_map_path' switch when
+# executing this script. Please type 'clk_wiz_1.sh -help' for more information.
+#
+# Additional references - 'Xilinx Vivado Design Suite User Guide:Logic simulation (UG900)'
+#
+#*********************************************************************************************************
+
+# Script info
+echo -e "clk_wiz_1.sh - Script generated by export_simulation (Vivado v2022.2 (64-bit)-id)\n"
+
+# Main steps
+run()
+{
+ check_args $# $1
+ setup $1 $2
+ compile
+ elaborate
+ simulate
+}
+
+# RUN_STEP: <compile>
+compile()
+{
+ source compile.do 2>&1 | tee -a compile.log
+}
+
+# RUN_STEP: <elaborate>
+elaborate()
+{
+ source elaborate.do 2>&1 | tee elaborate.log
+}
+
+# RUN_STEP: <simulate>
+simulate()
+{
+ vsim -64 -c -do "do {simulate.do}" -l simulate.log
+}
+
+# STEP: setup
+setup()
+{
+ case $1 in
+ "-lib_map_path" )
+ if [[ ($2 == "") ]]; then
+ echo -e "ERROR: Simulation library directory path not specified (type \"./clk_wiz_1.sh -help\" for more information)\n"
+ exit 1
+ fi
+ copy_setup_file $2
+ ;;
+ "-reset_run" )
+ reset_run
+ echo -e "INFO: Simulation run files deleted.\n"
+ exit 0
+ ;;
+ "-noclean_files" )
+ # do not remove previous data
+ ;;
+ * )
+ copy_setup_file $2
+ esac
+
+ create_lib_dir
+
+ # Add any setup/initialization commands here:-
+
+ # <user specific commands>
+
+}
+
+# Copy modelsim.ini file
+copy_setup_file()
+{
+ file="modelsim.ini"
+ lib_map_path="<SPECIFY_COMPILED_LIB_PATH>"
+ if [[ ($1 != "" && -e $1) ]]; then
+ lib_map_path="$1"
+ else
+ echo -e "ERROR: Compiled simulation library directory path not specified or does not exist (type "./top.sh -help" for more information)\n"
+ fi
+ if [[ ($lib_map_path != "") ]]; then
+ src_file="$lib_map_path/$file"
+ cp $src_file .
+ fi
+}
+
+# Create design library directory
+create_lib_dir()
+{
+ lib_dir="questa_lib"
+ if [[ -e $lib_dir ]]; then
+ rm -rf $lib_dir
+ fi
+
+ mkdir $lib_dir
+
+}
+
+# Delete generated data from the previous run
+reset_run()
+{
+ files_to_remove=(compile.log elaborate.log simulate.log vsim.wlf questa_lib)
+ for (( i=0; i<${#files_to_remove[*]}; i++ )); do
+ file="${files_to_remove[i]}"
+ if [[ -e $file ]]; then
+ rm -rf $file
+ fi
+ done
+
+ create_lib_dir
+}
+
+# Check command line arguments
+check_args()
+{
+ if [[ ($1 == 1 ) && ($2 != "-lib_map_path" && $2 != "-noclean_files" && $2 != "-reset_run" && $2 != "-help" && $2 != "-h") ]]; then
+ echo -e "ERROR: Unknown option specified '$2' (type \"./clk_wiz_1.sh -help\" for more information)\n"
+ exit 1
+ fi
+
+ if [[ ($2 == "-help" || $2 == "-h") ]]; then
+ usage
+ fi
+}
+
+# Script usage
+usage()
+{
+ msg="Usage: clk_wiz_1.sh [-help]\n\
+Usage: clk_wiz_1.sh [-lib_map_path]\n\
+Usage: clk_wiz_1.sh [-reset_run]\n\
+Usage: clk_wiz_1.sh [-noclean_files]\n\n\
+[-help] -- Print help information for this script\n\n\
+[-lib_map_path <path>] -- Compiled simulation library directory path. The simulation library is compiled\n\
+using the compile_simlib tcl command. Please see 'compile_simlib -help' for more information.\n\n\
+[-reset_run] -- Recreate simulator setup files and library mappings for a clean run. The generated files\n\
+from the previous run will be removed. If you don't want to remove the simulator generated files, use the\n\
+-noclean_files switch.\n\n\
+[-noclean_files] -- Reset previous run, but do not remove simulator generated files from the previous run.\n\n"
+ echo -e $msg
+ exit 1
+}
+
+# Launch script
+run $1 $2
diff --git a/game.ip_user_files/sim_scripts/clk_wiz_1/questa/clk_wiz_1.udo b/game.ip_user_files/sim_scripts/clk_wiz_1/questa/clk_wiz_1.udo
new file mode 100644
index 0000000000000000000000000000000000000000..e69de29bb2d1d6434b8b29ae775ad8c2e48c5391
diff --git a/game.ip_user_files/sim_scripts/clk_wiz_1/questa/compile.do b/game.ip_user_files/sim_scripts/clk_wiz_1/questa/compile.do
new file mode 100644
index 0000000000000000000000000000000000000000..45cbc5e86b707622e1d3606c97f8060dd4a1e371
--- /dev/null
+++ b/game.ip_user_files/sim_scripts/clk_wiz_1/questa/compile.do
@@ -0,0 +1,19 @@
+vlib questa_lib/work
+vlib questa_lib/msim
+
+vlib questa_lib/msim/xpm
+vlib questa_lib/msim/xil_defaultlib
+
+vmap xpm questa_lib/msim/xpm
+vmap xil_defaultlib questa_lib/msim/xil_defaultlib
+
+vlog -work xpm -64 -incr -mfcu -sv "+incdir+../../../../game.gen/sources_1/ip/clk_wiz_1" \
+"/opt/Xilinx/Vivado/2022.2/data/ip/xpm/xpm_cdc/hdl/xpm_cdc.sv" \
+
+vcom -work xpm -64 -93 \
+"/opt/Xilinx/Vivado/2022.2/data/ip/xpm/xpm_VCOMP.vhd" \
+
+
+vlog -work xil_defaultlib \
+"glbl.v"
+
diff --git a/game.ip_user_files/sim_scripts/clk_wiz_1/questa/elaborate.do b/game.ip_user_files/sim_scripts/clk_wiz_1/questa/elaborate.do
new file mode 100644
index 0000000000000000000000000000000000000000..fc770067309c5dccc55ca2312ccae59176ebf39a
--- /dev/null
+++ b/game.ip_user_files/sim_scripts/clk_wiz_1/questa/elaborate.do
@@ -0,0 +1 @@
+vopt -64 +acc=npr -l elaborate.log -L xpm -L unisims_ver -L unimacro_ver -L secureip -work xil_defaultlib xil_defaultlib.clk_wiz_1 xil_defaultlib.glbl -o clk_wiz_1_opt
diff --git a/game.ip_user_files/sim_scripts/clk_wiz_1/questa/file_info.txt b/game.ip_user_files/sim_scripts/clk_wiz_1/questa/file_info.txt
new file mode 100644
index 0000000000000000000000000000000000000000..1ead46294a6b3acba3055d40c9e081ce12d0e9c1
--- /dev/null
+++ b/game.ip_user_files/sim_scripts/clk_wiz_1/questa/file_info.txt
@@ -0,0 +1,3 @@
+xpm_cdc.sv,systemverilog,xpm,../../../opt/Xilinx/Vivado/2022.2/data/ip/xpm/xpm_cdc/hdl/xpm_cdc.sv,incdir="../../../../game.gen/sources_1/ip/clk_wiz_1"
+xpm_VCOMP.vhd,vhdl,xpm,../../../opt/Xilinx/Vivado/2022.2/data/ip/xpm/xpm_VCOMP.vhd,incdir="../../../../game.gen/sources_1/ip/clk_wiz_1"
+glbl.v,Verilog,xil_defaultlib,glbl.v
diff --git a/game.ip_user_files/sim_scripts/clk_wiz_1/questa/glbl.v b/game.ip_user_files/sim_scripts/clk_wiz_1/questa/glbl.v
new file mode 100644
index 0000000000000000000000000000000000000000..ed3b249ceef65a0d1b42790def9ee8179363679c
--- /dev/null
+++ b/game.ip_user_files/sim_scripts/clk_wiz_1/questa/glbl.v
@@ -0,0 +1,84 @@
+// $Header: /devl/xcs/repo/env/Databases/CAEInterfaces/verunilibs/data/glbl.v,v 1.14 2010/10/28 20:44:00 fphillip Exp $
+`ifndef GLBL
+`define GLBL
+`timescale 1 ps / 1 ps
+
+module glbl ();
+
+ parameter ROC_WIDTH = 100000;
+ parameter TOC_WIDTH = 0;
+ parameter GRES_WIDTH = 10000;
+ parameter GRES_START = 10000;
+
+//-------- STARTUP Globals --------------
+ wire GSR;
+ wire GTS;
+ wire GWE;
+ wire PRLD;
+ wire GRESTORE;
+ tri1 p_up_tmp;
+ tri (weak1, strong0) PLL_LOCKG = p_up_tmp;
+
+ wire PROGB_GLBL;
+ wire CCLKO_GLBL;
+ wire FCSBO_GLBL;
+ wire [3:0] DO_GLBL;
+ wire [3:0] DI_GLBL;
+
+ reg GSR_int;
+ reg GTS_int;
+ reg PRLD_int;
+ reg GRESTORE_int;
+
+//-------- JTAG Globals --------------
+ wire JTAG_TDO_GLBL;
+ wire JTAG_TCK_GLBL;
+ wire JTAG_TDI_GLBL;
+ wire JTAG_TMS_GLBL;
+ wire JTAG_TRST_GLBL;
+
+ reg JTAG_CAPTURE_GLBL;
+ reg JTAG_RESET_GLBL;
+ reg JTAG_SHIFT_GLBL;
+ reg JTAG_UPDATE_GLBL;
+ reg JTAG_RUNTEST_GLBL;
+
+ reg JTAG_SEL1_GLBL = 0;
+ reg JTAG_SEL2_GLBL = 0 ;
+ reg JTAG_SEL3_GLBL = 0;
+ reg JTAG_SEL4_GLBL = 0;
+
+ reg JTAG_USER_TDO1_GLBL = 1'bz;
+ reg JTAG_USER_TDO2_GLBL = 1'bz;
+ reg JTAG_USER_TDO3_GLBL = 1'bz;
+ reg JTAG_USER_TDO4_GLBL = 1'bz;
+
+ assign (strong1, weak0) GSR = GSR_int;
+ assign (strong1, weak0) GTS = GTS_int;
+ assign (weak1, weak0) PRLD = PRLD_int;
+ assign (strong1, weak0) GRESTORE = GRESTORE_int;
+
+ initial begin
+ GSR_int = 1'b1;
+ PRLD_int = 1'b1;
+ #(ROC_WIDTH)
+ GSR_int = 1'b0;
+ PRLD_int = 1'b0;
+ end
+
+ initial begin
+ GTS_int = 1'b1;
+ #(TOC_WIDTH)
+ GTS_int = 1'b0;
+ end
+
+ initial begin
+ GRESTORE_int = 1'b0;
+ #(GRES_START);
+ GRESTORE_int = 1'b1;
+ #(GRES_WIDTH);
+ GRESTORE_int = 1'b0;
+ end
+
+endmodule
+`endif
diff --git a/game.ip_user_files/sim_scripts/clk_wiz_1/questa/simulate.do b/game.ip_user_files/sim_scripts/clk_wiz_1/questa/simulate.do
new file mode 100644
index 0000000000000000000000000000000000000000..0614ca74ba6944cd56f97af933ae4f833562ae13
--- /dev/null
+++ b/game.ip_user_files/sim_scripts/clk_wiz_1/questa/simulate.do
@@ -0,0 +1,19 @@
+onbreak {quit -f}
+onerror {quit -f}
+
+vsim -lib xil_defaultlib clk_wiz_1_opt
+
+set NumericStdNoWarnings 1
+set StdArithNoWarnings 1
+
+do {wave.do}
+
+view wave
+view structure
+view signals
+
+do {clk_wiz_1.udo}
+
+run 1000ns
+
+quit -force
diff --git a/game.ip_user_files/sim_scripts/clk_wiz_1/questa/wave.do b/game.ip_user_files/sim_scripts/clk_wiz_1/questa/wave.do
new file mode 100644
index 0000000000000000000000000000000000000000..70157b0cf36569bda8275f1a9640c41911f8d5f7
--- /dev/null
+++ b/game.ip_user_files/sim_scripts/clk_wiz_1/questa/wave.do
@@ -0,0 +1,2 @@
+add wave *
+add wave /glbl/GSR
diff --git a/game.ip_user_files/sim_scripts/clk_wiz_1/riviera/README.txt b/game.ip_user_files/sim_scripts/clk_wiz_1/riviera/README.txt
new file mode 100644
index 0000000000000000000000000000000000000000..5895c5dd4ec54313cde5d4a854b86a0eb2180232
--- /dev/null
+++ b/game.ip_user_files/sim_scripts/clk_wiz_1/riviera/README.txt
@@ -0,0 +1,49 @@
+################################################################################
+# Vivado (TM) v2022.2 (64-bit)
+#
+# README.txt: Please read the sections below to understand the steps required to
+# run the exported script and information about the source files.
+#
+# Generated by export_simulation on Mon Feb 27 12:44:43 CET 2023
+#
+################################################################################
+
+1. How to run the generated simulation script:-
+
+From the shell prompt in the current directory, issue the following command:-
+
+./clk_wiz_1.sh
+
+This command will launch the 'compile', 'elaborate' and 'simulate' functions
+implemented in the script file for the 3-step flow. These functions are called
+from the main 'run' function in the script file.
+
+The 'run' function first executes the 'setup' function, the purpose of which is to
+create simulator specific setup files, create design library mappings and library
+directories and copy 'glbl.v' from the Vivado software install location into the
+current directory.
+
+The 'setup' function is also used for removing the simulator generated data in
+order to reset the current directory to the original state when export_simulation
+was launched from Vivado. This generated data can be removed by specifying the
+'-reset_run' switch to the './clk_wiz_1.sh' script.
+
+./clk_wiz_1.sh -reset_run
+
+To keep the generated data from the previous run but regenerate the setup files and
+library directories, use the '-noclean_files' switch.
+
+./clk_wiz_1.sh -noclean_files
+
+For more information on the script, please type './clk_wiz_1.sh -help'.
+
+2. Additional design information files:-
+
+export_simulation generates following additional file that can be used for fetching
+the design files information or for integrating with external custom scripts.
+
+Name : file_info.txt
+Purpose: This file contains detail design file information based on the compile order
+ when export_simulation was executed from Vivado. The file contains information
+ about the file type, name, whether it is part of the IP, associated library
+ and the file path information.
diff --git a/game.ip_user_files/sim_scripts/clk_wiz_1/riviera/clk_wiz_1.sh b/game.ip_user_files/sim_scripts/clk_wiz_1/riviera/clk_wiz_1.sh
new file mode 100755
index 0000000000000000000000000000000000000000..2a273350041c75bb3c8bbfcc6d53bdd69722e6f3
--- /dev/null
+++ b/game.ip_user_files/sim_scripts/clk_wiz_1/riviera/clk_wiz_1.sh
@@ -0,0 +1,151 @@
+#!/bin/bash -f
+#*********************************************************************************************************
+# Vivado (TM) v2022.2 (64-bit)
+#
+# Filename : clk_wiz_1.sh
+# Simulator : Aldec Riviera-PRO Simulator
+# Description : Simulation script for compiling, elaborating and verifying the project source files.
+# The script will automatically create the design libraries sub-directories in the run
+# directory, add the library logical mappings in the simulator setup file, create default
+# 'do/prj' file, execute compilation, elaboration and simulation steps.
+#
+# Generated by Vivado on Mon Feb 27 12:44:43 CET 2023
+# SW Build 3671981 on Fri Oct 14 04:59:54 MDT 2022
+#
+# Tool Version Limit: 2022.10
+#
+# usage: clk_wiz_1.sh [-help]
+# usage: clk_wiz_1.sh [-lib_map_path]
+# usage: clk_wiz_1.sh [-noclean_files]
+# usage: clk_wiz_1.sh [-reset_run]
+#
+# Prerequisite:- To compile and run simulation, you must compile the Xilinx simulation libraries using the
+# 'compile_simlib' TCL command. For more information about this command, run 'compile_simlib -help' in the
+# Vivado Tcl Shell. Once the libraries have been compiled successfully, specify the -lib_map_path switch
+# that points to these libraries and rerun export_simulation. For more information about this switch please
+# type 'export_simulation -help' in the Tcl shell.
+#
+# You can also point to the simulation libraries by either replacing the <SPECIFY_COMPILED_LIB_PATH> in this
+# script with the compiled library directory path or specify this path with the '-lib_map_path' switch when
+# executing this script. Please type 'clk_wiz_1.sh -help' for more information.
+#
+# Additional references - 'Xilinx Vivado Design Suite User Guide:Logic simulation (UG900)'
+#
+#*********************************************************************************************************
+
+# Script info
+echo -e "clk_wiz_1.sh - Script generated by export_simulation (Vivado v2022.2 (64-bit)-id)\n"
+
+# Main steps
+run()
+{
+ check_args $# $1
+ setup $1 $2
+ compile
+ simulate
+}
+
+# RUN_STEP: <compile>
+compile()
+{
+ source compile.do 2>&1 | tee -a compile.log
+}
+
+# RUN_STEP: <simulate>
+simulate()
+{
+ runvsimsa -l simulate.log -do "do {simulate.do}"
+}
+
+# STEP: setup
+setup()
+{
+ case $1 in
+ "-lib_map_path" )
+ if [[ ($2 == "") ]]; then
+ echo -e "ERROR: Simulation library directory path not specified (type \"./clk_wiz_1.sh -help\" for more information)\n"
+ exit 1
+ fi
+ map_setup_file $2
+ ;;
+ "-reset_run" )
+ reset_run
+ echo -e "INFO: Simulation run files deleted.\n"
+ exit 0
+ ;;
+ "-noclean_files" )
+ # do not remove previous data
+ ;;
+ * )
+ map_setup_file $2
+ esac
+
+ # Add any setup/initialization commands here:-
+
+ # <user specific commands>
+
+}
+
+# Map library.cfg file
+map_setup_file()
+{
+ file="library.cfg"
+ lib_map_path="<SPECIFY_COMPILED_LIB_PATH>"
+ if [[ ($1 != "" && -e $1) ]]; then
+ lib_map_path="$1"
+ else
+ echo -e "ERROR: Compiled simulation library directory path not specified or does not exist (type "./top.sh -help" for more information)\n"
+ fi
+ if [[ ($lib_map_path != "") ]]; then
+ src_file="$lib_map_path/$file"
+ if [[ -e $src_file ]]; then
+ vmap -link $lib_map_path
+ fi
+ fi
+}
+
+# Delete generated data from the previous run
+reset_run()
+{
+ files_to_remove=(compile.log elaboration.log simulate.log dataset.asdb work riviera)
+ for (( i=0; i<${#files_to_remove[*]}; i++ )); do
+ file="${files_to_remove[i]}"
+ if [[ -e $file ]]; then
+ rm -rf $file
+ fi
+ done
+}
+
+# Check command line arguments
+check_args()
+{
+ if [[ ($1 == 1 ) && ($2 != "-lib_map_path" && $2 != "-noclean_files" && $2 != "-reset_run" && $2 != "-help" && $2 != "-h") ]]; then
+ echo -e "ERROR: Unknown option specified '$2' (type \"./clk_wiz_1.sh -help\" for more information)\n"
+ exit 1
+ fi
+
+ if [[ ($2 == "-help" || $2 == "-h") ]]; then
+ usage
+ fi
+}
+
+# Script usage
+usage()
+{
+ msg="Usage: clk_wiz_1.sh [-help]\n\
+Usage: clk_wiz_1.sh [-lib_map_path]\n\
+Usage: clk_wiz_1.sh [-reset_run]\n\
+Usage: clk_wiz_1.sh [-noclean_files]\n\n\
+[-help] -- Print help information for this script\n\n\
+[-lib_map_path <path>] -- Compiled simulation library directory path. The simulation library is compiled\n\
+using the compile_simlib tcl command. Please see 'compile_simlib -help' for more information.\n\n\
+[-reset_run] -- Recreate simulator setup files and library mappings for a clean run. The generated files\n\
+from the previous run will be removed. If you don't want to remove the simulator generated files, use the\n\
+-noclean_files switch.\n\n\
+[-noclean_files] -- Reset previous run, but do not remove simulator generated files from the previous run.\n\n"
+ echo -e $msg
+ exit 1
+}
+
+# Launch script
+run $1 $2
diff --git a/game.ip_user_files/sim_scripts/clk_wiz_1/riviera/clk_wiz_1.udo b/game.ip_user_files/sim_scripts/clk_wiz_1/riviera/clk_wiz_1.udo
new file mode 100644
index 0000000000000000000000000000000000000000..e69de29bb2d1d6434b8b29ae775ad8c2e48c5391
diff --git a/game.ip_user_files/sim_scripts/clk_wiz_1/riviera/compile.do b/game.ip_user_files/sim_scripts/clk_wiz_1/riviera/compile.do
new file mode 100644
index 0000000000000000000000000000000000000000..cecc0dce43113621de9ecd03e5532716c0ab3de7
--- /dev/null
+++ b/game.ip_user_files/sim_scripts/clk_wiz_1/riviera/compile.do
@@ -0,0 +1,19 @@
+vlib work
+vlib riviera
+
+vlib riviera/xpm
+vlib riviera/xil_defaultlib
+
+vmap xpm riviera/xpm
+vmap xil_defaultlib riviera/xil_defaultlib
+
+vlog -work xpm -sv2k12 "+incdir+../../../../game.gen/sources_1/ip/clk_wiz_1" \
+"/opt/Xilinx/Vivado/2022.2/data/ip/xpm/xpm_cdc/hdl/xpm_cdc.sv" \
+
+vcom -work xpm -93 \
+"/opt/Xilinx/Vivado/2022.2/data/ip/xpm/xpm_VCOMP.vhd" \
+
+
+vlog -work xil_defaultlib \
+"glbl.v"
+
diff --git a/game.ip_user_files/sim_scripts/clk_wiz_1/riviera/file_info.txt b/game.ip_user_files/sim_scripts/clk_wiz_1/riviera/file_info.txt
new file mode 100644
index 0000000000000000000000000000000000000000..1ead46294a6b3acba3055d40c9e081ce12d0e9c1
--- /dev/null
+++ b/game.ip_user_files/sim_scripts/clk_wiz_1/riviera/file_info.txt
@@ -0,0 +1,3 @@
+xpm_cdc.sv,systemverilog,xpm,../../../opt/Xilinx/Vivado/2022.2/data/ip/xpm/xpm_cdc/hdl/xpm_cdc.sv,incdir="../../../../game.gen/sources_1/ip/clk_wiz_1"
+xpm_VCOMP.vhd,vhdl,xpm,../../../opt/Xilinx/Vivado/2022.2/data/ip/xpm/xpm_VCOMP.vhd,incdir="../../../../game.gen/sources_1/ip/clk_wiz_1"
+glbl.v,Verilog,xil_defaultlib,glbl.v
diff --git a/game.ip_user_files/sim_scripts/clk_wiz_1/riviera/glbl.v b/game.ip_user_files/sim_scripts/clk_wiz_1/riviera/glbl.v
new file mode 100644
index 0000000000000000000000000000000000000000..ed3b249ceef65a0d1b42790def9ee8179363679c
--- /dev/null
+++ b/game.ip_user_files/sim_scripts/clk_wiz_1/riviera/glbl.v
@@ -0,0 +1,84 @@
+// $Header: /devl/xcs/repo/env/Databases/CAEInterfaces/verunilibs/data/glbl.v,v 1.14 2010/10/28 20:44:00 fphillip Exp $
+`ifndef GLBL
+`define GLBL
+`timescale 1 ps / 1 ps
+
+module glbl ();
+
+ parameter ROC_WIDTH = 100000;
+ parameter TOC_WIDTH = 0;
+ parameter GRES_WIDTH = 10000;
+ parameter GRES_START = 10000;
+
+//-------- STARTUP Globals --------------
+ wire GSR;
+ wire GTS;
+ wire GWE;
+ wire PRLD;
+ wire GRESTORE;
+ tri1 p_up_tmp;
+ tri (weak1, strong0) PLL_LOCKG = p_up_tmp;
+
+ wire PROGB_GLBL;
+ wire CCLKO_GLBL;
+ wire FCSBO_GLBL;
+ wire [3:0] DO_GLBL;
+ wire [3:0] DI_GLBL;
+
+ reg GSR_int;
+ reg GTS_int;
+ reg PRLD_int;
+ reg GRESTORE_int;
+
+//-------- JTAG Globals --------------
+ wire JTAG_TDO_GLBL;
+ wire JTAG_TCK_GLBL;
+ wire JTAG_TDI_GLBL;
+ wire JTAG_TMS_GLBL;
+ wire JTAG_TRST_GLBL;
+
+ reg JTAG_CAPTURE_GLBL;
+ reg JTAG_RESET_GLBL;
+ reg JTAG_SHIFT_GLBL;
+ reg JTAG_UPDATE_GLBL;
+ reg JTAG_RUNTEST_GLBL;
+
+ reg JTAG_SEL1_GLBL = 0;
+ reg JTAG_SEL2_GLBL = 0 ;
+ reg JTAG_SEL3_GLBL = 0;
+ reg JTAG_SEL4_GLBL = 0;
+
+ reg JTAG_USER_TDO1_GLBL = 1'bz;
+ reg JTAG_USER_TDO2_GLBL = 1'bz;
+ reg JTAG_USER_TDO3_GLBL = 1'bz;
+ reg JTAG_USER_TDO4_GLBL = 1'bz;
+
+ assign (strong1, weak0) GSR = GSR_int;
+ assign (strong1, weak0) GTS = GTS_int;
+ assign (weak1, weak0) PRLD = PRLD_int;
+ assign (strong1, weak0) GRESTORE = GRESTORE_int;
+
+ initial begin
+ GSR_int = 1'b1;
+ PRLD_int = 1'b1;
+ #(ROC_WIDTH)
+ GSR_int = 1'b0;
+ PRLD_int = 1'b0;
+ end
+
+ initial begin
+ GTS_int = 1'b1;
+ #(TOC_WIDTH)
+ GTS_int = 1'b0;
+ end
+
+ initial begin
+ GRESTORE_int = 1'b0;
+ #(GRES_START);
+ GRESTORE_int = 1'b1;
+ #(GRES_WIDTH);
+ GRESTORE_int = 1'b0;
+ end
+
+endmodule
+`endif
diff --git a/game.ip_user_files/sim_scripts/clk_wiz_1/riviera/simulate.do b/game.ip_user_files/sim_scripts/clk_wiz_1/riviera/simulate.do
new file mode 100644
index 0000000000000000000000000000000000000000..acb65f14fbc5f08c61ae094499c34cde9fe87da2
--- /dev/null
+++ b/game.ip_user_files/sim_scripts/clk_wiz_1/riviera/simulate.do
@@ -0,0 +1,20 @@
+onbreak {quit -force}
+onerror {quit -force}
+
+asim +access +r +m+clk_wiz_1 -L xpm -L unisims_ver -L unimacro_ver -L secureip -O5 xil_defaultlib.clk_wiz_1 xil_defaultlib.glbl
+
+set NumericStdNoWarnings 1
+set StdArithNoWarnings 1
+
+do {wave.do}
+
+view wave
+view structure
+
+do {clk_wiz_1.udo}
+
+run 1000ns
+
+endsim
+
+quit -force
diff --git a/game.ip_user_files/sim_scripts/clk_wiz_1/riviera/wave.do b/game.ip_user_files/sim_scripts/clk_wiz_1/riviera/wave.do
new file mode 100644
index 0000000000000000000000000000000000000000..70157b0cf36569bda8275f1a9640c41911f8d5f7
--- /dev/null
+++ b/game.ip_user_files/sim_scripts/clk_wiz_1/riviera/wave.do
@@ -0,0 +1,2 @@
+add wave *
+add wave /glbl/GSR
diff --git a/game.ip_user_files/sim_scripts/clk_wiz_1/vcs/README.txt b/game.ip_user_files/sim_scripts/clk_wiz_1/vcs/README.txt
new file mode 100644
index 0000000000000000000000000000000000000000..5895c5dd4ec54313cde5d4a854b86a0eb2180232
--- /dev/null
+++ b/game.ip_user_files/sim_scripts/clk_wiz_1/vcs/README.txt
@@ -0,0 +1,49 @@
+################################################################################
+# Vivado (TM) v2022.2 (64-bit)
+#
+# README.txt: Please read the sections below to understand the steps required to
+# run the exported script and information about the source files.
+#
+# Generated by export_simulation on Mon Feb 27 12:44:43 CET 2023
+#
+################################################################################
+
+1. How to run the generated simulation script:-
+
+From the shell prompt in the current directory, issue the following command:-
+
+./clk_wiz_1.sh
+
+This command will launch the 'compile', 'elaborate' and 'simulate' functions
+implemented in the script file for the 3-step flow. These functions are called
+from the main 'run' function in the script file.
+
+The 'run' function first executes the 'setup' function, the purpose of which is to
+create simulator specific setup files, create design library mappings and library
+directories and copy 'glbl.v' from the Vivado software install location into the
+current directory.
+
+The 'setup' function is also used for removing the simulator generated data in
+order to reset the current directory to the original state when export_simulation
+was launched from Vivado. This generated data can be removed by specifying the
+'-reset_run' switch to the './clk_wiz_1.sh' script.
+
+./clk_wiz_1.sh -reset_run
+
+To keep the generated data from the previous run but regenerate the setup files and
+library directories, use the '-noclean_files' switch.
+
+./clk_wiz_1.sh -noclean_files
+
+For more information on the script, please type './clk_wiz_1.sh -help'.
+
+2. Additional design information files:-
+
+export_simulation generates following additional file that can be used for fetching
+the design files information or for integrating with external custom scripts.
+
+Name : file_info.txt
+Purpose: This file contains detail design file information based on the compile order
+ when export_simulation was executed from Vivado. The file contains information
+ about the file type, name, whether it is part of the IP, associated library
+ and the file path information.
diff --git a/game.ip_user_files/sim_scripts/clk_wiz_1/vcs/clk_wiz_1.sh b/game.ip_user_files/sim_scripts/clk_wiz_1/vcs/clk_wiz_1.sh
new file mode 100755
index 0000000000000000000000000000000000000000..27393e19fb16c0d279cd7e4e8b37897a931de123
--- /dev/null
+++ b/game.ip_user_files/sim_scripts/clk_wiz_1/vcs/clk_wiz_1.sh
@@ -0,0 +1,230 @@
+#!/bin/bash -f
+#*********************************************************************************************************
+# Vivado (TM) v2022.2 (64-bit)
+#
+# Filename : clk_wiz_1.sh
+# Simulator : Synopsys Verilog Compiler Simulator
+# Description : Simulation script for compiling, elaborating and verifying the project source files.
+# The script will automatically create the design libraries sub-directories in the run
+# directory, add the library logical mappings in the simulator setup file, create default
+# 'do/prj' file, execute compilation, elaboration and simulation steps.
+#
+# Generated by Vivado on Mon Feb 27 12:44:43 CET 2023
+# SW Build 3671981 on Fri Oct 14 04:59:54 MDT 2022
+#
+# Tool Version Limit: 2022.10
+#
+# usage: clk_wiz_1.sh [-help]
+# usage: clk_wiz_1.sh [-lib_map_path]
+# usage: clk_wiz_1.sh [-noclean_files]
+# usage: clk_wiz_1.sh [-reset_run]
+#
+# Prerequisite:- To compile and run simulation, you must compile the Xilinx simulation libraries using the
+# 'compile_simlib' TCL command. For more information about this command, run 'compile_simlib -help' in the
+# Vivado Tcl Shell. Once the libraries have been compiled successfully, specify the -lib_map_path switch
+# that points to these libraries and rerun export_simulation. For more information about this switch please
+# type 'export_simulation -help' in the Tcl shell.
+#
+# You can also point to the simulation libraries by either replacing the <SPECIFY_COMPILED_LIB_PATH> in this
+# script with the compiled library directory path or specify this path with the '-lib_map_path' switch when
+# executing this script. Please type 'clk_wiz_1.sh -help' for more information.
+#
+# Additional references - 'Xilinx Vivado Design Suite User Guide:Logic simulation (UG900)'
+#
+#*********************************************************************************************************
+
+# Directory path for design sources and include directories (if any) wrt this path
+ref_dir="."
+
+# Override directory with 'export_sim_ref_dir' env path value if set in the shell
+if [[ (! -z "$export_sim_ref_dir") && ($export_sim_ref_dir != "") ]]; then
+ ref_dir="$export_sim_ref_dir"
+fi
+
+# Set vlogan compile options
+vlogan_opts="-full64 "
+
+# Set vhdlan compile options
+vhdlan_opts="-full64 "
+
+# Set vcs elaboration options
+vcs_elab_opts="-full64 -debug_acc+pp+dmptf -t ps -licqueue -l elaborate.log "
+
+# Set vcs simulation options
+vcs_sim_opts="-ucli -licqueue -l simulate.log "
+
+# Design libraries
+design_libs=(xpm)
+
+# Simulation root library directory
+sim_lib_dir="vcs_lib"
+
+# Script info
+echo -e "clk_wiz_1.sh - Script generated by export_simulation (Vivado v2022.2 (64-bit)-id)\n"
+
+# Main steps
+run()
+{
+ check_args $# $1
+ setup $1 $2
+ compile
+ elaborate
+ simulate
+}
+
+# RUN_STEP: <compile>
+compile()
+{
+ vlogan -work xpm $vlogan_opts -sverilog +incdir+"$ref_dir/../../../../game.gen/sources_1/ip/clk_wiz_1" \
+ "/opt/Xilinx/Vivado/2022.2/data/ip/xpm/xpm_cdc/hdl/xpm_cdc.sv" \
+ 2>&1 | tee -a vlogan.log
+
+ vhdlan -work xpm $vhdlan_opts \
+ "/opt/Xilinx/Vivado/2022.2/data/ip/xpm/xpm_VCOMP.vhd" \
+ 2>&1 | tee -a vhdlan.log
+
+
+ vlogan -work xil_defaultlib $vlogan_opts +v2k \
+ glbl.v \
+ 2>&1 | tee -a vlogan.log
+}
+
+# RUN_STEP: <elaborate>
+elaborate()
+{
+ vcs $vcs_elab_opts xil_defaultlib.clk_wiz_1 xil_defaultlib.glbl -o clk_wiz_1_simv
+}
+
+# RUN_STEP: <simulate>
+simulate()
+{
+ ./clk_wiz_1_simv $vcs_sim_opts -do simulate.do
+}
+
+# STEP: setup
+setup()
+{
+ case $1 in
+ "-lib_map_path" )
+ if [[ ($2 == "") ]]; then
+ echo -e "ERROR: Simulation library directory path not specified (type \"./clk_wiz_1.sh -help\" for more information)\n"
+ exit 1
+ fi
+ create_lib_mappings $2
+ ;;
+ "-reset_run" )
+ reset_run
+ echo -e "INFO: Simulation run files deleted.\n"
+ exit 0
+ ;;
+ "-noclean_files" )
+ # do not remove previous data
+ ;;
+ * )
+ create_lib_mappings $2
+ esac
+
+ create_lib_dir
+
+ # Add any setup/initialization commands here:-
+
+ # <user specific commands>
+
+}
+
+# Define design library mappings
+create_lib_mappings()
+{
+ file="synopsys_sim.setup"
+ if [[ -e $file ]]; then
+ if [[ ($1 == "") ]]; then
+ return
+ else
+ rm -rf $file
+ fi
+ fi
+
+ touch $file
+
+ lib_map_path="<SPECIFY_COMPILED_LIB_PATH>"
+ if [[ ($1 != "" && -e $1) ]]; then
+ lib_map_path="$1"
+ else
+ echo -e "ERROR: Compiled simulation library directory path not specified or does not exist (type "./top.sh -help" for more information)\n"
+ fi
+
+ for (( i=0; i<${#design_libs[*]}; i++ )); do
+ lib="${design_libs[i]}"
+ mapping="$lib:$sim_lib_dir/$lib"
+ echo $mapping >> $file
+ done
+
+ if [[ ($lib_map_path != "") ]]; then
+ incl_ref="OTHERS=$lib_map_path/synopsys_sim.setup"
+ echo $incl_ref >> $file
+ fi
+}
+
+# Create design library directory paths
+create_lib_dir()
+{
+ if [[ -e $sim_lib_dir ]]; then
+ rm -rf $sim_lib_dir
+ fi
+
+ for (( i=0; i<${#design_libs[*]}; i++ )); do
+ lib="${design_libs[i]}"
+ lib_dir="$sim_lib_dir/$lib"
+ if [[ ! -e $lib_dir ]]; then
+ mkdir -p $lib_dir
+ fi
+ done
+}
+
+# Delete generated data from the previous run
+reset_run()
+{
+ files_to_remove=(ucli.key clk_wiz_1_simv vlogan.log vhdlan.log compile.log elaborate.log simulate.log .vlogansetup.env .vlogansetup.args .vcs_lib_lock scirocco_command.log 64 AN.DB csrc clk_wiz_1_simv.daidir)
+ for (( i=0; i<${#files_to_remove[*]}; i++ )); do
+ file="${files_to_remove[i]}"
+ if [[ -e $file ]]; then
+ rm -rf $file
+ fi
+ done
+
+ create_lib_dir
+}
+
+# Check command line arguments
+check_args()
+{
+ if [[ ($1 == 1 ) && ($2 != "-lib_map_path" && $2 != "-noclean_files" && $2 != "-reset_run" && $2 != "-help" && $2 != "-h") ]]; then
+ echo -e "ERROR: Unknown option specified '$2' (type \"./clk_wiz_1.sh -help\" for more information)\n"
+ exit 1
+ fi
+
+ if [[ ($2 == "-help" || $2 == "-h") ]]; then
+ usage
+ fi
+}
+
+# Script usage
+usage()
+{
+ msg="Usage: clk_wiz_1.sh [-help]\n\
+Usage: clk_wiz_1.sh [-lib_map_path]\n\
+Usage: clk_wiz_1.sh [-reset_run]\n\
+Usage: clk_wiz_1.sh [-noclean_files]\n\n\
+[-help] -- Print help information for this script\n\n\
+[-lib_map_path <path>] -- Compiled simulation library directory path. The simulation library is compiled\n\
+using the compile_simlib tcl command. Please see 'compile_simlib -help' for more information.\n\n\
+[-reset_run] -- Recreate simulator setup files and library mappings for a clean run. The generated files\n\
+from the previous run will be removed. If you don't want to remove the simulator generated files, use the\n\
+-noclean_files switch.\n\n\
+[-noclean_files] -- Reset previous run, but do not remove simulator generated files from the previous run.\n\n"
+ echo -e $msg
+ exit 1
+}
+
+# Launch script
+run $1 $2
diff --git a/game.ip_user_files/sim_scripts/clk_wiz_1/vcs/file_info.txt b/game.ip_user_files/sim_scripts/clk_wiz_1/vcs/file_info.txt
new file mode 100644
index 0000000000000000000000000000000000000000..1ead46294a6b3acba3055d40c9e081ce12d0e9c1
--- /dev/null
+++ b/game.ip_user_files/sim_scripts/clk_wiz_1/vcs/file_info.txt
@@ -0,0 +1,3 @@
+xpm_cdc.sv,systemverilog,xpm,../../../opt/Xilinx/Vivado/2022.2/data/ip/xpm/xpm_cdc/hdl/xpm_cdc.sv,incdir="../../../../game.gen/sources_1/ip/clk_wiz_1"
+xpm_VCOMP.vhd,vhdl,xpm,../../../opt/Xilinx/Vivado/2022.2/data/ip/xpm/xpm_VCOMP.vhd,incdir="../../../../game.gen/sources_1/ip/clk_wiz_1"
+glbl.v,Verilog,xil_defaultlib,glbl.v
diff --git a/game.ip_user_files/sim_scripts/clk_wiz_1/vcs/glbl.v b/game.ip_user_files/sim_scripts/clk_wiz_1/vcs/glbl.v
new file mode 100644
index 0000000000000000000000000000000000000000..ed3b249ceef65a0d1b42790def9ee8179363679c
--- /dev/null
+++ b/game.ip_user_files/sim_scripts/clk_wiz_1/vcs/glbl.v
@@ -0,0 +1,84 @@
+// $Header: /devl/xcs/repo/env/Databases/CAEInterfaces/verunilibs/data/glbl.v,v 1.14 2010/10/28 20:44:00 fphillip Exp $
+`ifndef GLBL
+`define GLBL
+`timescale 1 ps / 1 ps
+
+module glbl ();
+
+ parameter ROC_WIDTH = 100000;
+ parameter TOC_WIDTH = 0;
+ parameter GRES_WIDTH = 10000;
+ parameter GRES_START = 10000;
+
+//-------- STARTUP Globals --------------
+ wire GSR;
+ wire GTS;
+ wire GWE;
+ wire PRLD;
+ wire GRESTORE;
+ tri1 p_up_tmp;
+ tri (weak1, strong0) PLL_LOCKG = p_up_tmp;
+
+ wire PROGB_GLBL;
+ wire CCLKO_GLBL;
+ wire FCSBO_GLBL;
+ wire [3:0] DO_GLBL;
+ wire [3:0] DI_GLBL;
+
+ reg GSR_int;
+ reg GTS_int;
+ reg PRLD_int;
+ reg GRESTORE_int;
+
+//-------- JTAG Globals --------------
+ wire JTAG_TDO_GLBL;
+ wire JTAG_TCK_GLBL;
+ wire JTAG_TDI_GLBL;
+ wire JTAG_TMS_GLBL;
+ wire JTAG_TRST_GLBL;
+
+ reg JTAG_CAPTURE_GLBL;
+ reg JTAG_RESET_GLBL;
+ reg JTAG_SHIFT_GLBL;
+ reg JTAG_UPDATE_GLBL;
+ reg JTAG_RUNTEST_GLBL;
+
+ reg JTAG_SEL1_GLBL = 0;
+ reg JTAG_SEL2_GLBL = 0 ;
+ reg JTAG_SEL3_GLBL = 0;
+ reg JTAG_SEL4_GLBL = 0;
+
+ reg JTAG_USER_TDO1_GLBL = 1'bz;
+ reg JTAG_USER_TDO2_GLBL = 1'bz;
+ reg JTAG_USER_TDO3_GLBL = 1'bz;
+ reg JTAG_USER_TDO4_GLBL = 1'bz;
+
+ assign (strong1, weak0) GSR = GSR_int;
+ assign (strong1, weak0) GTS = GTS_int;
+ assign (weak1, weak0) PRLD = PRLD_int;
+ assign (strong1, weak0) GRESTORE = GRESTORE_int;
+
+ initial begin
+ GSR_int = 1'b1;
+ PRLD_int = 1'b1;
+ #(ROC_WIDTH)
+ GSR_int = 1'b0;
+ PRLD_int = 1'b0;
+ end
+
+ initial begin
+ GTS_int = 1'b1;
+ #(TOC_WIDTH)
+ GTS_int = 1'b0;
+ end
+
+ initial begin
+ GRESTORE_int = 1'b0;
+ #(GRES_START);
+ GRESTORE_int = 1'b1;
+ #(GRES_WIDTH);
+ GRESTORE_int = 1'b0;
+ end
+
+endmodule
+`endif
diff --git a/game.ip_user_files/sim_scripts/clk_wiz_1/vcs/simulate.do b/game.ip_user_files/sim_scripts/clk_wiz_1/vcs/simulate.do
new file mode 100644
index 0000000000000000000000000000000000000000..b77c6f13cc6afd61d4290ba7e26ed1b021638b31
--- /dev/null
+++ b/game.ip_user_files/sim_scripts/clk_wiz_1/vcs/simulate.do
@@ -0,0 +1,2 @@
+run 1000ns
+quit
diff --git a/game.ip_user_files/sim_scripts/clk_wiz_1/xcelium/README.txt b/game.ip_user_files/sim_scripts/clk_wiz_1/xcelium/README.txt
new file mode 100644
index 0000000000000000000000000000000000000000..bbfd6b9627706d077aaa470d8faab9df945481d4
--- /dev/null
+++ b/game.ip_user_files/sim_scripts/clk_wiz_1/xcelium/README.txt
@@ -0,0 +1,48 @@
+################################################################################
+# Vivado (TM) v2022.2 (64-bit)
+#
+# README.txt: Please read the sections below to understand the steps required to
+# run the exported script and information about the source files.
+#
+# Generated by export_simulation on Mon Feb 27 12:44:43 CET 2023
+#
+################################################################################
+
+1. How to run the generated simulation script:-
+
+From the shell prompt in the current directory, issue the following command:-
+
+./clk_wiz_1.sh
+
+This command will launch the 'execute' function for the single-step flow. This
+function is called from the main 'run' function in the script file.
+
+The 'run' function first executes the 'setup' function, the purpose of which is to
+create simulator specific setup files, create design library mappings and library
+directories and copy 'glbl.v' from the Vivado software install location into the
+current directory.
+
+The 'setup' function is also used for removing the simulator generated data in
+order to reset the current directory to the original state when export_simulation
+was launched from Vivado. This generated data can be removed by specifying the
+'-reset_run' switch to the './clk_wiz_1.sh' script.
+
+./clk_wiz_1.sh -reset_run
+
+To keep the generated data from the previous run but regenerate the setup files and
+library directories, use the '-noclean_files' switch.
+
+./clk_wiz_1.sh -noclean_files
+
+For more information on the script, please type './clk_wiz_1.sh -help'.
+
+2. Additional design information files:-
+
+export_simulation generates following additional file that can be used for fetching
+the design files information or for integrating with external custom scripts.
+
+Name : file_info.txt
+Purpose: This file contains detail design file information based on the compile order
+ when export_simulation was executed from Vivado. The file contains information
+ about the file type, name, whether it is part of the IP, associated library
+ and the file path information.
diff --git a/game.ip_user_files/sim_scripts/clk_wiz_1/xcelium/clk_wiz_1.sh b/game.ip_user_files/sim_scripts/clk_wiz_1/xcelium/clk_wiz_1.sh
new file mode 100755
index 0000000000000000000000000000000000000000..ca5ad3122d5bad6b51351db6d37f6d5d75003d9b
--- /dev/null
+++ b/game.ip_user_files/sim_scripts/clk_wiz_1/xcelium/clk_wiz_1.sh
@@ -0,0 +1,176 @@
+#!/bin/bash -f
+#*********************************************************************************************************
+# Vivado (TM) v2022.2 (64-bit)
+#
+# Filename : clk_wiz_1.sh
+# Simulator : Cadence Xcelium Parallel Simulator
+# Description : Simulation script for compiling, elaborating and verifying the project source files.
+# The script will automatically create the design libraries sub-directories in the run
+# directory, add the library logical mappings in the simulator setup file, create default
+# 'do/prj' file, execute compilation, elaboration and simulation steps.
+#
+# Generated by Vivado on Mon Feb 27 12:44:43 CET 2023
+# SW Build 3671981 on Fri Oct 14 04:59:54 MDT 2022
+#
+# Tool Version Limit: 2022.10
+#
+# usage: clk_wiz_1.sh [-help]
+# usage: clk_wiz_1.sh [-lib_map_path]
+# usage: clk_wiz_1.sh [-noclean_files]
+# usage: clk_wiz_1.sh [-reset_run]
+#
+# Prerequisite:- To compile and run simulation, you must compile the Xilinx simulation libraries using the
+# 'compile_simlib' TCL command. For more information about this command, run 'compile_simlib -help' in the
+# Vivado Tcl Shell. Once the libraries have been compiled successfully, specify the -lib_map_path switch
+# that points to these libraries and rerun export_simulation. For more information about this switch please
+# type 'export_simulation -help' in the Tcl shell.
+#
+# You can also point to the simulation libraries by either replacing the <SPECIFY_COMPILED_LIB_PATH> in this
+# script with the compiled library directory path or specify this path with the '-lib_map_path' switch when
+# executing this script. Please type 'clk_wiz_1.sh -help' for more information.
+#
+# Additional references - 'Xilinx Vivado Design Suite User Guide:Logic simulation (UG900)'
+#
+#*********************************************************************************************************
+
+# Directory path for design sources and include directories (if any) wrt this path
+ref_dir="."
+
+# Override directory with 'export_sim_ref_dir' env path value if set in the shell
+if [[ (! -z "$export_sim_ref_dir") && ($export_sim_ref_dir != "") ]]; then
+ ref_dir="$export_sim_ref_dir"
+fi
+
+# Set the compiled library directory path
+ref_lib_dir="."
+
+# Set xrun options
+xrun_opts="-64bit -v93 -relax -access +rwc -namemap_mixgen "
+
+# Design libraries
+design_libs=(simprims_ver xpm)
+
+# Simulation root library directory
+sim_lib_dir="xcelium_lib"
+
+# Script info
+echo -e "clk_wiz_1.sh - Script generated by export_simulation (Vivado v2022.2 (64-bit)-id)\n"
+
+# Main steps
+run()
+{
+ check_args $# $1
+ setup $1 $2
+ execute
+}
+
+# RUN_STEP: <execute>
+execute()
+{
+ xrun $xrun_opts \
+ -reflib "$ref_lib_dir/unisim:unisim" \
+ -reflib "$ref_lib_dir/unisims_ver:unisims_ver" \
+ -reflib "$ref_lib_dir/secureip:secureip" \
+ -reflib "$ref_lib_dir/unimacro:unimacro" \
+ -reflib "$ref_lib_dir/unimacro_ver:unimacro_ver" \
+ -top xil_defaultlib.clk_wiz_1 \
+ -f run.f \
+ -top glbl \
+ +incdir+"../../../../game.gen/sources_1/ip/clk_wiz_1" \
+ -input simulate.do
+}
+
+# STEP: setup
+setup()
+{
+ case $1 in
+ "-lib_map_path" )
+ if [[ ($2 == "") ]]; then
+ echo -e "ERROR: Simulation library directory path not specified (type \"./clk_wiz_1.sh -help\" for more information)\n"
+ exit 1
+ else
+ ref_lib_dir=$2
+ fi
+ ;;
+ "-reset_run" )
+ reset_run
+ echo -e "INFO: Simulation run files deleted.\n"
+ exit 0
+ ;;
+ "-noclean_files" )
+ # do not remove previous data
+ ;;
+ * )
+ esac
+
+ create_lib_dir
+
+ # Add any setup/initialization commands here:-
+
+ # <user specific commands>
+
+}
+
+# Create design library directory paths
+create_lib_dir()
+{
+ if [[ -e $sim_lib_dir ]]; then
+ rm -rf $sim_lib_dir
+ fi
+
+ for (( i=0; i<${#design_libs[*]}; i++ )); do
+ lib="${design_libs[i]}"
+ lib_dir="$sim_lib_dir/$lib"
+ if [[ ! -e $lib_dir ]]; then
+ mkdir -p $lib_dir
+ fi
+ done
+}
+
+# Delete generated data from the previous run
+reset_run()
+{
+ files_to_remove=(xmsim.key xrun.key xrun.log waves.shm xrun.history .simvision xcelium.d xcelium)
+ for (( i=0; i<${#files_to_remove[*]}; i++ )); do
+ file="${files_to_remove[i]}"
+ if [[ -e $file ]]; then
+ rm -rf $file
+ fi
+ done
+
+ create_lib_dir
+}
+
+# Check command line arguments
+check_args()
+{
+ if [[ ($1 == 1 ) && ($2 != "-lib_map_path" && $2 != "-noclean_files" && $2 != "-reset_run" && $2 != "-help" && $2 != "-h") ]]; then
+ echo -e "ERROR: Unknown option specified '$2' (type \"./clk_wiz_1.sh -help\" for more information)\n"
+ exit 1
+ fi
+
+ if [[ ($2 == "-help" || $2 == "-h") ]]; then
+ usage
+ fi
+}
+
+# Script usage
+usage()
+{
+ msg="Usage: clk_wiz_1.sh [-help]\n\
+Usage: clk_wiz_1.sh [-lib_map_path]\n\
+Usage: clk_wiz_1.sh [-reset_run]\n\
+Usage: clk_wiz_1.sh [-noclean_files]\n\n\
+[-help] -- Print help information for this script\n\n\
+[-lib_map_path <path>] -- Compiled simulation library directory path. The simulation library is compiled\n\
+using the compile_simlib tcl command. Please see 'compile_simlib -help' for more information.\n\n\
+[-reset_run] -- Recreate simulator setup files and library mappings for a clean run. The generated files\n\
+from the previous run will be removed. If you don't want to remove the simulator generated files, use the\n\
+-noclean_files switch.\n\n\
+[-noclean_files] -- Reset previous run, but do not remove simulator generated files from the previous run.\n\n"
+ echo -e $msg
+ exit 1
+}
+
+# Launch script
+run $1 $2
diff --git a/game.ip_user_files/sim_scripts/clk_wiz_1/xcelium/file_info.txt b/game.ip_user_files/sim_scripts/clk_wiz_1/xcelium/file_info.txt
new file mode 100644
index 0000000000000000000000000000000000000000..1ead46294a6b3acba3055d40c9e081ce12d0e9c1
--- /dev/null
+++ b/game.ip_user_files/sim_scripts/clk_wiz_1/xcelium/file_info.txt
@@ -0,0 +1,3 @@
+xpm_cdc.sv,systemverilog,xpm,../../../opt/Xilinx/Vivado/2022.2/data/ip/xpm/xpm_cdc/hdl/xpm_cdc.sv,incdir="../../../../game.gen/sources_1/ip/clk_wiz_1"
+xpm_VCOMP.vhd,vhdl,xpm,../../../opt/Xilinx/Vivado/2022.2/data/ip/xpm/xpm_VCOMP.vhd,incdir="../../../../game.gen/sources_1/ip/clk_wiz_1"
+glbl.v,Verilog,xil_defaultlib,glbl.v
diff --git a/game.ip_user_files/sim_scripts/clk_wiz_1/xcelium/glbl.v b/game.ip_user_files/sim_scripts/clk_wiz_1/xcelium/glbl.v
new file mode 100644
index 0000000000000000000000000000000000000000..ed3b249ceef65a0d1b42790def9ee8179363679c
--- /dev/null
+++ b/game.ip_user_files/sim_scripts/clk_wiz_1/xcelium/glbl.v
@@ -0,0 +1,84 @@
+// $Header: /devl/xcs/repo/env/Databases/CAEInterfaces/verunilibs/data/glbl.v,v 1.14 2010/10/28 20:44:00 fphillip Exp $
+`ifndef GLBL
+`define GLBL
+`timescale 1 ps / 1 ps
+
+module glbl ();
+
+ parameter ROC_WIDTH = 100000;
+ parameter TOC_WIDTH = 0;
+ parameter GRES_WIDTH = 10000;
+ parameter GRES_START = 10000;
+
+//-------- STARTUP Globals --------------
+ wire GSR;
+ wire GTS;
+ wire GWE;
+ wire PRLD;
+ wire GRESTORE;
+ tri1 p_up_tmp;
+ tri (weak1, strong0) PLL_LOCKG = p_up_tmp;
+
+ wire PROGB_GLBL;
+ wire CCLKO_GLBL;
+ wire FCSBO_GLBL;
+ wire [3:0] DO_GLBL;
+ wire [3:0] DI_GLBL;
+
+ reg GSR_int;
+ reg GTS_int;
+ reg PRLD_int;
+ reg GRESTORE_int;
+
+//-------- JTAG Globals --------------
+ wire JTAG_TDO_GLBL;
+ wire JTAG_TCK_GLBL;
+ wire JTAG_TDI_GLBL;
+ wire JTAG_TMS_GLBL;
+ wire JTAG_TRST_GLBL;
+
+ reg JTAG_CAPTURE_GLBL;
+ reg JTAG_RESET_GLBL;
+ reg JTAG_SHIFT_GLBL;
+ reg JTAG_UPDATE_GLBL;
+ reg JTAG_RUNTEST_GLBL;
+
+ reg JTAG_SEL1_GLBL = 0;
+ reg JTAG_SEL2_GLBL = 0 ;
+ reg JTAG_SEL3_GLBL = 0;
+ reg JTAG_SEL4_GLBL = 0;
+
+ reg JTAG_USER_TDO1_GLBL = 1'bz;
+ reg JTAG_USER_TDO2_GLBL = 1'bz;
+ reg JTAG_USER_TDO3_GLBL = 1'bz;
+ reg JTAG_USER_TDO4_GLBL = 1'bz;
+
+ assign (strong1, weak0) GSR = GSR_int;
+ assign (strong1, weak0) GTS = GTS_int;
+ assign (weak1, weak0) PRLD = PRLD_int;
+ assign (strong1, weak0) GRESTORE = GRESTORE_int;
+
+ initial begin
+ GSR_int = 1'b1;
+ PRLD_int = 1'b1;
+ #(ROC_WIDTH)
+ GSR_int = 1'b0;
+ PRLD_int = 1'b0;
+ end
+
+ initial begin
+ GTS_int = 1'b1;
+ #(TOC_WIDTH)
+ GTS_int = 1'b0;
+ end
+
+ initial begin
+ GRESTORE_int = 1'b0;
+ #(GRES_START);
+ GRESTORE_int = 1'b1;
+ #(GRES_WIDTH);
+ GRESTORE_int = 1'b0;
+ end
+
+endmodule
+`endif
diff --git a/game.ip_user_files/sim_scripts/clk_wiz_1/xcelium/run.f b/game.ip_user_files/sim_scripts/clk_wiz_1/xcelium/run.f
new file mode 100644
index 0000000000000000000000000000000000000000..7998e87504659e7ae744a65af061adfb940303c8
--- /dev/null
+++ b/game.ip_user_files/sim_scripts/clk_wiz_1/xcelium/run.f
@@ -0,0 +1,10 @@
+-makelib xcelium_lib/xpm -sv \
+ "/opt/Xilinx/Vivado/2022.2/data/ip/xpm/xpm_cdc/hdl/xpm_cdc.sv" \
+-endlib
+-makelib xcelium_lib/xpm \
+ "/opt/Xilinx/Vivado/2022.2/data/ip/xpm/xpm_VCOMP.vhd" \
+-endlib
+-makelib xcelium_lib/xil_defaultlib \
+ glbl.v
+-endlib
+
diff --git a/game.ip_user_files/sim_scripts/clk_wiz_1/xcelium/simulate.do b/game.ip_user_files/sim_scripts/clk_wiz_1/xcelium/simulate.do
new file mode 100644
index 0000000000000000000000000000000000000000..fb6d1f776970ca90fb0a9d24505e9f1691a90d27
--- /dev/null
+++ b/game.ip_user_files/sim_scripts/clk_wiz_1/xcelium/simulate.do
@@ -0,0 +1,2 @@
+run 1000ns
+exit
diff --git a/game.ip_user_files/sim_scripts/clk_wiz_1/xsim/README.txt b/game.ip_user_files/sim_scripts/clk_wiz_1/xsim/README.txt
new file mode 100644
index 0000000000000000000000000000000000000000..5895c5dd4ec54313cde5d4a854b86a0eb2180232
--- /dev/null
+++ b/game.ip_user_files/sim_scripts/clk_wiz_1/xsim/README.txt
@@ -0,0 +1,49 @@
+################################################################################
+# Vivado (TM) v2022.2 (64-bit)
+#
+# README.txt: Please read the sections below to understand the steps required to
+# run the exported script and information about the source files.
+#
+# Generated by export_simulation on Mon Feb 27 12:44:43 CET 2023
+#
+################################################################################
+
+1. How to run the generated simulation script:-
+
+From the shell prompt in the current directory, issue the following command:-
+
+./clk_wiz_1.sh
+
+This command will launch the 'compile', 'elaborate' and 'simulate' functions
+implemented in the script file for the 3-step flow. These functions are called
+from the main 'run' function in the script file.
+
+The 'run' function first executes the 'setup' function, the purpose of which is to
+create simulator specific setup files, create design library mappings and library
+directories and copy 'glbl.v' from the Vivado software install location into the
+current directory.
+
+The 'setup' function is also used for removing the simulator generated data in
+order to reset the current directory to the original state when export_simulation
+was launched from Vivado. This generated data can be removed by specifying the
+'-reset_run' switch to the './clk_wiz_1.sh' script.
+
+./clk_wiz_1.sh -reset_run
+
+To keep the generated data from the previous run but regenerate the setup files and
+library directories, use the '-noclean_files' switch.
+
+./clk_wiz_1.sh -noclean_files
+
+For more information on the script, please type './clk_wiz_1.sh -help'.
+
+2. Additional design information files:-
+
+export_simulation generates following additional file that can be used for fetching
+the design files information or for integrating with external custom scripts.
+
+Name : file_info.txt
+Purpose: This file contains detail design file information based on the compile order
+ when export_simulation was executed from Vivado. The file contains information
+ about the file type, name, whether it is part of the IP, associated library
+ and the file path information.
diff --git a/game.ip_user_files/sim_scripts/clk_wiz_1/xsim/clk_wiz_1.sh b/game.ip_user_files/sim_scripts/clk_wiz_1/xsim/clk_wiz_1.sh
new file mode 100755
index 0000000000000000000000000000000000000000..b4aa5feb7143498d0f3129f8c59f0f8c8c72e2b1
--- /dev/null
+++ b/game.ip_user_files/sim_scripts/clk_wiz_1/xsim/clk_wiz_1.sh
@@ -0,0 +1,212 @@
+#!/bin/bash -f
+#*********************************************************************************************************
+# Vivado (TM) v2022.2 (64-bit)
+#
+# Filename : clk_wiz_1.sh
+# Simulator : Xilinx Vivado Simulator
+# Description : Simulation script for compiling, elaborating and verifying the project source files.
+# The script will automatically create the design libraries sub-directories in the run
+# directory, add the library logical mappings in the simulator setup file, create default
+# 'do/prj' file, execute compilation, elaboration and simulation steps.
+#
+# Generated by Vivado on Mon Feb 27 12:44:43 CET 2023
+# SW Build 3671981 on Fri Oct 14 04:59:54 MDT 2022
+#
+# Tool Version Limit: 2022.10
+#
+# usage: clk_wiz_1.sh [-help]
+# usage: clk_wiz_1.sh [-lib_map_path]
+# usage: clk_wiz_1.sh [-noclean_files]
+# usage: clk_wiz_1.sh [-reset_run]
+#
+#*********************************************************************************************************
+
+# Set xvlog options
+xvlog_opts="--incr --relax "
+
+# Script info
+echo -e "clk_wiz_1.sh - Script generated by export_simulation (Vivado v2022.2 (64-bit)-id)\n"
+
+# Main steps
+run()
+{
+ check_args $# $1
+ setup $1 $2
+ compile
+ elaborate
+ simulate
+}
+
+# RUN_STEP: <compile>
+compile()
+{
+ # None (no simulation source files found)
+ echo -e "INFO: No simulation source file(s) to compile\n"
+ exit 0
+}
+# RUN_STEP: <elaborate>
+elaborate()
+{
+# None (no sources present)
+# RUN_STEP: <simulate>
+simulate()
+{
+# None (no sources present)
+# STEP: setup
+setup()
+{
+ case $1 in
+ "-lib_map_path" )
+ if [[ ($2 == "") ]]; then
+ echo -e "ERROR: Simulation library directory path not specified (type \"./clk_wiz_1.sh -help\" for more information)\n"
+ exit 1
+ fi
+ copy_setup_file $2
+ ;;
+ "-reset_run" )
+ reset_run
+ echo -e "INFO: Simulation run files deleted.\n"
+ exit 0
+ ;;
+ "-noclean_files" )
+ # do not remove previous data
+ ;;
+ * )
+ copy_setup_file $2
+ esac
+
+ # Add any setup/initialization commands here:-
+
+ # <user specific commands>
+
+}
+
+# Copy xsim.ini file
+copy_setup_file()
+{
+ file="xsim.ini"
+ lib_map_path="/opt/Xilinx/Vivado/2022.2/data/xsim"
+ if [[ ($1 != "") ]]; then
+ lib_map_path="$1"
+ fi
+ if [[ ($lib_map_path != "") ]]; then
+ src_file="$lib_map_path/$file"
+ if [[ -e $src_file ]]; then
+ cp $src_file .
+ fi
+
+ # Map local design libraries to xsim.ini
+ map_local_libs
+
+ fi
+}
+
+# Map local design libraries
+map_local_libs()
+{
+ updated_mappings=()
+ local_mappings=()
+
+ # Local design libraries
+ local_libs=()
+
+ if [[ 0 == ${#local_libs[@]} ]]; then
+ return
+ fi
+
+ file="xsim.ini"
+ file_backup="xsim.ini.bak"
+
+ if [[ -e $file ]]; then
+ rm -f $file_backup
+
+ # Create a backup copy of the xsim.ini file
+ cp $file $file_backup
+
+ # Read libraries from backup file and search in local library collection
+ while read -r line
+ do
+ IN=$line
+
+ # Split mapping entry with '=' delimiter to fetch library name and mapping
+ read lib_name mapping <<<$(IFS="="; echo $IN)
+
+ # If local library found, then construct the local mapping and add to local mapping collection
+ if `echo ${local_libs[@]} | grep -wq $lib_name` ; then
+ line="$lib_name=xsim.dir/$lib_name"
+ local_mappings+=("$lib_name")
+ fi
+
+ # Add to updated library mapping collection
+ updated_mappings+=("$line")
+ done < "$file_backup"
+
+ # Append local libraries not found originally from xsim.ini
+ for (( i=0; i<${#local_libs[*]}; i++ )); do
+ lib_name="${local_libs[i]}"
+ if `echo ${local_mappings[@]} | grep -wvq $lib_name` ; then
+ line="$lib_name=xsim.dir/$lib_name"
+ updated_mappings+=("$line")
+ fi
+ done
+
+ # Write updated mappings in xsim.ini
+ rm -f $file
+ for (( i=0; i<${#updated_mappings[*]}; i++ )); do
+ lib_name="${updated_mappings[i]}"
+ echo $lib_name >> $file
+ done
+ else
+ for (( i=0; i<${#local_libs[*]}; i++ )); do
+ lib_name="${local_libs[i]}"
+ mapping="$lib_name=xsim.dir/$lib_name"
+ echo $mapping >> $file
+ done
+ fi
+}
+
+# Delete generated data from the previous run
+reset_run()
+{
+ files_to_remove=(xelab.pb xsim.jou xvhdl.log xvlog.log compile.log elaborate.log simulate.log xelab.log xsim.log run.log xvhdl.pb xvlog.pb clk_wiz_1.wdb xsim.dir)
+ for (( i=0; i<${#files_to_remove[*]}; i++ )); do
+ file="${files_to_remove[i]}"
+ if [[ -e $file ]]; then
+ rm -rf $file
+ fi
+ done
+}
+
+# Check command line arguments
+check_args()
+{
+ if [[ ($1 == 1 ) && ($2 != "-lib_map_path" && $2 != "-noclean_files" && $2 != "-reset_run" && $2 != "-help" && $2 != "-h") ]]; then
+ echo -e "ERROR: Unknown option specified '$2' (type \"./clk_wiz_1.sh -help\" for more information)\n"
+ exit 1
+ fi
+
+ if [[ ($2 == "-help" || $2 == "-h") ]]; then
+ usage
+ fi
+}
+
+# Script usage
+usage()
+{
+ msg="Usage: clk_wiz_1.sh [-help]\n\
+Usage: clk_wiz_1.sh [-lib_map_path]\n\
+Usage: clk_wiz_1.sh [-reset_run]\n\
+Usage: clk_wiz_1.sh [-noclean_files]\n\n\
+[-help] -- Print help information for this script\n\n\
+[-lib_map_path <path>] -- Compiled simulation library directory path. The simulation library is compiled\n\
+using the compile_simlib tcl command. Please see 'compile_simlib -help' for more information.\n\n\
+[-reset_run] -- Recreate simulator setup files and library mappings for a clean run. The generated files\n\
+from the previous run will be removed. If you don't want to remove the simulator generated files, use the\n\
+-noclean_files switch.\n\n\
+[-noclean_files] -- Reset previous run, but do not remove simulator generated files from the previous run.\n\n"
+ echo -e $msg
+ exit 1
+}
+
+# Launch script
+run $1 $2
diff --git a/game.ip_user_files/sim_scripts/clk_wiz_1/xsim/file_info.txt b/game.ip_user_files/sim_scripts/clk_wiz_1/xsim/file_info.txt
new file mode 100644
index 0000000000000000000000000000000000000000..38264b9c9dc00d362234abde03fa0572c43198a4
--- /dev/null
+++ b/game.ip_user_files/sim_scripts/clk_wiz_1/xsim/file_info.txt
@@ -0,0 +1 @@
+glbl.v,Verilog,xil_defaultlib,glbl.v
diff --git a/game.ip_user_files/sim_scripts/clk_wiz_1/xsim/glbl.v b/game.ip_user_files/sim_scripts/clk_wiz_1/xsim/glbl.v
new file mode 100644
index 0000000000000000000000000000000000000000..ed3b249ceef65a0d1b42790def9ee8179363679c
--- /dev/null
+++ b/game.ip_user_files/sim_scripts/clk_wiz_1/xsim/glbl.v
@@ -0,0 +1,84 @@
+// $Header: /devl/xcs/repo/env/Databases/CAEInterfaces/verunilibs/data/glbl.v,v 1.14 2010/10/28 20:44:00 fphillip Exp $
+`ifndef GLBL
+`define GLBL
+`timescale 1 ps / 1 ps
+
+module glbl ();
+
+ parameter ROC_WIDTH = 100000;
+ parameter TOC_WIDTH = 0;
+ parameter GRES_WIDTH = 10000;
+ parameter GRES_START = 10000;
+
+//-------- STARTUP Globals --------------
+ wire GSR;
+ wire GTS;
+ wire GWE;
+ wire PRLD;
+ wire GRESTORE;
+ tri1 p_up_tmp;
+ tri (weak1, strong0) PLL_LOCKG = p_up_tmp;
+
+ wire PROGB_GLBL;
+ wire CCLKO_GLBL;
+ wire FCSBO_GLBL;
+ wire [3:0] DO_GLBL;
+ wire [3:0] DI_GLBL;
+
+ reg GSR_int;
+ reg GTS_int;
+ reg PRLD_int;
+ reg GRESTORE_int;
+
+//-------- JTAG Globals --------------
+ wire JTAG_TDO_GLBL;
+ wire JTAG_TCK_GLBL;
+ wire JTAG_TDI_GLBL;
+ wire JTAG_TMS_GLBL;
+ wire JTAG_TRST_GLBL;
+
+ reg JTAG_CAPTURE_GLBL;
+ reg JTAG_RESET_GLBL;
+ reg JTAG_SHIFT_GLBL;
+ reg JTAG_UPDATE_GLBL;
+ reg JTAG_RUNTEST_GLBL;
+
+ reg JTAG_SEL1_GLBL = 0;
+ reg JTAG_SEL2_GLBL = 0 ;
+ reg JTAG_SEL3_GLBL = 0;
+ reg JTAG_SEL4_GLBL = 0;
+
+ reg JTAG_USER_TDO1_GLBL = 1'bz;
+ reg JTAG_USER_TDO2_GLBL = 1'bz;
+ reg JTAG_USER_TDO3_GLBL = 1'bz;
+ reg JTAG_USER_TDO4_GLBL = 1'bz;
+
+ assign (strong1, weak0) GSR = GSR_int;
+ assign (strong1, weak0) GTS = GTS_int;
+ assign (weak1, weak0) PRLD = PRLD_int;
+ assign (strong1, weak0) GRESTORE = GRESTORE_int;
+
+ initial begin
+ GSR_int = 1'b1;
+ PRLD_int = 1'b1;
+ #(ROC_WIDTH)
+ GSR_int = 1'b0;
+ PRLD_int = 1'b0;
+ end
+
+ initial begin
+ GTS_int = 1'b1;
+ #(TOC_WIDTH)
+ GTS_int = 1'b0;
+ end
+
+ initial begin
+ GRESTORE_int = 1'b0;
+ #(GRES_START);
+ GRESTORE_int = 1'b1;
+ #(GRES_WIDTH);
+ GRESTORE_int = 1'b0;
+ end
+
+endmodule
+`endif
diff --git a/game.runs/.jobs/vrs_config_1.xml b/game.runs/.jobs/vrs_config_1.xml
new file mode 100644
index 0000000000000000000000000000000000000000..7e60f1f65445c98646aa5efef04a0ee89a3436eb
--- /dev/null
+++ b/game.runs/.jobs/vrs_config_1.xml
@@ -0,0 +1,9 @@
+<?xml version="1.0"?>
+<Runs Version="1" Minor="0">
+ <Run Id="clk_wiz_0_synth_1" LaunchDir="/home/prasic/game/game.runs/clk_wiz_0_synth_1" FlowId="Vivado_Synthesis" FromStepId="vivado" ToStepId="vivado"/>
+ <Parameters>
+ <Parameter Name="runs.monitorLSFJobs" Val="true" Type="bool"/>
+ <Parameter Name="runs.enableClusterConf" Val="true" Type="bool"/>
+ </Parameters>
+</Runs>
+
diff --git a/game.runs/.jobs/vrs_config_10.xml b/game.runs/.jobs/vrs_config_10.xml
new file mode 100644
index 0000000000000000000000000000000000000000..4d1886932883f856f240372afb5739d423832984
--- /dev/null
+++ b/game.runs/.jobs/vrs_config_10.xml
@@ -0,0 +1,12 @@
+<?xml version="1.0"?>
+<Runs Version="1" Minor="0">
+ <Run Id="synth_1" LaunchDir="/home/prasic/game/game.runs/synth_1" FlowId="Vivado_Synthesis" FromStepId="vivado" ToStepId="vivado"/>
+ <Run Id="impl_1" LaunchDir="/home/prasic/game/game.runs/impl_1" FlowId="Vivado_Implementation" FromStepId="init_design" ToStepId="write_bitstream">
+ <Parent Id="synth_1"/>
+ </Run>
+ <Parameters>
+ <Parameter Name="runs.monitorLSFJobs" Val="true" Type="bool"/>
+ <Parameter Name="runs.enableClusterConf" Val="true" Type="bool"/>
+ </Parameters>
+</Runs>
+
diff --git a/game.runs/.jobs/vrs_config_11.xml b/game.runs/.jobs/vrs_config_11.xml
new file mode 100644
index 0000000000000000000000000000000000000000..4d1886932883f856f240372afb5739d423832984
--- /dev/null
+++ b/game.runs/.jobs/vrs_config_11.xml
@@ -0,0 +1,12 @@
+<?xml version="1.0"?>
+<Runs Version="1" Minor="0">
+ <Run Id="synth_1" LaunchDir="/home/prasic/game/game.runs/synth_1" FlowId="Vivado_Synthesis" FromStepId="vivado" ToStepId="vivado"/>
+ <Run Id="impl_1" LaunchDir="/home/prasic/game/game.runs/impl_1" FlowId="Vivado_Implementation" FromStepId="init_design" ToStepId="write_bitstream">
+ <Parent Id="synth_1"/>
+ </Run>
+ <Parameters>
+ <Parameter Name="runs.monitorLSFJobs" Val="true" Type="bool"/>
+ <Parameter Name="runs.enableClusterConf" Val="true" Type="bool"/>
+ </Parameters>
+</Runs>
+
diff --git a/game.runs/.jobs/vrs_config_12.xml b/game.runs/.jobs/vrs_config_12.xml
new file mode 100644
index 0000000000000000000000000000000000000000..4d1886932883f856f240372afb5739d423832984
--- /dev/null
+++ b/game.runs/.jobs/vrs_config_12.xml
@@ -0,0 +1,12 @@
+<?xml version="1.0"?>
+<Runs Version="1" Minor="0">
+ <Run Id="synth_1" LaunchDir="/home/prasic/game/game.runs/synth_1" FlowId="Vivado_Synthesis" FromStepId="vivado" ToStepId="vivado"/>
+ <Run Id="impl_1" LaunchDir="/home/prasic/game/game.runs/impl_1" FlowId="Vivado_Implementation" FromStepId="init_design" ToStepId="write_bitstream">
+ <Parent Id="synth_1"/>
+ </Run>
+ <Parameters>
+ <Parameter Name="runs.monitorLSFJobs" Val="true" Type="bool"/>
+ <Parameter Name="runs.enableClusterConf" Val="true" Type="bool"/>
+ </Parameters>
+</Runs>
+
diff --git a/game.runs/.jobs/vrs_config_13.xml b/game.runs/.jobs/vrs_config_13.xml
new file mode 100644
index 0000000000000000000000000000000000000000..4d1886932883f856f240372afb5739d423832984
--- /dev/null
+++ b/game.runs/.jobs/vrs_config_13.xml
@@ -0,0 +1,12 @@
+<?xml version="1.0"?>
+<Runs Version="1" Minor="0">
+ <Run Id="synth_1" LaunchDir="/home/prasic/game/game.runs/synth_1" FlowId="Vivado_Synthesis" FromStepId="vivado" ToStepId="vivado"/>
+ <Run Id="impl_1" LaunchDir="/home/prasic/game/game.runs/impl_1" FlowId="Vivado_Implementation" FromStepId="init_design" ToStepId="write_bitstream">
+ <Parent Id="synth_1"/>
+ </Run>
+ <Parameters>
+ <Parameter Name="runs.monitorLSFJobs" Val="true" Type="bool"/>
+ <Parameter Name="runs.enableClusterConf" Val="true" Type="bool"/>
+ </Parameters>
+</Runs>
+
diff --git a/game.runs/.jobs/vrs_config_14.xml b/game.runs/.jobs/vrs_config_14.xml
new file mode 100644
index 0000000000000000000000000000000000000000..4d1886932883f856f240372afb5739d423832984
--- /dev/null
+++ b/game.runs/.jobs/vrs_config_14.xml
@@ -0,0 +1,12 @@
+<?xml version="1.0"?>
+<Runs Version="1" Minor="0">
+ <Run Id="synth_1" LaunchDir="/home/prasic/game/game.runs/synth_1" FlowId="Vivado_Synthesis" FromStepId="vivado" ToStepId="vivado"/>
+ <Run Id="impl_1" LaunchDir="/home/prasic/game/game.runs/impl_1" FlowId="Vivado_Implementation" FromStepId="init_design" ToStepId="write_bitstream">
+ <Parent Id="synth_1"/>
+ </Run>
+ <Parameters>
+ <Parameter Name="runs.monitorLSFJobs" Val="true" Type="bool"/>
+ <Parameter Name="runs.enableClusterConf" Val="true" Type="bool"/>
+ </Parameters>
+</Runs>
+
diff --git a/game.runs/.jobs/vrs_config_15.xml b/game.runs/.jobs/vrs_config_15.xml
new file mode 100644
index 0000000000000000000000000000000000000000..4d1886932883f856f240372afb5739d423832984
--- /dev/null
+++ b/game.runs/.jobs/vrs_config_15.xml
@@ -0,0 +1,12 @@
+<?xml version="1.0"?>
+<Runs Version="1" Minor="0">
+ <Run Id="synth_1" LaunchDir="/home/prasic/game/game.runs/synth_1" FlowId="Vivado_Synthesis" FromStepId="vivado" ToStepId="vivado"/>
+ <Run Id="impl_1" LaunchDir="/home/prasic/game/game.runs/impl_1" FlowId="Vivado_Implementation" FromStepId="init_design" ToStepId="write_bitstream">
+ <Parent Id="synth_1"/>
+ </Run>
+ <Parameters>
+ <Parameter Name="runs.monitorLSFJobs" Val="true" Type="bool"/>
+ <Parameter Name="runs.enableClusterConf" Val="true" Type="bool"/>
+ </Parameters>
+</Runs>
+
diff --git a/game.runs/.jobs/vrs_config_16.xml b/game.runs/.jobs/vrs_config_16.xml
new file mode 100644
index 0000000000000000000000000000000000000000..4d1886932883f856f240372afb5739d423832984
--- /dev/null
+++ b/game.runs/.jobs/vrs_config_16.xml
@@ -0,0 +1,12 @@
+<?xml version="1.0"?>
+<Runs Version="1" Minor="0">
+ <Run Id="synth_1" LaunchDir="/home/prasic/game/game.runs/synth_1" FlowId="Vivado_Synthesis" FromStepId="vivado" ToStepId="vivado"/>
+ <Run Id="impl_1" LaunchDir="/home/prasic/game/game.runs/impl_1" FlowId="Vivado_Implementation" FromStepId="init_design" ToStepId="write_bitstream">
+ <Parent Id="synth_1"/>
+ </Run>
+ <Parameters>
+ <Parameter Name="runs.monitorLSFJobs" Val="true" Type="bool"/>
+ <Parameter Name="runs.enableClusterConf" Val="true" Type="bool"/>
+ </Parameters>
+</Runs>
+
diff --git a/game.runs/.jobs/vrs_config_17.xml b/game.runs/.jobs/vrs_config_17.xml
new file mode 100644
index 0000000000000000000000000000000000000000..4d1886932883f856f240372afb5739d423832984
--- /dev/null
+++ b/game.runs/.jobs/vrs_config_17.xml
@@ -0,0 +1,12 @@
+<?xml version="1.0"?>
+<Runs Version="1" Minor="0">
+ <Run Id="synth_1" LaunchDir="/home/prasic/game/game.runs/synth_1" FlowId="Vivado_Synthesis" FromStepId="vivado" ToStepId="vivado"/>
+ <Run Id="impl_1" LaunchDir="/home/prasic/game/game.runs/impl_1" FlowId="Vivado_Implementation" FromStepId="init_design" ToStepId="write_bitstream">
+ <Parent Id="synth_1"/>
+ </Run>
+ <Parameters>
+ <Parameter Name="runs.monitorLSFJobs" Val="true" Type="bool"/>
+ <Parameter Name="runs.enableClusterConf" Val="true" Type="bool"/>
+ </Parameters>
+</Runs>
+
diff --git a/game.runs/.jobs/vrs_config_18.xml b/game.runs/.jobs/vrs_config_18.xml
new file mode 100644
index 0000000000000000000000000000000000000000..4d1886932883f856f240372afb5739d423832984
--- /dev/null
+++ b/game.runs/.jobs/vrs_config_18.xml
@@ -0,0 +1,12 @@
+<?xml version="1.0"?>
+<Runs Version="1" Minor="0">
+ <Run Id="synth_1" LaunchDir="/home/prasic/game/game.runs/synth_1" FlowId="Vivado_Synthesis" FromStepId="vivado" ToStepId="vivado"/>
+ <Run Id="impl_1" LaunchDir="/home/prasic/game/game.runs/impl_1" FlowId="Vivado_Implementation" FromStepId="init_design" ToStepId="write_bitstream">
+ <Parent Id="synth_1"/>
+ </Run>
+ <Parameters>
+ <Parameter Name="runs.monitorLSFJobs" Val="true" Type="bool"/>
+ <Parameter Name="runs.enableClusterConf" Val="true" Type="bool"/>
+ </Parameters>
+</Runs>
+
diff --git a/game.runs/.jobs/vrs_config_19.xml b/game.runs/.jobs/vrs_config_19.xml
new file mode 100644
index 0000000000000000000000000000000000000000..5bdc25d491b5a8218a6d1bd248af4c552c10a94e
--- /dev/null
+++ b/game.runs/.jobs/vrs_config_19.xml
@@ -0,0 +1,9 @@
+<?xml version="1.0"?>
+<Runs Version="1" Minor="0">
+ <Run Id="impl_1" LaunchDir="/home/prasic/game/game.runs/impl_1" FlowId="Vivado_Implementation" FromStepId="write_bitstream" ToStepId="write_bitstream"/>
+ <Parameters>
+ <Parameter Name="runs.monitorLSFJobs" Val="true" Type="bool"/>
+ <Parameter Name="runs.enableClusterConf" Val="true" Type="bool"/>
+ </Parameters>
+</Runs>
+
diff --git a/game.runs/.jobs/vrs_config_2.xml b/game.runs/.jobs/vrs_config_2.xml
new file mode 100644
index 0000000000000000000000000000000000000000..bf9e98bf01abe10267a1b82e745cc4fb4838b666
--- /dev/null
+++ b/game.runs/.jobs/vrs_config_2.xml
@@ -0,0 +1,9 @@
+<?xml version="1.0"?>
+<Runs Version="1" Minor="0">
+ <Run Id="synth_1" LaunchDir="/home/prasic/game/game.runs/synth_1" FlowId="Vivado_Synthesis" FromStepId="vivado" ToStepId="vivado"/>
+ <Parameters>
+ <Parameter Name="runs.monitorLSFJobs" Val="true" Type="bool"/>
+ <Parameter Name="runs.enableClusterConf" Val="true" Type="bool"/>
+ </Parameters>
+</Runs>
+
diff --git a/game.runs/.jobs/vrs_config_20.xml b/game.runs/.jobs/vrs_config_20.xml
new file mode 100644
index 0000000000000000000000000000000000000000..4d1886932883f856f240372afb5739d423832984
--- /dev/null
+++ b/game.runs/.jobs/vrs_config_20.xml
@@ -0,0 +1,12 @@
+<?xml version="1.0"?>
+<Runs Version="1" Minor="0">
+ <Run Id="synth_1" LaunchDir="/home/prasic/game/game.runs/synth_1" FlowId="Vivado_Synthesis" FromStepId="vivado" ToStepId="vivado"/>
+ <Run Id="impl_1" LaunchDir="/home/prasic/game/game.runs/impl_1" FlowId="Vivado_Implementation" FromStepId="init_design" ToStepId="write_bitstream">
+ <Parent Id="synth_1"/>
+ </Run>
+ <Parameters>
+ <Parameter Name="runs.monitorLSFJobs" Val="true" Type="bool"/>
+ <Parameter Name="runs.enableClusterConf" Val="true" Type="bool"/>
+ </Parameters>
+</Runs>
+
diff --git a/game.runs/.jobs/vrs_config_21.xml b/game.runs/.jobs/vrs_config_21.xml
new file mode 100644
index 0000000000000000000000000000000000000000..4d1886932883f856f240372afb5739d423832984
--- /dev/null
+++ b/game.runs/.jobs/vrs_config_21.xml
@@ -0,0 +1,12 @@
+<?xml version="1.0"?>
+<Runs Version="1" Minor="0">
+ <Run Id="synth_1" LaunchDir="/home/prasic/game/game.runs/synth_1" FlowId="Vivado_Synthesis" FromStepId="vivado" ToStepId="vivado"/>
+ <Run Id="impl_1" LaunchDir="/home/prasic/game/game.runs/impl_1" FlowId="Vivado_Implementation" FromStepId="init_design" ToStepId="write_bitstream">
+ <Parent Id="synth_1"/>
+ </Run>
+ <Parameters>
+ <Parameter Name="runs.monitorLSFJobs" Val="true" Type="bool"/>
+ <Parameter Name="runs.enableClusterConf" Val="true" Type="bool"/>
+ </Parameters>
+</Runs>
+
diff --git a/game.runs/.jobs/vrs_config_22.xml b/game.runs/.jobs/vrs_config_22.xml
new file mode 100644
index 0000000000000000000000000000000000000000..4d1886932883f856f240372afb5739d423832984
--- /dev/null
+++ b/game.runs/.jobs/vrs_config_22.xml
@@ -0,0 +1,12 @@
+<?xml version="1.0"?>
+<Runs Version="1" Minor="0">
+ <Run Id="synth_1" LaunchDir="/home/prasic/game/game.runs/synth_1" FlowId="Vivado_Synthesis" FromStepId="vivado" ToStepId="vivado"/>
+ <Run Id="impl_1" LaunchDir="/home/prasic/game/game.runs/impl_1" FlowId="Vivado_Implementation" FromStepId="init_design" ToStepId="write_bitstream">
+ <Parent Id="synth_1"/>
+ </Run>
+ <Parameters>
+ <Parameter Name="runs.monitorLSFJobs" Val="true" Type="bool"/>
+ <Parameter Name="runs.enableClusterConf" Val="true" Type="bool"/>
+ </Parameters>
+</Runs>
+
diff --git a/game.runs/.jobs/vrs_config_23.xml b/game.runs/.jobs/vrs_config_23.xml
new file mode 100644
index 0000000000000000000000000000000000000000..4d1886932883f856f240372afb5739d423832984
--- /dev/null
+++ b/game.runs/.jobs/vrs_config_23.xml
@@ -0,0 +1,12 @@
+<?xml version="1.0"?>
+<Runs Version="1" Minor="0">
+ <Run Id="synth_1" LaunchDir="/home/prasic/game/game.runs/synth_1" FlowId="Vivado_Synthesis" FromStepId="vivado" ToStepId="vivado"/>
+ <Run Id="impl_1" LaunchDir="/home/prasic/game/game.runs/impl_1" FlowId="Vivado_Implementation" FromStepId="init_design" ToStepId="write_bitstream">
+ <Parent Id="synth_1"/>
+ </Run>
+ <Parameters>
+ <Parameter Name="runs.monitorLSFJobs" Val="true" Type="bool"/>
+ <Parameter Name="runs.enableClusterConf" Val="true" Type="bool"/>
+ </Parameters>
+</Runs>
+
diff --git a/game.runs/.jobs/vrs_config_24.xml b/game.runs/.jobs/vrs_config_24.xml
new file mode 100644
index 0000000000000000000000000000000000000000..4d1886932883f856f240372afb5739d423832984
--- /dev/null
+++ b/game.runs/.jobs/vrs_config_24.xml
@@ -0,0 +1,12 @@
+<?xml version="1.0"?>
+<Runs Version="1" Minor="0">
+ <Run Id="synth_1" LaunchDir="/home/prasic/game/game.runs/synth_1" FlowId="Vivado_Synthesis" FromStepId="vivado" ToStepId="vivado"/>
+ <Run Id="impl_1" LaunchDir="/home/prasic/game/game.runs/impl_1" FlowId="Vivado_Implementation" FromStepId="init_design" ToStepId="write_bitstream">
+ <Parent Id="synth_1"/>
+ </Run>
+ <Parameters>
+ <Parameter Name="runs.monitorLSFJobs" Val="true" Type="bool"/>
+ <Parameter Name="runs.enableClusterConf" Val="true" Type="bool"/>
+ </Parameters>
+</Runs>
+
diff --git a/game.runs/.jobs/vrs_config_25.xml b/game.runs/.jobs/vrs_config_25.xml
new file mode 100644
index 0000000000000000000000000000000000000000..4d1886932883f856f240372afb5739d423832984
--- /dev/null
+++ b/game.runs/.jobs/vrs_config_25.xml
@@ -0,0 +1,12 @@
+<?xml version="1.0"?>
+<Runs Version="1" Minor="0">
+ <Run Id="synth_1" LaunchDir="/home/prasic/game/game.runs/synth_1" FlowId="Vivado_Synthesis" FromStepId="vivado" ToStepId="vivado"/>
+ <Run Id="impl_1" LaunchDir="/home/prasic/game/game.runs/impl_1" FlowId="Vivado_Implementation" FromStepId="init_design" ToStepId="write_bitstream">
+ <Parent Id="synth_1"/>
+ </Run>
+ <Parameters>
+ <Parameter Name="runs.monitorLSFJobs" Val="true" Type="bool"/>
+ <Parameter Name="runs.enableClusterConf" Val="true" Type="bool"/>
+ </Parameters>
+</Runs>
+
diff --git a/game.runs/.jobs/vrs_config_26.xml b/game.runs/.jobs/vrs_config_26.xml
new file mode 100644
index 0000000000000000000000000000000000000000..4d1886932883f856f240372afb5739d423832984
--- /dev/null
+++ b/game.runs/.jobs/vrs_config_26.xml
@@ -0,0 +1,12 @@
+<?xml version="1.0"?>
+<Runs Version="1" Minor="0">
+ <Run Id="synth_1" LaunchDir="/home/prasic/game/game.runs/synth_1" FlowId="Vivado_Synthesis" FromStepId="vivado" ToStepId="vivado"/>
+ <Run Id="impl_1" LaunchDir="/home/prasic/game/game.runs/impl_1" FlowId="Vivado_Implementation" FromStepId="init_design" ToStepId="write_bitstream">
+ <Parent Id="synth_1"/>
+ </Run>
+ <Parameters>
+ <Parameter Name="runs.monitorLSFJobs" Val="true" Type="bool"/>
+ <Parameter Name="runs.enableClusterConf" Val="true" Type="bool"/>
+ </Parameters>
+</Runs>
+
diff --git a/game.runs/.jobs/vrs_config_27.xml b/game.runs/.jobs/vrs_config_27.xml
new file mode 100644
index 0000000000000000000000000000000000000000..4d1886932883f856f240372afb5739d423832984
--- /dev/null
+++ b/game.runs/.jobs/vrs_config_27.xml
@@ -0,0 +1,12 @@
+<?xml version="1.0"?>
+<Runs Version="1" Minor="0">
+ <Run Id="synth_1" LaunchDir="/home/prasic/game/game.runs/synth_1" FlowId="Vivado_Synthesis" FromStepId="vivado" ToStepId="vivado"/>
+ <Run Id="impl_1" LaunchDir="/home/prasic/game/game.runs/impl_1" FlowId="Vivado_Implementation" FromStepId="init_design" ToStepId="write_bitstream">
+ <Parent Id="synth_1"/>
+ </Run>
+ <Parameters>
+ <Parameter Name="runs.monitorLSFJobs" Val="true" Type="bool"/>
+ <Parameter Name="runs.enableClusterConf" Val="true" Type="bool"/>
+ </Parameters>
+</Runs>
+
diff --git a/game.runs/.jobs/vrs_config_28.xml b/game.runs/.jobs/vrs_config_28.xml
new file mode 100644
index 0000000000000000000000000000000000000000..4d1886932883f856f240372afb5739d423832984
--- /dev/null
+++ b/game.runs/.jobs/vrs_config_28.xml
@@ -0,0 +1,12 @@
+<?xml version="1.0"?>
+<Runs Version="1" Minor="0">
+ <Run Id="synth_1" LaunchDir="/home/prasic/game/game.runs/synth_1" FlowId="Vivado_Synthesis" FromStepId="vivado" ToStepId="vivado"/>
+ <Run Id="impl_1" LaunchDir="/home/prasic/game/game.runs/impl_1" FlowId="Vivado_Implementation" FromStepId="init_design" ToStepId="write_bitstream">
+ <Parent Id="synth_1"/>
+ </Run>
+ <Parameters>
+ <Parameter Name="runs.monitorLSFJobs" Val="true" Type="bool"/>
+ <Parameter Name="runs.enableClusterConf" Val="true" Type="bool"/>
+ </Parameters>
+</Runs>
+
diff --git a/game.runs/.jobs/vrs_config_29.xml b/game.runs/.jobs/vrs_config_29.xml
new file mode 100644
index 0000000000000000000000000000000000000000..4d1886932883f856f240372afb5739d423832984
--- /dev/null
+++ b/game.runs/.jobs/vrs_config_29.xml
@@ -0,0 +1,12 @@
+<?xml version="1.0"?>
+<Runs Version="1" Minor="0">
+ <Run Id="synth_1" LaunchDir="/home/prasic/game/game.runs/synth_1" FlowId="Vivado_Synthesis" FromStepId="vivado" ToStepId="vivado"/>
+ <Run Id="impl_1" LaunchDir="/home/prasic/game/game.runs/impl_1" FlowId="Vivado_Implementation" FromStepId="init_design" ToStepId="write_bitstream">
+ <Parent Id="synth_1"/>
+ </Run>
+ <Parameters>
+ <Parameter Name="runs.monitorLSFJobs" Val="true" Type="bool"/>
+ <Parameter Name="runs.enableClusterConf" Val="true" Type="bool"/>
+ </Parameters>
+</Runs>
+
diff --git a/game.runs/.jobs/vrs_config_3.xml b/game.runs/.jobs/vrs_config_3.xml
new file mode 100644
index 0000000000000000000000000000000000000000..4d1886932883f856f240372afb5739d423832984
--- /dev/null
+++ b/game.runs/.jobs/vrs_config_3.xml
@@ -0,0 +1,12 @@
+<?xml version="1.0"?>
+<Runs Version="1" Minor="0">
+ <Run Id="synth_1" LaunchDir="/home/prasic/game/game.runs/synth_1" FlowId="Vivado_Synthesis" FromStepId="vivado" ToStepId="vivado"/>
+ <Run Id="impl_1" LaunchDir="/home/prasic/game/game.runs/impl_1" FlowId="Vivado_Implementation" FromStepId="init_design" ToStepId="write_bitstream">
+ <Parent Id="synth_1"/>
+ </Run>
+ <Parameters>
+ <Parameter Name="runs.monitorLSFJobs" Val="true" Type="bool"/>
+ <Parameter Name="runs.enableClusterConf" Val="true" Type="bool"/>
+ </Parameters>
+</Runs>
+
diff --git a/game.runs/.jobs/vrs_config_30.xml b/game.runs/.jobs/vrs_config_30.xml
new file mode 100644
index 0000000000000000000000000000000000000000..4d1886932883f856f240372afb5739d423832984
--- /dev/null
+++ b/game.runs/.jobs/vrs_config_30.xml
@@ -0,0 +1,12 @@
+<?xml version="1.0"?>
+<Runs Version="1" Minor="0">
+ <Run Id="synth_1" LaunchDir="/home/prasic/game/game.runs/synth_1" FlowId="Vivado_Synthesis" FromStepId="vivado" ToStepId="vivado"/>
+ <Run Id="impl_1" LaunchDir="/home/prasic/game/game.runs/impl_1" FlowId="Vivado_Implementation" FromStepId="init_design" ToStepId="write_bitstream">
+ <Parent Id="synth_1"/>
+ </Run>
+ <Parameters>
+ <Parameter Name="runs.monitorLSFJobs" Val="true" Type="bool"/>
+ <Parameter Name="runs.enableClusterConf" Val="true" Type="bool"/>
+ </Parameters>
+</Runs>
+
diff --git a/game.runs/.jobs/vrs_config_31.xml b/game.runs/.jobs/vrs_config_31.xml
new file mode 100644
index 0000000000000000000000000000000000000000..4d1886932883f856f240372afb5739d423832984
--- /dev/null
+++ b/game.runs/.jobs/vrs_config_31.xml
@@ -0,0 +1,12 @@
+<?xml version="1.0"?>
+<Runs Version="1" Minor="0">
+ <Run Id="synth_1" LaunchDir="/home/prasic/game/game.runs/synth_1" FlowId="Vivado_Synthesis" FromStepId="vivado" ToStepId="vivado"/>
+ <Run Id="impl_1" LaunchDir="/home/prasic/game/game.runs/impl_1" FlowId="Vivado_Implementation" FromStepId="init_design" ToStepId="write_bitstream">
+ <Parent Id="synth_1"/>
+ </Run>
+ <Parameters>
+ <Parameter Name="runs.monitorLSFJobs" Val="true" Type="bool"/>
+ <Parameter Name="runs.enableClusterConf" Val="true" Type="bool"/>
+ </Parameters>
+</Runs>
+
diff --git a/game.runs/.jobs/vrs_config_32.xml b/game.runs/.jobs/vrs_config_32.xml
new file mode 100644
index 0000000000000000000000000000000000000000..4d1886932883f856f240372afb5739d423832984
--- /dev/null
+++ b/game.runs/.jobs/vrs_config_32.xml
@@ -0,0 +1,12 @@
+<?xml version="1.0"?>
+<Runs Version="1" Minor="0">
+ <Run Id="synth_1" LaunchDir="/home/prasic/game/game.runs/synth_1" FlowId="Vivado_Synthesis" FromStepId="vivado" ToStepId="vivado"/>
+ <Run Id="impl_1" LaunchDir="/home/prasic/game/game.runs/impl_1" FlowId="Vivado_Implementation" FromStepId="init_design" ToStepId="write_bitstream">
+ <Parent Id="synth_1"/>
+ </Run>
+ <Parameters>
+ <Parameter Name="runs.monitorLSFJobs" Val="true" Type="bool"/>
+ <Parameter Name="runs.enableClusterConf" Val="true" Type="bool"/>
+ </Parameters>
+</Runs>
+
diff --git a/game.runs/.jobs/vrs_config_33.xml b/game.runs/.jobs/vrs_config_33.xml
new file mode 100644
index 0000000000000000000000000000000000000000..4d1886932883f856f240372afb5739d423832984
--- /dev/null
+++ b/game.runs/.jobs/vrs_config_33.xml
@@ -0,0 +1,12 @@
+<?xml version="1.0"?>
+<Runs Version="1" Minor="0">
+ <Run Id="synth_1" LaunchDir="/home/prasic/game/game.runs/synth_1" FlowId="Vivado_Synthesis" FromStepId="vivado" ToStepId="vivado"/>
+ <Run Id="impl_1" LaunchDir="/home/prasic/game/game.runs/impl_1" FlowId="Vivado_Implementation" FromStepId="init_design" ToStepId="write_bitstream">
+ <Parent Id="synth_1"/>
+ </Run>
+ <Parameters>
+ <Parameter Name="runs.monitorLSFJobs" Val="true" Type="bool"/>
+ <Parameter Name="runs.enableClusterConf" Val="true" Type="bool"/>
+ </Parameters>
+</Runs>
+
diff --git a/game.runs/.jobs/vrs_config_34.xml b/game.runs/.jobs/vrs_config_34.xml
new file mode 100644
index 0000000000000000000000000000000000000000..4d1886932883f856f240372afb5739d423832984
--- /dev/null
+++ b/game.runs/.jobs/vrs_config_34.xml
@@ -0,0 +1,12 @@
+<?xml version="1.0"?>
+<Runs Version="1" Minor="0">
+ <Run Id="synth_1" LaunchDir="/home/prasic/game/game.runs/synth_1" FlowId="Vivado_Synthesis" FromStepId="vivado" ToStepId="vivado"/>
+ <Run Id="impl_1" LaunchDir="/home/prasic/game/game.runs/impl_1" FlowId="Vivado_Implementation" FromStepId="init_design" ToStepId="write_bitstream">
+ <Parent Id="synth_1"/>
+ </Run>
+ <Parameters>
+ <Parameter Name="runs.monitorLSFJobs" Val="true" Type="bool"/>
+ <Parameter Name="runs.enableClusterConf" Val="true" Type="bool"/>
+ </Parameters>
+</Runs>
+
diff --git a/game.runs/.jobs/vrs_config_35.xml b/game.runs/.jobs/vrs_config_35.xml
new file mode 100644
index 0000000000000000000000000000000000000000..4d1886932883f856f240372afb5739d423832984
--- /dev/null
+++ b/game.runs/.jobs/vrs_config_35.xml
@@ -0,0 +1,12 @@
+<?xml version="1.0"?>
+<Runs Version="1" Minor="0">
+ <Run Id="synth_1" LaunchDir="/home/prasic/game/game.runs/synth_1" FlowId="Vivado_Synthesis" FromStepId="vivado" ToStepId="vivado"/>
+ <Run Id="impl_1" LaunchDir="/home/prasic/game/game.runs/impl_1" FlowId="Vivado_Implementation" FromStepId="init_design" ToStepId="write_bitstream">
+ <Parent Id="synth_1"/>
+ </Run>
+ <Parameters>
+ <Parameter Name="runs.monitorLSFJobs" Val="true" Type="bool"/>
+ <Parameter Name="runs.enableClusterConf" Val="true" Type="bool"/>
+ </Parameters>
+</Runs>
+
diff --git a/game.runs/.jobs/vrs_config_36.xml b/game.runs/.jobs/vrs_config_36.xml
new file mode 100644
index 0000000000000000000000000000000000000000..4d1886932883f856f240372afb5739d423832984
--- /dev/null
+++ b/game.runs/.jobs/vrs_config_36.xml
@@ -0,0 +1,12 @@
+<?xml version="1.0"?>
+<Runs Version="1" Minor="0">
+ <Run Id="synth_1" LaunchDir="/home/prasic/game/game.runs/synth_1" FlowId="Vivado_Synthesis" FromStepId="vivado" ToStepId="vivado"/>
+ <Run Id="impl_1" LaunchDir="/home/prasic/game/game.runs/impl_1" FlowId="Vivado_Implementation" FromStepId="init_design" ToStepId="write_bitstream">
+ <Parent Id="synth_1"/>
+ </Run>
+ <Parameters>
+ <Parameter Name="runs.monitorLSFJobs" Val="true" Type="bool"/>
+ <Parameter Name="runs.enableClusterConf" Val="true" Type="bool"/>
+ </Parameters>
+</Runs>
+
diff --git a/game.runs/.jobs/vrs_config_37.xml b/game.runs/.jobs/vrs_config_37.xml
new file mode 100644
index 0000000000000000000000000000000000000000..4d1886932883f856f240372afb5739d423832984
--- /dev/null
+++ b/game.runs/.jobs/vrs_config_37.xml
@@ -0,0 +1,12 @@
+<?xml version="1.0"?>
+<Runs Version="1" Minor="0">
+ <Run Id="synth_1" LaunchDir="/home/prasic/game/game.runs/synth_1" FlowId="Vivado_Synthesis" FromStepId="vivado" ToStepId="vivado"/>
+ <Run Id="impl_1" LaunchDir="/home/prasic/game/game.runs/impl_1" FlowId="Vivado_Implementation" FromStepId="init_design" ToStepId="write_bitstream">
+ <Parent Id="synth_1"/>
+ </Run>
+ <Parameters>
+ <Parameter Name="runs.monitorLSFJobs" Val="true" Type="bool"/>
+ <Parameter Name="runs.enableClusterConf" Val="true" Type="bool"/>
+ </Parameters>
+</Runs>
+
diff --git a/game.runs/.jobs/vrs_config_38.xml b/game.runs/.jobs/vrs_config_38.xml
new file mode 100644
index 0000000000000000000000000000000000000000..4d1886932883f856f240372afb5739d423832984
--- /dev/null
+++ b/game.runs/.jobs/vrs_config_38.xml
@@ -0,0 +1,12 @@
+<?xml version="1.0"?>
+<Runs Version="1" Minor="0">
+ <Run Id="synth_1" LaunchDir="/home/prasic/game/game.runs/synth_1" FlowId="Vivado_Synthesis" FromStepId="vivado" ToStepId="vivado"/>
+ <Run Id="impl_1" LaunchDir="/home/prasic/game/game.runs/impl_1" FlowId="Vivado_Implementation" FromStepId="init_design" ToStepId="write_bitstream">
+ <Parent Id="synth_1"/>
+ </Run>
+ <Parameters>
+ <Parameter Name="runs.monitorLSFJobs" Val="true" Type="bool"/>
+ <Parameter Name="runs.enableClusterConf" Val="true" Type="bool"/>
+ </Parameters>
+</Runs>
+
diff --git a/game.runs/.jobs/vrs_config_39.xml b/game.runs/.jobs/vrs_config_39.xml
new file mode 100644
index 0000000000000000000000000000000000000000..4d1886932883f856f240372afb5739d423832984
--- /dev/null
+++ b/game.runs/.jobs/vrs_config_39.xml
@@ -0,0 +1,12 @@
+<?xml version="1.0"?>
+<Runs Version="1" Minor="0">
+ <Run Id="synth_1" LaunchDir="/home/prasic/game/game.runs/synth_1" FlowId="Vivado_Synthesis" FromStepId="vivado" ToStepId="vivado"/>
+ <Run Id="impl_1" LaunchDir="/home/prasic/game/game.runs/impl_1" FlowId="Vivado_Implementation" FromStepId="init_design" ToStepId="write_bitstream">
+ <Parent Id="synth_1"/>
+ </Run>
+ <Parameters>
+ <Parameter Name="runs.monitorLSFJobs" Val="true" Type="bool"/>
+ <Parameter Name="runs.enableClusterConf" Val="true" Type="bool"/>
+ </Parameters>
+</Runs>
+
diff --git a/game.runs/.jobs/vrs_config_4.xml b/game.runs/.jobs/vrs_config_4.xml
new file mode 100644
index 0000000000000000000000000000000000000000..07b1a23e598be57019cd48f9045dc9a5af3e5f44
--- /dev/null
+++ b/game.runs/.jobs/vrs_config_4.xml
@@ -0,0 +1,12 @@
+<?xml version="1.0"?>
+<Runs Version="1" Minor="0">
+ <Run Id="synth_1" LaunchDir="/home/prasic/game/game.runs/synth_1" FlowId="Vivado_Synthesis" FromStepId="vivado" ToStepId="vivado"/>
+ <Run Id="impl_1" LaunchDir="/home/prasic/game/game.runs/impl_1" FlowId="Vivado_Implementation" FromStepId="init_design" ToStepId="route_design">
+ <Parent Id="synth_1"/>
+ </Run>
+ <Parameters>
+ <Parameter Name="runs.monitorLSFJobs" Val="true" Type="bool"/>
+ <Parameter Name="runs.enableClusterConf" Val="true" Type="bool"/>
+ </Parameters>
+</Runs>
+
diff --git a/game.runs/.jobs/vrs_config_40.xml b/game.runs/.jobs/vrs_config_40.xml
new file mode 100644
index 0000000000000000000000000000000000000000..4d1886932883f856f240372afb5739d423832984
--- /dev/null
+++ b/game.runs/.jobs/vrs_config_40.xml
@@ -0,0 +1,12 @@
+<?xml version="1.0"?>
+<Runs Version="1" Minor="0">
+ <Run Id="synth_1" LaunchDir="/home/prasic/game/game.runs/synth_1" FlowId="Vivado_Synthesis" FromStepId="vivado" ToStepId="vivado"/>
+ <Run Id="impl_1" LaunchDir="/home/prasic/game/game.runs/impl_1" FlowId="Vivado_Implementation" FromStepId="init_design" ToStepId="write_bitstream">
+ <Parent Id="synth_1"/>
+ </Run>
+ <Parameters>
+ <Parameter Name="runs.monitorLSFJobs" Val="true" Type="bool"/>
+ <Parameter Name="runs.enableClusterConf" Val="true" Type="bool"/>
+ </Parameters>
+</Runs>
+
diff --git a/game.runs/.jobs/vrs_config_41.xml b/game.runs/.jobs/vrs_config_41.xml
new file mode 100644
index 0000000000000000000000000000000000000000..4d1886932883f856f240372afb5739d423832984
--- /dev/null
+++ b/game.runs/.jobs/vrs_config_41.xml
@@ -0,0 +1,12 @@
+<?xml version="1.0"?>
+<Runs Version="1" Minor="0">
+ <Run Id="synth_1" LaunchDir="/home/prasic/game/game.runs/synth_1" FlowId="Vivado_Synthesis" FromStepId="vivado" ToStepId="vivado"/>
+ <Run Id="impl_1" LaunchDir="/home/prasic/game/game.runs/impl_1" FlowId="Vivado_Implementation" FromStepId="init_design" ToStepId="write_bitstream">
+ <Parent Id="synth_1"/>
+ </Run>
+ <Parameters>
+ <Parameter Name="runs.monitorLSFJobs" Val="true" Type="bool"/>
+ <Parameter Name="runs.enableClusterConf" Val="true" Type="bool"/>
+ </Parameters>
+</Runs>
+
diff --git a/game.runs/.jobs/vrs_config_42.xml b/game.runs/.jobs/vrs_config_42.xml
new file mode 100644
index 0000000000000000000000000000000000000000..4d1886932883f856f240372afb5739d423832984
--- /dev/null
+++ b/game.runs/.jobs/vrs_config_42.xml
@@ -0,0 +1,12 @@
+<?xml version="1.0"?>
+<Runs Version="1" Minor="0">
+ <Run Id="synth_1" LaunchDir="/home/prasic/game/game.runs/synth_1" FlowId="Vivado_Synthesis" FromStepId="vivado" ToStepId="vivado"/>
+ <Run Id="impl_1" LaunchDir="/home/prasic/game/game.runs/impl_1" FlowId="Vivado_Implementation" FromStepId="init_design" ToStepId="write_bitstream">
+ <Parent Id="synth_1"/>
+ </Run>
+ <Parameters>
+ <Parameter Name="runs.monitorLSFJobs" Val="true" Type="bool"/>
+ <Parameter Name="runs.enableClusterConf" Val="true" Type="bool"/>
+ </Parameters>
+</Runs>
+
diff --git a/game.runs/.jobs/vrs_config_43.xml b/game.runs/.jobs/vrs_config_43.xml
new file mode 100644
index 0000000000000000000000000000000000000000..4d1886932883f856f240372afb5739d423832984
--- /dev/null
+++ b/game.runs/.jobs/vrs_config_43.xml
@@ -0,0 +1,12 @@
+<?xml version="1.0"?>
+<Runs Version="1" Minor="0">
+ <Run Id="synth_1" LaunchDir="/home/prasic/game/game.runs/synth_1" FlowId="Vivado_Synthesis" FromStepId="vivado" ToStepId="vivado"/>
+ <Run Id="impl_1" LaunchDir="/home/prasic/game/game.runs/impl_1" FlowId="Vivado_Implementation" FromStepId="init_design" ToStepId="write_bitstream">
+ <Parent Id="synth_1"/>
+ </Run>
+ <Parameters>
+ <Parameter Name="runs.monitorLSFJobs" Val="true" Type="bool"/>
+ <Parameter Name="runs.enableClusterConf" Val="true" Type="bool"/>
+ </Parameters>
+</Runs>
+
diff --git a/game.runs/.jobs/vrs_config_44.xml b/game.runs/.jobs/vrs_config_44.xml
new file mode 100644
index 0000000000000000000000000000000000000000..4d1886932883f856f240372afb5739d423832984
--- /dev/null
+++ b/game.runs/.jobs/vrs_config_44.xml
@@ -0,0 +1,12 @@
+<?xml version="1.0"?>
+<Runs Version="1" Minor="0">
+ <Run Id="synth_1" LaunchDir="/home/prasic/game/game.runs/synth_1" FlowId="Vivado_Synthesis" FromStepId="vivado" ToStepId="vivado"/>
+ <Run Id="impl_1" LaunchDir="/home/prasic/game/game.runs/impl_1" FlowId="Vivado_Implementation" FromStepId="init_design" ToStepId="write_bitstream">
+ <Parent Id="synth_1"/>
+ </Run>
+ <Parameters>
+ <Parameter Name="runs.monitorLSFJobs" Val="true" Type="bool"/>
+ <Parameter Name="runs.enableClusterConf" Val="true" Type="bool"/>
+ </Parameters>
+</Runs>
+
diff --git a/game.runs/.jobs/vrs_config_45.xml b/game.runs/.jobs/vrs_config_45.xml
new file mode 100644
index 0000000000000000000000000000000000000000..4d1886932883f856f240372afb5739d423832984
--- /dev/null
+++ b/game.runs/.jobs/vrs_config_45.xml
@@ -0,0 +1,12 @@
+<?xml version="1.0"?>
+<Runs Version="1" Minor="0">
+ <Run Id="synth_1" LaunchDir="/home/prasic/game/game.runs/synth_1" FlowId="Vivado_Synthesis" FromStepId="vivado" ToStepId="vivado"/>
+ <Run Id="impl_1" LaunchDir="/home/prasic/game/game.runs/impl_1" FlowId="Vivado_Implementation" FromStepId="init_design" ToStepId="write_bitstream">
+ <Parent Id="synth_1"/>
+ </Run>
+ <Parameters>
+ <Parameter Name="runs.monitorLSFJobs" Val="true" Type="bool"/>
+ <Parameter Name="runs.enableClusterConf" Val="true" Type="bool"/>
+ </Parameters>
+</Runs>
+
diff --git a/game.runs/.jobs/vrs_config_46.xml b/game.runs/.jobs/vrs_config_46.xml
new file mode 100644
index 0000000000000000000000000000000000000000..4d1886932883f856f240372afb5739d423832984
--- /dev/null
+++ b/game.runs/.jobs/vrs_config_46.xml
@@ -0,0 +1,12 @@
+<?xml version="1.0"?>
+<Runs Version="1" Minor="0">
+ <Run Id="synth_1" LaunchDir="/home/prasic/game/game.runs/synth_1" FlowId="Vivado_Synthesis" FromStepId="vivado" ToStepId="vivado"/>
+ <Run Id="impl_1" LaunchDir="/home/prasic/game/game.runs/impl_1" FlowId="Vivado_Implementation" FromStepId="init_design" ToStepId="write_bitstream">
+ <Parent Id="synth_1"/>
+ </Run>
+ <Parameters>
+ <Parameter Name="runs.monitorLSFJobs" Val="true" Type="bool"/>
+ <Parameter Name="runs.enableClusterConf" Val="true" Type="bool"/>
+ </Parameters>
+</Runs>
+
diff --git a/game.runs/.jobs/vrs_config_47.xml b/game.runs/.jobs/vrs_config_47.xml
new file mode 100644
index 0000000000000000000000000000000000000000..4d1886932883f856f240372afb5739d423832984
--- /dev/null
+++ b/game.runs/.jobs/vrs_config_47.xml
@@ -0,0 +1,12 @@
+<?xml version="1.0"?>
+<Runs Version="1" Minor="0">
+ <Run Id="synth_1" LaunchDir="/home/prasic/game/game.runs/synth_1" FlowId="Vivado_Synthesis" FromStepId="vivado" ToStepId="vivado"/>
+ <Run Id="impl_1" LaunchDir="/home/prasic/game/game.runs/impl_1" FlowId="Vivado_Implementation" FromStepId="init_design" ToStepId="write_bitstream">
+ <Parent Id="synth_1"/>
+ </Run>
+ <Parameters>
+ <Parameter Name="runs.monitorLSFJobs" Val="true" Type="bool"/>
+ <Parameter Name="runs.enableClusterConf" Val="true" Type="bool"/>
+ </Parameters>
+</Runs>
+
diff --git a/game.runs/.jobs/vrs_config_48.xml b/game.runs/.jobs/vrs_config_48.xml
new file mode 100644
index 0000000000000000000000000000000000000000..4d1886932883f856f240372afb5739d423832984
--- /dev/null
+++ b/game.runs/.jobs/vrs_config_48.xml
@@ -0,0 +1,12 @@
+<?xml version="1.0"?>
+<Runs Version="1" Minor="0">
+ <Run Id="synth_1" LaunchDir="/home/prasic/game/game.runs/synth_1" FlowId="Vivado_Synthesis" FromStepId="vivado" ToStepId="vivado"/>
+ <Run Id="impl_1" LaunchDir="/home/prasic/game/game.runs/impl_1" FlowId="Vivado_Implementation" FromStepId="init_design" ToStepId="write_bitstream">
+ <Parent Id="synth_1"/>
+ </Run>
+ <Parameters>
+ <Parameter Name="runs.monitorLSFJobs" Val="true" Type="bool"/>
+ <Parameter Name="runs.enableClusterConf" Val="true" Type="bool"/>
+ </Parameters>
+</Runs>
+
diff --git a/game.runs/.jobs/vrs_config_49.xml b/game.runs/.jobs/vrs_config_49.xml
new file mode 100644
index 0000000000000000000000000000000000000000..4d1886932883f856f240372afb5739d423832984
--- /dev/null
+++ b/game.runs/.jobs/vrs_config_49.xml
@@ -0,0 +1,12 @@
+<?xml version="1.0"?>
+<Runs Version="1" Minor="0">
+ <Run Id="synth_1" LaunchDir="/home/prasic/game/game.runs/synth_1" FlowId="Vivado_Synthesis" FromStepId="vivado" ToStepId="vivado"/>
+ <Run Id="impl_1" LaunchDir="/home/prasic/game/game.runs/impl_1" FlowId="Vivado_Implementation" FromStepId="init_design" ToStepId="write_bitstream">
+ <Parent Id="synth_1"/>
+ </Run>
+ <Parameters>
+ <Parameter Name="runs.monitorLSFJobs" Val="true" Type="bool"/>
+ <Parameter Name="runs.enableClusterConf" Val="true" Type="bool"/>
+ </Parameters>
+</Runs>
+
diff --git a/game.runs/.jobs/vrs_config_5.xml b/game.runs/.jobs/vrs_config_5.xml
new file mode 100644
index 0000000000000000000000000000000000000000..4d1886932883f856f240372afb5739d423832984
--- /dev/null
+++ b/game.runs/.jobs/vrs_config_5.xml
@@ -0,0 +1,12 @@
+<?xml version="1.0"?>
+<Runs Version="1" Minor="0">
+ <Run Id="synth_1" LaunchDir="/home/prasic/game/game.runs/synth_1" FlowId="Vivado_Synthesis" FromStepId="vivado" ToStepId="vivado"/>
+ <Run Id="impl_1" LaunchDir="/home/prasic/game/game.runs/impl_1" FlowId="Vivado_Implementation" FromStepId="init_design" ToStepId="write_bitstream">
+ <Parent Id="synth_1"/>
+ </Run>
+ <Parameters>
+ <Parameter Name="runs.monitorLSFJobs" Val="true" Type="bool"/>
+ <Parameter Name="runs.enableClusterConf" Val="true" Type="bool"/>
+ </Parameters>
+</Runs>
+
diff --git a/game.runs/.jobs/vrs_config_50.xml b/game.runs/.jobs/vrs_config_50.xml
new file mode 100644
index 0000000000000000000000000000000000000000..4d1886932883f856f240372afb5739d423832984
--- /dev/null
+++ b/game.runs/.jobs/vrs_config_50.xml
@@ -0,0 +1,12 @@
+<?xml version="1.0"?>
+<Runs Version="1" Minor="0">
+ <Run Id="synth_1" LaunchDir="/home/prasic/game/game.runs/synth_1" FlowId="Vivado_Synthesis" FromStepId="vivado" ToStepId="vivado"/>
+ <Run Id="impl_1" LaunchDir="/home/prasic/game/game.runs/impl_1" FlowId="Vivado_Implementation" FromStepId="init_design" ToStepId="write_bitstream">
+ <Parent Id="synth_1"/>
+ </Run>
+ <Parameters>
+ <Parameter Name="runs.monitorLSFJobs" Val="true" Type="bool"/>
+ <Parameter Name="runs.enableClusterConf" Val="true" Type="bool"/>
+ </Parameters>
+</Runs>
+
diff --git a/game.runs/.jobs/vrs_config_51.xml b/game.runs/.jobs/vrs_config_51.xml
new file mode 100644
index 0000000000000000000000000000000000000000..4d1886932883f856f240372afb5739d423832984
--- /dev/null
+++ b/game.runs/.jobs/vrs_config_51.xml
@@ -0,0 +1,12 @@
+<?xml version="1.0"?>
+<Runs Version="1" Minor="0">
+ <Run Id="synth_1" LaunchDir="/home/prasic/game/game.runs/synth_1" FlowId="Vivado_Synthesis" FromStepId="vivado" ToStepId="vivado"/>
+ <Run Id="impl_1" LaunchDir="/home/prasic/game/game.runs/impl_1" FlowId="Vivado_Implementation" FromStepId="init_design" ToStepId="write_bitstream">
+ <Parent Id="synth_1"/>
+ </Run>
+ <Parameters>
+ <Parameter Name="runs.monitorLSFJobs" Val="true" Type="bool"/>
+ <Parameter Name="runs.enableClusterConf" Val="true" Type="bool"/>
+ </Parameters>
+</Runs>
+
diff --git a/game.runs/.jobs/vrs_config_52.xml b/game.runs/.jobs/vrs_config_52.xml
new file mode 100644
index 0000000000000000000000000000000000000000..4d1886932883f856f240372afb5739d423832984
--- /dev/null
+++ b/game.runs/.jobs/vrs_config_52.xml
@@ -0,0 +1,12 @@
+<?xml version="1.0"?>
+<Runs Version="1" Minor="0">
+ <Run Id="synth_1" LaunchDir="/home/prasic/game/game.runs/synth_1" FlowId="Vivado_Synthesis" FromStepId="vivado" ToStepId="vivado"/>
+ <Run Id="impl_1" LaunchDir="/home/prasic/game/game.runs/impl_1" FlowId="Vivado_Implementation" FromStepId="init_design" ToStepId="write_bitstream">
+ <Parent Id="synth_1"/>
+ </Run>
+ <Parameters>
+ <Parameter Name="runs.monitorLSFJobs" Val="true" Type="bool"/>
+ <Parameter Name="runs.enableClusterConf" Val="true" Type="bool"/>
+ </Parameters>
+</Runs>
+
diff --git a/game.runs/.jobs/vrs_config_53.xml b/game.runs/.jobs/vrs_config_53.xml
new file mode 100644
index 0000000000000000000000000000000000000000..4d1886932883f856f240372afb5739d423832984
--- /dev/null
+++ b/game.runs/.jobs/vrs_config_53.xml
@@ -0,0 +1,12 @@
+<?xml version="1.0"?>
+<Runs Version="1" Minor="0">
+ <Run Id="synth_1" LaunchDir="/home/prasic/game/game.runs/synth_1" FlowId="Vivado_Synthesis" FromStepId="vivado" ToStepId="vivado"/>
+ <Run Id="impl_1" LaunchDir="/home/prasic/game/game.runs/impl_1" FlowId="Vivado_Implementation" FromStepId="init_design" ToStepId="write_bitstream">
+ <Parent Id="synth_1"/>
+ </Run>
+ <Parameters>
+ <Parameter Name="runs.monitorLSFJobs" Val="true" Type="bool"/>
+ <Parameter Name="runs.enableClusterConf" Val="true" Type="bool"/>
+ </Parameters>
+</Runs>
+
diff --git a/game.runs/.jobs/vrs_config_54.xml b/game.runs/.jobs/vrs_config_54.xml
new file mode 100644
index 0000000000000000000000000000000000000000..4d1886932883f856f240372afb5739d423832984
--- /dev/null
+++ b/game.runs/.jobs/vrs_config_54.xml
@@ -0,0 +1,12 @@
+<?xml version="1.0"?>
+<Runs Version="1" Minor="0">
+ <Run Id="synth_1" LaunchDir="/home/prasic/game/game.runs/synth_1" FlowId="Vivado_Synthesis" FromStepId="vivado" ToStepId="vivado"/>
+ <Run Id="impl_1" LaunchDir="/home/prasic/game/game.runs/impl_1" FlowId="Vivado_Implementation" FromStepId="init_design" ToStepId="write_bitstream">
+ <Parent Id="synth_1"/>
+ </Run>
+ <Parameters>
+ <Parameter Name="runs.monitorLSFJobs" Val="true" Type="bool"/>
+ <Parameter Name="runs.enableClusterConf" Val="true" Type="bool"/>
+ </Parameters>
+</Runs>
+
diff --git a/game.runs/.jobs/vrs_config_55.xml b/game.runs/.jobs/vrs_config_55.xml
new file mode 100644
index 0000000000000000000000000000000000000000..4d1886932883f856f240372afb5739d423832984
--- /dev/null
+++ b/game.runs/.jobs/vrs_config_55.xml
@@ -0,0 +1,12 @@
+<?xml version="1.0"?>
+<Runs Version="1" Minor="0">
+ <Run Id="synth_1" LaunchDir="/home/prasic/game/game.runs/synth_1" FlowId="Vivado_Synthesis" FromStepId="vivado" ToStepId="vivado"/>
+ <Run Id="impl_1" LaunchDir="/home/prasic/game/game.runs/impl_1" FlowId="Vivado_Implementation" FromStepId="init_design" ToStepId="write_bitstream">
+ <Parent Id="synth_1"/>
+ </Run>
+ <Parameters>
+ <Parameter Name="runs.monitorLSFJobs" Val="true" Type="bool"/>
+ <Parameter Name="runs.enableClusterConf" Val="true" Type="bool"/>
+ </Parameters>
+</Runs>
+
diff --git a/game.runs/.jobs/vrs_config_56.xml b/game.runs/.jobs/vrs_config_56.xml
new file mode 100644
index 0000000000000000000000000000000000000000..4d1886932883f856f240372afb5739d423832984
--- /dev/null
+++ b/game.runs/.jobs/vrs_config_56.xml
@@ -0,0 +1,12 @@
+<?xml version="1.0"?>
+<Runs Version="1" Minor="0">
+ <Run Id="synth_1" LaunchDir="/home/prasic/game/game.runs/synth_1" FlowId="Vivado_Synthesis" FromStepId="vivado" ToStepId="vivado"/>
+ <Run Id="impl_1" LaunchDir="/home/prasic/game/game.runs/impl_1" FlowId="Vivado_Implementation" FromStepId="init_design" ToStepId="write_bitstream">
+ <Parent Id="synth_1"/>
+ </Run>
+ <Parameters>
+ <Parameter Name="runs.monitorLSFJobs" Val="true" Type="bool"/>
+ <Parameter Name="runs.enableClusterConf" Val="true" Type="bool"/>
+ </Parameters>
+</Runs>
+
diff --git a/game.runs/.jobs/vrs_config_57.xml b/game.runs/.jobs/vrs_config_57.xml
new file mode 100644
index 0000000000000000000000000000000000000000..4d1886932883f856f240372afb5739d423832984
--- /dev/null
+++ b/game.runs/.jobs/vrs_config_57.xml
@@ -0,0 +1,12 @@
+<?xml version="1.0"?>
+<Runs Version="1" Minor="0">
+ <Run Id="synth_1" LaunchDir="/home/prasic/game/game.runs/synth_1" FlowId="Vivado_Synthesis" FromStepId="vivado" ToStepId="vivado"/>
+ <Run Id="impl_1" LaunchDir="/home/prasic/game/game.runs/impl_1" FlowId="Vivado_Implementation" FromStepId="init_design" ToStepId="write_bitstream">
+ <Parent Id="synth_1"/>
+ </Run>
+ <Parameters>
+ <Parameter Name="runs.monitorLSFJobs" Val="true" Type="bool"/>
+ <Parameter Name="runs.enableClusterConf" Val="true" Type="bool"/>
+ </Parameters>
+</Runs>
+
diff --git a/game.runs/.jobs/vrs_config_58.xml b/game.runs/.jobs/vrs_config_58.xml
new file mode 100644
index 0000000000000000000000000000000000000000..4d1886932883f856f240372afb5739d423832984
--- /dev/null
+++ b/game.runs/.jobs/vrs_config_58.xml
@@ -0,0 +1,12 @@
+<?xml version="1.0"?>
+<Runs Version="1" Minor="0">
+ <Run Id="synth_1" LaunchDir="/home/prasic/game/game.runs/synth_1" FlowId="Vivado_Synthesis" FromStepId="vivado" ToStepId="vivado"/>
+ <Run Id="impl_1" LaunchDir="/home/prasic/game/game.runs/impl_1" FlowId="Vivado_Implementation" FromStepId="init_design" ToStepId="write_bitstream">
+ <Parent Id="synth_1"/>
+ </Run>
+ <Parameters>
+ <Parameter Name="runs.monitorLSFJobs" Val="true" Type="bool"/>
+ <Parameter Name="runs.enableClusterConf" Val="true" Type="bool"/>
+ </Parameters>
+</Runs>
+
diff --git a/game.runs/.jobs/vrs_config_6.xml b/game.runs/.jobs/vrs_config_6.xml
new file mode 100644
index 0000000000000000000000000000000000000000..4d1886932883f856f240372afb5739d423832984
--- /dev/null
+++ b/game.runs/.jobs/vrs_config_6.xml
@@ -0,0 +1,12 @@
+<?xml version="1.0"?>
+<Runs Version="1" Minor="0">
+ <Run Id="synth_1" LaunchDir="/home/prasic/game/game.runs/synth_1" FlowId="Vivado_Synthesis" FromStepId="vivado" ToStepId="vivado"/>
+ <Run Id="impl_1" LaunchDir="/home/prasic/game/game.runs/impl_1" FlowId="Vivado_Implementation" FromStepId="init_design" ToStepId="write_bitstream">
+ <Parent Id="synth_1"/>
+ </Run>
+ <Parameters>
+ <Parameter Name="runs.monitorLSFJobs" Val="true" Type="bool"/>
+ <Parameter Name="runs.enableClusterConf" Val="true" Type="bool"/>
+ </Parameters>
+</Runs>
+
diff --git a/game.runs/.jobs/vrs_config_7.xml b/game.runs/.jobs/vrs_config_7.xml
new file mode 100644
index 0000000000000000000000000000000000000000..4d1886932883f856f240372afb5739d423832984
--- /dev/null
+++ b/game.runs/.jobs/vrs_config_7.xml
@@ -0,0 +1,12 @@
+<?xml version="1.0"?>
+<Runs Version="1" Minor="0">
+ <Run Id="synth_1" LaunchDir="/home/prasic/game/game.runs/synth_1" FlowId="Vivado_Synthesis" FromStepId="vivado" ToStepId="vivado"/>
+ <Run Id="impl_1" LaunchDir="/home/prasic/game/game.runs/impl_1" FlowId="Vivado_Implementation" FromStepId="init_design" ToStepId="write_bitstream">
+ <Parent Id="synth_1"/>
+ </Run>
+ <Parameters>
+ <Parameter Name="runs.monitorLSFJobs" Val="true" Type="bool"/>
+ <Parameter Name="runs.enableClusterConf" Val="true" Type="bool"/>
+ </Parameters>
+</Runs>
+
diff --git a/game.runs/.jobs/vrs_config_8.xml b/game.runs/.jobs/vrs_config_8.xml
new file mode 100644
index 0000000000000000000000000000000000000000..07b1a23e598be57019cd48f9045dc9a5af3e5f44
--- /dev/null
+++ b/game.runs/.jobs/vrs_config_8.xml
@@ -0,0 +1,12 @@
+<?xml version="1.0"?>
+<Runs Version="1" Minor="0">
+ <Run Id="synth_1" LaunchDir="/home/prasic/game/game.runs/synth_1" FlowId="Vivado_Synthesis" FromStepId="vivado" ToStepId="vivado"/>
+ <Run Id="impl_1" LaunchDir="/home/prasic/game/game.runs/impl_1" FlowId="Vivado_Implementation" FromStepId="init_design" ToStepId="route_design">
+ <Parent Id="synth_1"/>
+ </Run>
+ <Parameters>
+ <Parameter Name="runs.monitorLSFJobs" Val="true" Type="bool"/>
+ <Parameter Name="runs.enableClusterConf" Val="true" Type="bool"/>
+ </Parameters>
+</Runs>
+
diff --git a/game.runs/.jobs/vrs_config_9.xml b/game.runs/.jobs/vrs_config_9.xml
new file mode 100644
index 0000000000000000000000000000000000000000..5bdc25d491b5a8218a6d1bd248af4c552c10a94e
--- /dev/null
+++ b/game.runs/.jobs/vrs_config_9.xml
@@ -0,0 +1,9 @@
+<?xml version="1.0"?>
+<Runs Version="1" Minor="0">
+ <Run Id="impl_1" LaunchDir="/home/prasic/game/game.runs/impl_1" FlowId="Vivado_Implementation" FromStepId="write_bitstream" ToStepId="write_bitstream"/>
+ <Parameters>
+ <Parameter Name="runs.monitorLSFJobs" Val="true" Type="bool"/>
+ <Parameter Name="runs.enableClusterConf" Val="true" Type="bool"/>
+ </Parameters>
+</Runs>
+
diff --git a/game.runs/clk_wiz_0_synth_1/.Vivado_Synthesis.queue.rst b/game.runs/clk_wiz_0_synth_1/.Vivado_Synthesis.queue.rst
new file mode 100644
index 0000000000000000000000000000000000000000..e69de29bb2d1d6434b8b29ae775ad8c2e48c5391
diff --git a/game.runs/clk_wiz_0_synth_1/.Xil/clk_wiz_0_propImpl.xdc b/game.runs/clk_wiz_0_synth_1/.Xil/clk_wiz_0_propImpl.xdc
new file mode 100644
index 0000000000000000000000000000000000000000..10d1bcc148c5efb9a4eb261f3b8a33d2160ce12c
--- /dev/null
+++ b/game.runs/clk_wiz_0_synth_1/.Xil/clk_wiz_0_propImpl.xdc
@@ -0,0 +1,4 @@
+set_property SRC_FILE_INFO {cfile:/home/prasic/game/game.gen/sources_1/ip/clk_wiz_0/clk_wiz_0.xdc rfile:../../../game.gen/sources_1/ip/clk_wiz_0/clk_wiz_0.xdc id:1 order:EARLY scoped_inst:inst} [current_design]
+current_instance inst
+set_property src_info {type:SCOPED_XDC file:1 line:57 export:INPUT save:INPUT read:READ} [current_design]
+set_input_jitter [get_clocks -of_objects [get_ports clk_in1]] 0.100
diff --git a/game.runs/clk_wiz_0_synth_1/.vivado.begin.rst b/game.runs/clk_wiz_0_synth_1/.vivado.begin.rst
new file mode 100644
index 0000000000000000000000000000000000000000..e1928c71648ec86381c275abf569ddceecf47b10
--- /dev/null
+++ b/game.runs/clk_wiz_0_synth_1/.vivado.begin.rst
@@ -0,0 +1,5 @@
+<?xml version="1.0"?>
+<ProcessHandle Version="1" Minor="0">
+ <Process Command="vivado" Owner="prasic" Host="LikeUE06" Pid="21225" HostCore="8" HostMemory="16307824">
+ </Process>
+</ProcessHandle>
diff --git a/game.runs/clk_wiz_0_synth_1/.vivado.end.rst b/game.runs/clk_wiz_0_synth_1/.vivado.end.rst
new file mode 100644
index 0000000000000000000000000000000000000000..e69de29bb2d1d6434b8b29ae775ad8c2e48c5391
diff --git a/game.runs/clk_wiz_0_synth_1/ISEWrap.js b/game.runs/clk_wiz_0_synth_1/ISEWrap.js
new file mode 100755
index 0000000000000000000000000000000000000000..db0a51077cfb3a198d0bcb1b84080b9210b5b593
--- /dev/null
+++ b/game.runs/clk_wiz_0_synth_1/ISEWrap.js
@@ -0,0 +1,269 @@
+//
+// Vivado(TM)
+// ISEWrap.js: Vivado Runs Script for WSH 5.1/5.6
+// Copyright 1986-1999, 2001-2013,2015 Xilinx, Inc. All Rights Reserved.
+//
+
+// GLOBAL VARIABLES
+var ISEShell = new ActiveXObject( "WScript.Shell" );
+var ISEFileSys = new ActiveXObject( "Scripting.FileSystemObject" );
+var ISERunDir = "";
+var ISELogFile = "runme.log";
+var ISELogFileStr = null;
+var ISELogEcho = true;
+var ISEOldVersionWSH = false;
+
+
+
+// BOOTSTRAP
+ISEInit();
+
+
+
+//
+// ISE FUNCTIONS
+//
+function ISEInit() {
+
+ // 1. RUN DIR setup
+ var ISEScrFP = WScript.ScriptFullName;
+ var ISEScrN = WScript.ScriptName;
+ ISERunDir =
+ ISEScrFP.substr( 0, ISEScrFP.length - ISEScrN.length - 1 );
+
+ // 2. LOG file setup
+ ISELogFileStr = ISEOpenFile( ISELogFile );
+
+ // 3. LOG echo?
+ var ISEScriptArgs = WScript.Arguments;
+ for ( var loopi=0; loopi<ISEScriptArgs.length; loopi++ ) {
+ if ( ISEScriptArgs(loopi) == "-quiet" ) {
+ ISELogEcho = false;
+ break;
+ }
+ }
+
+ // 4. WSH version check
+ var ISEOptimalVersionWSH = 5.6;
+ var ISECurrentVersionWSH = WScript.Version;
+ if ( ISECurrentVersionWSH < ISEOptimalVersionWSH ) {
+
+ ISEStdErr( "" );
+ ISEStdErr( "Warning: ExploreAhead works best with Microsoft WSH " +
+ ISEOptimalVersionWSH + " or higher. Downloads" );
+ ISEStdErr( " for upgrading your Windows Scripting Host can be found here: " );
+ ISEStdErr( " http://msdn.microsoft.com/downloads/list/webdev.asp" );
+ ISEStdErr( "" );
+
+ ISEOldVersionWSH = true;
+ }
+
+}
+
+function ISEStep( ISEProg, ISEArgs ) {
+
+ // CHECK for a STOP FILE
+ if ( ISEFileSys.FileExists(ISERunDir + "/.stop.rst") ) {
+ ISEStdErr( "" );
+ ISEStdErr( "*** Halting run - EA reset detected ***" );
+ ISEStdErr( "" );
+ WScript.Quit( 1 );
+ }
+
+ // WRITE STEP HEADER to LOG
+ ISEStdOut( "" );
+ ISEStdOut( "*** Running " + ISEProg );
+ ISEStdOut( " with args " + ISEArgs );
+ ISEStdOut( "" );
+
+ // LAUNCH!
+ var ISEExitCode = ISEExec( ISEProg, ISEArgs );
+ if ( ISEExitCode != 0 ) {
+ WScript.Quit( ISEExitCode );
+ }
+
+}
+
+function ISEExec( ISEProg, ISEArgs ) {
+
+ var ISEStep = ISEProg;
+ if (ISEProg == "realTimeFpga" || ISEProg == "planAhead" || ISEProg == "vivado") {
+ ISEProg += ".bat";
+ }
+
+ var ISECmdLine = ISEProg + " " + ISEArgs;
+ var ISEExitCode = 1;
+
+ if ( ISEOldVersionWSH ) { // WSH 5.1
+
+ // BEGIN file creation
+ ISETouchFile( ISEStep, "begin" );
+
+ // LAUNCH!
+ ISELogFileStr.Close();
+ ISECmdLine =
+ "%comspec% /c " + ISECmdLine + " >> " + ISELogFile + " 2>&1";
+ ISEExitCode = ISEShell.Run( ISECmdLine, 0, true );
+ ISELogFileStr = ISEOpenFile( ISELogFile );
+
+ } else { // WSH 5.6
+
+ // LAUNCH!
+ ISEShell.CurrentDirectory = ISERunDir;
+
+ // Redirect STDERR to STDOUT
+ ISECmdLine = "%comspec% /c " + ISECmdLine + " 2>&1";
+ var ISEProcess = ISEShell.Exec( ISECmdLine );
+
+ // BEGIN file creation
+ var wbemFlagReturnImmediately = 0x10;
+ var wbemFlagForwardOnly = 0x20;
+ var objWMIService = GetObject ("winmgmts:{impersonationLevel=impersonate, (Systemtime)}!//./root/cimv2");
+ var processor = objWMIService.ExecQuery("SELECT * FROM Win32_Processor", "WQL",wbemFlagReturnImmediately | wbemFlagForwardOnly);
+ var computerSystem = objWMIService.ExecQuery("SELECT * FROM Win32_ComputerSystem", "WQL", wbemFlagReturnImmediately | wbemFlagForwardOnly);
+ var NOC = 0;
+ var NOLP = 0;
+ var TPM = 0;
+ var cpuInfos = new Enumerator(processor);
+ for(;!cpuInfos.atEnd(); cpuInfos.moveNext()) {
+ var cpuInfo = cpuInfos.item();
+ NOC += cpuInfo.NumberOfCores;
+ NOLP += cpuInfo.NumberOfLogicalProcessors;
+ }
+ var csInfos = new Enumerator(computerSystem);
+ for(;!csInfos.atEnd(); csInfos.moveNext()) {
+ var csInfo = csInfos.item();
+ TPM += csInfo.TotalPhysicalMemory;
+ }
+
+ var ISEHOSTCORE = NOLP
+ var ISEMEMTOTAL = TPM
+
+ var ISENetwork = WScript.CreateObject( "WScript.Network" );
+ var ISEHost = ISENetwork.ComputerName;
+ var ISEUser = ISENetwork.UserName;
+ var ISEPid = ISEProcess.ProcessID;
+ var ISEBeginFile = ISEOpenFile( "." + ISEStep + ".begin.rst" );
+ ISEBeginFile.WriteLine( "<?xml version=\"1.0\"?>" );
+ ISEBeginFile.WriteLine( "<ProcessHandle Version=\"1\" Minor=\"0\">" );
+ ISEBeginFile.WriteLine( " <Process Command=\"" + ISEProg +
+ "\" Owner=\"" + ISEUser +
+ "\" Host=\"" + ISEHost +
+ "\" Pid=\"" + ISEPid +
+ "\" HostCore=\"" + ISEHOSTCORE +
+ "\" HostMemory=\"" + ISEMEMTOTAL +
+ "\">" );
+ ISEBeginFile.WriteLine( " </Process>" );
+ ISEBeginFile.WriteLine( "</ProcessHandle>" );
+ ISEBeginFile.Close();
+
+ var ISEOutStr = ISEProcess.StdOut;
+ var ISEErrStr = ISEProcess.StdErr;
+
+ // WAIT for ISEStep to finish
+ while ( ISEProcess.Status == 0 ) {
+
+ // dump stdout then stderr - feels a little arbitrary
+ while ( !ISEOutStr.AtEndOfStream ) {
+ ISEStdOut( ISEOutStr.ReadLine() );
+ }
+
+ WScript.Sleep( 100 );
+ }
+
+ ISEExitCode = ISEProcess.ExitCode;
+ }
+
+ ISELogFileStr.Close();
+
+ // END/ERROR file creation
+ if ( ISEExitCode != 0 ) {
+ ISETouchFile( ISEStep, "error" );
+
+ } else {
+ ISETouchFile( ISEStep, "end" );
+ }
+
+ return ISEExitCode;
+}
+
+
+//
+// UTILITIES
+//
+function ISEStdOut( ISELine ) {
+
+ ISELogFileStr.WriteLine( ISELine );
+
+ if ( ISELogEcho ) {
+ WScript.StdOut.WriteLine( ISELine );
+ }
+}
+
+function ISEStdErr( ISELine ) {
+
+ ISELogFileStr.WriteLine( ISELine );
+
+ if ( ISELogEcho ) {
+ WScript.StdErr.WriteLine( ISELine );
+ }
+}
+
+function ISETouchFile( ISERoot, ISEStatus ) {
+
+ var ISETFile =
+ ISEOpenFile( "." + ISERoot + "." + ISEStatus + ".rst" );
+ ISETFile.Close();
+}
+
+function ISEOpenFile( ISEFilename ) {
+
+ // This function has been updated to deal with a problem seen in CR #870871.
+ // In that case the user runs a script that runs impl_1, and then turns around
+ // and runs impl_1 -to_step write_bitstream. That second run takes place in
+ // the same directory, which means we may hit some of the same files, and in
+ // particular, we will open the runme.log file. Even though this script closes
+ // the file (now), we see cases where a subsequent attempt to open the file
+ // fails. Perhaps the OS is slow to release the lock, or the disk comes into
+ // play? In any case, we try to work around this by first waiting if the file
+ // is already there for an arbitrary 5 seconds. Then we use a try-catch block
+ // and try to open the file 10 times with a one second delay after each attempt.
+ // Again, 10 is arbitrary. But these seem to stop the hang in CR #870871.
+ // If there is an unrecognized exception when trying to open the file, we output
+ // an error message and write details to an exception.log file.
+ var ISEFullPath = ISERunDir + "/" + ISEFilename;
+ if (ISEFileSys.FileExists(ISEFullPath)) {
+ // File is already there. This could be a problem. Wait in case it is still in use.
+ WScript.Sleep(5000);
+ }
+ var i;
+ for (i = 0; i < 10; ++i) {
+ try {
+ return ISEFileSys.OpenTextFile(ISEFullPath, 8, true);
+ } catch (exception) {
+ var error_code = exception.number & 0xFFFF; // The other bits are a facility code.
+ if (error_code == 52) { // 52 is bad file name or number.
+ // Wait a second and try again.
+ WScript.Sleep(1000);
+ continue;
+ } else {
+ WScript.StdErr.WriteLine("ERROR: Exception caught trying to open file " + ISEFullPath);
+ var exceptionFilePath = ISERunDir + "/exception.log";
+ if (!ISEFileSys.FileExists(exceptionFilePath)) {
+ WScript.StdErr.WriteLine("See file " + exceptionFilePath + " for details.");
+ var exceptionFile = ISEFileSys.OpenTextFile(exceptionFilePath, 8, true);
+ exceptionFile.WriteLine("ERROR: Exception caught trying to open file " + ISEFullPath);
+ exceptionFile.WriteLine("\tException name: " + exception.name);
+ exceptionFile.WriteLine("\tException error code: " + error_code);
+ exceptionFile.WriteLine("\tException message: " + exception.message);
+ exceptionFile.Close();
+ }
+ throw exception;
+ }
+ }
+ }
+ // If we reached this point, we failed to open the file after 10 attempts.
+ // We need to error out.
+ WScript.StdErr.WriteLine("ERROR: Failed to open file " + ISEFullPath);
+ WScript.Quit(1);
+}
diff --git a/game.runs/clk_wiz_0_synth_1/ISEWrap.sh b/game.runs/clk_wiz_0_synth_1/ISEWrap.sh
new file mode 100755
index 0000000000000000000000000000000000000000..c2fbbb6098d6a14cfa1bdac6a65050244f5a6c7d
--- /dev/null
+++ b/game.runs/clk_wiz_0_synth_1/ISEWrap.sh
@@ -0,0 +1,84 @@
+#!/bin/sh
+
+#
+# Vivado(TM)
+# ISEWrap.sh: Vivado Runs Script for UNIX
+# Copyright 1986-1999, 2001-2013 Xilinx, Inc. All Rights Reserved.
+#
+
+cmd_exists()
+{
+ command -v "$1" >/dev/null 2>&1
+}
+
+HD_LOG=$1
+shift
+
+# CHECK for a STOP FILE
+if [ -f .stop.rst ]
+then
+echo "" >> $HD_LOG
+echo "*** Halting run - EA reset detected ***" >> $HD_LOG
+echo "" >> $HD_LOG
+exit 1
+fi
+
+ISE_STEP=$1
+shift
+
+# WRITE STEP HEADER to LOG
+echo "" >> $HD_LOG
+echo "*** Running $ISE_STEP" >> $HD_LOG
+echo " with args $@" >> $HD_LOG
+echo "" >> $HD_LOG
+
+# LAUNCH!
+$ISE_STEP "$@" >> $HD_LOG 2>&1 &
+
+# BEGIN file creation
+ISE_PID=$!
+
+HostNameFile=/proc/sys/kernel/hostname
+if cmd_exists hostname
+then
+ISE_HOST=$(hostname)
+elif cmd_exists uname
+then
+ISE_HOST=$(uname -n)
+elif [ -f "$HostNameFile" ] && [ -r $HostNameFile ] && [ -s $HostNameFile ]
+then
+ISE_HOST=$(cat $HostNameFile)
+elif [ X != X$HOSTNAME ]
+then
+ISE_HOST=$HOSTNAME #bash
+else
+ISE_HOST=$HOST #csh
+fi
+
+ISE_USER=$USER
+
+ISE_HOSTCORE=$(awk '/^processor/{print $3}' /proc/cpuinfo | wc -l)
+ISE_MEMTOTAL=$(awk '/MemTotal/ {print $2}' /proc/meminfo)
+
+ISE_BEGINFILE=.$ISE_STEP.begin.rst
+/bin/touch $ISE_BEGINFILE
+echo "<?xml version=\"1.0\"?>" >> $ISE_BEGINFILE
+echo "<ProcessHandle Version=\"1\" Minor=\"0\">" >> $ISE_BEGINFILE
+echo " <Process Command=\"$ISE_STEP\" Owner=\"$ISE_USER\" Host=\"$ISE_HOST\" Pid=\"$ISE_PID\" HostCore=\"$ISE_HOSTCORE\" HostMemory=\"$ISE_MEMTOTAL\">" >> $ISE_BEGINFILE
+echo " </Process>" >> $ISE_BEGINFILE
+echo "</ProcessHandle>" >> $ISE_BEGINFILE
+
+# WAIT for ISEStep to finish
+wait $ISE_PID
+
+# END/ERROR file creation
+RETVAL=$?
+if [ $RETVAL -eq 0 ]
+then
+ /bin/touch .$ISE_STEP.end.rst
+else
+ /bin/touch .$ISE_STEP.error.rst
+fi
+
+exit $RETVAL
+
diff --git a/game.runs/clk_wiz_0_synth_1/__synthesis_is_complete__ b/game.runs/clk_wiz_0_synth_1/__synthesis_is_complete__
new file mode 100644
index 0000000000000000000000000000000000000000..e69de29bb2d1d6434b8b29ae775ad8c2e48c5391
diff --git a/game.runs/clk_wiz_0_synth_1/clk_wiz_0.dcp b/game.runs/clk_wiz_0_synth_1/clk_wiz_0.dcp
new file mode 100644
index 0000000000000000000000000000000000000000..08b3e248e4bbd9eb3a5701ea43e6671ccdbfd720
Binary files /dev/null and b/game.runs/clk_wiz_0_synth_1/clk_wiz_0.dcp differ
diff --git a/game.runs/clk_wiz_0_synth_1/clk_wiz_0.tcl b/game.runs/clk_wiz_0_synth_1/clk_wiz_0.tcl
new file mode 100644
index 0000000000000000000000000000000000000000..06ff876e250b0c52d503fa81ac05c37a3e20e2d9
--- /dev/null
+++ b/game.runs/clk_wiz_0_synth_1/clk_wiz_0.tcl
@@ -0,0 +1,246 @@
+#
+# Synthesis run script generated by Vivado
+#
+
+set TIME_start [clock seconds]
+namespace eval ::optrace {
+ variable script "/home/prasic/game/game.runs/clk_wiz_0_synth_1/clk_wiz_0.tcl"
+ variable category "vivado_synth"
+}
+
+# Try to connect to running dispatch if we haven't done so already.
+# This code assumes that the Tcl interpreter is not using threads,
+# since the ::dispatch::connected variable isn't mutex protected.
+if {![info exists ::dispatch::connected]} {
+ namespace eval ::dispatch {
+ variable connected false
+ if {[llength [array get env XILINX_CD_CONNECT_ID]] > 0} {
+ set result "true"
+ if {[catch {
+ if {[lsearch -exact [package names] DispatchTcl] < 0} {
+ set result [load librdi_cd_clienttcl[info sharedlibextension]]
+ }
+ if {$result eq "false"} {
+ puts "WARNING: Could not load dispatch client library"
+ }
+ set connect_id [ ::dispatch::init_client -mode EXISTING_SERVER ]
+ if { $connect_id eq "" } {
+ puts "WARNING: Could not initialize dispatch client"
+ } else {
+ puts "INFO: Dispatch client connection id - $connect_id"
+ set connected true
+ }
+ } catch_res]} {
+ puts "WARNING: failed to connect to dispatch server - $catch_res"
+ }
+ }
+ }
+}
+if {$::dispatch::connected} {
+ # Remove the dummy proc if it exists.
+ if { [expr {[llength [info procs ::OPTRACE]] > 0}] } {
+ rename ::OPTRACE ""
+ }
+ proc ::OPTRACE { task action {tags {} } } {
+ ::vitis_log::op_trace "$task" $action -tags $tags -script $::optrace::script -category $::optrace::category
+ }
+ # dispatch is generic. We specifically want to attach logging.
+ ::vitis_log::connect_client
+} else {
+ # Add dummy proc if it doesn't exist.
+ if { [expr {[llength [info procs ::OPTRACE]] == 0}] } {
+ proc ::OPTRACE {{arg1 \"\" } {arg2 \"\"} {arg3 \"\" } {arg4 \"\"} {arg5 \"\" } {arg6 \"\"}} {
+ # Do nothing
+ }
+ }
+}
+
+proc create_report { reportName command } {
+ set status "."
+ append status $reportName ".fail"
+ if { [file exists $status] } {
+ eval file delete [glob $status]
+ }
+ send_msg_id runtcl-4 info "Executing : $command"
+ set retval [eval catch { $command } msg]
+ if { $retval != 0 } {
+ set fp [open $status w]
+ close $fp
+ send_msg_id runtcl-5 warning "$msg"
+ }
+}
+OPTRACE "clk_wiz_0_synth_1" START { ROLLUP_AUTO }
+set_param xicom.use_bs_reader 1
+set_param project.vivado.isBlockSynthRun true
+set_msg_config -msgmgr_mode ooc_run
+OPTRACE "Creating in-memory project" START { }
+create_project -in_memory -part xc7a100tcsg324-1
+
+set_param project.singleFileAddWarning.threshold 0
+set_param project.compositeFile.enableAutoGeneration 0
+set_param synth.vivado.isSynthRun true
+set_msg_config -source 4 -id {IP_Flow 19-2162} -severity warning -new_severity info
+set_property webtalk.parent_dir /home/prasic/game/game.cache/wt [current_project]
+set_property parent.project_path /home/prasic/game/game.xpr [current_project]
+set_property XPM_LIBRARIES XPM_CDC [current_project]
+set_property default_lib xil_defaultlib [current_project]
+set_property target_language VHDL [current_project]
+set_property ip_output_repo /home/prasic/game/game.cache/ip [current_project]
+set_property ip_cache_permissions {read write} [current_project]
+OPTRACE "Creating in-memory project" END { }
+OPTRACE "Adding files" START { }
+read_ip -quiet /home/prasic/game/game.srcs/sources_1/ip/clk_wiz_0/clk_wiz_0.xci
+set_property used_in_implementation false [get_files -all /home/prasic/game/game.gen/sources_1/ip/clk_wiz_0/clk_wiz_0_board.xdc]
+set_property used_in_implementation false [get_files -all /home/prasic/game/game.gen/sources_1/ip/clk_wiz_0/clk_wiz_0.xdc]
+set_property used_in_implementation false [get_files -all /home/prasic/game/game.gen/sources_1/ip/clk_wiz_0/clk_wiz_0_ooc.xdc]
+
+OPTRACE "Adding files" END { }
+# Mark all dcp files as not used in implementation to prevent them from being
+# stitched into the results of this synthesis run. Any black boxes in the
+# design are intentionally left as such for best results. Dcp files will be
+# stitched into the design at a later time, either when this synthesis run is
+# opened, or when it is stitched into a dependent implementation run.
+foreach dcp [get_files -quiet -all -filter file_type=="Design\ Checkpoint"] {
+ set_property used_in_implementation false $dcp
+}
+read_xdc dont_touch.xdc
+set_property used_in_implementation false [get_files dont_touch.xdc]
+set_param ips.enableIPCacheLiteLoad 1
+OPTRACE "Configure IP Cache" START { }
+
+set cacheID [config_ip_cache -export -no_bom -dir /home/prasic/game/game.runs/clk_wiz_0_synth_1 -new_name clk_wiz_0 -ip [get_ips clk_wiz_0]]
+
+OPTRACE "Configure IP Cache" END { }
+if { $cacheID == "" } {
+close [open __synthesis_is_running__ w]
+
+OPTRACE "synth_design" START { }
+synth_design -top clk_wiz_0 -part xc7a100tcsg324-1 -incremental_mode off -mode out_of_context
+OPTRACE "synth_design" END { }
+OPTRACE "Write IP Cache" START { }
+
+#---------------------------------------------------------
+# Generate Checkpoint/Stub/Simulation Files For IP Cache
+#---------------------------------------------------------
+# disable binary constraint mode for IPCache checkpoints
+set_param constraints.enableBinaryConstraints false
+
+catch {
+ write_checkpoint -force -noxdef -rename_prefix clk_wiz_0_ clk_wiz_0.dcp
+
+ set ipCachedFiles {}
+ write_verilog -force -mode synth_stub -rename_top decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix -prefix decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_ clk_wiz_0_stub.v
+ lappend ipCachedFiles clk_wiz_0_stub.v
+
+ write_vhdl -force -mode synth_stub -rename_top decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix -prefix decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_ clk_wiz_0_stub.vhdl
+ lappend ipCachedFiles clk_wiz_0_stub.vhdl
+
+ write_verilog -force -mode funcsim -rename_top decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix -prefix decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_ clk_wiz_0_sim_netlist.v
+ lappend ipCachedFiles clk_wiz_0_sim_netlist.v
+
+ write_vhdl -force -mode funcsim -rename_top decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix -prefix decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_ clk_wiz_0_sim_netlist.vhdl
+ lappend ipCachedFiles clk_wiz_0_sim_netlist.vhdl
+ set TIME_taken [expr [clock seconds] - $TIME_start]
+
+ if { [get_msg_config -count -severity {CRITICAL WARNING}] == 0 } {
+ config_ip_cache -add -dcp clk_wiz_0.dcp -move_files $ipCachedFiles -synth_runtime $TIME_taken -ip [get_ips clk_wiz_0]
+ }
+OPTRACE "Write IP Cache" END { }
+}
+if { [get_msg_config -count -severity {CRITICAL WARNING}] > 0 } {
+ send_msg_id runtcl-6 info "Synthesis results are not added to the cache due to CRITICAL_WARNING"
+}
+
+rename_ref -prefix_all clk_wiz_0_
+
+OPTRACE "write_checkpoint" START { CHECKPOINT }
+# disable binary constraint mode for synth run checkpoints
+set_param constraints.enableBinaryConstraints false
+write_checkpoint -force -noxdef clk_wiz_0.dcp
+OPTRACE "write_checkpoint" END { }
+OPTRACE "synth reports" START { REPORT }
+create_report "clk_wiz_0_synth_1_synth_report_utilization_0" "report_utilization -file clk_wiz_0_utilization_synth.rpt -pb clk_wiz_0_utilization_synth.pb"
+OPTRACE "synth reports" END { }
+
+if { [catch {
+ file copy -force /home/prasic/game/game.runs/clk_wiz_0_synth_1/clk_wiz_0.dcp /home/prasic/game/game.gen/sources_1/ip/clk_wiz_0/clk_wiz_0.dcp
+} _RESULT ] } {
+ send_msg_id runtcl-3 status "ERROR: Unable to successfully create or copy the sub-design checkpoint file."
+ error "ERROR: Unable to successfully create or copy the sub-design checkpoint file."
+}
+
+if { [catch {
+ write_verilog -force -mode synth_stub /home/prasic/game/game.gen/sources_1/ip/clk_wiz_0/clk_wiz_0_stub.v
+} _RESULT ] } {
+ puts "CRITICAL WARNING: Unable to successfully create a Verilog synthesis stub for the sub-design. This may lead to errors in top level synthesis of the design. Error reported: $_RESULT"
+}
+
+if { [catch {
+ write_vhdl -force -mode synth_stub /home/prasic/game/game.gen/sources_1/ip/clk_wiz_0/clk_wiz_0_stub.vhdl
+} _RESULT ] } {
+ puts "CRITICAL WARNING: Unable to successfully create a VHDL synthesis stub for the sub-design. This may lead to errors in top level synthesis of the design. Error reported: $_RESULT"
+}
+
+if { [catch {
+ write_verilog -force -mode funcsim /home/prasic/game/game.gen/sources_1/ip/clk_wiz_0/clk_wiz_0_sim_netlist.v
+} _RESULT ] } {
+ puts "CRITICAL WARNING: Unable to successfully create the Verilog functional simulation sub-design file. Post-Synthesis Functional Simulation with this file may not be possible or may give incorrect results. Error reported: $_RESULT"
+}
+
+if { [catch {
+ write_vhdl -force -mode funcsim /home/prasic/game/game.gen/sources_1/ip/clk_wiz_0/clk_wiz_0_sim_netlist.vhdl
+} _RESULT ] } {
+ puts "CRITICAL WARNING: Unable to successfully create the VHDL functional simulation sub-design file. Post-Synthesis Functional Simulation with this file may not be possible or may give incorrect results. Error reported: $_RESULT"
+}
+
+
+} else {
+
+
+if { [catch {
+ file copy -force /home/prasic/game/game.runs/clk_wiz_0_synth_1/clk_wiz_0.dcp /home/prasic/game/game.gen/sources_1/ip/clk_wiz_0/clk_wiz_0.dcp
+} _RESULT ] } {
+ send_msg_id runtcl-3 status "ERROR: Unable to successfully create or copy the sub-design checkpoint file."
+ error "ERROR: Unable to successfully create or copy the sub-design checkpoint file."
+}
+
+if { [catch {
+ file rename -force /home/prasic/game/game.runs/clk_wiz_0_synth_1/clk_wiz_0_stub.v /home/prasic/game/game.gen/sources_1/ip/clk_wiz_0/clk_wiz_0_stub.v
+} _RESULT ] } {
+ puts "CRITICAL WARNING: Unable to successfully create a Verilog synthesis stub for the sub-design. This may lead to errors in top level synthesis of the design. Error reported: $_RESULT"
+}
+
+if { [catch {
+ file rename -force /home/prasic/game/game.runs/clk_wiz_0_synth_1/clk_wiz_0_stub.vhdl /home/prasic/game/game.gen/sources_1/ip/clk_wiz_0/clk_wiz_0_stub.vhdl
+} _RESULT ] } {
+ puts "CRITICAL WARNING: Unable to successfully create a VHDL synthesis stub for the sub-design. This may lead to errors in top level synthesis of the design. Error reported: $_RESULT"
+}
+
+if { [catch {
+ file rename -force /home/prasic/game/game.runs/clk_wiz_0_synth_1/clk_wiz_0_sim_netlist.v /home/prasic/game/game.gen/sources_1/ip/clk_wiz_0/clk_wiz_0_sim_netlist.v
+} _RESULT ] } {
+ puts "CRITICAL WARNING: Unable to successfully create the Verilog functional simulation sub-design file. Post-Synthesis Functional Simulation with this file may not be possible or may give incorrect results. Error reported: $_RESULT"
+}
+
+if { [catch {
+ file rename -force /home/prasic/game/game.runs/clk_wiz_0_synth_1/clk_wiz_0_sim_netlist.vhdl /home/prasic/game/game.gen/sources_1/ip/clk_wiz_0/clk_wiz_0_sim_netlist.vhdl
+} _RESULT ] } {
+ puts "CRITICAL WARNING: Unable to successfully create the VHDL functional simulation sub-design file. Post-Synthesis Functional Simulation with this file may not be possible or may give incorrect results. Error reported: $_RESULT"
+}
+
+}; # end if cacheID
+
+if {[file isdir /home/prasic/game/game.ip_user_files/ip/clk_wiz_0]} {
+ catch {
+ file copy -force /home/prasic/game/game.gen/sources_1/ip/clk_wiz_0/clk_wiz_0_stub.v /home/prasic/game/game.ip_user_files/ip/clk_wiz_0
+ }
+}
+
+if {[file isdir /home/prasic/game/game.ip_user_files/ip/clk_wiz_0]} {
+ catch {
+ file copy -force /home/prasic/game/game.gen/sources_1/ip/clk_wiz_0/clk_wiz_0_stub.vhdl /home/prasic/game/game.ip_user_files/ip/clk_wiz_0
+ }
+}
+file delete __synthesis_is_running__
+close [open __synthesis_is_complete__ w]
+OPTRACE "clk_wiz_0_synth_1" END { }
diff --git a/game.runs/clk_wiz_0_synth_1/clk_wiz_0.vds b/game.runs/clk_wiz_0_synth_1/clk_wiz_0.vds
new file mode 100644
index 0000000000000000000000000000000000000000..61cd9e1577535a929fe2ce1bd6c6694184c4b676
--- /dev/null
+++ b/game.runs/clk_wiz_0_synth_1/clk_wiz_0.vds
@@ -0,0 +1,280 @@
+#-----------------------------------------------------------
+# Vivado v2022.2 (64-bit)
+# SW Build 3671981 on Fri Oct 14 04:59:54 MDT 2022
+# IP Build 3669848 on Fri Oct 14 08:30:02 MDT 2022
+# Start of session at: Mon Feb 27 10:46:19 2023
+# Process ID: 21266
+# Current directory: /home/prasic/game/game.runs/clk_wiz_0_synth_1
+# Command line: vivado -log clk_wiz_0.vds -product Vivado -mode batch -messageDb vivado.pb -notrace -source clk_wiz_0.tcl
+# Log file: /home/prasic/game/game.runs/clk_wiz_0_synth_1/clk_wiz_0.vds
+# Journal file: /home/prasic/game/game.runs/clk_wiz_0_synth_1/vivado.jou
+# Running On: LikeUE06, OS: Linux, CPU Frequency: 3167.195 MHz, CPU Physical cores: 4, Host memory: 16699 MB
+#-----------------------------------------------------------
+source clk_wiz_0.tcl -notrace
+INFO: [IP_Flow 19-6924] IPCACHE: Running cache check for IP inst: clk_wiz_0
+Command: synth_design -top clk_wiz_0 -part xc7a100tcsg324-1 -incremental_mode off -mode out_of_context
+Starting synth_design
+Attempting to get a license for feature 'Synthesis' and/or device 'xc7a100t'
+INFO: [Common 17-349] Got license for feature 'Synthesis' and/or device 'xc7a100t'
+INFO: [Device 21-403] Loading part xc7a100tcsg324-1
+INFO: [Synth 8-7079] Multithreading enabled for synth_design using a maximum of 4 processes.
+INFO: [Synth 8-7078] Launching helper process for spawning children vivado processes
+INFO: [Synth 8-7075] Helper process launched with PID 21293
+INFO: [Synth 8-11241] undeclared symbol 'REGCCE', assumed default net type 'wire' [/opt/Xilinx/Vivado/2022.2/data/verilog/src/unimacro/BRAM_SINGLE_MACRO.v:2170]
+---------------------------------------------------------------------------------
+Starting RTL Elaboration : Time (s): cpu = 00:00:03 ; elapsed = 00:00:04 . Memory (MB): peak = 1957.090 ; gain = 369.656 ; free physical = 6382 ; free virtual = 32373
+Synthesis current peak Physical Memory [PSS] (MB): peak = 1391.227; parent = 1181.156; children = 210.070
+Synthesis current peak Virtual Memory [VSS] (MB): peak = 2962.531; parent = 1960.062; children = 1002.469
+---------------------------------------------------------------------------------
+INFO: [Synth 8-6157] synthesizing module 'clk_wiz_0' [/home/prasic/game/game.gen/sources_1/ip/clk_wiz_0/clk_wiz_0.v:68]
+INFO: [Synth 8-6157] synthesizing module 'clk_wiz_0_clk_wiz' [/home/prasic/game/game.gen/sources_1/ip/clk_wiz_0/clk_wiz_0_clk_wiz.v:68]
+INFO: [Synth 8-6157] synthesizing module 'IBUF' [/opt/Xilinx/Vivado/2022.2/scripts/rt/data/unisim_comp.v:71326]
+INFO: [Synth 8-6155] done synthesizing module 'IBUF' (0#1) [/opt/Xilinx/Vivado/2022.2/scripts/rt/data/unisim_comp.v:71326]
+INFO: [Synth 8-6157] synthesizing module 'MMCME2_ADV' [/opt/Xilinx/Vivado/2022.2/scripts/rt/data/unisim_comp.v:79852]
+ Parameter BANDWIDTH bound to: OPTIMIZED - type: string
+ Parameter CLKFBOUT_MULT_F bound to: 9.125000 - type: double
+ Parameter CLKFBOUT_PHASE bound to: 0.000000 - type: double
+ Parameter CLKFBOUT_USE_FINE_PS bound to: FALSE - type: string
+ Parameter CLKIN1_PERIOD bound to: 10.000000 - type: double
+ Parameter CLKOUT0_DIVIDE_F bound to: 36.500000 - type: double
+ Parameter CLKOUT0_DUTY_CYCLE bound to: 0.500000 - type: double
+ Parameter CLKOUT0_PHASE bound to: 0.000000 - type: double
+ Parameter CLKOUT0_USE_FINE_PS bound to: FALSE - type: string
+ Parameter CLKOUT4_CASCADE bound to: FALSE - type: string
+ Parameter COMPENSATION bound to: ZHOLD - type: string
+ Parameter DIVCLK_DIVIDE bound to: 1 - type: integer
+ Parameter STARTUP_WAIT bound to: FALSE - type: string
+INFO: [Synth 8-6155] done synthesizing module 'MMCME2_ADV' (0#1) [/opt/Xilinx/Vivado/2022.2/scripts/rt/data/unisim_comp.v:79852]
+INFO: [Synth 8-6157] synthesizing module 'BUFG' [/opt/Xilinx/Vivado/2022.2/scripts/rt/data/unisim_comp.v:1082]
+INFO: [Synth 8-6155] done synthesizing module 'BUFG' (0#1) [/opt/Xilinx/Vivado/2022.2/scripts/rt/data/unisim_comp.v:1082]
+INFO: [Synth 8-6155] done synthesizing module 'clk_wiz_0_clk_wiz' (0#1) [/home/prasic/game/game.gen/sources_1/ip/clk_wiz_0/clk_wiz_0_clk_wiz.v:68]
+INFO: [Synth 8-6155] done synthesizing module 'clk_wiz_0' (0#1) [/home/prasic/game/game.gen/sources_1/ip/clk_wiz_0/clk_wiz_0.v:68]
+---------------------------------------------------------------------------------
+Finished RTL Elaboration : Time (s): cpu = 00:00:05 ; elapsed = 00:00:05 . Memory (MB): peak = 2025.027 ; gain = 437.594 ; free physical = 6471 ; free virtual = 32465
+Synthesis current peak Physical Memory [PSS] (MB): peak = 1391.227; parent = 1181.156; children = 210.070
+Synthesis current peak Virtual Memory [VSS] (MB): peak = 3027.500; parent = 2025.031; children = 1002.469
+---------------------------------------------------------------------------------
+---------------------------------------------------------------------------------
+Start Handling Custom Attributes
+---------------------------------------------------------------------------------
+---------------------------------------------------------------------------------
+Finished Handling Custom Attributes : Time (s): cpu = 00:00:05 ; elapsed = 00:00:05 . Memory (MB): peak = 2042.840 ; gain = 455.406 ; free physical = 6471 ; free virtual = 32464
+Synthesis current peak Physical Memory [PSS] (MB): peak = 1391.227; parent = 1181.156; children = 210.070
+Synthesis current peak Virtual Memory [VSS] (MB): peak = 3045.312; parent = 2042.844; children = 1002.469
+---------------------------------------------------------------------------------
+---------------------------------------------------------------------------------
+Finished RTL Optimization Phase 1 : Time (s): cpu = 00:00:05 ; elapsed = 00:00:05 . Memory (MB): peak = 2042.840 ; gain = 455.406 ; free physical = 6471 ; free virtual = 32464
+Synthesis current peak Physical Memory [PSS] (MB): peak = 1391.227; parent = 1181.156; children = 210.070
+Synthesis current peak Virtual Memory [VSS] (MB): peak = 3045.312; parent = 2042.844; children = 1002.469
+---------------------------------------------------------------------------------
+Netlist sorting complete. Time (s): cpu = 00:00:00 ; elapsed = 00:00:00 . Memory (MB): peak = 2048.777 ; gain = 0.000 ; free physical = 6463 ; free virtual = 32456
+INFO: [Netlist 29-17] Analyzing 1 Unisim elements for replacement
+INFO: [Netlist 29-28] Unisim Transformation completed in 0 CPU seconds
+INFO: [Project 1-570] Preparing netlist for logic optimization
+
+Processing XDC Constraints
+Initializing timing engine
+Parsing XDC File [/home/prasic/game/game.gen/sources_1/ip/clk_wiz_0/clk_wiz_0_ooc.xdc] for cell 'inst'
+Finished Parsing XDC File [/home/prasic/game/game.gen/sources_1/ip/clk_wiz_0/clk_wiz_0_ooc.xdc] for cell 'inst'
+Parsing XDC File [/home/prasic/game/game.gen/sources_1/ip/clk_wiz_0/clk_wiz_0_board.xdc] for cell 'inst'
+Finished Parsing XDC File [/home/prasic/game/game.gen/sources_1/ip/clk_wiz_0/clk_wiz_0_board.xdc] for cell 'inst'
+Parsing XDC File [/home/prasic/game/game.gen/sources_1/ip/clk_wiz_0/clk_wiz_0.xdc] for cell 'inst'
+Finished Parsing XDC File [/home/prasic/game/game.gen/sources_1/ip/clk_wiz_0/clk_wiz_0.xdc] for cell 'inst'
+INFO: [Project 1-236] Implementation specific constraints were found while reading constraint file [/home/prasic/game/game.gen/sources_1/ip/clk_wiz_0/clk_wiz_0.xdc]. These constraints will be ignored for synthesis but will be used in implementation. Impacted constraints are listed in the file [.Xil/clk_wiz_0_propImpl.xdc].
+Resolution: To avoid this warning, move constraints listed in [.Xil/clk_wiz_0_propImpl.xdc] to another XDC file and exclude this new file from synthesis with the used_in_synthesis property (File Properties dialog in GUI) and re-run elaboration/synthesis.
+INFO: [Timing 38-2] Deriving generated clocks
+Parsing XDC File [/home/prasic/game/game.runs/clk_wiz_0_synth_1/dont_touch.xdc]
+Finished Parsing XDC File [/home/prasic/game/game.runs/clk_wiz_0_synth_1/dont_touch.xdc]
+Completed Processing XDC Constraints
+
+Netlist sorting complete. Time (s): cpu = 00:00:00 ; elapsed = 00:00:00 . Memory (MB): peak = 2121.715 ; gain = 0.000 ; free physical = 6372 ; free virtual = 32379
+INFO: [Project 1-111] Unisim Transformation Summary:
+No Unisim elements were transformed.
+
+Constraint Validation Runtime : Time (s): cpu = 00:00:00.01 ; elapsed = 00:00:00 . Memory (MB): peak = 2121.715 ; gain = 0.000 ; free physical = 6372 ; free virtual = 32379
+INFO: [Designutils 20-5008] Incremental synthesis strategy off
+INFO: [Synth 8-11241] undeclared symbol 'REGCCE', assumed default net type 'wire' [/opt/Xilinx/Vivado/2022.2/data/verilog/src/unimacro/BRAM_SINGLE_MACRO.v:2170]
+---------------------------------------------------------------------------------
+Finished Constraint Validation : Time (s): cpu = 00:00:11 ; elapsed = 00:00:11 . Memory (MB): peak = 2121.715 ; gain = 534.281 ; free physical = 6429 ; free virtual = 32437
+Synthesis current peak Physical Memory [PSS] (MB): peak = 1391.227; parent = 1181.156; children = 210.070
+Synthesis current peak Virtual Memory [VSS] (MB): peak = 3092.172; parent = 2089.703; children = 1002.469
+---------------------------------------------------------------------------------
+---------------------------------------------------------------------------------
+Start Loading Part and Timing Information
+---------------------------------------------------------------------------------
+Loading part: xc7a100tcsg324-1
+---------------------------------------------------------------------------------
+Finished Loading Part and Timing Information : Time (s): cpu = 00:00:11 ; elapsed = 00:00:11 . Memory (MB): peak = 2121.715 ; gain = 534.281 ; free physical = 6429 ; free virtual = 32437
+Synthesis current peak Physical Memory [PSS] (MB): peak = 1391.227; parent = 1181.156; children = 210.070
+Synthesis current peak Virtual Memory [VSS] (MB): peak = 3092.172; parent = 2089.703; children = 1002.469
+---------------------------------------------------------------------------------
+---------------------------------------------------------------------------------
+Start Applying 'set_property' XDC Constraints
+---------------------------------------------------------------------------------
+Applied set_property KEEP_HIERARCHY = SOFT for inst. (constraint file /home/prasic/game/game.runs/clk_wiz_0_synth_1/dont_touch.xdc, line 9).
+---------------------------------------------------------------------------------
+Finished applying 'set_property' XDC Constraints : Time (s): cpu = 00:00:11 ; elapsed = 00:00:11 . Memory (MB): peak = 2121.715 ; gain = 534.281 ; free physical = 6432 ; free virtual = 32440
+Synthesis current peak Physical Memory [PSS] (MB): peak = 1391.227; parent = 1181.156; children = 210.070
+Synthesis current peak Virtual Memory [VSS] (MB): peak = 3092.172; parent = 2089.703; children = 1002.469
+---------------------------------------------------------------------------------
+---------------------------------------------------------------------------------
+Finished RTL Optimization Phase 2 : Time (s): cpu = 00:00:11 ; elapsed = 00:00:11 . Memory (MB): peak = 2121.715 ; gain = 534.281 ; free physical = 6430 ; free virtual = 32439
+Synthesis current peak Physical Memory [PSS] (MB): peak = 1391.227; parent = 1181.156; children = 210.070
+Synthesis current peak Virtual Memory [VSS] (MB): peak = 3092.172; parent = 2089.703; children = 1002.469
+---------------------------------------------------------------------------------
+---------------------------------------------------------------------------------
+Start RTL Component Statistics
+---------------------------------------------------------------------------------
+Detailed RTL Component Info :
+---------------------------------------------------------------------------------
+Finished RTL Component Statistics
+---------------------------------------------------------------------------------
+---------------------------------------------------------------------------------
+Start Part Resource Summary
+---------------------------------------------------------------------------------
+Part Resources:
+DSPs: 240 (col length:80)
+BRAMs: 270 (col length: RAMB18 80 RAMB36 40)
+---------------------------------------------------------------------------------
+Finished Part Resource Summary
+---------------------------------------------------------------------------------
+---------------------------------------------------------------------------------
+Start Cross Boundary and Area Optimization
+---------------------------------------------------------------------------------
+WARNING: [Synth 8-7080] Parallel synthesis criteria is not met
+---------------------------------------------------------------------------------
+Finished Cross Boundary and Area Optimization : Time (s): cpu = 00:00:12 ; elapsed = 00:00:12 . Memory (MB): peak = 2121.715 ; gain = 534.281 ; free physical = 6416 ; free virtual = 32429
+Synthesis current peak Physical Memory [PSS] (MB): peak = 1391.227; parent = 1181.156; children = 210.070
+Synthesis current peak Virtual Memory [VSS] (MB): peak = 3092.172; parent = 2089.703; children = 1002.469
+---------------------------------------------------------------------------------
+---------------------------------------------------------------------------------
+Start Applying XDC Timing Constraints
+---------------------------------------------------------------------------------
+---------------------------------------------------------------------------------
+Finished Applying XDC Timing Constraints : Time (s): cpu = 00:00:16 ; elapsed = 00:00:17 . Memory (MB): peak = 2121.715 ; gain = 534.281 ; free physical = 6294 ; free virtual = 32314
+Synthesis current peak Physical Memory [PSS] (MB): peak = 1472.491; parent = 1263.150; children = 210.070
+Synthesis current peak Virtual Memory [VSS] (MB): peak = 3092.172; parent = 2089.703; children = 1002.469
+---------------------------------------------------------------------------------
+---------------------------------------------------------------------------------
+Start Timing Optimization
+---------------------------------------------------------------------------------
+---------------------------------------------------------------------------------
+Finished Timing Optimization : Time (s): cpu = 00:00:16 ; elapsed = 00:00:17 . Memory (MB): peak = 2121.715 ; gain = 534.281 ; free physical = 6294 ; free virtual = 32314
+Synthesis current peak Physical Memory [PSS] (MB): peak = 1472.667; parent = 1263.330; children = 210.070
+Synthesis current peak Virtual Memory [VSS] (MB): peak = 3092.172; parent = 2089.703; children = 1002.469
+---------------------------------------------------------------------------------
+---------------------------------------------------------------------------------
+Start Technology Mapping
+---------------------------------------------------------------------------------
+---------------------------------------------------------------------------------
+Finished Technology Mapping : Time (s): cpu = 00:00:16 ; elapsed = 00:00:17 . Memory (MB): peak = 2121.715 ; gain = 534.281 ; free physical = 6293 ; free virtual = 32313
+Synthesis current peak Physical Memory [PSS] (MB): peak = 1472.929; parent = 1263.592; children = 210.070
+Synthesis current peak Virtual Memory [VSS] (MB): peak = 3092.172; parent = 2089.703; children = 1002.469
+---------------------------------------------------------------------------------
+---------------------------------------------------------------------------------
+Start IO Insertion
+---------------------------------------------------------------------------------
+---------------------------------------------------------------------------------
+Start Flattening Before IO Insertion
+---------------------------------------------------------------------------------
+---------------------------------------------------------------------------------
+Finished Flattening Before IO Insertion
+---------------------------------------------------------------------------------
+---------------------------------------------------------------------------------
+Start Final Netlist Cleanup
+---------------------------------------------------------------------------------
+---------------------------------------------------------------------------------
+Finished Final Netlist Cleanup
+---------------------------------------------------------------------------------
+---------------------------------------------------------------------------------
+Finished IO Insertion : Time (s): cpu = 00:00:19 ; elapsed = 00:00:20 . Memory (MB): peak = 2121.715 ; gain = 534.281 ; free physical = 6293 ; free virtual = 32313
+Synthesis current peak Physical Memory [PSS] (MB): peak = 1473.108; parent = 1263.771; children = 210.070
+Synthesis current peak Virtual Memory [VSS] (MB): peak = 3092.172; parent = 2089.703; children = 1002.469
+---------------------------------------------------------------------------------
+---------------------------------------------------------------------------------
+Start Renaming Generated Instances
+---------------------------------------------------------------------------------
+---------------------------------------------------------------------------------
+Finished Renaming Generated Instances : Time (s): cpu = 00:00:19 ; elapsed = 00:00:20 . Memory (MB): peak = 2121.715 ; gain = 534.281 ; free physical = 6293 ; free virtual = 32313
+Synthesis current peak Physical Memory [PSS] (MB): peak = 1473.187; parent = 1263.850; children = 210.070
+Synthesis current peak Virtual Memory [VSS] (MB): peak = 3092.172; parent = 2089.703; children = 1002.469
+---------------------------------------------------------------------------------
+---------------------------------------------------------------------------------
+Start Rebuilding User Hierarchy
+---------------------------------------------------------------------------------
+---------------------------------------------------------------------------------
+Finished Rebuilding User Hierarchy : Time (s): cpu = 00:00:19 ; elapsed = 00:00:20 . Memory (MB): peak = 2121.715 ; gain = 534.281 ; free physical = 6293 ; free virtual = 32313
+Synthesis current peak Physical Memory [PSS] (MB): peak = 1473.202; parent = 1263.865; children = 210.070
+Synthesis current peak Virtual Memory [VSS] (MB): peak = 3092.172; parent = 2089.703; children = 1002.469
+---------------------------------------------------------------------------------
+---------------------------------------------------------------------------------
+Start Renaming Generated Ports
+---------------------------------------------------------------------------------
+---------------------------------------------------------------------------------
+Finished Renaming Generated Ports : Time (s): cpu = 00:00:19 ; elapsed = 00:00:20 . Memory (MB): peak = 2121.715 ; gain = 534.281 ; free physical = 6293 ; free virtual = 32313
+Synthesis current peak Physical Memory [PSS] (MB): peak = 1473.202; parent = 1263.865; children = 210.070
+Synthesis current peak Virtual Memory [VSS] (MB): peak = 3092.172; parent = 2089.703; children = 1002.469
+---------------------------------------------------------------------------------
+---------------------------------------------------------------------------------
+Start Handling Custom Attributes
+---------------------------------------------------------------------------------
+---------------------------------------------------------------------------------
+Finished Handling Custom Attributes : Time (s): cpu = 00:00:19 ; elapsed = 00:00:20 . Memory (MB): peak = 2121.715 ; gain = 534.281 ; free physical = 6293 ; free virtual = 32313
+Synthesis current peak Physical Memory [PSS] (MB): peak = 1473.202; parent = 1263.865; children = 210.070
+Synthesis current peak Virtual Memory [VSS] (MB): peak = 3092.172; parent = 2089.703; children = 1002.469
+---------------------------------------------------------------------------------
+---------------------------------------------------------------------------------
+Start Renaming Generated Nets
+---------------------------------------------------------------------------------
+---------------------------------------------------------------------------------
+Finished Renaming Generated Nets : Time (s): cpu = 00:00:19 ; elapsed = 00:00:20 . Memory (MB): peak = 2121.715 ; gain = 534.281 ; free physical = 6293 ; free virtual = 32313
+Synthesis current peak Physical Memory [PSS] (MB): peak = 1473.218; parent = 1263.881; children = 210.070
+Synthesis current peak Virtual Memory [VSS] (MB): peak = 3092.172; parent = 2089.703; children = 1002.469
+---------------------------------------------------------------------------------
+---------------------------------------------------------------------------------
+Start Writing Synthesis Report
+---------------------------------------------------------------------------------
+
+Report BlackBoxes:
++-+--------------+----------+
+| |BlackBox name |Instances |
++-+--------------+----------+
++-+--------------+----------+
+
+Report Cell Usage:
++------+-----------+------+
+| |Cell |Count |
++------+-----------+------+
+|1 |BUFG | 2|
+|2 |LUT1 | 1|
+|3 |MMCME2_ADV | 1|
+|4 |IBUF | 1|
++------+-----------+------+
+---------------------------------------------------------------------------------
+Finished Writing Synthesis Report : Time (s): cpu = 00:00:19 ; elapsed = 00:00:20 . Memory (MB): peak = 2121.715 ; gain = 534.281 ; free physical = 6293 ; free virtual = 32313
+Synthesis current peak Physical Memory [PSS] (MB): peak = 1473.249; parent = 1263.912; children = 210.070
+Synthesis current peak Virtual Memory [VSS] (MB): peak = 3092.172; parent = 2089.703; children = 1002.469
+---------------------------------------------------------------------------------
+Synthesis finished with 0 errors, 0 critical warnings and 1 warnings.
+Synthesis Optimization Runtime : Time (s): cpu = 00:00:17 ; elapsed = 00:00:18 . Memory (MB): peak = 2121.715 ; gain = 455.406 ; free physical = 6344 ; free virtual = 32364
+Synthesis Optimization Complete : Time (s): cpu = 00:00:19 ; elapsed = 00:00:20 . Memory (MB): peak = 2121.715 ; gain = 534.281 ; free physical = 6344 ; free virtual = 32364
+INFO: [Project 1-571] Translating synthesized netlist
+Netlist sorting complete. Time (s): cpu = 00:00:00 ; elapsed = 00:00:00 . Memory (MB): peak = 2121.715 ; gain = 0.000 ; free physical = 6338 ; free virtual = 32358
+INFO: [Netlist 29-17] Analyzing 1 Unisim elements for replacement
+INFO: [Netlist 29-28] Unisim Transformation completed in 0 CPU seconds
+INFO: [Project 1-570] Preparing netlist for logic optimization
+INFO: [Opt 31-138] Pushed 0 inverter(s) to 0 load pin(s).
+Netlist sorting complete. Time (s): cpu = 00:00:00 ; elapsed = 00:00:00 . Memory (MB): peak = 2121.715 ; gain = 0.000 ; free physical = 6386 ; free virtual = 32408
+INFO: [Project 1-111] Unisim Transformation Summary:
+No Unisim elements were transformed.
+
+Synth Design complete, checksum: 5dda54c
+INFO: [Common 17-83] Releasing license: Synthesis
+32 Infos, 1 Warnings, 0 Critical Warnings and 0 Errors encountered.
+synth_design completed successfully
+synth_design: Time (s): cpu = 00:00:26 ; elapsed = 00:00:24 . Memory (MB): peak = 2121.715 ; gain = 860.691 ; free physical = 6591 ; free virtual = 32613
+INFO: [Common 17-1381] The checkpoint '/home/prasic/game/game.runs/clk_wiz_0_synth_1/clk_wiz_0.dcp' has been generated.
+INFO: [Coretcl 2-1648] Added synthesis output to IP cache for IP clk_wiz_0, cache-ID = 186611fea06d2870
+INFO: [Common 17-1381] The checkpoint '/home/prasic/game/game.runs/clk_wiz_0_synth_1/clk_wiz_0.dcp' has been generated.
+INFO: [runtcl-4] Executing : report_utilization -file clk_wiz_0_utilization_synth.rpt -pb clk_wiz_0_utilization_synth.pb
+INFO: [Common 17-206] Exiting Vivado at Mon Feb 27 10:46:52 2023...
diff --git a/game.runs/clk_wiz_0_synth_1/clk_wiz_0_utilization_synth.pb b/game.runs/clk_wiz_0_synth_1/clk_wiz_0_utilization_synth.pb
new file mode 100644
index 0000000000000000000000000000000000000000..e20e8f8455f49f15761ba815bebf973f13280a32
Binary files /dev/null and b/game.runs/clk_wiz_0_synth_1/clk_wiz_0_utilization_synth.pb differ
diff --git a/game.runs/clk_wiz_0_synth_1/clk_wiz_0_utilization_synth.rpt b/game.runs/clk_wiz_0_synth_1/clk_wiz_0_utilization_synth.rpt
new file mode 100644
index 0000000000000000000000000000000000000000..691f1dfac443e71fb31f88ed081acb2c7b2f17b2
--- /dev/null
+++ b/game.runs/clk_wiz_0_synth_1/clk_wiz_0_utilization_synth.rpt
@@ -0,0 +1,173 @@
+Copyright 1986-2022 Xilinx, Inc. All Rights Reserved.
+-------------------------------------------------------------------------------------------------------------
+| Tool Version : Vivado v.2022.2 (lin64) Build 3671981 Fri Oct 14 04:59:54 MDT 2022
+| Date : Mon Feb 27 10:46:52 2023
+| Host : LikeUE06 running 64-bit Linux Mint 20.3
+| Command : report_utilization -file clk_wiz_0_utilization_synth.rpt -pb clk_wiz_0_utilization_synth.pb
+| Design : clk_wiz_0
+| Device : xc7a100tcsg324-1
+| Speed File : -1
+| Design State : Synthesized
+-------------------------------------------------------------------------------------------------------------
+
+Utilization Design Information
+
+Table of Contents
+-----------------
+1. Slice Logic
+1.1 Summary of Registers by Type
+2. Memory
+3. DSP
+4. IO and GT Specific
+5. Clocking
+6. Specific Feature
+7. Primitives
+8. Black Boxes
+9. Instantiated Netlists
+
+1. Slice Logic
+--------------
+
++-------------------------+------+-------+------------+-----------+-------+
+| Site Type | Used | Fixed | Prohibited | Available | Util% |
++-------------------------+------+-------+------------+-----------+-------+
+| Slice LUTs* | 1 | 0 | 0 | 63400 | <0.01 |
+| LUT as Logic | 1 | 0 | 0 | 63400 | <0.01 |
+| LUT as Memory | 0 | 0 | 0 | 19000 | 0.00 |
+| Slice Registers | 0 | 0 | 0 | 126800 | 0.00 |
+| Register as Flip Flop | 0 | 0 | 0 | 126800 | 0.00 |
+| Register as Latch | 0 | 0 | 0 | 126800 | 0.00 |
+| F7 Muxes | 0 | 0 | 0 | 31700 | 0.00 |
+| F8 Muxes | 0 | 0 | 0 | 15850 | 0.00 |
++-------------------------+------+-------+------------+-----------+-------+
+* Warning! The Final LUT count, after physical optimizations and full implementation, is typically lower. Run opt_design after synthesis, if not already completed, for a more realistic count.
+Warning! LUT value is adjusted to account for LUT combining.
+
+
+1.1 Summary of Registers by Type
+--------------------------------
+
++-------+--------------+-------------+--------------+
+| Total | Clock Enable | Synchronous | Asynchronous |
++-------+--------------+-------------+--------------+
+| 0 | _ | - | - |
+| 0 | _ | - | Set |
+| 0 | _ | - | Reset |
+| 0 | _ | Set | - |
+| 0 | _ | Reset | - |
+| 0 | Yes | - | - |
+| 0 | Yes | - | Set |
+| 0 | Yes | - | Reset |
+| 0 | Yes | Set | - |
+| 0 | Yes | Reset | - |
++-------+--------------+-------------+--------------+
+
+
+2. Memory
+---------
+
++----------------+------+-------+------------+-----------+-------+
+| Site Type | Used | Fixed | Prohibited | Available | Util% |
++----------------+------+-------+------------+-----------+-------+
+| Block RAM Tile | 0 | 0 | 0 | 135 | 0.00 |
+| RAMB36/FIFO* | 0 | 0 | 0 | 135 | 0.00 |
+| RAMB18 | 0 | 0 | 0 | 270 | 0.00 |
++----------------+------+-------+------------+-----------+-------+
+* Note: Each Block RAM Tile only has one FIFO logic available and therefore can accommodate only one FIFO36E1 or one FIFO18E1. However, if a FIFO18E1 occupies a Block RAM Tile, that tile can still accommodate a RAMB18E1
+
+
+3. DSP
+------
+
++-----------+------+-------+------------+-----------+-------+
+| Site Type | Used | Fixed | Prohibited | Available | Util% |
++-----------+------+-------+------------+-----------+-------+
+| DSPs | 0 | 0 | 0 | 240 | 0.00 |
++-----------+------+-------+------------+-----------+-------+
+
+
+4. IO and GT Specific
+---------------------
+
++-----------------------------+------+-------+------------+-----------+-------+
+| Site Type | Used | Fixed | Prohibited | Available | Util% |
++-----------------------------+------+-------+------------+-----------+-------+
+| Bonded IOB | 1 | 0 | 0 | 210 | 0.48 |
+| Bonded IPADs | 0 | 0 | 0 | 2 | 0.00 |
+| PHY_CONTROL | 0 | 0 | 0 | 6 | 0.00 |
+| PHASER_REF | 0 | 0 | 0 | 6 | 0.00 |
+| OUT_FIFO | 0 | 0 | 0 | 24 | 0.00 |
+| IN_FIFO | 0 | 0 | 0 | 24 | 0.00 |
+| IDELAYCTRL | 0 | 0 | 0 | 6 | 0.00 |
+| IBUFDS | 0 | 0 | 0 | 202 | 0.00 |
+| PHASER_OUT/PHASER_OUT_PHY | 0 | 0 | 0 | 24 | 0.00 |
+| PHASER_IN/PHASER_IN_PHY | 0 | 0 | 0 | 24 | 0.00 |
+| IDELAYE2/IDELAYE2_FINEDELAY | 0 | 0 | 0 | 300 | 0.00 |
+| ILOGIC | 0 | 0 | 0 | 210 | 0.00 |
+| OLOGIC | 0 | 0 | 0 | 210 | 0.00 |
++-----------------------------+------+-------+------------+-----------+-------+
+
+
+5. Clocking
+-----------
+
++------------+------+-------+------------+-----------+-------+
+| Site Type | Used | Fixed | Prohibited | Available | Util% |
++------------+------+-------+------------+-----------+-------+
+| BUFGCTRL | 2 | 0 | 0 | 32 | 6.25 |
+| BUFIO | 0 | 0 | 0 | 24 | 0.00 |
+| MMCME2_ADV | 1 | 0 | 0 | 6 | 16.67 |
+| PLLE2_ADV | 0 | 0 | 0 | 6 | 0.00 |
+| BUFMRCE | 0 | 0 | 0 | 12 | 0.00 |
+| BUFHCE | 0 | 0 | 0 | 96 | 0.00 |
+| BUFR | 0 | 0 | 0 | 24 | 0.00 |
++------------+------+-------+------------+-----------+-------+
+
+
+6. Specific Feature
+-------------------
+
++-------------+------+-------+------------+-----------+-------+
+| Site Type | Used | Fixed | Prohibited | Available | Util% |
++-------------+------+-------+------------+-----------+-------+
+| BSCANE2 | 0 | 0 | 0 | 4 | 0.00 |
+| CAPTUREE2 | 0 | 0 | 0 | 1 | 0.00 |
+| DNA_PORT | 0 | 0 | 0 | 1 | 0.00 |
+| EFUSE_USR | 0 | 0 | 0 | 1 | 0.00 |
+| FRAME_ECCE2 | 0 | 0 | 0 | 1 | 0.00 |
+| ICAPE2 | 0 | 0 | 0 | 2 | 0.00 |
+| PCIE_2_1 | 0 | 0 | 0 | 1 | 0.00 |
+| STARTUPE2 | 0 | 0 | 0 | 1 | 0.00 |
+| XADC | 0 | 0 | 0 | 1 | 0.00 |
++-------------+------+-------+------------+-----------+-------+
+
+
+7. Primitives
+-------------
+
++------------+------+---------------------+
+| Ref Name | Used | Functional Category |
++------------+------+---------------------+
+| BUFG | 2 | Clock |
+| MMCME2_ADV | 1 | Clock |
+| LUT1 | 1 | LUT |
+| IBUF | 1 | IO |
++------------+------+---------------------+
+
+
+8. Black Boxes
+--------------
+
++----------+------+
+| Ref Name | Used |
++----------+------+
+
+
+9. Instantiated Netlists
+------------------------
+
++----------+------+
+| Ref Name | Used |
++----------+------+
+
+
diff --git a/game.runs/clk_wiz_0_synth_1/dont_touch.xdc b/game.runs/clk_wiz_0_synth_1/dont_touch.xdc
new file mode 100644
index 0000000000000000000000000000000000000000..2c3b700e1cf00f331a2e1ccb0a425eb454b8a52f
--- /dev/null
+++ b/game.runs/clk_wiz_0_synth_1/dont_touch.xdc
@@ -0,0 +1,32 @@
+# This file is automatically generated.
+# It contains project source information necessary for synthesis and implementation.
+
+# IP: /home/prasic/game/game.srcs/sources_1/ip/clk_wiz_0/clk_wiz_0.xci
+# IP: The module: 'clk_wiz_0' is the root of the design. Do not add the DONT_TOUCH constraint.
+
+# XDC: /home/prasic/game/game.gen/sources_1/ip/clk_wiz_0/clk_wiz_0_board.xdc
+# XDC: The top module name and the constraint reference have the same name: 'clk_wiz_0'. Do not add the DONT_TOUCH constraint.
+set_property KEEP_HIERARCHY SOFT [get_cells inst -quiet] -quiet
+
+# XDC: /home/prasic/game/game.gen/sources_1/ip/clk_wiz_0/clk_wiz_0.xdc
+# XDC: The top module name and the constraint reference have the same name: 'clk_wiz_0'. Do not add the DONT_TOUCH constraint.
+#dup# set_property KEEP_HIERARCHY SOFT [get_cells inst -quiet] -quiet
+
+# XDC: /home/prasic/game/game.gen/sources_1/ip/clk_wiz_0/clk_wiz_0_ooc.xdc
+# XDC: The top module name and the constraint reference have the same name: 'clk_wiz_0'. Do not add the DONT_TOUCH constraint.
+#dup# set_property KEEP_HIERARCHY SOFT [get_cells inst -quiet] -quiet
+
+# IP: /home/prasic/game/game.srcs/sources_1/ip/clk_wiz_0/clk_wiz_0.xci
+# IP: The module: 'clk_wiz_0' is the root of the design. Do not add the DONT_TOUCH constraint.
+
+# XDC: /home/prasic/game/game.gen/sources_1/ip/clk_wiz_0/clk_wiz_0_board.xdc
+# XDC: The top module name and the constraint reference have the same name: 'clk_wiz_0'. Do not add the DONT_TOUCH constraint.
+#dup# set_property KEEP_HIERARCHY SOFT [get_cells inst -quiet] -quiet
+
+# XDC: /home/prasic/game/game.gen/sources_1/ip/clk_wiz_0/clk_wiz_0.xdc
+# XDC: The top module name and the constraint reference have the same name: 'clk_wiz_0'. Do not add the DONT_TOUCH constraint.
+#dup# set_property KEEP_HIERARCHY SOFT [get_cells inst -quiet] -quiet
+
+# XDC: /home/prasic/game/game.gen/sources_1/ip/clk_wiz_0/clk_wiz_0_ooc.xdc
+# XDC: The top module name and the constraint reference have the same name: 'clk_wiz_0'. Do not add the DONT_TOUCH constraint.
+#dup# set_property KEEP_HIERARCHY SOFT [get_cells inst -quiet] -quiet
diff --git a/game.runs/clk_wiz_0_synth_1/gen_run.xml b/game.runs/clk_wiz_0_synth_1/gen_run.xml
new file mode 100644
index 0000000000000000000000000000000000000000..15401175875883766428ac5a5acbc896788f7cc8
--- /dev/null
+++ b/game.runs/clk_wiz_0_synth_1/gen_run.xml
@@ -0,0 +1,45 @@
+<?xml version="1.0" encoding="UTF-8"?>
+<GenRun Id="clk_wiz_0_synth_1" LaunchPart="xc7a100tcsg324-1" LaunchTime="1677491176">
+ <File Type="RDS-DCP" Name="clk_wiz_0.dcp"/>
+ <File Type="RDS-UTIL-PB" Name="clk_wiz_0_utilization_synth.pb"/>
+ <File Type="PA-TCL" Name="clk_wiz_0.tcl"/>
+ <File Type="RDS-UTIL" Name="clk_wiz_0_utilization_synth.rpt"/>
+ <File Type="REPORTS-TCL" Name="clk_wiz_0_reports.tcl"/>
+ <File Type="RDS-RDS" Name="clk_wiz_0.vds"/>
+ <FileSet Name="sources" Type="BlockSrcs" RelSrcDir="$PSRCDIR/clk_wiz_0">
+ <File Path="$PSRCDIR/sources_1/ip/clk_wiz_0/clk_wiz_0.xci">
+ <FileInfo>
+ <Attr Name="UsedIn" Val="synthesis"/>
+ <Attr Name="UsedIn" Val="implementation"/>
+ <Attr Name="UsedIn" Val="simulation"/>
+ </FileInfo>
+ </File>
+ <Config>
+ <Option Name="TopModule" Val="clk_wiz_0"/>
+ <Option Name="UseBlackboxStub" Val="1"/>
+ </Config>
+ </FileSet>
+ <FileSet Name="constrs_in" Type="BlockSrcs" RelSrcDir="$PSRCDIR/clk_wiz_0">
+ <File Path="$PSRCDIR/sources_1/ip/clk_wiz_0/clk_wiz_0.xci">
+ <FileInfo>
+ <Attr Name="UsedIn" Val="synthesis"/>
+ <Attr Name="UsedIn" Val="implementation"/>
+ <Attr Name="UsedIn" Val="simulation"/>
+ </FileInfo>
+ </File>
+ <Config>
+ <Option Name="TopModule" Val="clk_wiz_0"/>
+ <Option Name="UseBlackboxStub" Val="1"/>
+ </Config>
+ </FileSet>
+ <FileSet Name="utils" Type="Utils" RelSrcDir="$PSRCDIR/utils_1">
+ <Filter Type="Utils"/>
+ <Config>
+ <Option Name="TopAutoSet" Val="TRUE"/>
+ </Config>
+ </FileSet>
+ <Strategy Version="1" Minor="2">
+ <StratHandle Name="Vivado Synthesis Defaults" Flow="Vivado Synthesis 2022"/>
+ <Step Id="synth_design"/>
+ </Strategy>
+</GenRun>
diff --git a/game.runs/clk_wiz_0_synth_1/htr.txt b/game.runs/clk_wiz_0_synth_1/htr.txt
new file mode 100644
index 0000000000000000000000000000000000000000..3ddc6ff3dbf9b4450b0499e7b7374150323c1d5e
--- /dev/null
+++ b/game.runs/clk_wiz_0_synth_1/htr.txt
@@ -0,0 +1,9 @@
+#
+# Vivado(TM)
+# htr.txt: a Vivado-generated description of how-to-repeat the
+# the basic steps of a run. Note that runme.bat/sh needs
+# to be invoked for Vivado to track run status.
+# Copyright 1986-2022 Xilinx, Inc. All Rights Reserved.
+#
+
+vivado -log clk_wiz_0.vds -m64 -product Vivado -mode batch -messageDb vivado.pb -notrace -source clk_wiz_0.tcl
diff --git a/game.runs/clk_wiz_0_synth_1/project.wdf b/game.runs/clk_wiz_0_synth_1/project.wdf
new file mode 100644
index 0000000000000000000000000000000000000000..4cc2dc612e9c18c416a2099550e92039bab551cc
--- /dev/null
+++ b/game.runs/clk_wiz_0_synth_1/project.wdf
@@ -0,0 +1,32 @@
+version:1
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+70726f6a656374:76697661646f5f75736167655c70726f6a6563745f64617461:6578706f72745f73696d756c6174696f6e5f61637469766568646c:30:00:00
+5f5f48494444454e5f5f:5f5f48494444454e5f5f:50726f6a65637455554944:6636316632346539316466643436376561323639363231653035643630613965:506172656e742050412070726f6a656374204944:00
+eof:2446048647
diff --git a/game.runs/clk_wiz_0_synth_1/rundef.js b/game.runs/clk_wiz_0_synth_1/rundef.js
new file mode 100644
index 0000000000000000000000000000000000000000..c1782fc908f6cde15ab6916900587e2b5a6daaa6
--- /dev/null
+++ b/game.runs/clk_wiz_0_synth_1/rundef.js
@@ -0,0 +1,40 @@
+//
+// Vivado(TM)
+// rundef.js: a Vivado-generated Runs Script for WSH 5.1/5.6
+// Copyright 1986-2022 Xilinx, Inc. All Rights Reserved.
+//
+
+echo "This script was generated under a different operating system."
+echo "Please update the PATH variable below, before executing this script"
+exit
+
+var WshShell = new ActiveXObject( "WScript.Shell" );
+var ProcEnv = WshShell.Environment( "Process" );
+var PathVal = ProcEnv("PATH");
+if ( PathVal.length == 0 ) {
+ PathVal = "/opt/Xilinx/Vivado/2022.2/ids_lite/ISE/bin/lin64;/opt/Xilinx/Vivado/2022.2/bin;";
+} else {
+ PathVal = "/opt/Xilinx/Vivado/2022.2/ids_lite/ISE/bin/lin64;/opt/Xilinx/Vivado/2022.2/bin;" + PathVal;
+}
+
+ProcEnv("PATH") = PathVal;
+
+var RDScrFP = WScript.ScriptFullName;
+var RDScrN = WScript.ScriptName;
+var RDScrDir = RDScrFP.substr( 0, RDScrFP.length - RDScrN.length - 1 );
+var ISEJScriptLib = RDScrDir + "/ISEWrap.js";
+eval( EAInclude(ISEJScriptLib) );
+
+
+ISEStep( "vivado",
+ "-log clk_wiz_0.vds -m64 -product Vivado -mode batch -messageDb vivado.pb -notrace -source clk_wiz_0.tcl" );
+
+
+
+function EAInclude( EAInclFilename ) {
+ var EAFso = new ActiveXObject( "Scripting.FileSystemObject" );
+ var EAInclFile = EAFso.OpenTextFile( EAInclFilename );
+ var EAIFContents = EAInclFile.ReadAll();
+ EAInclFile.Close();
+ return EAIFContents;
+}
diff --git a/game.runs/clk_wiz_0_synth_1/runme.bat b/game.runs/clk_wiz_0_synth_1/runme.bat
new file mode 100644
index 0000000000000000000000000000000000000000..c51ae31743272e84250ece027d86207732473138
--- /dev/null
+++ b/game.runs/clk_wiz_0_synth_1/runme.bat
@@ -0,0 +1,11 @@
+@echo off
+
+rem Vivado (TM)
+rem runme.bat: a Vivado-generated Script
+rem Copyright 1986-2022 Xilinx, Inc. All Rights Reserved.
+
+
+set HD_SDIR=%~dp0
+cd /d "%HD_SDIR%"
+set PATH=%SYSTEMROOT%\system32;%PATH%
+cscript /nologo /E:JScript "%HD_SDIR%\rundef.js" %*
diff --git a/game.runs/clk_wiz_0_synth_1/runme.log b/game.runs/clk_wiz_0_synth_1/runme.log
new file mode 100644
index 0000000000000000000000000000000000000000..a2e99d1bc09f02af16252ea51d1945b0f74ff440
--- /dev/null
+++ b/game.runs/clk_wiz_0_synth_1/runme.log
@@ -0,0 +1,278 @@
+
+*** Running vivado
+ with args -log clk_wiz_0.vds -m64 -product Vivado -mode batch -messageDb vivado.pb -notrace -source clk_wiz_0.tcl
+
+
+****** Vivado v2022.2 (64-bit)
+ **** SW Build 3671981 on Fri Oct 14 04:59:54 MDT 2022
+ **** IP Build 3669848 on Fri Oct 14 08:30:02 MDT 2022
+ ** Copyright 1986-2022 Xilinx, Inc. All Rights Reserved.
+
+source clk_wiz_0.tcl -notrace
+INFO: [IP_Flow 19-6924] IPCACHE: Running cache check for IP inst: clk_wiz_0
+Command: synth_design -top clk_wiz_0 -part xc7a100tcsg324-1 -incremental_mode off -mode out_of_context
+Starting synth_design
+Attempting to get a license for feature 'Synthesis' and/or device 'xc7a100t'
+INFO: [Common 17-349] Got license for feature 'Synthesis' and/or device 'xc7a100t'
+INFO: [Device 21-403] Loading part xc7a100tcsg324-1
+INFO: [Synth 8-7079] Multithreading enabled for synth_design using a maximum of 4 processes.
+INFO: [Synth 8-7078] Launching helper process for spawning children vivado processes
+INFO: [Synth 8-7075] Helper process launched with PID 21293
+INFO: [Synth 8-11241] undeclared symbol 'REGCCE', assumed default net type 'wire' [/opt/Xilinx/Vivado/2022.2/data/verilog/src/unimacro/BRAM_SINGLE_MACRO.v:2170]
+---------------------------------------------------------------------------------
+Starting RTL Elaboration : Time (s): cpu = 00:00:03 ; elapsed = 00:00:04 . Memory (MB): peak = 1957.090 ; gain = 369.656 ; free physical = 6382 ; free virtual = 32373
+Synthesis current peak Physical Memory [PSS] (MB): peak = 1391.227; parent = 1181.156; children = 210.070
+Synthesis current peak Virtual Memory [VSS] (MB): peak = 2962.531; parent = 1960.062; children = 1002.469
+---------------------------------------------------------------------------------
+INFO: [Synth 8-6157] synthesizing module 'clk_wiz_0' [/home/prasic/game/game.gen/sources_1/ip/clk_wiz_0/clk_wiz_0.v:68]
+INFO: [Synth 8-6157] synthesizing module 'clk_wiz_0_clk_wiz' [/home/prasic/game/game.gen/sources_1/ip/clk_wiz_0/clk_wiz_0_clk_wiz.v:68]
+INFO: [Synth 8-6157] synthesizing module 'IBUF' [/opt/Xilinx/Vivado/2022.2/scripts/rt/data/unisim_comp.v:71326]
+INFO: [Synth 8-6155] done synthesizing module 'IBUF' (0#1) [/opt/Xilinx/Vivado/2022.2/scripts/rt/data/unisim_comp.v:71326]
+INFO: [Synth 8-6157] synthesizing module 'MMCME2_ADV' [/opt/Xilinx/Vivado/2022.2/scripts/rt/data/unisim_comp.v:79852]
+ Parameter BANDWIDTH bound to: OPTIMIZED - type: string
+ Parameter CLKFBOUT_MULT_F bound to: 9.125000 - type: double
+ Parameter CLKFBOUT_PHASE bound to: 0.000000 - type: double
+ Parameter CLKFBOUT_USE_FINE_PS bound to: FALSE - type: string
+ Parameter CLKIN1_PERIOD bound to: 10.000000 - type: double
+ Parameter CLKOUT0_DIVIDE_F bound to: 36.500000 - type: double
+ Parameter CLKOUT0_DUTY_CYCLE bound to: 0.500000 - type: double
+ Parameter CLKOUT0_PHASE bound to: 0.000000 - type: double
+ Parameter CLKOUT0_USE_FINE_PS bound to: FALSE - type: string
+ Parameter CLKOUT4_CASCADE bound to: FALSE - type: string
+ Parameter COMPENSATION bound to: ZHOLD - type: string
+ Parameter DIVCLK_DIVIDE bound to: 1 - type: integer
+ Parameter STARTUP_WAIT bound to: FALSE - type: string
+INFO: [Synth 8-6155] done synthesizing module 'MMCME2_ADV' (0#1) [/opt/Xilinx/Vivado/2022.2/scripts/rt/data/unisim_comp.v:79852]
+INFO: [Synth 8-6157] synthesizing module 'BUFG' [/opt/Xilinx/Vivado/2022.2/scripts/rt/data/unisim_comp.v:1082]
+INFO: [Synth 8-6155] done synthesizing module 'BUFG' (0#1) [/opt/Xilinx/Vivado/2022.2/scripts/rt/data/unisim_comp.v:1082]
+INFO: [Synth 8-6155] done synthesizing module 'clk_wiz_0_clk_wiz' (0#1) [/home/prasic/game/game.gen/sources_1/ip/clk_wiz_0/clk_wiz_0_clk_wiz.v:68]
+INFO: [Synth 8-6155] done synthesizing module 'clk_wiz_0' (0#1) [/home/prasic/game/game.gen/sources_1/ip/clk_wiz_0/clk_wiz_0.v:68]
+---------------------------------------------------------------------------------
+Finished RTL Elaboration : Time (s): cpu = 00:00:05 ; elapsed = 00:00:05 . Memory (MB): peak = 2025.027 ; gain = 437.594 ; free physical = 6471 ; free virtual = 32465
+Synthesis current peak Physical Memory [PSS] (MB): peak = 1391.227; parent = 1181.156; children = 210.070
+Synthesis current peak Virtual Memory [VSS] (MB): peak = 3027.500; parent = 2025.031; children = 1002.469
+---------------------------------------------------------------------------------
+---------------------------------------------------------------------------------
+Start Handling Custom Attributes
+---------------------------------------------------------------------------------
+---------------------------------------------------------------------------------
+Finished Handling Custom Attributes : Time (s): cpu = 00:00:05 ; elapsed = 00:00:05 . Memory (MB): peak = 2042.840 ; gain = 455.406 ; free physical = 6471 ; free virtual = 32464
+Synthesis current peak Physical Memory [PSS] (MB): peak = 1391.227; parent = 1181.156; children = 210.070
+Synthesis current peak Virtual Memory [VSS] (MB): peak = 3045.312; parent = 2042.844; children = 1002.469
+---------------------------------------------------------------------------------
+---------------------------------------------------------------------------------
+Finished RTL Optimization Phase 1 : Time (s): cpu = 00:00:05 ; elapsed = 00:00:05 . Memory (MB): peak = 2042.840 ; gain = 455.406 ; free physical = 6471 ; free virtual = 32464
+Synthesis current peak Physical Memory [PSS] (MB): peak = 1391.227; parent = 1181.156; children = 210.070
+Synthesis current peak Virtual Memory [VSS] (MB): peak = 3045.312; parent = 2042.844; children = 1002.469
+---------------------------------------------------------------------------------
+Netlist sorting complete. Time (s): cpu = 00:00:00 ; elapsed = 00:00:00 . Memory (MB): peak = 2048.777 ; gain = 0.000 ; free physical = 6463 ; free virtual = 32456
+INFO: [Netlist 29-17] Analyzing 1 Unisim elements for replacement
+INFO: [Netlist 29-28] Unisim Transformation completed in 0 CPU seconds
+INFO: [Project 1-570] Preparing netlist for logic optimization
+
+Processing XDC Constraints
+Initializing timing engine
+Parsing XDC File [/home/prasic/game/game.gen/sources_1/ip/clk_wiz_0/clk_wiz_0_ooc.xdc] for cell 'inst'
+Finished Parsing XDC File [/home/prasic/game/game.gen/sources_1/ip/clk_wiz_0/clk_wiz_0_ooc.xdc] for cell 'inst'
+Parsing XDC File [/home/prasic/game/game.gen/sources_1/ip/clk_wiz_0/clk_wiz_0_board.xdc] for cell 'inst'
+Finished Parsing XDC File [/home/prasic/game/game.gen/sources_1/ip/clk_wiz_0/clk_wiz_0_board.xdc] for cell 'inst'
+Parsing XDC File [/home/prasic/game/game.gen/sources_1/ip/clk_wiz_0/clk_wiz_0.xdc] for cell 'inst'
+Finished Parsing XDC File [/home/prasic/game/game.gen/sources_1/ip/clk_wiz_0/clk_wiz_0.xdc] for cell 'inst'
+INFO: [Project 1-236] Implementation specific constraints were found while reading constraint file [/home/prasic/game/game.gen/sources_1/ip/clk_wiz_0/clk_wiz_0.xdc]. These constraints will be ignored for synthesis but will be used in implementation. Impacted constraints are listed in the file [.Xil/clk_wiz_0_propImpl.xdc].
+Resolution: To avoid this warning, move constraints listed in [.Xil/clk_wiz_0_propImpl.xdc] to another XDC file and exclude this new file from synthesis with the used_in_synthesis property (File Properties dialog in GUI) and re-run elaboration/synthesis.
+INFO: [Timing 38-2] Deriving generated clocks
+Parsing XDC File [/home/prasic/game/game.runs/clk_wiz_0_synth_1/dont_touch.xdc]
+Finished Parsing XDC File [/home/prasic/game/game.runs/clk_wiz_0_synth_1/dont_touch.xdc]
+Completed Processing XDC Constraints
+
+Netlist sorting complete. Time (s): cpu = 00:00:00 ; elapsed = 00:00:00 . Memory (MB): peak = 2121.715 ; gain = 0.000 ; free physical = 6372 ; free virtual = 32379
+INFO: [Project 1-111] Unisim Transformation Summary:
+No Unisim elements were transformed.
+
+Constraint Validation Runtime : Time (s): cpu = 00:00:00.01 ; elapsed = 00:00:00 . Memory (MB): peak = 2121.715 ; gain = 0.000 ; free physical = 6372 ; free virtual = 32379
+INFO: [Designutils 20-5008] Incremental synthesis strategy off
+INFO: [Synth 8-11241] undeclared symbol 'REGCCE', assumed default net type 'wire' [/opt/Xilinx/Vivado/2022.2/data/verilog/src/unimacro/BRAM_SINGLE_MACRO.v:2170]
+---------------------------------------------------------------------------------
+Finished Constraint Validation : Time (s): cpu = 00:00:11 ; elapsed = 00:00:11 . Memory (MB): peak = 2121.715 ; gain = 534.281 ; free physical = 6429 ; free virtual = 32437
+Synthesis current peak Physical Memory [PSS] (MB): peak = 1391.227; parent = 1181.156; children = 210.070
+Synthesis current peak Virtual Memory [VSS] (MB): peak = 3092.172; parent = 2089.703; children = 1002.469
+---------------------------------------------------------------------------------
+---------------------------------------------------------------------------------
+Start Loading Part and Timing Information
+---------------------------------------------------------------------------------
+Loading part: xc7a100tcsg324-1
+---------------------------------------------------------------------------------
+Finished Loading Part and Timing Information : Time (s): cpu = 00:00:11 ; elapsed = 00:00:11 . Memory (MB): peak = 2121.715 ; gain = 534.281 ; free physical = 6429 ; free virtual = 32437
+Synthesis current peak Physical Memory [PSS] (MB): peak = 1391.227; parent = 1181.156; children = 210.070
+Synthesis current peak Virtual Memory [VSS] (MB): peak = 3092.172; parent = 2089.703; children = 1002.469
+---------------------------------------------------------------------------------
+---------------------------------------------------------------------------------
+Start Applying 'set_property' XDC Constraints
+---------------------------------------------------------------------------------
+Applied set_property KEEP_HIERARCHY = SOFT for inst. (constraint file /home/prasic/game/game.runs/clk_wiz_0_synth_1/dont_touch.xdc, line 9).
+---------------------------------------------------------------------------------
+Finished applying 'set_property' XDC Constraints : Time (s): cpu = 00:00:11 ; elapsed = 00:00:11 . Memory (MB): peak = 2121.715 ; gain = 534.281 ; free physical = 6432 ; free virtual = 32440
+Synthesis current peak Physical Memory [PSS] (MB): peak = 1391.227; parent = 1181.156; children = 210.070
+Synthesis current peak Virtual Memory [VSS] (MB): peak = 3092.172; parent = 2089.703; children = 1002.469
+---------------------------------------------------------------------------------
+---------------------------------------------------------------------------------
+Finished RTL Optimization Phase 2 : Time (s): cpu = 00:00:11 ; elapsed = 00:00:11 . Memory (MB): peak = 2121.715 ; gain = 534.281 ; free physical = 6430 ; free virtual = 32439
+Synthesis current peak Physical Memory [PSS] (MB): peak = 1391.227; parent = 1181.156; children = 210.070
+Synthesis current peak Virtual Memory [VSS] (MB): peak = 3092.172; parent = 2089.703; children = 1002.469
+---------------------------------------------------------------------------------
+---------------------------------------------------------------------------------
+Start RTL Component Statistics
+---------------------------------------------------------------------------------
+Detailed RTL Component Info :
+---------------------------------------------------------------------------------
+Finished RTL Component Statistics
+---------------------------------------------------------------------------------
+---------------------------------------------------------------------------------
+Start Part Resource Summary
+---------------------------------------------------------------------------------
+Part Resources:
+DSPs: 240 (col length:80)
+BRAMs: 270 (col length: RAMB18 80 RAMB36 40)
+---------------------------------------------------------------------------------
+Finished Part Resource Summary
+---------------------------------------------------------------------------------
+---------------------------------------------------------------------------------
+Start Cross Boundary and Area Optimization
+---------------------------------------------------------------------------------
+WARNING: [Synth 8-7080] Parallel synthesis criteria is not met
+---------------------------------------------------------------------------------
+Finished Cross Boundary and Area Optimization : Time (s): cpu = 00:00:12 ; elapsed = 00:00:12 . Memory (MB): peak = 2121.715 ; gain = 534.281 ; free physical = 6416 ; free virtual = 32429
+Synthesis current peak Physical Memory [PSS] (MB): peak = 1391.227; parent = 1181.156; children = 210.070
+Synthesis current peak Virtual Memory [VSS] (MB): peak = 3092.172; parent = 2089.703; children = 1002.469
+---------------------------------------------------------------------------------
+---------------------------------------------------------------------------------
+Start Applying XDC Timing Constraints
+---------------------------------------------------------------------------------
+---------------------------------------------------------------------------------
+Finished Applying XDC Timing Constraints : Time (s): cpu = 00:00:16 ; elapsed = 00:00:17 . Memory (MB): peak = 2121.715 ; gain = 534.281 ; free physical = 6294 ; free virtual = 32314
+Synthesis current peak Physical Memory [PSS] (MB): peak = 1472.491; parent = 1263.150; children = 210.070
+Synthesis current peak Virtual Memory [VSS] (MB): peak = 3092.172; parent = 2089.703; children = 1002.469
+---------------------------------------------------------------------------------
+---------------------------------------------------------------------------------
+Start Timing Optimization
+---------------------------------------------------------------------------------
+---------------------------------------------------------------------------------
+Finished Timing Optimization : Time (s): cpu = 00:00:16 ; elapsed = 00:00:17 . Memory (MB): peak = 2121.715 ; gain = 534.281 ; free physical = 6294 ; free virtual = 32314
+Synthesis current peak Physical Memory [PSS] (MB): peak = 1472.667; parent = 1263.330; children = 210.070
+Synthesis current peak Virtual Memory [VSS] (MB): peak = 3092.172; parent = 2089.703; children = 1002.469
+---------------------------------------------------------------------------------
+---------------------------------------------------------------------------------
+Start Technology Mapping
+---------------------------------------------------------------------------------
+---------------------------------------------------------------------------------
+Finished Technology Mapping : Time (s): cpu = 00:00:16 ; elapsed = 00:00:17 . Memory (MB): peak = 2121.715 ; gain = 534.281 ; free physical = 6293 ; free virtual = 32313
+Synthesis current peak Physical Memory [PSS] (MB): peak = 1472.929; parent = 1263.592; children = 210.070
+Synthesis current peak Virtual Memory [VSS] (MB): peak = 3092.172; parent = 2089.703; children = 1002.469
+---------------------------------------------------------------------------------
+---------------------------------------------------------------------------------
+Start IO Insertion
+---------------------------------------------------------------------------------
+---------------------------------------------------------------------------------
+Start Flattening Before IO Insertion
+---------------------------------------------------------------------------------
+---------------------------------------------------------------------------------
+Finished Flattening Before IO Insertion
+---------------------------------------------------------------------------------
+---------------------------------------------------------------------------------
+Start Final Netlist Cleanup
+---------------------------------------------------------------------------------
+---------------------------------------------------------------------------------
+Finished Final Netlist Cleanup
+---------------------------------------------------------------------------------
+---------------------------------------------------------------------------------
+Finished IO Insertion : Time (s): cpu = 00:00:19 ; elapsed = 00:00:20 . Memory (MB): peak = 2121.715 ; gain = 534.281 ; free physical = 6293 ; free virtual = 32313
+Synthesis current peak Physical Memory [PSS] (MB): peak = 1473.108; parent = 1263.771; children = 210.070
+Synthesis current peak Virtual Memory [VSS] (MB): peak = 3092.172; parent = 2089.703; children = 1002.469
+---------------------------------------------------------------------------------
+---------------------------------------------------------------------------------
+Start Renaming Generated Instances
+---------------------------------------------------------------------------------
+---------------------------------------------------------------------------------
+Finished Renaming Generated Instances : Time (s): cpu = 00:00:19 ; elapsed = 00:00:20 . Memory (MB): peak = 2121.715 ; gain = 534.281 ; free physical = 6293 ; free virtual = 32313
+Synthesis current peak Physical Memory [PSS] (MB): peak = 1473.187; parent = 1263.850; children = 210.070
+Synthesis current peak Virtual Memory [VSS] (MB): peak = 3092.172; parent = 2089.703; children = 1002.469
+---------------------------------------------------------------------------------
+---------------------------------------------------------------------------------
+Start Rebuilding User Hierarchy
+---------------------------------------------------------------------------------
+---------------------------------------------------------------------------------
+Finished Rebuilding User Hierarchy : Time (s): cpu = 00:00:19 ; elapsed = 00:00:20 . Memory (MB): peak = 2121.715 ; gain = 534.281 ; free physical = 6293 ; free virtual = 32313
+Synthesis current peak Physical Memory [PSS] (MB): peak = 1473.202; parent = 1263.865; children = 210.070
+Synthesis current peak Virtual Memory [VSS] (MB): peak = 3092.172; parent = 2089.703; children = 1002.469
+---------------------------------------------------------------------------------
+---------------------------------------------------------------------------------
+Start Renaming Generated Ports
+---------------------------------------------------------------------------------
+---------------------------------------------------------------------------------
+Finished Renaming Generated Ports : Time (s): cpu = 00:00:19 ; elapsed = 00:00:20 . Memory (MB): peak = 2121.715 ; gain = 534.281 ; free physical = 6293 ; free virtual = 32313
+Synthesis current peak Physical Memory [PSS] (MB): peak = 1473.202; parent = 1263.865; children = 210.070
+Synthesis current peak Virtual Memory [VSS] (MB): peak = 3092.172; parent = 2089.703; children = 1002.469
+---------------------------------------------------------------------------------
+---------------------------------------------------------------------------------
+Start Handling Custom Attributes
+---------------------------------------------------------------------------------
+---------------------------------------------------------------------------------
+Finished Handling Custom Attributes : Time (s): cpu = 00:00:19 ; elapsed = 00:00:20 . Memory (MB): peak = 2121.715 ; gain = 534.281 ; free physical = 6293 ; free virtual = 32313
+Synthesis current peak Physical Memory [PSS] (MB): peak = 1473.202; parent = 1263.865; children = 210.070
+Synthesis current peak Virtual Memory [VSS] (MB): peak = 3092.172; parent = 2089.703; children = 1002.469
+---------------------------------------------------------------------------------
+---------------------------------------------------------------------------------
+Start Renaming Generated Nets
+---------------------------------------------------------------------------------
+---------------------------------------------------------------------------------
+Finished Renaming Generated Nets : Time (s): cpu = 00:00:19 ; elapsed = 00:00:20 . Memory (MB): peak = 2121.715 ; gain = 534.281 ; free physical = 6293 ; free virtual = 32313
+Synthesis current peak Physical Memory [PSS] (MB): peak = 1473.218; parent = 1263.881; children = 210.070
+Synthesis current peak Virtual Memory [VSS] (MB): peak = 3092.172; parent = 2089.703; children = 1002.469
+---------------------------------------------------------------------------------
+---------------------------------------------------------------------------------
+Start Writing Synthesis Report
+---------------------------------------------------------------------------------
+
+Report BlackBoxes:
++-+--------------+----------+
+| |BlackBox name |Instances |
++-+--------------+----------+
++-+--------------+----------+
+
+Report Cell Usage:
++------+-----------+------+
+| |Cell |Count |
++------+-----------+------+
+|1 |BUFG | 2|
+|2 |LUT1 | 1|
+|3 |MMCME2_ADV | 1|
+|4 |IBUF | 1|
++------+-----------+------+
+---------------------------------------------------------------------------------
+Finished Writing Synthesis Report : Time (s): cpu = 00:00:19 ; elapsed = 00:00:20 . Memory (MB): peak = 2121.715 ; gain = 534.281 ; free physical = 6293 ; free virtual = 32313
+Synthesis current peak Physical Memory [PSS] (MB): peak = 1473.249; parent = 1263.912; children = 210.070
+Synthesis current peak Virtual Memory [VSS] (MB): peak = 3092.172; parent = 2089.703; children = 1002.469
+---------------------------------------------------------------------------------
+Synthesis finished with 0 errors, 0 critical warnings and 1 warnings.
+Synthesis Optimization Runtime : Time (s): cpu = 00:00:17 ; elapsed = 00:00:18 . Memory (MB): peak = 2121.715 ; gain = 455.406 ; free physical = 6344 ; free virtual = 32364
+Synthesis Optimization Complete : Time (s): cpu = 00:00:19 ; elapsed = 00:00:20 . Memory (MB): peak = 2121.715 ; gain = 534.281 ; free physical = 6344 ; free virtual = 32364
+INFO: [Project 1-571] Translating synthesized netlist
+Netlist sorting complete. Time (s): cpu = 00:00:00 ; elapsed = 00:00:00 . Memory (MB): peak = 2121.715 ; gain = 0.000 ; free physical = 6338 ; free virtual = 32358
+INFO: [Netlist 29-17] Analyzing 1 Unisim elements for replacement
+INFO: [Netlist 29-28] Unisim Transformation completed in 0 CPU seconds
+INFO: [Project 1-570] Preparing netlist for logic optimization
+INFO: [Opt 31-138] Pushed 0 inverter(s) to 0 load pin(s).
+Netlist sorting complete. Time (s): cpu = 00:00:00 ; elapsed = 00:00:00 . Memory (MB): peak = 2121.715 ; gain = 0.000 ; free physical = 6386 ; free virtual = 32408
+INFO: [Project 1-111] Unisim Transformation Summary:
+No Unisim elements were transformed.
+
+Synth Design complete, checksum: 5dda54c
+INFO: [Common 17-83] Releasing license: Synthesis
+32 Infos, 1 Warnings, 0 Critical Warnings and 0 Errors encountered.
+synth_design completed successfully
+synth_design: Time (s): cpu = 00:00:26 ; elapsed = 00:00:24 . Memory (MB): peak = 2121.715 ; gain = 860.691 ; free physical = 6591 ; free virtual = 32613
+INFO: [Common 17-1381] The checkpoint '/home/prasic/game/game.runs/clk_wiz_0_synth_1/clk_wiz_0.dcp' has been generated.
+INFO: [Coretcl 2-1648] Added synthesis output to IP cache for IP clk_wiz_0, cache-ID = 186611fea06d2870
+INFO: [Common 17-1381] The checkpoint '/home/prasic/game/game.runs/clk_wiz_0_synth_1/clk_wiz_0.dcp' has been generated.
+INFO: [runtcl-4] Executing : report_utilization -file clk_wiz_0_utilization_synth.rpt -pb clk_wiz_0_utilization_synth.pb
+INFO: [Common 17-206] Exiting Vivado at Mon Feb 27 10:46:52 2023...
diff --git a/game.runs/clk_wiz_0_synth_1/runme.sh b/game.runs/clk_wiz_0_synth_1/runme.sh
new file mode 100755
index 0000000000000000000000000000000000000000..4bb6b81d502bdd5920a6c92617e7d7de6ba61fcd
--- /dev/null
+++ b/game.runs/clk_wiz_0_synth_1/runme.sh
@@ -0,0 +1,39 @@
+#!/bin/sh
+
+#
+# Vivado(TM)
+# runme.sh: a Vivado-generated Runs Script for UNIX
+# Copyright 1986-2022 Xilinx, Inc. All Rights Reserved.
+#
+
+if [ -z "$PATH" ]; then
+ PATH=/opt/Xilinx/Vivado/2022.2/ids_lite/ISE/bin/lin64:/opt/Xilinx/Vivado/2022.2/bin
+else
+ PATH=/opt/Xilinx/Vivado/2022.2/ids_lite/ISE/bin/lin64:/opt/Xilinx/Vivado/2022.2/bin:$PATH
+fi
+export PATH
+
+if [ -z "$LD_LIBRARY_PATH" ]; then
+ LD_LIBRARY_PATH=
+else
+ LD_LIBRARY_PATH=:$LD_LIBRARY_PATH
+fi
+export LD_LIBRARY_PATH
+
+HD_PWD='/home/prasic/game/game.runs/clk_wiz_0_synth_1'
+cd "$HD_PWD"
+
+HD_LOG=runme.log
+/bin/touch $HD_LOG
+
+ISEStep="./ISEWrap.sh"
+EAStep()
+{
+ $ISEStep $HD_LOG "$@" >> $HD_LOG 2>&1
+ if [ $? -ne 0 ]
+ then
+ exit
+ fi
+}
+
+EAStep vivado -log clk_wiz_0.vds -m64 -product Vivado -mode batch -messageDb vivado.pb -notrace -source clk_wiz_0.tcl
diff --git a/game.runs/clk_wiz_0_synth_1/vivado.jou b/game.runs/clk_wiz_0_synth_1/vivado.jou
new file mode 100644
index 0000000000000000000000000000000000000000..ef43e7219eec67c8b1c97cbe829c857ee51e9502
--- /dev/null
+++ b/game.runs/clk_wiz_0_synth_1/vivado.jou
@@ -0,0 +1,13 @@
+#-----------------------------------------------------------
+# Vivado v2022.2 (64-bit)
+# SW Build 3671981 on Fri Oct 14 04:59:54 MDT 2022
+# IP Build 3669848 on Fri Oct 14 08:30:02 MDT 2022
+# Start of session at: Mon Feb 27 10:46:19 2023
+# Process ID: 21266
+# Current directory: /home/prasic/game/game.runs/clk_wiz_0_synth_1
+# Command line: vivado -log clk_wiz_0.vds -product Vivado -mode batch -messageDb vivado.pb -notrace -source clk_wiz_0.tcl
+# Log file: /home/prasic/game/game.runs/clk_wiz_0_synth_1/clk_wiz_0.vds
+# Journal file: /home/prasic/game/game.runs/clk_wiz_0_synth_1/vivado.jou
+# Running On: LikeUE06, OS: Linux, CPU Frequency: 3167.195 MHz, CPU Physical cores: 4, Host memory: 16699 MB
+#-----------------------------------------------------------
+source clk_wiz_0.tcl -notrace
diff --git a/game.runs/clk_wiz_0_synth_1/vivado.pb b/game.runs/clk_wiz_0_synth_1/vivado.pb
new file mode 100644
index 0000000000000000000000000000000000000000..abf5a5b3f4b2698a389d5bea5b5671998d138cb5
Binary files /dev/null and b/game.runs/clk_wiz_0_synth_1/vivado.pb differ
diff --git a/game.runs/impl_1/.Vivado_Implementation.queue.rst b/game.runs/impl_1/.Vivado_Implementation.queue.rst
new file mode 100644
index 0000000000000000000000000000000000000000..e69de29bb2d1d6434b8b29ae775ad8c2e48c5391
diff --git a/game.runs/impl_1/.init_design.begin.rst b/game.runs/impl_1/.init_design.begin.rst
new file mode 100644
index 0000000000000000000000000000000000000000..d0f069f17d46b35d85623f923974fdfef9a4791d
--- /dev/null
+++ b/game.runs/impl_1/.init_design.begin.rst
@@ -0,0 +1,5 @@
+<?xml version="1.0"?>
+<ProcessHandle Version="1" Minor="0">
+ <Process Command=".planAhead." Owner="prasic" Host="" Pid="238972">
+ </Process>
+</ProcessHandle>
diff --git a/game.runs/impl_1/.init_design.end.rst b/game.runs/impl_1/.init_design.end.rst
new file mode 100644
index 0000000000000000000000000000000000000000..e69de29bb2d1d6434b8b29ae775ad8c2e48c5391
diff --git a/game.runs/impl_1/.opt_design.begin.rst b/game.runs/impl_1/.opt_design.begin.rst
new file mode 100644
index 0000000000000000000000000000000000000000..d0f069f17d46b35d85623f923974fdfef9a4791d
--- /dev/null
+++ b/game.runs/impl_1/.opt_design.begin.rst
@@ -0,0 +1,5 @@
+<?xml version="1.0"?>
+<ProcessHandle Version="1" Minor="0">
+ <Process Command=".planAhead." Owner="prasic" Host="" Pid="238972">
+ </Process>
+</ProcessHandle>
diff --git a/game.runs/impl_1/.opt_design.end.rst b/game.runs/impl_1/.opt_design.end.rst
new file mode 100644
index 0000000000000000000000000000000000000000..e69de29bb2d1d6434b8b29ae775ad8c2e48c5391
diff --git a/game.runs/impl_1/.phys_opt_design.begin.rst b/game.runs/impl_1/.phys_opt_design.begin.rst
new file mode 100644
index 0000000000000000000000000000000000000000..d0f069f17d46b35d85623f923974fdfef9a4791d
--- /dev/null
+++ b/game.runs/impl_1/.phys_opt_design.begin.rst
@@ -0,0 +1,5 @@
+<?xml version="1.0"?>
+<ProcessHandle Version="1" Minor="0">
+ <Process Command=".planAhead." Owner="prasic" Host="" Pid="238972">
+ </Process>
+</ProcessHandle>
diff --git a/game.runs/impl_1/.phys_opt_design.end.rst b/game.runs/impl_1/.phys_opt_design.end.rst
new file mode 100644
index 0000000000000000000000000000000000000000..e69de29bb2d1d6434b8b29ae775ad8c2e48c5391
diff --git a/game.runs/impl_1/.place_design.begin.rst b/game.runs/impl_1/.place_design.begin.rst
new file mode 100644
index 0000000000000000000000000000000000000000..d0f069f17d46b35d85623f923974fdfef9a4791d
--- /dev/null
+++ b/game.runs/impl_1/.place_design.begin.rst
@@ -0,0 +1,5 @@
+<?xml version="1.0"?>
+<ProcessHandle Version="1" Minor="0">
+ <Process Command=".planAhead." Owner="prasic" Host="" Pid="238972">
+ </Process>
+</ProcessHandle>
diff --git a/game.runs/impl_1/.place_design.end.rst b/game.runs/impl_1/.place_design.end.rst
new file mode 100644
index 0000000000000000000000000000000000000000..e69de29bb2d1d6434b8b29ae775ad8c2e48c5391
diff --git a/game.runs/impl_1/.route_design.begin.rst b/game.runs/impl_1/.route_design.begin.rst
new file mode 100644
index 0000000000000000000000000000000000000000..d0f069f17d46b35d85623f923974fdfef9a4791d
--- /dev/null
+++ b/game.runs/impl_1/.route_design.begin.rst
@@ -0,0 +1,5 @@
+<?xml version="1.0"?>
+<ProcessHandle Version="1" Minor="0">
+ <Process Command=".planAhead." Owner="prasic" Host="" Pid="238972">
+ </Process>
+</ProcessHandle>
diff --git a/game.runs/impl_1/.route_design.end.rst b/game.runs/impl_1/.route_design.end.rst
new file mode 100644
index 0000000000000000000000000000000000000000..e69de29bb2d1d6434b8b29ae775ad8c2e48c5391
diff --git a/game.runs/impl_1/.vivado.begin.rst b/game.runs/impl_1/.vivado.begin.rst
new file mode 100644
index 0000000000000000000000000000000000000000..a59d34dede9b39c9520149cac6ef99dd2e25de8d
--- /dev/null
+++ b/game.runs/impl_1/.vivado.begin.rst
@@ -0,0 +1,5 @@
+<?xml version="1.0"?>
+<ProcessHandle Version="1" Minor="0">
+ <Process Command="vivado" Owner="prasic" Host="LikeUE06" Pid="238931" HostCore="8" HostMemory="16307816">
+ </Process>
+</ProcessHandle>
diff --git a/game.runs/impl_1/.vivado.end.rst b/game.runs/impl_1/.vivado.end.rst
new file mode 100644
index 0000000000000000000000000000000000000000..e69de29bb2d1d6434b8b29ae775ad8c2e48c5391
diff --git a/game.runs/impl_1/.write_bitstream.begin.rst b/game.runs/impl_1/.write_bitstream.begin.rst
new file mode 100644
index 0000000000000000000000000000000000000000..d0f069f17d46b35d85623f923974fdfef9a4791d
--- /dev/null
+++ b/game.runs/impl_1/.write_bitstream.begin.rst
@@ -0,0 +1,5 @@
+<?xml version="1.0"?>
+<ProcessHandle Version="1" Minor="0">
+ <Process Command=".planAhead." Owner="prasic" Host="" Pid="238972">
+ </Process>
+</ProcessHandle>
diff --git a/game.runs/impl_1/.write_bitstream.end.rst b/game.runs/impl_1/.write_bitstream.end.rst
new file mode 100644
index 0000000000000000000000000000000000000000..e69de29bb2d1d6434b8b29ae775ad8c2e48c5391
diff --git a/game.runs/impl_1/ISEWrap.js b/game.runs/impl_1/ISEWrap.js
new file mode 100755
index 0000000000000000000000000000000000000000..db0a51077cfb3a198d0bcb1b84080b9210b5b593
--- /dev/null
+++ b/game.runs/impl_1/ISEWrap.js
@@ -0,0 +1,269 @@
+//
+// Vivado(TM)
+// ISEWrap.js: Vivado Runs Script for WSH 5.1/5.6
+// Copyright 1986-1999, 2001-2013,2015 Xilinx, Inc. All Rights Reserved.
+//
+
+// GLOBAL VARIABLES
+var ISEShell = new ActiveXObject( "WScript.Shell" );
+var ISEFileSys = new ActiveXObject( "Scripting.FileSystemObject" );
+var ISERunDir = "";
+var ISELogFile = "runme.log";
+var ISELogFileStr = null;
+var ISELogEcho = true;
+var ISEOldVersionWSH = false;
+
+
+
+// BOOTSTRAP
+ISEInit();
+
+
+
+//
+// ISE FUNCTIONS
+//
+function ISEInit() {
+
+ // 1. RUN DIR setup
+ var ISEScrFP = WScript.ScriptFullName;
+ var ISEScrN = WScript.ScriptName;
+ ISERunDir =
+ ISEScrFP.substr( 0, ISEScrFP.length - ISEScrN.length - 1 );
+
+ // 2. LOG file setup
+ ISELogFileStr = ISEOpenFile( ISELogFile );
+
+ // 3. LOG echo?
+ var ISEScriptArgs = WScript.Arguments;
+ for ( var loopi=0; loopi<ISEScriptArgs.length; loopi++ ) {
+ if ( ISEScriptArgs(loopi) == "-quiet" ) {
+ ISELogEcho = false;
+ break;
+ }
+ }
+
+ // 4. WSH version check
+ var ISEOptimalVersionWSH = 5.6;
+ var ISECurrentVersionWSH = WScript.Version;
+ if ( ISECurrentVersionWSH < ISEOptimalVersionWSH ) {
+
+ ISEStdErr( "" );
+ ISEStdErr( "Warning: ExploreAhead works best with Microsoft WSH " +
+ ISEOptimalVersionWSH + " or higher. Downloads" );
+ ISEStdErr( " for upgrading your Windows Scripting Host can be found here: " );
+ ISEStdErr( " http://msdn.microsoft.com/downloads/list/webdev.asp" );
+ ISEStdErr( "" );
+
+ ISEOldVersionWSH = true;
+ }
+
+}
+
+function ISEStep( ISEProg, ISEArgs ) {
+
+ // CHECK for a STOP FILE
+ if ( ISEFileSys.FileExists(ISERunDir + "/.stop.rst") ) {
+ ISEStdErr( "" );
+ ISEStdErr( "*** Halting run - EA reset detected ***" );
+ ISEStdErr( "" );
+ WScript.Quit( 1 );
+ }
+
+ // WRITE STEP HEADER to LOG
+ ISEStdOut( "" );
+ ISEStdOut( "*** Running " + ISEProg );
+ ISEStdOut( " with args " + ISEArgs );
+ ISEStdOut( "" );
+
+ // LAUNCH!
+ var ISEExitCode = ISEExec( ISEProg, ISEArgs );
+ if ( ISEExitCode != 0 ) {
+ WScript.Quit( ISEExitCode );
+ }
+
+}
+
+function ISEExec( ISEProg, ISEArgs ) {
+
+ var ISEStep = ISEProg;
+ if (ISEProg == "realTimeFpga" || ISEProg == "planAhead" || ISEProg == "vivado") {
+ ISEProg += ".bat";
+ }
+
+ var ISECmdLine = ISEProg + " " + ISEArgs;
+ var ISEExitCode = 1;
+
+ if ( ISEOldVersionWSH ) { // WSH 5.1
+
+ // BEGIN file creation
+ ISETouchFile( ISEStep, "begin" );
+
+ // LAUNCH!
+ ISELogFileStr.Close();
+ ISECmdLine =
+ "%comspec% /c " + ISECmdLine + " >> " + ISELogFile + " 2>&1";
+ ISEExitCode = ISEShell.Run( ISECmdLine, 0, true );
+ ISELogFileStr = ISEOpenFile( ISELogFile );
+
+ } else { // WSH 5.6
+
+ // LAUNCH!
+ ISEShell.CurrentDirectory = ISERunDir;
+
+ // Redirect STDERR to STDOUT
+ ISECmdLine = "%comspec% /c " + ISECmdLine + " 2>&1";
+ var ISEProcess = ISEShell.Exec( ISECmdLine );
+
+ // BEGIN file creation
+ var wbemFlagReturnImmediately = 0x10;
+ var wbemFlagForwardOnly = 0x20;
+ var objWMIService = GetObject ("winmgmts:{impersonationLevel=impersonate, (Systemtime)}!//./root/cimv2");
+ var processor = objWMIService.ExecQuery("SELECT * FROM Win32_Processor", "WQL",wbemFlagReturnImmediately | wbemFlagForwardOnly);
+ var computerSystem = objWMIService.ExecQuery("SELECT * FROM Win32_ComputerSystem", "WQL", wbemFlagReturnImmediately | wbemFlagForwardOnly);
+ var NOC = 0;
+ var NOLP = 0;
+ var TPM = 0;
+ var cpuInfos = new Enumerator(processor);
+ for(;!cpuInfos.atEnd(); cpuInfos.moveNext()) {
+ var cpuInfo = cpuInfos.item();
+ NOC += cpuInfo.NumberOfCores;
+ NOLP += cpuInfo.NumberOfLogicalProcessors;
+ }
+ var csInfos = new Enumerator(computerSystem);
+ for(;!csInfos.atEnd(); csInfos.moveNext()) {
+ var csInfo = csInfos.item();
+ TPM += csInfo.TotalPhysicalMemory;
+ }
+
+ var ISEHOSTCORE = NOLP
+ var ISEMEMTOTAL = TPM
+
+ var ISENetwork = WScript.CreateObject( "WScript.Network" );
+ var ISEHost = ISENetwork.ComputerName;
+ var ISEUser = ISENetwork.UserName;
+ var ISEPid = ISEProcess.ProcessID;
+ var ISEBeginFile = ISEOpenFile( "." + ISEStep + ".begin.rst" );
+ ISEBeginFile.WriteLine( "<?xml version=\"1.0\"?>" );
+ ISEBeginFile.WriteLine( "<ProcessHandle Version=\"1\" Minor=\"0\">" );
+ ISEBeginFile.WriteLine( " <Process Command=\"" + ISEProg +
+ "\" Owner=\"" + ISEUser +
+ "\" Host=\"" + ISEHost +
+ "\" Pid=\"" + ISEPid +
+ "\" HostCore=\"" + ISEHOSTCORE +
+ "\" HostMemory=\"" + ISEMEMTOTAL +
+ "\">" );
+ ISEBeginFile.WriteLine( " </Process>" );
+ ISEBeginFile.WriteLine( "</ProcessHandle>" );
+ ISEBeginFile.Close();
+
+ var ISEOutStr = ISEProcess.StdOut;
+ var ISEErrStr = ISEProcess.StdErr;
+
+ // WAIT for ISEStep to finish
+ while ( ISEProcess.Status == 0 ) {
+
+ // dump stdout then stderr - feels a little arbitrary
+ while ( !ISEOutStr.AtEndOfStream ) {
+ ISEStdOut( ISEOutStr.ReadLine() );
+ }
+
+ WScript.Sleep( 100 );
+ }
+
+ ISEExitCode = ISEProcess.ExitCode;
+ }
+
+ ISELogFileStr.Close();
+
+ // END/ERROR file creation
+ if ( ISEExitCode != 0 ) {
+ ISETouchFile( ISEStep, "error" );
+
+ } else {
+ ISETouchFile( ISEStep, "end" );
+ }
+
+ return ISEExitCode;
+}
+
+
+//
+// UTILITIES
+//
+function ISEStdOut( ISELine ) {
+
+ ISELogFileStr.WriteLine( ISELine );
+
+ if ( ISELogEcho ) {
+ WScript.StdOut.WriteLine( ISELine );
+ }
+}
+
+function ISEStdErr( ISELine ) {
+
+ ISELogFileStr.WriteLine( ISELine );
+
+ if ( ISELogEcho ) {
+ WScript.StdErr.WriteLine( ISELine );
+ }
+}
+
+function ISETouchFile( ISERoot, ISEStatus ) {
+
+ var ISETFile =
+ ISEOpenFile( "." + ISERoot + "." + ISEStatus + ".rst" );
+ ISETFile.Close();
+}
+
+function ISEOpenFile( ISEFilename ) {
+
+ // This function has been updated to deal with a problem seen in CR #870871.
+ // In that case the user runs a script that runs impl_1, and then turns around
+ // and runs impl_1 -to_step write_bitstream. That second run takes place in
+ // the same directory, which means we may hit some of the same files, and in
+ // particular, we will open the runme.log file. Even though this script closes
+ // the file (now), we see cases where a subsequent attempt to open the file
+ // fails. Perhaps the OS is slow to release the lock, or the disk comes into
+ // play? In any case, we try to work around this by first waiting if the file
+ // is already there for an arbitrary 5 seconds. Then we use a try-catch block
+ // and try to open the file 10 times with a one second delay after each attempt.
+ // Again, 10 is arbitrary. But these seem to stop the hang in CR #870871.
+ // If there is an unrecognized exception when trying to open the file, we output
+ // an error message and write details to an exception.log file.
+ var ISEFullPath = ISERunDir + "/" + ISEFilename;
+ if (ISEFileSys.FileExists(ISEFullPath)) {
+ // File is already there. This could be a problem. Wait in case it is still in use.
+ WScript.Sleep(5000);
+ }
+ var i;
+ for (i = 0; i < 10; ++i) {
+ try {
+ return ISEFileSys.OpenTextFile(ISEFullPath, 8, true);
+ } catch (exception) {
+ var error_code = exception.number & 0xFFFF; // The other bits are a facility code.
+ if (error_code == 52) { // 52 is bad file name or number.
+ // Wait a second and try again.
+ WScript.Sleep(1000);
+ continue;
+ } else {
+ WScript.StdErr.WriteLine("ERROR: Exception caught trying to open file " + ISEFullPath);
+ var exceptionFilePath = ISERunDir + "/exception.log";
+ if (!ISEFileSys.FileExists(exceptionFilePath)) {
+ WScript.StdErr.WriteLine("See file " + exceptionFilePath + " for details.");
+ var exceptionFile = ISEFileSys.OpenTextFile(exceptionFilePath, 8, true);
+ exceptionFile.WriteLine("ERROR: Exception caught trying to open file " + ISEFullPath);
+ exceptionFile.WriteLine("\tException name: " + exception.name);
+ exceptionFile.WriteLine("\tException error code: " + error_code);
+ exceptionFile.WriteLine("\tException message: " + exception.message);
+ exceptionFile.Close();
+ }
+ throw exception;
+ }
+ }
+ }
+ // If we reached this point, we failed to open the file after 10 attempts.
+ // We need to error out.
+ WScript.StdErr.WriteLine("ERROR: Failed to open file " + ISEFullPath);
+ WScript.Quit(1);
+}
diff --git a/game.runs/impl_1/ISEWrap.sh b/game.runs/impl_1/ISEWrap.sh
new file mode 100755
index 0000000000000000000000000000000000000000..c2fbbb6098d6a14cfa1bdac6a65050244f5a6c7d
--- /dev/null
+++ b/game.runs/impl_1/ISEWrap.sh
@@ -0,0 +1,84 @@
+#!/bin/sh
+
+#
+# Vivado(TM)
+# ISEWrap.sh: Vivado Runs Script for UNIX
+# Copyright 1986-1999, 2001-2013 Xilinx, Inc. All Rights Reserved.
+#
+
+cmd_exists()
+{
+ command -v "$1" >/dev/null 2>&1
+}
+
+HD_LOG=$1
+shift
+
+# CHECK for a STOP FILE
+if [ -f .stop.rst ]
+then
+echo "" >> $HD_LOG
+echo "*** Halting run - EA reset detected ***" >> $HD_LOG
+echo "" >> $HD_LOG
+exit 1
+fi
+
+ISE_STEP=$1
+shift
+
+# WRITE STEP HEADER to LOG
+echo "" >> $HD_LOG
+echo "*** Running $ISE_STEP" >> $HD_LOG
+echo " with args $@" >> $HD_LOG
+echo "" >> $HD_LOG
+
+# LAUNCH!
+$ISE_STEP "$@" >> $HD_LOG 2>&1 &
+
+# BEGIN file creation
+ISE_PID=$!
+
+HostNameFile=/proc/sys/kernel/hostname
+if cmd_exists hostname
+then
+ISE_HOST=$(hostname)
+elif cmd_exists uname
+then
+ISE_HOST=$(uname -n)
+elif [ -f "$HostNameFile" ] && [ -r $HostNameFile ] && [ -s $HostNameFile ]
+then
+ISE_HOST=$(cat $HostNameFile)
+elif [ X != X$HOSTNAME ]
+then
+ISE_HOST=$HOSTNAME #bash
+else
+ISE_HOST=$HOST #csh
+fi
+
+ISE_USER=$USER
+
+ISE_HOSTCORE=$(awk '/^processor/{print $3}' /proc/cpuinfo | wc -l)
+ISE_MEMTOTAL=$(awk '/MemTotal/ {print $2}' /proc/meminfo)
+
+ISE_BEGINFILE=.$ISE_STEP.begin.rst
+/bin/touch $ISE_BEGINFILE
+echo "<?xml version=\"1.0\"?>" >> $ISE_BEGINFILE
+echo "<ProcessHandle Version=\"1\" Minor=\"0\">" >> $ISE_BEGINFILE
+echo " <Process Command=\"$ISE_STEP\" Owner=\"$ISE_USER\" Host=\"$ISE_HOST\" Pid=\"$ISE_PID\" HostCore=\"$ISE_HOSTCORE\" HostMemory=\"$ISE_MEMTOTAL\">" >> $ISE_BEGINFILE
+echo " </Process>" >> $ISE_BEGINFILE
+echo "</ProcessHandle>" >> $ISE_BEGINFILE
+
+# WAIT for ISEStep to finish
+wait $ISE_PID
+
+# END/ERROR file creation
+RETVAL=$?
+if [ $RETVAL -eq 0 ]
+then
+ /bin/touch .$ISE_STEP.end.rst
+else
+ /bin/touch .$ISE_STEP.error.rst
+fi
+
+exit $RETVAL
+
diff --git a/game.runs/impl_1/TopModule.bit b/game.runs/impl_1/TopModule.bit
new file mode 100644
index 0000000000000000000000000000000000000000..c18c55677ed5674e35e11c868a572d043bcdbcf5
Binary files /dev/null and b/game.runs/impl_1/TopModule.bit differ
diff --git a/game.runs/impl_1/TopModule.tcl b/game.runs/impl_1/TopModule.tcl
new file mode 100644
index 0000000000000000000000000000000000000000..ac57c712dcbbb51a80276c89f240913d28238d59
--- /dev/null
+++ b/game.runs/impl_1/TopModule.tcl
@@ -0,0 +1,336 @@
+#
+# Report generation script generated by Vivado
+#
+
+proc create_report { reportName command } {
+ set status "."
+ append status $reportName ".fail"
+ if { [file exists $status] } {
+ eval file delete [glob $status]
+ }
+ send_msg_id runtcl-4 info "Executing : $command"
+ set retval [eval catch { $command } msg]
+ if { $retval != 0 } {
+ set fp [open $status w]
+ close $fp
+ send_msg_id runtcl-5 warning "$msg"
+ }
+}
+namespace eval ::optrace {
+ variable script "/home/prasic/game/game.runs/impl_1/TopModule.tcl"
+ variable category "vivado_impl"
+}
+
+# Try to connect to running dispatch if we haven't done so already.
+# This code assumes that the Tcl interpreter is not using threads,
+# since the ::dispatch::connected variable isn't mutex protected.
+if {![info exists ::dispatch::connected]} {
+ namespace eval ::dispatch {
+ variable connected false
+ if {[llength [array get env XILINX_CD_CONNECT_ID]] > 0} {
+ set result "true"
+ if {[catch {
+ if {[lsearch -exact [package names] DispatchTcl] < 0} {
+ set result [load librdi_cd_clienttcl[info sharedlibextension]]
+ }
+ if {$result eq "false"} {
+ puts "WARNING: Could not load dispatch client library"
+ }
+ set connect_id [ ::dispatch::init_client -mode EXISTING_SERVER ]
+ if { $connect_id eq "" } {
+ puts "WARNING: Could not initialize dispatch client"
+ } else {
+ puts "INFO: Dispatch client connection id - $connect_id"
+ set connected true
+ }
+ } catch_res]} {
+ puts "WARNING: failed to connect to dispatch server - $catch_res"
+ }
+ }
+ }
+}
+if {$::dispatch::connected} {
+ # Remove the dummy proc if it exists.
+ if { [expr {[llength [info procs ::OPTRACE]] > 0}] } {
+ rename ::OPTRACE ""
+ }
+ proc ::OPTRACE { task action {tags {} } } {
+ ::vitis_log::op_trace "$task" $action -tags $tags -script $::optrace::script -category $::optrace::category
+ }
+ # dispatch is generic. We specifically want to attach logging.
+ ::vitis_log::connect_client
+} else {
+ # Add dummy proc if it doesn't exist.
+ if { [expr {[llength [info procs ::OPTRACE]] == 0}] } {
+ proc ::OPTRACE {{arg1 \"\" } {arg2 \"\"} {arg3 \"\" } {arg4 \"\"} {arg5 \"\" } {arg6 \"\"}} {
+ # Do nothing
+ }
+ }
+}
+
+proc start_step { step } {
+ set stopFile ".stop.rst"
+ if {[file isfile .stop.rst]} {
+ puts ""
+ puts "*** Halting run - EA reset detected ***"
+ puts ""
+ puts ""
+ return -code error
+ }
+ set beginFile ".$step.begin.rst"
+ set platform "$::tcl_platform(platform)"
+ set user "$::tcl_platform(user)"
+ set pid [pid]
+ set host ""
+ if { [string equal $platform unix] } {
+ if { [info exist ::env(HOSTNAME)] } {
+ set host $::env(HOSTNAME)
+ } elseif { [info exist ::env(HOST)] } {
+ set host $::env(HOST)
+ }
+ } else {
+ if { [info exist ::env(COMPUTERNAME)] } {
+ set host $::env(COMPUTERNAME)
+ }
+ }
+ set ch [open $beginFile w]
+ puts $ch "<?xml version=\"1.0\"?>"
+ puts $ch "<ProcessHandle Version=\"1\" Minor=\"0\">"
+ puts $ch " <Process Command=\".planAhead.\" Owner=\"$user\" Host=\"$host\" Pid=\"$pid\">"
+ puts $ch " </Process>"
+ puts $ch "</ProcessHandle>"
+ close $ch
+}
+
+proc end_step { step } {
+ set endFile ".$step.end.rst"
+ set ch [open $endFile w]
+ close $ch
+}
+
+proc step_failed { step } {
+ set endFile ".$step.error.rst"
+ set ch [open $endFile w]
+ close $ch
+OPTRACE "impl_1" END { }
+}
+
+set_msg_config -id {Common 17-41} -limit 10000000
+set_msg_config -id {Synth 8-256} -limit 10000
+set_msg_config -id {Synth 8-638} -limit 10000
+
+OPTRACE "impl_1" START { ROLLUP_1 }
+OPTRACE "Phase: Init Design" START { ROLLUP_AUTO }
+start_step init_design
+set ACTIVE_STEP init_design
+set rc [catch {
+ create_msg_db init_design.pb
+ set_param xicom.use_bs_reader 1
+ set_param chipscope.maxJobs 2
+ set_param checkpoint.writeSynthRtdsInDcp 1
+ set_param synth.incrementalSynthesisCache ./.Xil/Vivado-73025-LikeUE06/incrSyn
+OPTRACE "create in-memory project" START { }
+ create_project -in_memory -part xc7a100tcsg324-1
+ set_property design_mode GateLvl [current_fileset]
+ set_param project.singleFileAddWarning.threshold 0
+OPTRACE "create in-memory project" END { }
+OPTRACE "set parameters" START { }
+ set_property webtalk.parent_dir /home/prasic/game/game.cache/wt [current_project]
+ set_property parent.project_path /home/prasic/game/game.xpr [current_project]
+ set_property ip_output_repo /home/prasic/game/game.cache/ip [current_project]
+ set_property ip_cache_permissions {read write} [current_project]
+ set_property XPM_LIBRARIES XPM_CDC [current_project]
+OPTRACE "set parameters" END { }
+OPTRACE "add files" START { }
+ add_files -quiet /home/prasic/game/game.runs/synth_1/TopModule.dcp
+ read_ip -quiet /home/prasic/game/game.srcs/sources_1/ip/clk_wiz_0/clk_wiz_0.xci
+OPTRACE "read constraints: implementation" START { }
+ read_xdc /home/prasic/game/game.srcs/constrs_1/imports/PrASIC_Data/Nexys4_Master.xdc
+OPTRACE "read constraints: implementation" END { }
+OPTRACE "add files" END { }
+OPTRACE "link_design" START { }
+ link_design -top TopModule -part xc7a100tcsg324-1
+OPTRACE "link_design" END { }
+OPTRACE "gray box cells" START { }
+OPTRACE "gray box cells" END { }
+OPTRACE "init_design_reports" START { REPORT }
+OPTRACE "init_design_reports" END { }
+OPTRACE "init_design_write_hwdef" START { }
+OPTRACE "init_design_write_hwdef" END { }
+ close_msg_db -file init_design.pb
+} RESULT]
+if {$rc} {
+ step_failed init_design
+ return -code error $RESULT
+} else {
+ end_step init_design
+ unset ACTIVE_STEP
+}
+
+OPTRACE "Phase: Init Design" END { }
+OPTRACE "Phase: Opt Design" START { ROLLUP_AUTO }
+start_step opt_design
+set ACTIVE_STEP opt_design
+set rc [catch {
+ create_msg_db opt_design.pb
+OPTRACE "read constraints: opt_design" START { }
+OPTRACE "read constraints: opt_design" END { }
+OPTRACE "opt_design" START { }
+ opt_design
+OPTRACE "opt_design" END { }
+OPTRACE "read constraints: opt_design_post" START { }
+OPTRACE "read constraints: opt_design_post" END { }
+OPTRACE "Opt Design: write_checkpoint" START { CHECKPOINT }
+ write_checkpoint -force TopModule_opt.dcp
+OPTRACE "Opt Design: write_checkpoint" END { }
+OPTRACE "opt_design reports" START { REPORT }
+ create_report "impl_1_opt_report_drc_0" "report_drc -file TopModule_drc_opted.rpt -pb TopModule_drc_opted.pb -rpx TopModule_drc_opted.rpx"
+OPTRACE "opt_design reports" END { }
+ close_msg_db -file opt_design.pb
+} RESULT]
+if {$rc} {
+ step_failed opt_design
+ return -code error $RESULT
+} else {
+ end_step opt_design
+ unset ACTIVE_STEP
+}
+
+OPTRACE "Phase: Opt Design" END { }
+OPTRACE "Phase: Place Design" START { ROLLUP_AUTO }
+start_step place_design
+set ACTIVE_STEP place_design
+set rc [catch {
+ create_msg_db place_design.pb
+OPTRACE "read constraints: place_design" START { }
+OPTRACE "read constraints: place_design" END { }
+ if { [llength [get_debug_cores -quiet] ] > 0 } {
+OPTRACE "implement_debug_core" START { }
+ implement_debug_core
+OPTRACE "implement_debug_core" END { }
+ }
+OPTRACE "place_design" START { }
+ place_design
+OPTRACE "place_design" END { }
+OPTRACE "read constraints: place_design_post" START { }
+OPTRACE "read constraints: place_design_post" END { }
+OPTRACE "Place Design: write_checkpoint" START { CHECKPOINT }
+ write_checkpoint -force TopModule_placed.dcp
+OPTRACE "Place Design: write_checkpoint" END { }
+OPTRACE "place_design reports" START { REPORT }
+ create_report "impl_1_place_report_io_0" "report_io -file TopModule_io_placed.rpt"
+ create_report "impl_1_place_report_utilization_0" "report_utilization -file TopModule_utilization_placed.rpt -pb TopModule_utilization_placed.pb"
+ create_report "impl_1_place_report_control_sets_0" "report_control_sets -verbose -file TopModule_control_sets_placed.rpt"
+OPTRACE "place_design reports" END { }
+ close_msg_db -file place_design.pb
+} RESULT]
+if {$rc} {
+ step_failed place_design
+ return -code error $RESULT
+} else {
+ end_step place_design
+ unset ACTIVE_STEP
+}
+
+OPTRACE "Phase: Place Design" END { }
+OPTRACE "Phase: Physical Opt Design" START { ROLLUP_AUTO }
+start_step phys_opt_design
+set ACTIVE_STEP phys_opt_design
+set rc [catch {
+ create_msg_db phys_opt_design.pb
+OPTRACE "read constraints: phys_opt_design" START { }
+OPTRACE "read constraints: phys_opt_design" END { }
+OPTRACE "phys_opt_design" START { }
+ phys_opt_design
+OPTRACE "phys_opt_design" END { }
+OPTRACE "read constraints: phys_opt_design_post" START { }
+OPTRACE "read constraints: phys_opt_design_post" END { }
+OPTRACE "Post-Place Phys Opt Design: write_checkpoint" START { CHECKPOINT }
+ write_checkpoint -force TopModule_physopt.dcp
+OPTRACE "Post-Place Phys Opt Design: write_checkpoint" END { }
+OPTRACE "phys_opt_design report" START { REPORT }
+OPTRACE "phys_opt_design report" END { }
+ close_msg_db -file phys_opt_design.pb
+} RESULT]
+if {$rc} {
+ step_failed phys_opt_design
+ return -code error $RESULT
+} else {
+ end_step phys_opt_design
+ unset ACTIVE_STEP
+}
+
+OPTRACE "Phase: Physical Opt Design" END { }
+OPTRACE "Phase: Route Design" START { ROLLUP_AUTO }
+start_step route_design
+set ACTIVE_STEP route_design
+set rc [catch {
+ create_msg_db route_design.pb
+OPTRACE "read constraints: route_design" START { }
+OPTRACE "read constraints: route_design" END { }
+OPTRACE "route_design" START { }
+ route_design
+OPTRACE "route_design" END { }
+OPTRACE "read constraints: route_design_post" START { }
+OPTRACE "read constraints: route_design_post" END { }
+OPTRACE "Route Design: write_checkpoint" START { CHECKPOINT }
+ write_checkpoint -force TopModule_routed.dcp
+OPTRACE "Route Design: write_checkpoint" END { }
+OPTRACE "route_design reports" START { REPORT }
+ create_report "impl_1_route_report_drc_0" "report_drc -file TopModule_drc_routed.rpt -pb TopModule_drc_routed.pb -rpx TopModule_drc_routed.rpx"
+ create_report "impl_1_route_report_methodology_0" "report_methodology -file TopModule_methodology_drc_routed.rpt -pb TopModule_methodology_drc_routed.pb -rpx TopModule_methodology_drc_routed.rpx"
+ create_report "impl_1_route_report_power_0" "report_power -file TopModule_power_routed.rpt -pb TopModule_power_summary_routed.pb -rpx TopModule_power_routed.rpx"
+ create_report "impl_1_route_report_route_status_0" "report_route_status -file TopModule_route_status.rpt -pb TopModule_route_status.pb"
+ create_report "impl_1_route_report_timing_summary_0" "report_timing_summary -max_paths 10 -report_unconstrained -file TopModule_timing_summary_routed.rpt -pb TopModule_timing_summary_routed.pb -rpx TopModule_timing_summary_routed.rpx -warn_on_violation "
+ create_report "impl_1_route_report_incremental_reuse_0" "report_incremental_reuse -file TopModule_incremental_reuse_routed.rpt"
+ create_report "impl_1_route_report_clock_utilization_0" "report_clock_utilization -file TopModule_clock_utilization_routed.rpt"
+ create_report "impl_1_route_report_bus_skew_0" "report_bus_skew -warn_on_violation -file TopModule_bus_skew_routed.rpt -pb TopModule_bus_skew_routed.pb -rpx TopModule_bus_skew_routed.rpx"
+OPTRACE "route_design reports" END { }
+OPTRACE "route_design misc" START { }
+ close_msg_db -file route_design.pb
+} RESULT]
+if {$rc} {
+OPTRACE "route_design write_checkpoint" START { CHECKPOINT }
+OPTRACE "route_design write_checkpoint" END { }
+ write_checkpoint -force TopModule_routed_error.dcp
+ step_failed route_design
+ return -code error $RESULT
+} else {
+ end_step route_design
+ unset ACTIVE_STEP
+}
+
+OPTRACE "route_design misc" END { }
+OPTRACE "Phase: Route Design" END { }
+OPTRACE "Phase: Write Bitstream" START { ROLLUP_AUTO }
+OPTRACE "write_bitstream setup" START { }
+start_step write_bitstream
+set ACTIVE_STEP write_bitstream
+set rc [catch {
+ create_msg_db write_bitstream.pb
+OPTRACE "read constraints: write_bitstream" START { }
+OPTRACE "read constraints: write_bitstream" END { }
+ set_property XPM_LIBRARIES XPM_CDC [current_project]
+ catch { write_mem_info -force -no_partial_mmi TopModule.mmi }
+OPTRACE "write_bitstream setup" END { }
+OPTRACE "write_bitstream" START { }
+ write_bitstream -force TopModule.bit
+OPTRACE "write_bitstream" END { }
+OPTRACE "write_bitstream misc" START { }
+OPTRACE "read constraints: write_bitstream_post" START { }
+OPTRACE "read constraints: write_bitstream_post" END { }
+ catch {write_debug_probes -quiet -force TopModule}
+ catch {file copy -force TopModule.ltx debug_nets.ltx}
+ close_msg_db -file write_bitstream.pb
+} RESULT]
+if {$rc} {
+ step_failed write_bitstream
+ return -code error $RESULT
+} else {
+ end_step write_bitstream
+ unset ACTIVE_STEP
+}
+
+OPTRACE "write_bitstream misc" END { }
+OPTRACE "Phase: Write Bitstream" END { }
+OPTRACE "impl_1" END { }
diff --git a/game.runs/impl_1/TopModule.vdi b/game.runs/impl_1/TopModule.vdi
new file mode 100644
index 0000000000000000000000000000000000000000..8bd7da272e711f543570afab046a7ee2526479b1
--- /dev/null
+++ b/game.runs/impl_1/TopModule.vdi
@@ -0,0 +1,641 @@
+#-----------------------------------------------------------
+# Vivado v2022.2 (64-bit)
+# SW Build 3671981 on Fri Oct 14 04:59:54 MDT 2022
+# IP Build 3669848 on Fri Oct 14 08:30:02 MDT 2022
+# Start of session at: Tue Feb 28 17:01:47 2023
+# Process ID: 238972
+# Current directory: /home/prasic/game/game.runs/impl_1
+# Command line: vivado -log TopModule.vdi -applog -product Vivado -messageDb vivado.pb -mode batch -source TopModule.tcl -notrace
+# Log file: /home/prasic/game/game.runs/impl_1/TopModule.vdi
+# Journal file: /home/prasic/game/game.runs/impl_1/vivado.jou
+# Running On: LikeUE06, OS: Linux, CPU Frequency: 3077.891 MHz, CPU Physical cores: 4, Host memory: 16699 MB
+#-----------------------------------------------------------
+source TopModule.tcl -notrace
+Command: link_design -top TopModule -part xc7a100tcsg324-1
+Design is defaulting to srcset: sources_1
+Design is defaulting to constrset: constrs_1
+INFO: [Device 21-403] Loading part xc7a100tcsg324-1
+INFO: [Project 1-454] Reading design checkpoint '/home/prasic/game/game.gen/sources_1/ip/clk_wiz_0/clk_wiz_0.dcp' for cell 'pixelClk'
+Netlist sorting complete. Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.01 . Memory (MB): peak = 1606.039 ; gain = 0.000 ; free physical = 4908 ; free virtual = 31886
+INFO: [Netlist 29-17] Analyzing 57 Unisim elements for replacement
+INFO: [Netlist 29-28] Unisim Transformation completed in 0 CPU seconds
+INFO: [Project 1-479] Netlist was created with Vivado 2022.2
+INFO: [Project 1-570] Preparing netlist for logic optimization
+Parsing XDC File [/home/prasic/game/game.gen/sources_1/ip/clk_wiz_0/clk_wiz_0_board.xdc] for cell 'pixelClk/inst'
+Finished Parsing XDC File [/home/prasic/game/game.gen/sources_1/ip/clk_wiz_0/clk_wiz_0_board.xdc] for cell 'pixelClk/inst'
+Parsing XDC File [/home/prasic/game/game.gen/sources_1/ip/clk_wiz_0/clk_wiz_0.xdc] for cell 'pixelClk/inst'
+INFO: [Timing 38-35] Done setting XDC timing constraints. [/home/prasic/game/game.gen/sources_1/ip/clk_wiz_0/clk_wiz_0.xdc:57]
+INFO: [Timing 38-2] Deriving generated clocks [/home/prasic/game/game.gen/sources_1/ip/clk_wiz_0/clk_wiz_0.xdc:57]
+get_clocks: Time (s): cpu = 00:00:07 ; elapsed = 00:00:07 . Memory (MB): peak = 2300.449 ; gain = 548.789 ; free physical = 4424 ; free virtual = 31402
+Finished Parsing XDC File [/home/prasic/game/game.gen/sources_1/ip/clk_wiz_0/clk_wiz_0.xdc] for cell 'pixelClk/inst'
+Parsing XDC File [/home/prasic/game/game.srcs/constrs_1/imports/PrASIC_Data/Nexys4_Master.xdc]
+Finished Parsing XDC File [/home/prasic/game/game.srcs/constrs_1/imports/PrASIC_Data/Nexys4_Master.xdc]
+INFO: [Opt 31-138] Pushed 0 inverter(s) to 0 load pin(s).
+Netlist sorting complete. Time (s): cpu = 00:00:00 ; elapsed = 00:00:00 . Memory (MB): peak = 2300.449 ; gain = 0.000 ; free physical = 4423 ; free virtual = 31401
+INFO: [Project 1-111] Unisim Transformation Summary:
+No Unisim elements were transformed.
+
+10 Infos, 0 Warnings, 0 Critical Warnings and 0 Errors encountered.
+link_design completed successfully
+link_design: Time (s): cpu = 00:00:12 ; elapsed = 00:00:12 . Memory (MB): peak = 2300.449 ; gain = 1034.520 ; free physical = 4423 ; free virtual = 31401
+Command: opt_design
+Attempting to get a license for feature 'Implementation' and/or device 'xc7a100t'
+INFO: [Common 17-349] Got license for feature 'Implementation' and/or device 'xc7a100t'
+Running DRC as a precondition to command opt_design
+
+Starting DRC Task
+INFO: [DRC 23-27] Running DRC with 8 threads
+INFO: [Project 1-461] DRC finished with 0 Errors
+INFO: [Project 1-462] Please refer to the DRC report (report_drc) for more information.
+
+Time (s): cpu = 00:00:01 ; elapsed = 00:00:00.76 . Memory (MB): peak = 2364.480 ; gain = 64.031 ; free physical = 4413 ; free virtual = 31390
+
+Starting Cache Timing Information Task
+INFO: [Timing 38-35] Done setting XDC timing constraints.
+INFO: [Timing 38-2] Deriving generated clocks
+Ending Cache Timing Information Task | Checksum: 14d4bc14b
+
+Time (s): cpu = 00:00:00.05 ; elapsed = 00:00:00.03 . Memory (MB): peak = 2364.480 ; gain = 0.000 ; free physical = 4413 ; free virtual = 31390
+
+Starting Logic Optimization Task
+
+Phase 1 Retarget
+INFO: [Opt 31-1287] Pulled Inverter vgaInterface/vgaRed_OBUF[2]_inst_i_1 into driver instance vgaInterface/vgaRed_OBUF[3]_inst_i_3, which resulted in an inversion of 7 pins
+INFO: [Opt 31-138] Pushed 1 inverter(s) to 1 load pin(s).
+INFO: [Opt 31-49] Retargeted 0 cell(s).
+Phase 1 Retarget | Checksum: 18dadb2af
+
+Time (s): cpu = 00:00:00.1 ; elapsed = 00:00:00.04 . Memory (MB): peak = 2616.262 ; gain = 0.000 ; free physical = 4167 ; free virtual = 31144
+INFO: [Opt 31-389] Phase Retarget created 0 cells and removed 3 cells
+INFO: [Opt 31-1021] In phase Retarget, 1 netlist objects are constrained preventing optimization. Please run opt_design with -debug_log to get more detail.
+
+Phase 2 Constant propagation
+INFO: [Opt 31-138] Pushed 0 inverter(s) to 0 load pin(s).
+Phase 2 Constant propagation | Checksum: 18dadb2af
+
+Time (s): cpu = 00:00:00.1 ; elapsed = 00:00:00.05 . Memory (MB): peak = 2616.262 ; gain = 0.000 ; free physical = 4167 ; free virtual = 31144
+INFO: [Opt 31-389] Phase Constant propagation created 0 cells and removed 0 cells
+
+Phase 3 Sweep
+Phase 3 Sweep | Checksum: 1ae9a062c
+
+Time (s): cpu = 00:00:00.11 ; elapsed = 00:00:00.06 . Memory (MB): peak = 2616.262 ; gain = 0.000 ; free physical = 4167 ; free virtual = 31144
+INFO: [Opt 31-389] Phase Sweep created 3 cells and removed 0 cells
+
+Phase 4 BUFG optimization
+Phase 4 BUFG optimization | Checksum: 1ae9a062c
+
+Time (s): cpu = 00:00:00.12 ; elapsed = 00:00:00.06 . Memory (MB): peak = 2616.262 ; gain = 0.000 ; free physical = 4167 ; free virtual = 31144
+INFO: [Opt 31-662] Phase BUFG optimization created 0 cells of which 0 are BUFGs and removed 0 cells.
+
+Phase 5 Shift Register Optimization
+INFO: [Opt 31-1064] SRL Remap converted 0 SRLs to 0 registers and converted 0 registers of register chains to 0 SRLs
+Phase 5 Shift Register Optimization | Checksum: 1ae9a062c
+
+Time (s): cpu = 00:00:00.13 ; elapsed = 00:00:00.07 . Memory (MB): peak = 2616.262 ; gain = 0.000 ; free physical = 4167 ; free virtual = 31144
+INFO: [Opt 31-389] Phase Shift Register Optimization created 0 cells and removed 0 cells
+
+Phase 6 Post Processing Netlist
+Phase 6 Post Processing Netlist | Checksum: 173c369ee
+
+Time (s): cpu = 00:00:00.13 ; elapsed = 00:00:00.07 . Memory (MB): peak = 2616.262 ; gain = 0.000 ; free physical = 4167 ; free virtual = 31144
+INFO: [Opt 31-389] Phase Post Processing Netlist created 0 cells and removed 0 cells
+Opt_design Change Summary
+=========================
+
+
+-------------------------------------------------------------------------------------------------------------------------
+| Phase | #Cells created | #Cells Removed | #Constrained objects preventing optimizations |
+-------------------------------------------------------------------------------------------------------------------------
+| Retarget | 0 | 3 | 1 |
+| Constant propagation | 0 | 0 | 0 |
+| Sweep | 3 | 0 | 0 |
+| BUFG optimization | 0 | 0 | 0 |
+| Shift Register Optimization | 0 | 0 | 0 |
+| Post Processing Netlist | 0 | 0 | 0 |
+-------------------------------------------------------------------------------------------------------------------------
+
+
+
+Starting Connectivity Check Task
+
+Time (s): cpu = 00:00:00.01 ; elapsed = 00:00:00.01 . Memory (MB): peak = 2616.262 ; gain = 0.000 ; free physical = 4167 ; free virtual = 31144
+Ending Logic Optimization Task | Checksum: 1e32b2645
+
+Time (s): cpu = 00:00:00.17 ; elapsed = 00:00:00.1 . Memory (MB): peak = 2616.262 ; gain = 0.000 ; free physical = 4167 ; free virtual = 31144
+
+Starting Power Optimization Task
+INFO: [Pwropt 34-132] Skipping clock gating for clocks with a period < 2.00 ns.
+Ending Power Optimization Task | Checksum: 1e32b2645
+
+Time (s): cpu = 00:00:00 ; elapsed = 00:00:00 . Memory (MB): peak = 2616.262 ; gain = 0.000 ; free physical = 4167 ; free virtual = 31144
+
+Starting Final Cleanup Task
+Ending Final Cleanup Task | Checksum: 1e32b2645
+
+Time (s): cpu = 00:00:00 ; elapsed = 00:00:00 . Memory (MB): peak = 2616.262 ; gain = 0.000 ; free physical = 4167 ; free virtual = 31144
+
+Starting Netlist Obfuscation Task
+Netlist sorting complete. Time (s): cpu = 00:00:00 ; elapsed = 00:00:00 . Memory (MB): peak = 2616.262 ; gain = 0.000 ; free physical = 4167 ; free virtual = 31144
+Ending Netlist Obfuscation Task | Checksum: 1e32b2645
+
+Time (s): cpu = 00:00:00 ; elapsed = 00:00:00 . Memory (MB): peak = 2616.262 ; gain = 0.000 ; free physical = 4167 ; free virtual = 31144
+INFO: [Common 17-83] Releasing license: Implementation
+30 Infos, 0 Warnings, 0 Critical Warnings and 0 Errors encountered.
+opt_design completed successfully
+INFO: [Timing 38-480] Writing timing data to binary archive.
+Writing XDEF routing.
+Writing XDEF routing logical nets.
+Writing XDEF routing special nets.
+Write XDEF Complete: Time (s): cpu = 00:00:00.08 ; elapsed = 00:00:00.02 . Memory (MB): peak = 2648.277 ; gain = 24.012 ; free physical = 4161 ; free virtual = 31138
+INFO: [Common 17-1381] The checkpoint '/home/prasic/game/game.runs/impl_1/TopModule_opt.dcp' has been generated.
+INFO: [runtcl-4] Executing : report_drc -file TopModule_drc_opted.rpt -pb TopModule_drc_opted.pb -rpx TopModule_drc_opted.rpx
+Command: report_drc -file TopModule_drc_opted.rpt -pb TopModule_drc_opted.pb -rpx TopModule_drc_opted.rpx
+INFO: [IP_Flow 19-1839] IP Catalog is up to date.
+INFO: [DRC 23-27] Running DRC with 8 threads
+INFO: [Vivado_Tcl 2-168] The results of DRC are in file /home/prasic/game/game.runs/impl_1/TopModule_drc_opted.rpt.
+report_drc completed successfully
+Command: place_design
+Attempting to get a license for feature 'Implementation' and/or device 'xc7a100t'
+INFO: [Common 17-349] Got license for feature 'Implementation' and/or device 'xc7a100t'
+INFO: [DRC 23-27] Running DRC with 8 threads
+INFO: [Vivado_Tcl 4-198] DRC finished with 0 Errors
+INFO: [Vivado_Tcl 4-199] Please refer to the DRC report (report_drc) for more information.
+Running DRC as a precondition to command place_design
+INFO: [DRC 23-27] Running DRC with 8 threads
+INFO: [Vivado_Tcl 4-198] DRC finished with 0 Errors
+INFO: [Vivado_Tcl 4-199] Please refer to the DRC report (report_drc) for more information.
+
+Starting Placer Task
+INFO: [Place 30-611] Multithreading enabled for place_design using a maximum of 8 CPUs
+
+Phase 1 Placer Initialization
+
+Phase 1.1 Placer Initialization Netlist Sorting
+Netlist sorting complete. Time (s): cpu = 00:00:00 ; elapsed = 00:00:00 . Memory (MB): peak = 2720.312 ; gain = 0.000 ; free physical = 4145 ; free virtual = 31122
+Phase 1.1 Placer Initialization Netlist Sorting | Checksum: 15c9b26e4
+
+Time (s): cpu = 00:00:00.01 ; elapsed = 00:00:00.03 . Memory (MB): peak = 2720.312 ; gain = 0.000 ; free physical = 4145 ; free virtual = 31122
+Netlist sorting complete. Time (s): cpu = 00:00:00 ; elapsed = 00:00:00 . Memory (MB): peak = 2720.312 ; gain = 0.000 ; free physical = 4145 ; free virtual = 31122
+
+Phase 1.2 IO Placement/ Clock Placement/ Build Placer Device
+INFO: [Timing 38-35] Done setting XDC timing constraints.
+Phase 1.2 IO Placement/ Clock Placement/ Build Placer Device | Checksum: 105221de9
+
+Time (s): cpu = 00:00:00.25 ; elapsed = 00:00:00.19 . Memory (MB): peak = 2720.312 ; gain = 0.000 ; free physical = 4127 ; free virtual = 31105
+
+Phase 1.3 Build Placer Netlist Model
+Phase 1.3 Build Placer Netlist Model | Checksum: 12e30e91e
+
+Time (s): cpu = 00:00:00.49 ; elapsed = 00:00:00.32 . Memory (MB): peak = 2720.312 ; gain = 0.000 ; free physical = 4142 ; free virtual = 31120
+
+Phase 1.4 Constrain Clocks/Macros
+Phase 1.4 Constrain Clocks/Macros | Checksum: 12e30e91e
+
+Time (s): cpu = 00:00:00.5 ; elapsed = 00:00:00.32 . Memory (MB): peak = 2720.312 ; gain = 0.000 ; free physical = 4142 ; free virtual = 31120
+Phase 1 Placer Initialization | Checksum: 12e30e91e
+
+Time (s): cpu = 00:00:00.5 ; elapsed = 00:00:00.33 . Memory (MB): peak = 2720.312 ; gain = 0.000 ; free physical = 4142 ; free virtual = 31120
+
+Phase 2 Global Placement
+
+Phase 2.1 Floorplanning
+Phase 2.1 Floorplanning | Checksum: 1aac329f3
+
+Time (s): cpu = 00:00:00.65 ; elapsed = 00:00:00.38 . Memory (MB): peak = 2720.312 ; gain = 0.000 ; free physical = 4138 ; free virtual = 31116
+
+Phase 2.2 Update Timing before SLR Path Opt
+Phase 2.2 Update Timing before SLR Path Opt | Checksum: 160e19f20
+
+Time (s): cpu = 00:00:00.7 ; elapsed = 00:00:00.42 . Memory (MB): peak = 2720.312 ; gain = 0.000 ; free physical = 4139 ; free virtual = 31116
+
+Phase 2.3 Post-Processing in Floorplanning
+Phase 2.3 Post-Processing in Floorplanning | Checksum: 160e19f20
+
+Time (s): cpu = 00:00:00.71 ; elapsed = 00:00:00.42 . Memory (MB): peak = 2720.312 ; gain = 0.000 ; free physical = 4139 ; free virtual = 31116
+
+Phase 2.4 Global Placement Core
+
+Phase 2.4.1 UpdateTiming Before Physical Synthesis
+Phase 2.4.1 UpdateTiming Before Physical Synthesis | Checksum: 17a45fbe4
+
+Time (s): cpu = 00:00:03 ; elapsed = 00:00:01 . Memory (MB): peak = 2720.312 ; gain = 0.000 ; free physical = 4112 ; free virtual = 31089
+
+Phase 2.4.2 Physical Synthesis In Placer
+INFO: [Physopt 32-1035] Found 0 LUTNM shape to break, 3 LUT instances to create LUTNM shape
+INFO: [Physopt 32-1044] Break lutnm for timing: one critical 0, two critical 0, total 0, new lutff created 0
+INFO: [Physopt 32-1138] End 1 Pass. Optimized 1 net or LUT. Breaked 0 LUT, combined 1 existing LUT and moved 0 existing LUT
+INFO: [Physopt 32-65] No nets found for high-fanout optimization.
+INFO: [Physopt 32-232] Optimized 0 net. Created 0 new instance.
+INFO: [Physopt 32-775] End 1 Pass. Optimized 0 net or cell. Created 0 new cell, deleted 0 existing cell and moved 0 existing cell
+INFO: [Physopt 32-670] No setup violation found. DSP Register Optimization was not performed.
+INFO: [Physopt 32-670] No setup violation found. Shift Register to Pipeline Optimization was not performed.
+INFO: [Physopt 32-670] No setup violation found. Shift Register Optimization was not performed.
+INFO: [Physopt 32-670] No setup violation found. BRAM Register Optimization was not performed.
+INFO: [Physopt 32-670] No setup violation found. URAM Register Optimization was not performed.
+INFO: [Physopt 32-949] No candidate nets found for dynamic/static region interface net replication
+INFO: [Physopt 32-775] End 1 Pass. Optimized 0 net or cell. Created 0 new cell, deleted 0 existing cell and moved 0 existing cell
+Netlist sorting complete. Time (s): cpu = 00:00:00 ; elapsed = 00:00:00 . Memory (MB): peak = 2720.312 ; gain = 0.000 ; free physical = 4110 ; free virtual = 31088
+
+Summary of Physical Synthesis Optimizations
+============================================
+
+
+-----------------------------------------------------------------------------------------------------------------------------------------------------------
+| Optimization | Added Cells | Removed Cells | Optimized Cells/Nets | Dont Touch | Iterations | Elapsed |
+-----------------------------------------------------------------------------------------------------------------------------------------------------------
+| LUT Combining | 0 | 1 | 1 | 0 | 1 | 00:00:00 |
+| Retime | 0 | 0 | 0 | 0 | 1 | 00:00:00 |
+| Very High Fanout | 0 | 0 | 0 | 0 | 1 | 00:00:00 |
+| DSP Register | 0 | 0 | 0 | 0 | 0 | 00:00:00 |
+| Shift Register to Pipeline | 0 | 0 | 0 | 0 | 0 | 00:00:00 |
+| Shift Register | 0 | 0 | 0 | 0 | 0 | 00:00:00 |
+| BRAM Register | 0 | 0 | 0 | 0 | 0 | 00:00:00 |
+| URAM Register | 0 | 0 | 0 | 0 | 0 | 00:00:00 |
+| Dynamic/Static Region Interface Net Replication | 0 | 0 | 0 | 0 | 1 | 00:00:00 |
+| Total | 0 | 1 | 1 | 0 | 4 | 00:00:00 |
+-----------------------------------------------------------------------------------------------------------------------------------------------------------
+
+
+Phase 2.4.2 Physical Synthesis In Placer | Checksum: 1ec4d2c29
+
+Time (s): cpu = 00:00:04 ; elapsed = 00:00:02 . Memory (MB): peak = 2720.312 ; gain = 0.000 ; free physical = 4111 ; free virtual = 31088
+Phase 2.4 Global Placement Core | Checksum: 1697c68ea
+
+Time (s): cpu = 00:00:04 ; elapsed = 00:00:02 . Memory (MB): peak = 2720.312 ; gain = 0.000 ; free physical = 4110 ; free virtual = 31088
+Phase 2 Global Placement | Checksum: 1697c68ea
+
+Time (s): cpu = 00:00:04 ; elapsed = 00:00:02 . Memory (MB): peak = 2720.312 ; gain = 0.000 ; free physical = 4110 ; free virtual = 31088
+
+Phase 3 Detail Placement
+
+Phase 3.1 Commit Multi Column Macros
+Phase 3.1 Commit Multi Column Macros | Checksum: 179bc14ed
+
+Time (s): cpu = 00:00:04 ; elapsed = 00:00:02 . Memory (MB): peak = 2720.312 ; gain = 0.000 ; free physical = 4110 ; free virtual = 31088
+
+Phase 3.2 Commit Most Macros & LUTRAMs
+Phase 3.2 Commit Most Macros & LUTRAMs | Checksum: 2070ef4b2
+
+Time (s): cpu = 00:00:04 ; elapsed = 00:00:02 . Memory (MB): peak = 2720.312 ; gain = 0.000 ; free physical = 4110 ; free virtual = 31087
+
+Phase 3.3 Area Swap Optimization
+Phase 3.3 Area Swap Optimization | Checksum: 1b6d58336
+
+Time (s): cpu = 00:00:04 ; elapsed = 00:00:02 . Memory (MB): peak = 2720.312 ; gain = 0.000 ; free physical = 4110 ; free virtual = 31087
+
+Phase 3.4 Pipeline Register Optimization
+Phase 3.4 Pipeline Register Optimization | Checksum: 2647924a7
+
+Time (s): cpu = 00:00:04 ; elapsed = 00:00:02 . Memory (MB): peak = 2720.312 ; gain = 0.000 ; free physical = 4110 ; free virtual = 31087
+
+Phase 3.5 Small Shape Detail Placement
+Phase 3.5 Small Shape Detail Placement | Checksum: 1c3fcab4d
+
+Time (s): cpu = 00:00:04 ; elapsed = 00:00:02 . Memory (MB): peak = 2720.312 ; gain = 0.000 ; free physical = 4108 ; free virtual = 31085
+
+Phase 3.6 Re-assign LUT pins
+Phase 3.6 Re-assign LUT pins | Checksum: 1edbbe9db
+
+Time (s): cpu = 00:00:04 ; elapsed = 00:00:02 . Memory (MB): peak = 2720.312 ; gain = 0.000 ; free physical = 4108 ; free virtual = 31086
+
+Phase 3.7 Pipeline Register Optimization
+Phase 3.7 Pipeline Register Optimization | Checksum: 17c18496c
+
+Time (s): cpu = 00:00:04 ; elapsed = 00:00:02 . Memory (MB): peak = 2720.312 ; gain = 0.000 ; free physical = 4108 ; free virtual = 31086
+Phase 3 Detail Placement | Checksum: 17c18496c
+
+Time (s): cpu = 00:00:04 ; elapsed = 00:00:02 . Memory (MB): peak = 2720.312 ; gain = 0.000 ; free physical = 4108 ; free virtual = 31086
+
+Phase 4 Post Placement Optimization and Clean-Up
+
+Phase 4.1 Post Commit Optimization
+INFO: [Timing 38-35] Done setting XDC timing constraints.
+
+Phase 4.1.1 Post Placement Optimization
+Post Placement Optimization Initialization | Checksum: 109529687
+
+Phase 4.1.1.1 BUFG Insertion
+
+Starting Physical Synthesis Task
+
+Phase 1 Physical Synthesis Initialization
+INFO: [Physopt 32-721] Multithreading enabled for phys_opt_design using a maximum of 8 CPUs
+INFO: [Physopt 32-619] Estimated Timing Summary | WNS=26.291 | TNS=0.000 |
+Phase 1 Physical Synthesis Initialization | Checksum: 14543fbd3
+
+Time (s): cpu = 00:00:00.04 ; elapsed = 00:00:00.02 . Memory (MB): peak = 2720.312 ; gain = 0.000 ; free physical = 4108 ; free virtual = 31085
+INFO: [Place 46-56] BUFG insertion identified 0 candidate nets. Inserted BUFG: 0, Replicated BUFG Driver: 0, Skipped due to Placement/Routing Conflicts: 0, Skipped due to Timing Degradation: 0, Skipped due to Illegal Netlist: 0.
+Ending Physical Synthesis Task | Checksum: 15d4ad102
+
+Time (s): cpu = 00:00:00.05 ; elapsed = 00:00:00.02 . Memory (MB): peak = 2720.312 ; gain = 0.000 ; free physical = 4108 ; free virtual = 31085
+Phase 4.1.1.1 BUFG Insertion | Checksum: 109529687
+
+Time (s): cpu = 00:00:05 ; elapsed = 00:00:02 . Memory (MB): peak = 2720.312 ; gain = 0.000 ; free physical = 4108 ; free virtual = 31085
+
+Phase 4.1.1.2 Post Placement Timing Optimization
+INFO: [Place 30-746] Post Placement Timing Summary WNS=26.291. For the most accurate timing information please run report_timing.
+Phase 4.1.1.2 Post Placement Timing Optimization | Checksum: 1084ee129
+
+Time (s): cpu = 00:00:05 ; elapsed = 00:00:02 . Memory (MB): peak = 2720.312 ; gain = 0.000 ; free physical = 4108 ; free virtual = 31085
+
+Time (s): cpu = 00:00:05 ; elapsed = 00:00:02 . Memory (MB): peak = 2720.312 ; gain = 0.000 ; free physical = 4107 ; free virtual = 31085
+Phase 4.1 Post Commit Optimization | Checksum: 1084ee129
+
+Time (s): cpu = 00:00:05 ; elapsed = 00:00:02 . Memory (MB): peak = 2720.312 ; gain = 0.000 ; free physical = 4107 ; free virtual = 31085
+
+Phase 4.2 Post Placement Cleanup
+Phase 4.2 Post Placement Cleanup | Checksum: 1084ee129
+
+Time (s): cpu = 00:00:05 ; elapsed = 00:00:02 . Memory (MB): peak = 2720.312 ; gain = 0.000 ; free physical = 4108 ; free virtual = 31086
+
+Phase 4.3 Placer Reporting
+
+Phase 4.3.1 Print Estimated Congestion
+INFO: [Place 30-612] Post-Placement Estimated Congestion
+ ____________________________________________________
+| | Global Congestion | Short Congestion |
+| Direction | Region Size | Region Size |
+|___________|___________________|___________________|
+| North| 1x1| 1x1|
+|___________|___________________|___________________|
+| South| 1x1| 1x1|
+|___________|___________________|___________________|
+| East| 1x1| 1x1|
+|___________|___________________|___________________|
+| West| 1x1| 1x1|
+|___________|___________________|___________________|
+
+Phase 4.3.1 Print Estimated Congestion | Checksum: 1084ee129
+
+Time (s): cpu = 00:00:05 ; elapsed = 00:00:02 . Memory (MB): peak = 2720.312 ; gain = 0.000 ; free physical = 4108 ; free virtual = 31086
+Phase 4.3 Placer Reporting | Checksum: 1084ee129
+
+Time (s): cpu = 00:00:05 ; elapsed = 00:00:02 . Memory (MB): peak = 2720.312 ; gain = 0.000 ; free physical = 4108 ; free virtual = 31086
+
+Phase 4.4 Final Placement Cleanup
+Netlist sorting complete. Time (s): cpu = 00:00:00 ; elapsed = 00:00:00 . Memory (MB): peak = 2720.312 ; gain = 0.000 ; free physical = 4108 ; free virtual = 31086
+
+Time (s): cpu = 00:00:05 ; elapsed = 00:00:02 . Memory (MB): peak = 2720.312 ; gain = 0.000 ; free physical = 4108 ; free virtual = 31086
+Phase 4 Post Placement Optimization and Clean-Up | Checksum: b64880c0
+
+Time (s): cpu = 00:00:05 ; elapsed = 00:00:02 . Memory (MB): peak = 2720.312 ; gain = 0.000 ; free physical = 4108 ; free virtual = 31086
+Ending Placer Task | Checksum: 84b47138
+
+Time (s): cpu = 00:00:05 ; elapsed = 00:00:02 . Memory (MB): peak = 2720.312 ; gain = 0.000 ; free physical = 4108 ; free virtual = 31086
+INFO: [Common 17-83] Releasing license: Implementation
+65 Infos, 0 Warnings, 0 Critical Warnings and 0 Errors encountered.
+place_design completed successfully
+INFO: [Timing 38-480] Writing timing data to binary archive.
+Writing XDEF routing.
+Writing XDEF routing logical nets.
+Writing XDEF routing special nets.
+Write XDEF Complete: Time (s): cpu = 00:00:00.14 ; elapsed = 00:00:00.05 . Memory (MB): peak = 2720.312 ; gain = 0.000 ; free physical = 4134 ; free virtual = 31112
+INFO: [Common 17-1381] The checkpoint '/home/prasic/game/game.runs/impl_1/TopModule_placed.dcp' has been generated.
+INFO: [runtcl-4] Executing : report_io -file TopModule_io_placed.rpt
+report_io: Time (s): cpu = 00:00:00.13 ; elapsed = 00:00:00.17 . Memory (MB): peak = 2720.312 ; gain = 0.000 ; free physical = 4125 ; free virtual = 31103
+INFO: [runtcl-4] Executing : report_utilization -file TopModule_utilization_placed.rpt -pb TopModule_utilization_placed.pb
+INFO: [runtcl-4] Executing : report_control_sets -verbose -file TopModule_control_sets_placed.rpt
+report_control_sets: Time (s): cpu = 00:00:00.05 ; elapsed = 00:00:00.1 . Memory (MB): peak = 2720.312 ; gain = 0.000 ; free physical = 4133 ; free virtual = 31111
+Command: phys_opt_design
+Attempting to get a license for feature 'Implementation' and/or device 'xc7a100t'
+INFO: [Common 17-349] Got license for feature 'Implementation' and/or device 'xc7a100t'
+
+Starting Initial Update Timing Task
+
+Time (s): cpu = 00:00:00.2 ; elapsed = 00:00:00.1 . Memory (MB): peak = 2720.312 ; gain = 0.000 ; free physical = 4104 ; free virtual = 31081
+INFO: [Vivado_Tcl 4-383] Design worst setup slack (WNS) is greater than or equal to 0.000 ns. Skipping all physical synthesis optimizations.
+INFO: [Vivado_Tcl 4-232] No setup violation found. The netlist was not modified.
+INFO: [Common 17-83] Releasing license: Implementation
+74 Infos, 0 Warnings, 0 Critical Warnings and 0 Errors encountered.
+phys_opt_design completed successfully
+INFO: [Timing 38-480] Writing timing data to binary archive.
+Writing XDEF routing.
+Writing XDEF routing logical nets.
+Writing XDEF routing special nets.
+Write XDEF Complete: Time (s): cpu = 00:00:00.16 ; elapsed = 00:00:00.06 . Memory (MB): peak = 2720.312 ; gain = 0.000 ; free physical = 4099 ; free virtual = 31078
+INFO: [Common 17-1381] The checkpoint '/home/prasic/game/game.runs/impl_1/TopModule_physopt.dcp' has been generated.
+Command: route_design
+Attempting to get a license for feature 'Implementation' and/or device 'xc7a100t'
+INFO: [Common 17-349] Got license for feature 'Implementation' and/or device 'xc7a100t'
+Running DRC as a precondition to command route_design
+INFO: [DRC 23-27] Running DRC with 8 threads
+INFO: [Vivado_Tcl 4-198] DRC finished with 0 Errors
+INFO: [Vivado_Tcl 4-199] Please refer to the DRC report (report_drc) for more information.
+
+
+Starting Routing Task
+INFO: [Route 35-254] Multithreading enabled for route_design using a maximum of 8 CPUs
+
+Phase 1 Build RT Design
+Checksum: PlaceDB: 4a9e9a15 ConstDB: 0 ShapeSum: 3a15d723 RouteDB: 0
+Post Restoration Checksum: NetGraph: fcfe40d0 NumContArr: ada2d337 Constraints: 0 Timing: 0
+Phase 1 Build RT Design | Checksum: 1aaa11407
+
+Time (s): cpu = 00:00:26 ; elapsed = 00:00:22 . Memory (MB): peak = 2777.801 ; gain = 54.957 ; free physical = 3955 ; free virtual = 30934
+
+Phase 2 Router Initialization
+
+Phase 2.1 Fix Topology Constraints
+Phase 2.1 Fix Topology Constraints | Checksum: 1aaa11407
+
+Time (s): cpu = 00:00:26 ; elapsed = 00:00:22 . Memory (MB): peak = 2810.801 ; gain = 87.957 ; free physical = 3921 ; free virtual = 30899
+
+Phase 2.2 Pre Route Cleanup
+Phase 2.2 Pre Route Cleanup | Checksum: 1aaa11407
+
+Time (s): cpu = 00:00:26 ; elapsed = 00:00:22 . Memory (MB): peak = 2810.801 ; gain = 87.957 ; free physical = 3921 ; free virtual = 30899
+ Number of Nodes with overlaps = 0
+
+Phase 2.3 Update Timing
+Phase 2.3 Update Timing | Checksum: 1be465fec
+
+Time (s): cpu = 00:00:26 ; elapsed = 00:00:22 . Memory (MB): peak = 2826.098 ; gain = 103.254 ; free physical = 3910 ; free virtual = 30889
+INFO: [Route 35-416] Intermediate Timing Summary | WNS=26.479 | TNS=0.000 | WHS=-0.254 | THS=-14.153|
+
+
+Router Utilization Summary
+ Global Vertical Routing Utilization = 0 %
+ Global Horizontal Routing Utilization = 0 %
+ Routable Net Status*
+ *Does not include unroutable nets such as driverless and loadless.
+ Run report_route_status for detailed report.
+ Number of Failed Nets = 381
+ (Failed Nets is the sum of unrouted and partially routed nets)
+ Number of Unrouted Nets = 381
+ Number of Partially Routed Nets = 0
+ Number of Node Overlaps = 0
+
+Phase 2 Router Initialization | Checksum: 2470b9ba4
+
+Time (s): cpu = 00:00:27 ; elapsed = 00:00:22 . Memory (MB): peak = 2831.129 ; gain = 108.285 ; free physical = 3907 ; free virtual = 30885
+
+Phase 3 Initial Routing
+
+Phase 3.1 Global Routing
+Phase 3.1 Global Routing | Checksum: 2470b9ba4
+
+Time (s): cpu = 00:00:27 ; elapsed = 00:00:22 . Memory (MB): peak = 2831.129 ; gain = 108.285 ; free physical = 3907 ; free virtual = 30885
+Phase 3 Initial Routing | Checksum: 19684a300
+
+Time (s): cpu = 00:00:28 ; elapsed = 00:00:23 . Memory (MB): peak = 2831.129 ; gain = 108.285 ; free physical = 3906 ; free virtual = 30884
+
+Phase 4 Rip-up And Reroute
+
+Phase 4.1 Global Iteration 0
+ Number of Nodes with overlaps = 21
+ Number of Nodes with overlaps = 0
+INFO: [Route 35-416] Intermediate Timing Summary | WNS=24.829 | TNS=0.000 | WHS=N/A | THS=N/A |
+
+Phase 4.1 Global Iteration 0 | Checksum: be565e86
+
+Time (s): cpu = 00:00:28 ; elapsed = 00:00:23 . Memory (MB): peak = 2831.129 ; gain = 108.285 ; free physical = 3905 ; free virtual = 30884
+Phase 4 Rip-up And Reroute | Checksum: be565e86
+
+Time (s): cpu = 00:00:28 ; elapsed = 00:00:23 . Memory (MB): peak = 2831.129 ; gain = 108.285 ; free physical = 3905 ; free virtual = 30884
+
+Phase 5 Delay and Skew Optimization
+
+Phase 5.1 Delay CleanUp
+Phase 5.1 Delay CleanUp | Checksum: be565e86
+
+Time (s): cpu = 00:00:28 ; elapsed = 00:00:23 . Memory (MB): peak = 2831.129 ; gain = 108.285 ; free physical = 3905 ; free virtual = 30884
+
+Phase 5.2 Clock Skew Optimization
+Phase 5.2 Clock Skew Optimization | Checksum: be565e86
+
+Time (s): cpu = 00:00:28 ; elapsed = 00:00:23 . Memory (MB): peak = 2831.129 ; gain = 108.285 ; free physical = 3905 ; free virtual = 30884
+Phase 5 Delay and Skew Optimization | Checksum: be565e86
+
+Time (s): cpu = 00:00:28 ; elapsed = 00:00:23 . Memory (MB): peak = 2831.129 ; gain = 108.285 ; free physical = 3905 ; free virtual = 30884
+
+Phase 6 Post Hold Fix
+
+Phase 6.1 Hold Fix Iter
+
+Phase 6.1.1 Update Timing
+Phase 6.1.1 Update Timing | Checksum: baf05697
+
+Time (s): cpu = 00:00:28 ; elapsed = 00:00:23 . Memory (MB): peak = 2831.129 ; gain = 108.285 ; free physical = 3905 ; free virtual = 30884
+INFO: [Route 35-416] Intermediate Timing Summary | WNS=24.908 | TNS=0.000 | WHS=0.057 | THS=0.000 |
+
+Phase 6.1 Hold Fix Iter | Checksum: baf05697
+
+Time (s): cpu = 00:00:28 ; elapsed = 00:00:23 . Memory (MB): peak = 2831.129 ; gain = 108.285 ; free physical = 3905 ; free virtual = 30884
+Phase 6 Post Hold Fix | Checksum: baf05697
+
+Time (s): cpu = 00:00:28 ; elapsed = 00:00:23 . Memory (MB): peak = 2831.129 ; gain = 108.285 ; free physical = 3905 ; free virtual = 30884
+
+Phase 7 Route finalize
+
+Router Utilization Summary
+ Global Vertical Routing Utilization = 0.0907864 %
+ Global Horizontal Routing Utilization = 0.0622336 %
+ Routable Net Status*
+ *Does not include unroutable nets such as driverless and loadless.
+ Run report_route_status for detailed report.
+ Number of Failed Nets = 0
+ (Failed Nets is the sum of unrouted and partially routed nets)
+ Number of Unrouted Nets = 0
+ Number of Partially Routed Nets = 0
+ Number of Node Overlaps = 0
+
+Phase 7 Route finalize | Checksum: ae742c66
+
+Time (s): cpu = 00:00:28 ; elapsed = 00:00:23 . Memory (MB): peak = 2831.129 ; gain = 108.285 ; free physical = 3905 ; free virtual = 30884
+
+Phase 8 Verifying routed nets
+
+ Verification completed successfully
+Phase 8 Verifying routed nets | Checksum: ae742c66
+
+Time (s): cpu = 00:00:28 ; elapsed = 00:00:23 . Memory (MB): peak = 2831.129 ; gain = 108.285 ; free physical = 3904 ; free virtual = 30883
+
+Phase 9 Depositing Routes
+Phase 9 Depositing Routes | Checksum: e93cd8e7
+
+Time (s): cpu = 00:00:28 ; elapsed = 00:00:23 . Memory (MB): peak = 2847.137 ; gain = 124.293 ; free physical = 3904 ; free virtual = 30883
+
+Phase 10 Post Router Timing
+INFO: [Route 35-57] Estimated Timing Summary | WNS=24.908 | TNS=0.000 | WHS=0.057 | THS=0.000 |
+
+INFO: [Route 35-327] The final timing numbers are based on the router estimated timing analysis. For a complete and accurate timing signoff, please run report_timing_summary.
+Phase 10 Post Router Timing | Checksum: e93cd8e7
+
+Time (s): cpu = 00:00:28 ; elapsed = 00:00:23 . Memory (MB): peak = 2847.137 ; gain = 124.293 ; free physical = 3905 ; free virtual = 30884
+INFO: [Route 35-16] Router Completed Successfully
+
+Time (s): cpu = 00:00:28 ; elapsed = 00:00:23 . Memory (MB): peak = 2847.137 ; gain = 124.293 ; free physical = 3944 ; free virtual = 30922
+
+Routing Is Done.
+INFO: [Common 17-83] Releasing license: Implementation
+88 Infos, 0 Warnings, 0 Critical Warnings and 0 Errors encountered.
+route_design completed successfully
+route_design: Time (s): cpu = 00:00:29 ; elapsed = 00:00:23 . Memory (MB): peak = 2847.137 ; gain = 126.824 ; free physical = 3944 ; free virtual = 30922
+INFO: [Timing 38-480] Writing timing data to binary archive.
+Writing XDEF routing.
+Writing XDEF routing logical nets.
+Writing XDEF routing special nets.
+Write XDEF Complete: Time (s): cpu = 00:00:00.15 ; elapsed = 00:00:00.06 . Memory (MB): peak = 2847.137 ; gain = 0.000 ; free physical = 3939 ; free virtual = 30919
+INFO: [Common 17-1381] The checkpoint '/home/prasic/game/game.runs/impl_1/TopModule_routed.dcp' has been generated.
+INFO: [runtcl-4] Executing : report_drc -file TopModule_drc_routed.rpt -pb TopModule_drc_routed.pb -rpx TopModule_drc_routed.rpx
+Command: report_drc -file TopModule_drc_routed.rpt -pb TopModule_drc_routed.pb -rpx TopModule_drc_routed.rpx
+INFO: [IP_Flow 19-1839] IP Catalog is up to date.
+INFO: [DRC 23-27] Running DRC with 8 threads
+INFO: [Vivado_Tcl 2-168] The results of DRC are in file /home/prasic/game/game.runs/impl_1/TopModule_drc_routed.rpt.
+report_drc completed successfully
+INFO: [runtcl-4] Executing : report_methodology -file TopModule_methodology_drc_routed.rpt -pb TopModule_methodology_drc_routed.pb -rpx TopModule_methodology_drc_routed.rpx
+Command: report_methodology -file TopModule_methodology_drc_routed.rpt -pb TopModule_methodology_drc_routed.pb -rpx TopModule_methodology_drc_routed.rpx
+INFO: [Timing 38-35] Done setting XDC timing constraints.
+INFO: [DRC 23-133] Running Methodology with 8 threads
+INFO: [Vivado_Tcl 2-1520] The results of Report Methodology are in file /home/prasic/game/game.runs/impl_1/TopModule_methodology_drc_routed.rpt.
+report_methodology completed successfully
+INFO: [runtcl-4] Executing : report_power -file TopModule_power_routed.rpt -pb TopModule_power_summary_routed.pb -rpx TopModule_power_routed.rpx
+Command: report_power -file TopModule_power_routed.rpt -pb TopModule_power_summary_routed.pb -rpx TopModule_power_routed.rpx
+INFO: [Timing 38-35] Done setting XDC timing constraints.
+Running Vector-less Activity Propagation...
+
+Finished Running Vector-less Activity Propagation
+100 Infos, 0 Warnings, 0 Critical Warnings and 0 Errors encountered.
+report_power completed successfully
+INFO: [runtcl-4] Executing : report_route_status -file TopModule_route_status.rpt -pb TopModule_route_status.pb
+INFO: [runtcl-4] Executing : report_timing_summary -max_paths 10 -report_unconstrained -file TopModule_timing_summary_routed.rpt -pb TopModule_timing_summary_routed.pb -rpx TopModule_timing_summary_routed.rpx -warn_on_violation
+INFO: [Timing 38-91] UpdateTimingParams: Speed grade: -1, Delay Type: min_max.
+INFO: [Timing 38-191] Multithreading enabled for timing update using a maximum of 8 CPUs
+INFO: [runtcl-4] Executing : report_incremental_reuse -file TopModule_incremental_reuse_routed.rpt
+INFO: [Vivado_Tcl 4-1062] Incremental flow is disabled. No incremental reuse Info to report.
+INFO: [runtcl-4] Executing : report_clock_utilization -file TopModule_clock_utilization_routed.rpt
+INFO: [runtcl-4] Executing : report_bus_skew -warn_on_violation -file TopModule_bus_skew_routed.rpt -pb TopModule_bus_skew_routed.pb -rpx TopModule_bus_skew_routed.rpx
+INFO: [Timing 38-91] UpdateTimingParams: Speed grade: -1, Delay Type: min_max.
+INFO: [Timing 38-191] Multithreading enabled for timing update using a maximum of 8 CPUs
+Command: write_bitstream -force TopModule.bit
+Attempting to get a license for feature 'Implementation' and/or device 'xc7a100t'
+INFO: [Common 17-349] Got license for feature 'Implementation' and/or device 'xc7a100t'
+Running DRC as a precondition to command write_bitstream
+INFO: [IP_Flow 19-1839] IP Catalog is up to date.
+INFO: [DRC 23-27] Running DRC with 8 threads
+WARNING: [DRC CFGBVS-1] Missing CFGBVS and CONFIG_VOLTAGE Design Properties: Neither the CFGBVS nor CONFIG_VOLTAGE voltage property is set in the current_design. Configuration bank voltage select (CFGBVS) must be set to VCCO or GND, and CONFIG_VOLTAGE must be set to the correct configuration voltage, in order to determine the I/O voltage support for the pins in bank 0. It is suggested to specify these either using the 'Edit Device Properties' function in the GUI or directly in the XDC file using the following syntax:
+
+ set_property CFGBVS value1 [current_design]
+ #where value1 is either VCCO or GND
+
+ set_property CONFIG_VOLTAGE value2 [current_design]
+ #where value2 is the voltage provided to configuration bank 0
+
+Refer to the device configuration user guide for more information.
+INFO: [Vivado 12-3199] DRC finished with 0 Errors, 1 Warnings
+INFO: [Vivado 12-3200] Please refer to the DRC report (report_drc) for more information.
+INFO: [Designutils 20-2272] Running write_bitstream with 8 threads.
+Loading data files...
+Loading site data...
+Loading route data...
+Processing options...
+Creating bitmap...
+Creating bitstream...
+Writing bitstream ./TopModule.bit...
+INFO: [Vivado 12-1842] Bitgen Completed Successfully.
+INFO: [Common 17-83] Releasing license: Implementation
+11 Infos, 1 Warnings, 0 Critical Warnings and 0 Errors encountered.
+write_bitstream completed successfully
+write_bitstream: Time (s): cpu = 00:00:11 ; elapsed = 00:00:18 . Memory (MB): peak = 3175.145 ; gain = 233.242 ; free physical = 3916 ; free virtual = 30901
+INFO: [Common 17-206] Exiting Vivado at Tue Feb 28 17:03:00 2023...
diff --git a/game.runs/impl_1/TopModule_bus_skew_routed.pb b/game.runs/impl_1/TopModule_bus_skew_routed.pb
new file mode 100644
index 0000000000000000000000000000000000000000..3390588d5da71a6f6866045d7ae5646edfab7b0e
Binary files /dev/null and b/game.runs/impl_1/TopModule_bus_skew_routed.pb differ
diff --git a/game.runs/impl_1/TopModule_bus_skew_routed.rpt b/game.runs/impl_1/TopModule_bus_skew_routed.rpt
new file mode 100644
index 0000000000000000000000000000000000000000..784a0d95954967489c61d30545804a576a8cca2b
--- /dev/null
+++ b/game.runs/impl_1/TopModule_bus_skew_routed.rpt
@@ -0,0 +1,15 @@
+Copyright 1986-2022 Xilinx, Inc. All Rights Reserved.
+------------------------------------------------------------------------------------------------------------------------------------------------------------
+| Tool Version : Vivado v.2022.2 (lin64) Build 3671981 Fri Oct 14 04:59:54 MDT 2022
+| Date : Tue Feb 28 17:02:42 2023
+| Host : LikeUE06 running 64-bit Linux Mint 20.3
+| Command : report_bus_skew -warn_on_violation -file TopModule_bus_skew_routed.rpt -pb TopModule_bus_skew_routed.pb -rpx TopModule_bus_skew_routed.rpx
+| Design : TopModule
+| Device : 7a100t-csg324
+| Speed File : -1 PRODUCTION 1.23 2018-06-13
+------------------------------------------------------------------------------------------------------------------------------------------------------------
+
+Bus Skew Report
+
+No bus skew constraints
+
diff --git a/game.runs/impl_1/TopModule_bus_skew_routed.rpx b/game.runs/impl_1/TopModule_bus_skew_routed.rpx
new file mode 100644
index 0000000000000000000000000000000000000000..272b1719a5e10d91ed2239b51224f136dccfbfdf
Binary files /dev/null and b/game.runs/impl_1/TopModule_bus_skew_routed.rpx differ
diff --git a/game.runs/impl_1/TopModule_clock_utilization_routed.rpt b/game.runs/impl_1/TopModule_clock_utilization_routed.rpt
new file mode 100644
index 0000000000000000000000000000000000000000..66f4eb74b0b24cf89a7eea7bef2beca807abcd15
--- /dev/null
+++ b/game.runs/impl_1/TopModule_clock_utilization_routed.rpt
@@ -0,0 +1,192 @@
+Copyright 1986-2022 Xilinx, Inc. All Rights Reserved.
+---------------------------------------------------------------------------------------
+| Tool Version : Vivado v.2022.2 (lin64) Build 3671981 Fri Oct 14 04:59:54 MDT 2022
+| Date : Tue Feb 28 17:02:42 2023
+| Host : LikeUE06 running 64-bit Linux Mint 20.3
+| Command : report_clock_utilization -file TopModule_clock_utilization_routed.rpt
+| Design : TopModule
+| Device : 7a100t-csg324
+| Speed File : -1 PRODUCTION 1.23 2018-06-13
+| Design State : Routed
+---------------------------------------------------------------------------------------
+
+Clock Utilization Report
+
+Table of Contents
+-----------------
+1. Clock Primitive Utilization
+2. Global Clock Resources
+3. Global Clock Source Details
+4. Clock Regions: Key Resource Utilization
+5. Clock Regions : Global Clock Summary
+6. Device Cell Placement Summary for Global Clock g0
+7. Device Cell Placement Summary for Global Clock g1
+8. Clock Region Cell Placement per Global Clock: Region X1Y1
+9. Clock Region Cell Placement per Global Clock: Region X1Y2
+
+1. Clock Primitive Utilization
+------------------------------
+
++----------+------+-----------+-----+--------------+--------+
+| Type | Used | Available | LOC | Clock Region | Pblock |
++----------+------+-----------+-----+--------------+--------+
+| BUFGCTRL | 2 | 32 | 0 | 0 | 0 |
+| BUFH | 0 | 96 | 0 | 0 | 0 |
+| BUFIO | 0 | 24 | 0 | 0 | 0 |
+| BUFMR | 0 | 12 | 0 | 0 | 0 |
+| BUFR | 0 | 24 | 0 | 0 | 0 |
+| MMCM | 1 | 6 | 0 | 0 | 0 |
+| PLL | 0 | 6 | 0 | 0 | 0 |
++----------+------+-----------+-----+--------------+--------+
+
+
+2. Global Clock Resources
+-------------------------
+
++-----------+-----------+-----------------+------------+----------------+--------------+-------------------+-------------+-----------------+--------------+----------------------+-----------------------------+--------------------------------------+
+| Global Id | Source Id | Driver Type/Pin | Constraint | Site | Clock Region | Load Clock Region | Clock Loads | Non-Clock Loads | Clock Period | Clock | Driver Pin | Net |
++-----------+-----------+-----------------+------------+----------------+--------------+-------------------+-------------+-----------------+--------------+----------------------+-----------------------------+--------------------------------------+
+| g0 | src0 | BUFG/O | None | BUFGCTRL_X0Y16 | n/a | 1 | 127 | 0 | 40.000 | clk_out1_clk_wiz_0 | pixelClk/inst/clkout1_buf/O | pixelClk/inst/clk_out1 |
+| g1 | src1 | BUFG/O | None | BUFGCTRL_X0Y17 | n/a | 1 | 1 | 0 | 10.000 | clkfbout_clk_wiz_0_1 | pixelClk/inst/clkf_buf/O | pixelClk/inst/clkfbout_buf_clk_wiz_0 |
++-----------+-----------+-----------------+------------+----------------+--------------+-------------------+-------------+-----------------+--------------+----------------------+-----------------------------+--------------------------------------+
+* Clock Loads column represents cell count of net connects that connect to a clock pin. Internal cell leaf pins are not considered
+** Non-Clock Loads column represents cell count of non-clock pin loads
+
+
+3. Global Clock Source Details
+------------------------------
+
++-----------+-----------+---------------------+------------+-----------------+--------------+-------------+-----------------+---------------------+--------------+--------------------------------------+----------------------------------+
+| Source Id | Global Id | Driver Type/Pin | Constraint | Site | Clock Region | Clock Loads | Non-Clock Loads | Source Clock Period | Source Clock | Driver Pin | Net |
++-----------+-----------+---------------------+------------+-----------------+--------------+-------------+-----------------+---------------------+--------------+--------------------------------------+----------------------------------+
+| src0 | g0 | MMCME2_ADV/CLKOUT0 | None | MMCME2_ADV_X1Y2 | X1Y2 | 1 | 0 | 40.000 | Multiple | pixelClk/inst/mmcm_adv_inst/CLKOUT0 | pixelClk/inst/clk_out1_clk_wiz_0 |
+| src1 | g1 | MMCME2_ADV/CLKFBOUT | None | MMCME2_ADV_X1Y2 | X1Y2 | 1 | 0 | 10.000 | Multiple | pixelClk/inst/mmcm_adv_inst/CLKFBOUT | pixelClk/inst/clkfbout_clk_wiz_0 |
++-----------+-----------+---------------------+------------+-----------------+--------------+-------------+-----------------+---------------------+--------------+--------------------------------------+----------------------------------+
+* Clock Loads column represents cell count of net connects that connect to a clock pin. Internal cell leaf pins are not considered
+** Non-Clock Loads column represents cell count of non-clock pin loads
+
+
+4. Clock Regions: Key Resource Utilization
+------------------------------------------
+
++-------------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+
+| | Global Clock | BUFRs | BUFMRs | BUFIOs | MMCM | PLL | GT | PCI | ILOGIC | OLOGIC | FF | LUTM | RAMB18 | RAMB36 | DSP48E2 |
++-------------------+------+-------+------+-------+------+-------+------+-------+------+-------+------+-------+------+-------+------+-------+------+-------+------+-------+------+-------+------+-------+------+-------+------+-------+------+-------+
+| Clock Region Name | Used | Avail | Used | Avail | Used | Avail | Used | Avail | Used | Avail | Used | Avail | Used | Avail | Used | Avail | Used | Avail | Used | Avail | Used | Avail | Used | Avail | Used | Avail | Used | Avail | Used | Avail |
++-------------------+------+-------+------+-------+------+-------+------+-------+------+-------+------+-------+------+-------+------+-------+------+-------+------+-------+------+-------+------+-------+------+-------+------+-------+------+-------+
+| X0Y0 | 0 | 12 | 0 | 4 | 0 | 2 | 0 | 4 | 0 | 1 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 50 | 0 | 50 | 0 | 2600 | 0 | 600 | 0 | 20 | 0 | 10 | 0 | 20 |
+| X1Y0 | 0 | 12 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 4 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1500 | 0 | 550 | 0 | 40 | 0 | 20 | 0 | 40 |
+| X0Y1 | 0 | 12 | 0 | 4 | 0 | 2 | 0 | 4 | 0 | 1 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 50 | 0 | 50 | 0 | 2000 | 0 | 600 | 0 | 20 | 0 | 10 | 0 | 20 |
+| X1Y1 | 1 | 12 | 0 | 4 | 0 | 2 | 0 | 4 | 0 | 1 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 50 | 0 | 50 | 127 | 1900 | 47 | 650 | 0 | 60 | 0 | 30 | 0 | 40 |
+| X0Y2 | 0 | 12 | 0 | 4 | 0 | 2 | 0 | 4 | 0 | 1 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 50 | 0 | 50 | 0 | 2000 | 0 | 600 | 0 | 20 | 0 | 10 | 0 | 20 |
+| X1Y2 | 1 | 12 | 0 | 4 | 0 | 2 | 0 | 4 | 1 | 1 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 50 | 0 | 50 | 0 | 1900 | 0 | 650 | 0 | 60 | 0 | 30 | 0 | 40 |
+| X0Y3 | 0 | 12 | 0 | 4 | 0 | 2 | 0 | 4 | 0 | 1 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 50 | 0 | 50 | 0 | 2600 | 0 | 600 | 0 | 20 | 0 | 10 | 0 | 20 |
+| X1Y3 | 0 | 12 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 4 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 1350 | 0 | 500 | 0 | 30 | 0 | 15 | 0 | 40 |
++-------------------+------+-------+------+-------+------+-------+------+-------+------+-------+------+-------+------+-------+------+-------+------+-------+------+-------+------+-------+------+-------+------+-------+------+-------+------+-------+
+* Global Clock column represents track count; while other columns represents cell counts
+
+
+5. Clock Regions : Global Clock Summary
+---------------------------------------
+
+All Modules
++----+----+----+
+| | X0 | X1 |
++----+----+----+
+| Y3 | 0 | 0 |
+| Y2 | 0 | 1 |
+| Y1 | 0 | 1 |
+| Y0 | 0 | 0 |
++----+----+----+
+
+
+6. Device Cell Placement Summary for Global Clock g0
+----------------------------------------------------
+
++-----------+-----------------+-------------------+----------+-------------+----------------+-------------+----------+----------------+----------+------------------------+
+| Global Id | Driver Type/Pin | Driver Region (D) | Clock | Period (ns) | Waveform (ns) | Slice Loads | IO Loads | Clocking Loads | GT Loads | Net |
++-----------+-----------------+-------------------+----------+-------------+----------------+-------------+----------+----------------+----------+------------------------+
+| g0 | BUFG/O | n/a | Multiple | 40.000 | {0.000 20.000} | 127 | 0 | 0 | 0 | pixelClk/inst/clk_out1 |
++-----------+-----------------+-------------------+----------+-------------+----------------+-------------+----------+----------------+----------+------------------------+
+* Slice Loads column represents load cell count of all cell types other than IO, GT and clock resources
+** IO Loads column represents load cell count of IO types
+*** Clocking Loads column represents load cell count that are clock resources (global clock buffer, MMCM, PLL, etc)
+**** GT Loads column represents load cell count of GT types
+
+
++----+----+------+-----------------------+
+| | X0 | X1 | HORIZONTAL PROG DELAY |
++----+----+------+-----------------------+
+| Y3 | 0 | 0 | - |
+| Y2 | 0 | 0 | - |
+| Y1 | 0 | 127 | 0 |
+| Y0 | 0 | 0 | - |
++----+----+------+-----------------------+
+
+
+7. Device Cell Placement Summary for Global Clock g1
+----------------------------------------------------
+
++-----------+-----------------+-------------------+----------+-------------+---------------+-------------+----------+----------------+----------+--------------------------------------+
+| Global Id | Driver Type/Pin | Driver Region (D) | Clock | Period (ns) | Waveform (ns) | Slice Loads | IO Loads | Clocking Loads | GT Loads | Net |
++-----------+-----------------+-------------------+----------+-------------+---------------+-------------+----------+----------------+----------+--------------------------------------+
+| g1 | BUFG/O | n/a | Multiple | 10.000 | {0.000 5.000} | 0 | 0 | 1 | 0 | pixelClk/inst/clkfbout_buf_clk_wiz_0 |
++-----------+-----------------+-------------------+----------+-------------+---------------+-------------+----------+----------------+----------+--------------------------------------+
+* Slice Loads column represents load cell count of all cell types other than IO, GT and clock resources
+** IO Loads column represents load cell count of IO types
+*** Clocking Loads column represents load cell count that are clock resources (global clock buffer, MMCM, PLL, etc)
+**** GT Loads column represents load cell count of GT types
+
+
++----+----+----+-----------------------+
+| | X0 | X1 | HORIZONTAL PROG DELAY |
++----+----+----+-----------------------+
+| Y3 | 0 | 0 | - |
+| Y2 | 0 | 1 | 0 |
+| Y1 | 0 | 0 | - |
+| Y0 | 0 | 0 | - |
++----+----+----+-----------------------+
+
+
+8. Clock Region Cell Placement per Global Clock: Region X1Y1
+------------------------------------------------------------
+
++-----------+-------+-----------------+------------+-------------+-----------------+-----+-------------+------+-----+----+------+-----+---------+------------------------+
+| Global Id | Track | Driver Type/Pin | Constraint | Clock Loads | Non-Clock Loads | FF | Memory LUTs | RAMB | DSP | GT | MMCM | PLL | Hard IP | Net |
++-----------+-------+-----------------+------------+-------------+-----------------+-----+-------------+------+-----+----+------+-----+---------+------------------------+
+| g0 | n/a | BUFG/O | None | 127 | 0 | 127 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | pixelClk/inst/clk_out1 |
++-----------+-------+-----------------+------------+-------------+-----------------+-----+-------------+------+-----+----+------+-----+---------+------------------------+
+* Clock Loads column represents cell count of net connects that connect to a clock pin. Internal cell leaf pins are not considered
+** Non-Clock Loads column represents cell count of non-clock pin loads
+*** Columns FF, LUTRAM, RAMB through 'Hard IP' represents load cell counts
+
+
+9. Clock Region Cell Placement per Global Clock: Region X1Y2
+------------------------------------------------------------
+
++-----------+-------+-----------------+------------+-------------+-----------------+----+-------------+------+-----+----+------+-----+---------+--------------------------------------+
+| Global Id | Track | Driver Type/Pin | Constraint | Clock Loads | Non-Clock Loads | FF | Memory LUTs | RAMB | DSP | GT | MMCM | PLL | Hard IP | Net |
++-----------+-------+-----------------+------------+-------------+-----------------+----+-------------+------+-----+----+------+-----+---------+--------------------------------------+
+| g1 | n/a | BUFG/O | None | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | pixelClk/inst/clkfbout_buf_clk_wiz_0 |
++-----------+-------+-----------------+------------+-------------+-----------------+----+-------------+------+-----+----+------+-----+---------+--------------------------------------+
+* Clock Loads column represents cell count of net connects that connect to a clock pin. Internal cell leaf pins are not considered
+** Non-Clock Loads column represents cell count of non-clock pin loads
+*** Columns FF, LUTRAM, RAMB through 'Hard IP' represents load cell counts
+
+
+
+# Location of BUFG Primitives
+set_property LOC BUFGCTRL_X0Y17 [get_cells pixelClk/inst/clkf_buf]
+set_property LOC BUFGCTRL_X0Y16 [get_cells pixelClk/inst/clkout1_buf]
+
+# Location of IO Primitives which is load of clock spine
+
+# Location of clock ports
+set_property LOC IOB_X1Y126 [get_ports clk]
+
+# Clock net "pixelClk/inst/clk_out1" driven by instance "pixelClk/inst/clkout1_buf" located at site "BUFGCTRL_X0Y16"
+#startgroup
+create_pblock {CLKAG_pixelClk/inst/clk_out1}
+add_cells_to_pblock [get_pblocks {CLKAG_pixelClk/inst/clk_out1}] [get_cells -filter { PRIMITIVE_GROUP != I/O && IS_PRIMITIVE==1 && PRIMITIVE_LEVEL !=INTERNAL } -of_object [get_pins -filter {DIRECTION==IN} -of_objects [get_nets -hierarchical -filter {PARENT=="pixelClk/inst/clk_out1"}]]]
+resize_pblock [get_pblocks {CLKAG_pixelClk/inst/clk_out1}] -add {CLOCKREGION_X1Y1:CLOCKREGION_X1Y1}
+#endgroup
diff --git a/game.runs/impl_1/TopModule_control_sets_placed.rpt b/game.runs/impl_1/TopModule_control_sets_placed.rpt
new file mode 100644
index 0000000000000000000000000000000000000000..f139ddb554187b8d9e732eaa5ecc477e3eb0fb80
--- /dev/null
+++ b/game.runs/impl_1/TopModule_control_sets_placed.rpt
@@ -0,0 +1,87 @@
+Copyright 1986-2022 Xilinx, Inc. All Rights Reserved.
+--------------------------------------------------------------------------------------
+| Tool Version : Vivado v.2022.2 (lin64) Build 3671981 Fri Oct 14 04:59:54 MDT 2022
+| Date : Tue Feb 28 17:02:15 2023
+| Host : LikeUE06 running 64-bit Linux Mint 20.3
+| Command : report_control_sets -verbose -file TopModule_control_sets_placed.rpt
+| Design : TopModule
+| Device : xc7a100t
+--------------------------------------------------------------------------------------
+
+Control Set Information
+
+Table of Contents
+-----------------
+1. Summary
+2. Histogram
+3. Flip-Flop Distribution
+4. Detailed Control Set Information
+
+1. Summary
+----------
+
++----------------------------------------------------------+-------+
+| Status | Count |
++----------------------------------------------------------+-------+
+| Total control sets | 9 |
+| Minimum number of control sets | 9 |
+| Addition due to synthesis replication | 0 |
+| Addition due to physical synthesis replication | 0 |
+| Unused register locations in slices containing registers | 41 |
++----------------------------------------------------------+-------+
+* Control sets can be merged at opt_design using control_set_merge or merge_equivalent_drivers
+** Run report_qor_suggestions for automated merging and remapping suggestions
+
+
+2. Histogram
+------------
+
++--------------------+-------+
+| Fanout | Count |
++--------------------+-------+
+| Total control sets | 9 |
+| >= 0 to < 4 | 1 |
+| >= 4 to < 6 | 0 |
+| >= 6 to < 8 | 0 |
+| >= 8 to < 10 | 1 |
+| >= 10 to < 12 | 2 |
+| >= 12 to < 14 | 2 |
+| >= 14 to < 16 | 0 |
+| >= 16 | 3 |
++--------------------+-------+
+* Control sets can be remapped at either synth_design or opt_design
+
+
+3. Flip-Flop Distribution
+-------------------------
+
++--------------+-----------------------+------------------------+-----------------+--------------+
+| Clock Enable | Synchronous Set/Reset | Asynchronous Set/Reset | Total Registers | Total Slices |
++--------------+-----------------------+------------------------+-----------------+--------------+
+| No | No | No | 3 | 2 |
+| No | No | Yes | 11 | 4 |
+| No | Yes | No | 0 | 0 |
+| Yes | No | No | 29 | 12 |
+| Yes | No | Yes | 75 | 25 |
+| Yes | Yes | No | 9 | 3 |
++--------------+-----------------------+------------------------+-----------------+--------------+
+
+
+4. Detailed Control Set Information
+-----------------------------------
+
++-------------------------+------------------------------------+---------------------------------------------+------------------+----------------+--------------+
+| Clock Signal | Enable Signal | Set/Reset Signal | Slice Load Count | Bel Load Count | Bels / Slice |
++-------------------------+------------------------------------+---------------------------------------------+------------------+----------------+--------------+
+| pixelClk/inst/clk_out1 | | | 2 | 3 | 1.50 |
+| pixelClk/inst/clk_out1 | runnerObject/pos_object_y_target_2 | runnerObject/pos_object_y_target[8]_i_1_n_0 | 3 | 9 | 3.00 |
+| pixelClk/inst/clk_out1 | vgaInterface/counter_v[9]_i_1_n_0 | vgaInterface/btnCpuReset | 4 | 10 | 2.50 |
+| pixelClk/inst/clk_out1 | | vgaInterface/btnCpuReset | 4 | 11 | 2.75 |
+| pixelClk/inst/clk_out1 | vgaInterface/counter_f | vgaInterface/btnCpuReset | 3 | 12 | 4.00 |
+| pixelClk/inst/clk_out1 | runnerObject/fcount_edge0__0 | vgaInterface/btnCpuReset | 3 | 12 | 4.00 |
+| pixelClk/inst/clk_out1 | runnerObject/E[0] | vgaInterface/btnCpuReset | 6 | 19 | 3.17 |
+| pixelClk/inst/clk_out1 | vgaInterface/E[0] | vgaInterface/btnCpuReset | 9 | 22 | 2.44 |
+| pixelClk/inst/clk_out1 | vgaInterface/E[0] | | 12 | 29 | 2.42 |
++-------------------------+------------------------------------+---------------------------------------------+------------------+----------------+--------------+
+
+
diff --git a/game.runs/impl_1/TopModule_drc_opted.pb b/game.runs/impl_1/TopModule_drc_opted.pb
new file mode 100644
index 0000000000000000000000000000000000000000..70698d16a043af0b5d745495ba43bfe143354a40
Binary files /dev/null and b/game.runs/impl_1/TopModule_drc_opted.pb differ
diff --git a/game.runs/impl_1/TopModule_drc_opted.rpt b/game.runs/impl_1/TopModule_drc_opted.rpt
new file mode 100644
index 0000000000000000000000000000000000000000..d17b3c18ae989c61d8b6e40ea844b0ca502147a9
--- /dev/null
+++ b/game.runs/impl_1/TopModule_drc_opted.rpt
@@ -0,0 +1,49 @@
+Copyright 1986-2022 Xilinx, Inc. All Rights Reserved.
+------------------------------------------------------------------------------------------------------------------
+| Tool Version : Vivado v.2022.2 (lin64) Build 3671981 Fri Oct 14 04:59:54 MDT 2022
+| Date : Tue Feb 28 17:02:12 2023
+| Host : LikeUE06 running 64-bit Linux Mint 20.3
+| Command : report_drc -file TopModule_drc_opted.rpt -pb TopModule_drc_opted.pb -rpx TopModule_drc_opted.rpx
+| Design : TopModule
+| Device : xc7a100tcsg324-1
+| Speed File : -1
+| Design State : Synthesized
+------------------------------------------------------------------------------------------------------------------
+
+Report DRC
+
+Table of Contents
+-----------------
+1. REPORT SUMMARY
+2. REPORT DETAILS
+
+1. REPORT SUMMARY
+-----------------
+ Netlist: netlist
+ Floorplan: design_1
+ Design limits: <entire design considered>
+ Ruledeck: default
+ Max violations: <unlimited>
+ Violations found: 1
++----------+----------+-----------------------------------------------------+------------+
+| Rule | Severity | Description | Violations |
++----------+----------+-----------------------------------------------------+------------+
+| CFGBVS-1 | Warning | Missing CFGBVS and CONFIG_VOLTAGE Design Properties | 1 |
++----------+----------+-----------------------------------------------------+------------+
+
+2. REPORT DETAILS
+-----------------
+CFGBVS-1#1 Warning
+Missing CFGBVS and CONFIG_VOLTAGE Design Properties
+Neither the CFGBVS nor CONFIG_VOLTAGE voltage property is set in the current_design. Configuration bank voltage select (CFGBVS) must be set to VCCO or GND, and CONFIG_VOLTAGE must be set to the correct configuration voltage, in order to determine the I/O voltage support for the pins in bank 0. It is suggested to specify these either using the 'Edit Device Properties' function in the GUI or directly in the XDC file using the following syntax:
+
+ set_property CFGBVS value1 [current_design]
+ #where value1 is either VCCO or GND
+
+ set_property CONFIG_VOLTAGE value2 [current_design]
+ #where value2 is the voltage provided to configuration bank 0
+
+Refer to the device configuration user guide for more information.
+Related violations: <none>
+
+
diff --git a/game.runs/impl_1/TopModule_drc_opted.rpx b/game.runs/impl_1/TopModule_drc_opted.rpx
new file mode 100644
index 0000000000000000000000000000000000000000..06d2444790979f998c3e3a53dec6e5dfe71676c2
Binary files /dev/null and b/game.runs/impl_1/TopModule_drc_opted.rpx differ
diff --git a/game.runs/impl_1/TopModule_drc_routed.pb b/game.runs/impl_1/TopModule_drc_routed.pb
new file mode 100644
index 0000000000000000000000000000000000000000..70698d16a043af0b5d745495ba43bfe143354a40
Binary files /dev/null and b/game.runs/impl_1/TopModule_drc_routed.pb differ
diff --git a/game.runs/impl_1/TopModule_drc_routed.rpt b/game.runs/impl_1/TopModule_drc_routed.rpt
new file mode 100644
index 0000000000000000000000000000000000000000..7569538e8e0ff9d628334f4ff4c345a2561d1c7a
--- /dev/null
+++ b/game.runs/impl_1/TopModule_drc_routed.rpt
@@ -0,0 +1,49 @@
+Copyright 1986-2022 Xilinx, Inc. All Rights Reserved.
+---------------------------------------------------------------------------------------------------------------------
+| Tool Version : Vivado v.2022.2 (lin64) Build 3671981 Fri Oct 14 04:59:54 MDT 2022
+| Date : Tue Feb 28 17:02:40 2023
+| Host : LikeUE06 running 64-bit Linux Mint 20.3
+| Command : report_drc -file TopModule_drc_routed.rpt -pb TopModule_drc_routed.pb -rpx TopModule_drc_routed.rpx
+| Design : TopModule
+| Device : xc7a100tcsg324-1
+| Speed File : -1
+| Design State : Fully Routed
+---------------------------------------------------------------------------------------------------------------------
+
+Report DRC
+
+Table of Contents
+-----------------
+1. REPORT SUMMARY
+2. REPORT DETAILS
+
+1. REPORT SUMMARY
+-----------------
+ Netlist: netlist
+ Floorplan: design_1
+ Design limits: <entire design considered>
+ Ruledeck: default
+ Max violations: <unlimited>
+ Violations found: 1
++----------+----------+-----------------------------------------------------+------------+
+| Rule | Severity | Description | Violations |
++----------+----------+-----------------------------------------------------+------------+
+| CFGBVS-1 | Warning | Missing CFGBVS and CONFIG_VOLTAGE Design Properties | 1 |
++----------+----------+-----------------------------------------------------+------------+
+
+2. REPORT DETAILS
+-----------------
+CFGBVS-1#1 Warning
+Missing CFGBVS and CONFIG_VOLTAGE Design Properties
+Neither the CFGBVS nor CONFIG_VOLTAGE voltage property is set in the current_design. Configuration bank voltage select (CFGBVS) must be set to VCCO or GND, and CONFIG_VOLTAGE must be set to the correct configuration voltage, in order to determine the I/O voltage support for the pins in bank 0. It is suggested to specify these either using the 'Edit Device Properties' function in the GUI or directly in the XDC file using the following syntax:
+
+ set_property CFGBVS value1 [current_design]
+ #where value1 is either VCCO or GND
+
+ set_property CONFIG_VOLTAGE value2 [current_design]
+ #where value2 is the voltage provided to configuration bank 0
+
+Refer to the device configuration user guide for more information.
+Related violations: <none>
+
+
diff --git a/game.runs/impl_1/TopModule_drc_routed.rpx b/game.runs/impl_1/TopModule_drc_routed.rpx
new file mode 100644
index 0000000000000000000000000000000000000000..c3ea3aadbde8c06a45e05f92a14ef88fab340d6e
Binary files /dev/null and b/game.runs/impl_1/TopModule_drc_routed.rpx differ
diff --git a/game.runs/impl_1/TopModule_io_placed.rpt b/game.runs/impl_1/TopModule_io_placed.rpt
new file mode 100644
index 0000000000000000000000000000000000000000..1bb5e1488404b991416e8ce1eb2f34ccb71f545b
--- /dev/null
+++ b/game.runs/impl_1/TopModule_io_placed.rpt
@@ -0,0 +1,366 @@
+Copyright 1986-2022 Xilinx, Inc. All Rights Reserved.
+-------------------------------------------------------------------------------------------------
+| Tool Version : Vivado v.2022.2 (lin64) Build 3671981 Fri Oct 14 04:59:54 MDT 2022
+| Date : Tue Feb 28 17:02:15 2023
+| Host : LikeUE06 running 64-bit Linux Mint 20.3
+| Command : report_io -file TopModule_io_placed.rpt
+| Design : TopModule
+| Device : xc7a100t
+| Speed File : -1
+| Package : csg324
+| Package Version : FINAL 2012-07-17
+| Package Pin Delay Version : VERS. 2.0 2012-07-17
+-------------------------------------------------------------------------------------------------
+
+IO Information
+
+Table of Contents
+-----------------
+1. Summary
+2. IO Assignments by Package Pin
+
+1. Summary
+----------
+
++---------------+
+| Total User IO |
++---------------+
+| 33 |
++---------------+
+
+
+2. IO Assignments by Package Pin
+--------------------------------
+
++------------+-------------+------------+------------------------------+-------------+-------------+---------+------------+------+---------------------+----------------------+---------+------------+-----------+----------+------+------------------+--------------+-------------------+--------------+
+| Pin Number | Signal Name | Bank Type | Pin Name | Use | IO Standard | IO Bank | Drive (mA) | Slew | On-Chip Termination | Off-Chip Termination | Voltage | Constraint | Pull Type | DQS Bias | Vref | Signal Integrity | Pre Emphasis | Lvds Pre Emphasis | Equalization |
++------------+-------------+------------+------------------------------+-------------+-------------+---------+------------+------+---------------------+----------------------+---------+------------+-----------+----------+------+------------------+--------------+-------------------+--------------+
+| A1 | | High Range | IO_L9N_T1_DQS_AD7N_35 | User IO | | 35 | | | | | | | | | | | | | |
+| A2 | | | GND | GND | | | | | | | 0.0 | | | | | | | | |
+| A3 | vgaRed[0] | High Range | IO_L8N_T1_AD14N_35 | OUTPUT | LVCMOS33 | 35 | 12 | SLOW | | FP_VTT_50 | | FIXED | | | | NONE | | | |
+| A4 | vgaRed[3] | High Range | IO_L8P_T1_AD14P_35 | OUTPUT | LVCMOS33 | 35 | 12 | SLOW | | FP_VTT_50 | | FIXED | | | | NONE | | | |
+| A5 | vgaGreen[1] | High Range | IO_L3N_T0_DQS_AD5N_35 | OUTPUT | LVCMOS33 | 35 | 12 | SLOW | | FP_VTT_50 | | FIXED | | | | NONE | | | |
+| A6 | vgaGreen[3] | High Range | IO_L3P_T0_DQS_AD5P_35 | OUTPUT | LVCMOS33 | 35 | 12 | SLOW | | FP_VTT_50 | | FIXED | | | | NONE | | | |
+| A7 | | High Range | VCCO_35 | VCCO | | 35 | | | | | 3.30 | | | | | | | | |
+| A8 | | High Range | IO_L12N_T1_MRCC_16 | User IO | | 16 | | | | | | | | | | | | | |
+| A9 | | High Range | IO_L14N_T2_SRCC_16 | User IO | | 16 | | | | | | | | | | | | | |
+| A10 | | High Range | IO_L14P_T2_SRCC_16 | User IO | | 16 | | | | | | | | | | | | | |
+| A11 | | High Range | IO_L4N_T0_15 | User IO | | 15 | | | | | | | | | | | | | |
+| A12 | | | GND | GND | | | | | | | 0.0 | | | | | | | | |
+| A13 | | High Range | IO_L9P_T1_DQS_AD3P_15 | User IO | | 15 | | | | | | | | | | | | | |
+| A14 | | High Range | IO_L9N_T1_DQS_AD3N_15 | User IO | | 15 | | | | | | | | | | | | | |
+| A15 | | High Range | IO_L8P_T1_AD10P_15 | User IO | | 15 | | | | | | | | | | | | | |
+| A16 | | High Range | IO_L8N_T1_AD10N_15 | User IO | | 15 | | | | | | | | | | | | | |
+| A17 | | High Range | VCCO_15 | VCCO | | 15 | | | | | 3.30 | | | | | | | | |
+| A18 | | High Range | IO_L10N_T1_AD11N_15 | User IO | | 15 | | | | | | | | | | | | | |
+| B1 | | High Range | IO_L9P_T1_DQS_AD7P_35 | User IO | | 35 | | | | | | | | | | | | | |
+| B2 | | High Range | IO_L10N_T1_AD15N_35 | User IO | | 35 | | | | | | | | | | | | | |
+| B3 | | High Range | IO_L10P_T1_AD15P_35 | User IO | | 35 | | | | | | | | | | | | | |
+| B4 | vgaRed[1] | High Range | IO_L7N_T1_AD6N_35 | OUTPUT | LVCMOS33 | 35 | 12 | SLOW | | FP_VTT_50 | | FIXED | | | | NONE | | | |
+| B5 | | | GND | GND | | | | | | | 0.0 | | | | | | | | |
+| B6 | vgaGreen[2] | High Range | IO_L2N_T0_AD12N_35 | OUTPUT | LVCMOS33 | 35 | 12 | SLOW | | FP_VTT_50 | | FIXED | | | | NONE | | | |
+| B7 | vgaBlue[0] | High Range | IO_L2P_T0_AD12P_35 | OUTPUT | LVCMOS33 | 35 | 12 | SLOW | | FP_VTT_50 | | FIXED | | | | NONE | | | |
+| B8 | | High Range | IO_L12P_T1_MRCC_16 | User IO | | 16 | | | | | | | | | | | | | |
+| B9 | | High Range | IO_L11N_T1_SRCC_16 | User IO | | 16 | | | | | | | | | | | | | |
+| B10 | | High Range | VCCO_16 | VCCO | | 16 | | | | | any** | | | | | | | | |
+| B11 | Hsync | High Range | IO_L4P_T0_15 | OUTPUT | LVCMOS33 | 15 | 12 | SLOW | | FP_VTT_50 | | FIXED | | | | NONE | | | |
+| B12 | Vsync | High Range | IO_L3N_T0_DQS_AD1N_15 | OUTPUT | LVCMOS33 | 15 | 12 | SLOW | | FP_VTT_50 | | FIXED | | | | NONE | | | |
+| B13 | | High Range | IO_L2P_T0_AD8P_15 | User IO | | 15 | | | | | | | | | | | | | |
+| B14 | | High Range | IO_L2N_T0_AD8N_15 | User IO | | 15 | | | | | | | | | | | | | |
+| B15 | | | GND | GND | | | | | | | 0.0 | | | | | | | | |
+| B16 | | High Range | IO_L7P_T1_AD2P_15 | User IO | | 15 | | | | | | | | | | | | | |
+| B17 | | High Range | IO_L7N_T1_AD2N_15 | User IO | | 15 | | | | | | | | | | | | | |
+| B18 | | High Range | IO_L10P_T1_AD11P_15 | User IO | | 15 | | | | | | | | | | | | | |
+| C1 | | High Range | IO_L16N_T2_35 | User IO | | 35 | | | | | | | | | | | | | |
+| C2 | | High Range | IO_L16P_T2_35 | User IO | | 35 | | | | | | | | | | | | | |
+| C3 | | High Range | VCCO_35 | VCCO | | 35 | | | | | 3.30 | | | | | | | | |
+| C4 | | High Range | IO_L7P_T1_AD6P_35 | User IO | | 35 | | | | | | | | | | | | | |
+| C5 | vgaRed[2] | High Range | IO_L1N_T0_AD4N_35 | OUTPUT | LVCMOS33 | 35 | 12 | SLOW | | FP_VTT_50 | | FIXED | | | | NONE | | | |
+| C6 | vgaGreen[0] | High Range | IO_L1P_T0_AD4P_35 | OUTPUT | LVCMOS33 | 35 | 12 | SLOW | | FP_VTT_50 | | FIXED | | | | NONE | | | |
+| C7 | vgaBlue[1] | High Range | IO_L4N_T0_35 | OUTPUT | LVCMOS33 | 35 | 12 | SLOW | | FP_VTT_50 | | FIXED | | | | NONE | | | |
+| C8 | | | GND | GND | | | | | | | 0.0 | | | | | | | | |
+| C9 | | High Range | IO_L11P_T1_SRCC_16 | User IO | | 16 | | | | | | | | | | | | | |
+| C10 | | High Range | IO_L13N_T2_MRCC_16 | User IO | | 16 | | | | | | | | | | | | | |
+| C11 | | High Range | IO_L13P_T2_MRCC_16 | User IO | | 16 | | | | | | | | | | | | | |
+| C12 | btnCpuReset | High Range | IO_L3P_T0_DQS_AD1P_15 | INPUT | LVCMOS33 | 15 | | | | NONE | | FIXED | | | | NONE | | | |
+| C13 | | High Range | VCCO_15 | VCCO | | 15 | | | | | 3.30 | | | | | | | | |
+| C14 | | High Range | IO_L1N_T0_AD0N_15 | User IO | | 15 | | | | | | | | | | | | | |
+| C15 | | High Range | IO_L12N_T1_MRCC_15 | User IO | | 15 | | | | | | | | | | | | | |
+| C16 | | High Range | IO_L20P_T3_A20_15 | User IO | | 15 | | | | | | | | | | | | | |
+| C17 | | High Range | IO_L20N_T3_A19_15 | User IO | | 15 | | | | | | | | | | | | | |
+| C18 | | | GND | GND | | | | | | | 0.0 | | | | | | | | |
+| D1 | | | GND | GND | | | | | | | 0.0 | | | | | | | | |
+| D2 | | High Range | IO_L14N_T2_SRCC_35 | User IO | | 35 | | | | | | | | | | | | | |
+| D3 | | High Range | IO_L12N_T1_MRCC_35 | User IO | | 35 | | | | | | | | | | | | | |
+| D4 | | High Range | IO_L11N_T1_SRCC_35 | User IO | | 35 | | | | | | | | | | | | | |
+| D5 | | High Range | IO_L11P_T1_SRCC_35 | User IO | | 35 | | | | | | | | | | | | | |
+| D6 | | High Range | VCCO_35 | VCCO | | 35 | | | | | 3.30 | | | | | | | | |
+| D7 | vgaBlue[2] | High Range | IO_L6N_T0_VREF_35 | OUTPUT | LVCMOS33 | 35 | 12 | SLOW | | FP_VTT_50 | | FIXED | | | | NONE | | | |
+| D8 | vgaBlue[3] | High Range | IO_L4P_T0_35 | OUTPUT | LVCMOS33 | 35 | 12 | SLOW | | FP_VTT_50 | | FIXED | | | | NONE | | | |
+| D9 | | High Range | IO_L6N_T0_VREF_16 | User IO | | 16 | | | | | | | | | | | | | |
+| D10 | | High Range | IO_L19N_T3_VREF_16 | User IO | | 16 | | | | | | | | | | | | | |
+| D11 | | | GND | GND | | | | | | | 0.0 | | | | | | | | |
+| D12 | | High Range | IO_L6P_T0_15 | User IO | | 15 | | | | | | | | | | | | | |
+| D13 | | High Range | IO_L6N_T0_VREF_15 | User IO | | 15 | | | | | | | | | | | | | |
+| D14 | | High Range | IO_L1P_T0_AD0P_15 | User IO | | 15 | | | | | | | | | | | | | |
+| D15 | | High Range | IO_L12P_T1_MRCC_15 | User IO | | 15 | | | | | | | | | | | | | |
+| D16 | | High Range | VCCO_15 | VCCO | | 15 | | | | | 3.30 | | | | | | | | |
+| D17 | | High Range | IO_L16N_T2_A27_15 | User IO | | 15 | | | | | | | | | | | | | |
+| D18 | | High Range | IO_L21N_T3_DQS_A18_15 | User IO | | 15 | | | | | | | | | | | | | |
+| E1 | | High Range | IO_L18N_T2_35 | User IO | | 35 | | | | | | | | | | | | | |
+| E2 | | High Range | IO_L14P_T2_SRCC_35 | User IO | | 35 | | | | | | | | | | | | | |
+| E3 | clk | High Range | IO_L12P_T1_MRCC_35 | INPUT | LVCMOS33 | 35 | | | | NONE | | FIXED | | | | NONE | | | |
+| E4 | | | GND | GND | | | | | | | 0.0 | | | | | | | | |
+| E5 | | High Range | IO_L5N_T0_AD13N_35 | User IO | | 35 | | | | | | | | | | | | | |
+| E6 | | High Range | IO_L5P_T0_AD13P_35 | User IO | | 35 | | | | | | | | | | | | | |
+| E7 | | High Range | IO_L6P_T0_35 | User IO | | 35 | | | | | | | | | | | | | |
+| E8 | | Dedicated | VCCBATT_0 | Config | | 0 | | | | | | | | | | | | | |
+| E9 | | Dedicated | CCLK_0 | Config | | 0 | | | | | | | | | | | | | |
+| E10 | | Dedicated | TCK_0 | Config | | 0 | | | | | | | | | | | | | |
+| E11 | | Dedicated | TDI_0 | Config | | 0 | | | | | | | | | | | | | |
+| E12 | | Dedicated | TMS_0 | Config | | 0 | | | | | | | | | | | | | |
+| E13 | | Dedicated | TDO_0 | Config | | 0 | | | | | | | | | | | | | |
+| E14 | | | GND | GND | | | | | | | 0.0 | | | | | | | | |
+| E15 | | High Range | IO_L11P_T1_SRCC_15 | User IO | | 15 | | | | | | | | | | | | | |
+| E16 | | High Range | IO_L11N_T1_SRCC_15 | User IO | | 15 | | | | | | | | | | | | | |
+| E17 | | High Range | IO_L16P_T2_A28_15 | User IO | | 15 | | | | | | | | | | | | | |
+| E18 | | High Range | IO_L21P_T3_DQS_15 | User IO | | 15 | | | | | | | | | | | | | |
+| F1 | | High Range | IO_L18P_T2_35 | User IO | | 35 | | | | | | | | | | | | | |
+| F2 | | High Range | VCCO_35 | VCCO | | 35 | | | | | 3.30 | | | | | | | | |
+| F3 | | High Range | IO_L13N_T2_MRCC_35 | User IO | | 35 | | | | | | | | | | | | | |
+| F4 | | High Range | IO_L13P_T2_MRCC_35 | User IO | | 35 | | | | | | | | | | | | | |
+| F5 | | High Range | IO_0_35 | User IO | | 35 | | | | | | | | | | | | | |
+| F6 | | High Range | IO_L19N_T3_VREF_35 | User IO | | 35 | | | | | | | | | | | | | |
+| F7 | | | GND | GND | | | | | | | 0.0 | | | | | | | | |
+| F8 | | | VCCINT | VCCINT | | | | | | | | | | | | | | | |
+| F9 | | | GND | GND | | | | | | | 0.0 | | | | | | | | |
+| F10 | | | VCCBRAM | VCCBRAM | | | | | | | | | | | | | | | |
+| F11 | | | GND | GND | | | | | | | 0.0 | | | | | | | | |
+| F12 | | | VCCAUX | VCCAUX | | | | | | | 1.80 | | | | | | | | |
+| F13 | | High Range | IO_L5P_T0_AD9P_15 | User IO | | 15 | | | | | | | | | | | | | |
+| F14 | | High Range | IO_L5N_T0_AD9N_15 | User IO | | 15 | | | | | | | | | | | | | |
+| F15 | btnU | High Range | IO_L14P_T2_SRCC_15 | INPUT | LVCMOS33 | 15 | | | | NONE | | FIXED | | | | NONE | | | |
+| F16 | | High Range | IO_L14N_T2_SRCC_15 | User IO | | 15 | | | | | | | | | | | | | |
+| F17 | | | GND | GND | | | | | | | 0.0 | | | | | | | | |
+| F18 | | High Range | IO_L22N_T3_A16_15 | User IO | | 15 | | | | | | | | | | | | | |
+| G1 | | High Range | IO_L17N_T2_35 | User IO | | 35 | | | | | | | | | | | | | |
+| G2 | | High Range | IO_L15N_T2_DQS_35 | User IO | | 35 | | | | | | | | | | | | | |
+| G3 | | High Range | IO_L20N_T3_35 | User IO | | 35 | | | | | | | | | | | | | |
+| G4 | | High Range | IO_L20P_T3_35 | User IO | | 35 | | | | | | | | | | | | | |
+| G5 | | High Range | VCCO_35 | VCCO | | 35 | | | | | 3.30 | | | | | | | | |
+| G6 | | High Range | IO_L19P_T3_35 | User IO | | 35 | | | | | | | | | | | | | |
+| G7 | | | VCCINT | VCCINT | | | | | | | | | | | | | | | |
+| G8 | | | GND | GND | | | | | | | 0.0 | | | | | | | | |
+| G9 | | | VCCINT | VCCINT | | | | | | | | | | | | | | | |
+| G10 | | | GND | GND | | | | | | | 0.0 | | | | | | | | |
+| G11 | | | VCCBRAM | VCCBRAM | | | | | | | | | | | | | | | |
+| G12 | | | GND | GND | | | | | | | 0.0 | | | | | | | | |
+| G13 | | High Range | IO_0_15 | User IO | | 15 | | | | | | | | | | | | | |
+| G14 | | High Range | IO_L15N_T2_DQS_ADV_B_15 | User IO | | 15 | | | | | | | | | | | | | |
+| G15 | | High Range | VCCO_15 | VCCO | | 15 | | | | | 3.30 | | | | | | | | |
+| G16 | | High Range | IO_L13N_T2_MRCC_15 | User IO | | 15 | | | | | | | | | | | | | |
+| G17 | | High Range | IO_L18N_T2_A23_15 | User IO | | 15 | | | | | | | | | | | | | |
+| G18 | | High Range | IO_L22P_T3_A17_15 | User IO | | 15 | | | | | | | | | | | | | |
+| H1 | | High Range | IO_L17P_T2_35 | User IO | | 35 | | | | | | | | | | | | | |
+| H2 | | High Range | IO_L15P_T2_DQS_35 | User IO | | 35 | | | | | | | | | | | | | |
+| H3 | | | GND | GND | | | | | | | 0.0 | | | | | | | | |
+| H4 | | High Range | IO_L21N_T3_DQS_35 | User IO | | 35 | | | | | | | | | | | | | |
+| H5 | | High Range | IO_L24N_T3_35 | User IO | | 35 | | | | | | | | | | | | | |
+| H6 | | High Range | IO_L24P_T3_35 | User IO | | 35 | | | | | | | | | | | | | |
+| H7 | | | GND | GND | | | | | | | 0.0 | | | | | | | | |
+| H8 | | | VCCINT | VCCINT | | | | | | | | | | | | | | | |
+| H9 | | Dedicated | GNDADC_0 | XADC | | 0 | | | | | | | | | | | | | |
+| H10 | | Dedicated | VCCADC_0 | XADC | | 0 | | | | | | | | | | | | | |
+| H11 | | | GND | GND | | | | | | | 0.0 | | | | | | | | |
+| H12 | | | VCCAUX | VCCAUX | | | | | | | 1.80 | | | | | | | | |
+| H13 | | | GND | GND | | | | | | | 0.0 | | | | | | | | |
+| H14 | | High Range | IO_L15P_T2_DQS_15 | User IO | | 15 | | | | | | | | | | | | | |
+| H15 | | High Range | IO_L19N_T3_A21_VREF_15 | User IO | | 15 | | | | | | | | | | | | | |
+| H16 | | High Range | IO_L13P_T2_MRCC_15 | User IO | | 15 | | | | | | | | | | | | | |
+| H17 | | High Range | IO_L18P_T2_A24_15 | User IO | | 15 | | | | | | | | | | | | | |
+| H18 | | High Range | VCCO_15 | VCCO | | 15 | | | | | 3.30 | | | | | | | | |
+| J1 | | High Range | VCCO_35 | VCCO | | 35 | | | | | 3.30 | | | | | | | | |
+| J2 | | High Range | IO_L22N_T3_35 | User IO | | 35 | | | | | | | | | | | | | |
+| J3 | | High Range | IO_L22P_T3_35 | User IO | | 35 | | | | | | | | | | | | | |
+| J4 | | High Range | IO_L21P_T3_DQS_35 | User IO | | 35 | | | | | | | | | | | | | |
+| J5 | | High Range | IO_25_35 | User IO | | 35 | | | | | | | | | | | | | |
+| J6 | | | GND | GND | | | | | | | 0.0 | | | | | | | | |
+| J7 | | | VCCINT | VCCINT | | | | | | | | | | | | | | | |
+| J8 | | | GND | GND | | | | | | | 0.0 | | | | | | | | |
+| J9 | | Dedicated | VREFN_0 | XADC | | 0 | | | | | | | | | | | | | |
+| J10 | | Dedicated | VP_0 | XADC | | 0 | | | | | | | | | | | | | |
+| J11 | | | VCCINT | VCCINT | | | | | | | | | | | | | | | |
+| J12 | | | GND | GND | | | | | | | 0.0 | | | | | | | | |
+| J13 | | High Range | IO_L17N_T2_A25_15 | User IO | | 15 | | | | | | | | | | | | | |
+| J14 | | High Range | IO_L19P_T3_A22_15 | User IO | | 15 | | | | | | | | | | | | | |
+| J15 | | High Range | IO_L24N_T3_RS0_15 | User IO | | 15 | | | | | | | | | | | | | |
+| J16 | | | GND | GND | | | | | | | 0.0 | | | | | | | | |
+| J17 | | High Range | IO_L23P_T3_FOE_B_15 | User IO | | 15 | | | | | | | | | | | | | |
+| J18 | | High Range | IO_L23N_T3_FWE_B_15 | User IO | | 15 | | | | | | | | | | | | | |
+| K1 | | High Range | IO_L23N_T3_35 | User IO | | 35 | | | | | | | | | | | | | |
+| K2 | | High Range | IO_L23P_T3_35 | User IO | | 35 | | | | | | | | | | | | | |
+| K3 | | High Range | IO_L2P_T0_34 | User IO | | 34 | | | | | | | | | | | | | |
+| K4 | | High Range | VCCO_34 | VCCO | | 34 | | | | | 3.30 | | | | | | | | |
+| K5 | | High Range | IO_L5P_T0_34 | User IO | | 34 | | | | | | | | | | | | | |
+| K6 | | High Range | IO_0_34 | User IO | | 34 | | | | | | | | | | | | | |
+| K7 | | | GND | GND | | | | | | | 0.0 | | | | | | | | |
+| K8 | | | VCCINT | VCCINT | | | | | | | | | | | | | | | |
+| K9 | | Dedicated | VN_0 | XADC | | 0 | | | | | | | | | | | | | |
+| K10 | | Dedicated | VREFP_0 | XADC | | 0 | | | | | | | | | | | | | |
+| K11 | | | GND | GND | | | | | | | 0.0 | | | | | | | | |
+| K12 | | | VCCAUX | VCCAUX | | | | | | | 1.80 | | | | | | | | |
+| K13 | | High Range | IO_L17P_T2_A26_15 | User IO | | 15 | | | | | | | | | | | | | |
+| K14 | | High Range | VCCO_15 | VCCO | | 15 | | | | | 3.30 | | | | | | | | |
+| K15 | | High Range | IO_L24P_T3_RS1_15 | User IO | | 15 | | | | | | | | | | | | | |
+| K16 | | High Range | IO_25_15 | User IO | | 15 | | | | | | | | | | | | | |
+| K17 | | High Range | IO_L1P_T0_D00_MOSI_14 | User IO | | 14 | | | | | | | | | | | | | |
+| K18 | | High Range | IO_L1N_T0_D01_DIN_14 | User IO | | 14 | | | | | | | | | | | | | |
+| L1 | | High Range | IO_L1P_T0_34 | User IO | | 34 | | | | | | | | | | | | | |
+| L2 | | | GND | GND | | | | | | | 0.0 | | | | | | | | |
+| L3 | | High Range | IO_L2N_T0_34 | User IO | | 34 | | | | | | | | | | | | | |
+| L4 | | High Range | IO_L5N_T0_34 | User IO | | 34 | | | | | | | | | | | | | |
+| L5 | | High Range | IO_L6N_T0_VREF_34 | User IO | | 34 | | | | | | | | | | | | | |
+| L6 | | High Range | IO_L6P_T0_34 | User IO | | 34 | | | | | | | | | | | | | |
+| L7 | | | VCCINT | VCCINT | | | | | | | | | | | | | | | |
+| L8 | | | GND | GND | | | | | | | 0.0 | | | | | | | | |
+| L9 | | Dedicated | DXN_0 | Temp Sensor | | 0 | | | | | | | | | | | | | |
+| L10 | | Dedicated | DXP_0 | Temp Sensor | | 0 | | | | | | | | | | | | | |
+| L11 | | | VCCINT | VCCINT | | | | | | | | | | | | | | | |
+| L12 | | | GND | GND | | | | | | | 0.0 | | | | | | | | |
+| L13 | | High Range | IO_L6P_T0_FCS_B_14 | User IO | | 14 | | | | | | | | | | | | | |
+| L14 | | High Range | IO_L2P_T0_D02_14 | User IO | | 14 | | | | | | | | | | | | | |
+| L15 | | High Range | IO_L3P_T0_DQS_PUDC_B_14 | User IO | | 14 | | | | | | | | | | | | | |
+| L16 | | High Range | IO_L3N_T0_DQS_EMCCLK_14 | User IO | | 14 | | | | | | | | | | | | | |
+| L17 | | High Range | VCCO_14 | VCCO | | 14 | | | | | any** | | | | | | | | |
+| L18 | | High Range | IO_L4P_T0_D04_14 | User IO | | 14 | | | | | | | | | | | | | |
+| M1 | | High Range | IO_L1N_T0_34 | User IO | | 34 | | | | | | | | | | | | | |
+| M2 | | High Range | IO_L4N_T0_34 | User IO | | 34 | | | | | | | | | | | | | |
+| M3 | | High Range | IO_L4P_T0_34 | User IO | | 34 | | | | | | | | | | | | | |
+| M4 | | High Range | IO_L16P_T2_34 | User IO | | 34 | | | | | | | | | | | | | |
+| M5 | | | GND | GND | | | | | | | 0.0 | | | | | | | | |
+| M6 | | High Range | IO_L18P_T2_34 | User IO | | 34 | | | | | | | | | | | | | |
+| M7 | | | GND | GND | | | | | | | 0.0 | | | | | | | | |
+| M8 | | | VCCINT | VCCINT | | | | | | | | | | | | | | | |
+| M9 | | | GND | GND | | | | | | | 0.0 | | | | | | | | |
+| M10 | | | VCCINT | VCCINT | | | | | | | | | | | | | | | |
+| M11 | | | GND | GND | | | | | | | 0.0 | | | | | | | | |
+| M12 | | | VCCAUX | VCCAUX | | | | | | | 1.80 | | | | | | | | |
+| M13 | | High Range | IO_L6N_T0_D08_VREF_14 | User IO | | 14 | | | | | | | | | | | | | |
+| M14 | | High Range | IO_L2N_T0_D03_14 | User IO | | 14 | | | | | | | | | | | | | |
+| M15 | | | GND | GND | | | | | | | 0.0 | | | | | | | | |
+| M16 | | High Range | IO_L10P_T1_D14_14 | User IO | | 14 | | | | | | | | | | | | | |
+| M17 | | High Range | IO_L10N_T1_D15_14 | User IO | | 14 | | | | | | | | | | | | | |
+| M18 | | High Range | IO_L4N_T0_D05_14 | User IO | | 14 | | | | | | | | | | | | | |
+| N1 | | High Range | IO_L3N_T0_DQS_34 | User IO | | 34 | | | | | | | | | | | | | |
+| N2 | | High Range | IO_L3P_T0_DQS_34 | User IO | | 34 | | | | | | | | | | | | | |
+| N3 | | High Range | VCCO_34 | VCCO | | 34 | | | | | 3.30 | | | | | | | | |
+| N4 | | High Range | IO_L16N_T2_34 | User IO | | 34 | | | | | | | | | | | | | |
+| N5 | | High Range | IO_L13P_T2_MRCC_34 | User IO | | 34 | | | | | | | | | | | | | |
+| N6 | | High Range | IO_L18N_T2_34 | User IO | | 34 | | | | | | | | | | | | | |
+| N7 | | | VCCINT | VCCINT | | | | | | | | | | | | | | | |
+| N8 | | | GND | GND | | | | | | | 0.0 | | | | | | | | |
+| N9 | | | VCCINT | VCCINT | | | | | | | | | | | | | | | |
+| N10 | | | GND | GND | | | | | | | 0.0 | | | | | | | | |
+| N11 | | | VCCINT | VCCINT | | | | | | | | | | | | | | | |
+| N12 | | | GND | GND | | | | | | | 0.0 | | | | | | | | |
+| N13 | | High Range | VCCO_14 | VCCO | | 14 | | | | | any** | | | | | | | | |
+| N14 | | High Range | IO_L8P_T1_D11_14 | User IO | | 14 | | | | | | | | | | | | | |
+| N15 | | High Range | IO_L11P_T1_SRCC_14 | User IO | | 14 | | | | | | | | | | | | | |
+| N16 | | High Range | IO_L11N_T1_SRCC_14 | User IO | | 14 | | | | | | | | | | | | | |
+| N17 | | High Range | IO_L9P_T1_DQS_14 | User IO | | 14 | | | | | | | | | | | | | |
+| N18 | | | GND | GND | | | | | | | 0.0 | | | | | | | | |
+| P1 | | | GND | GND | | | | | | | 0.0 | | | | | | | | |
+| P2 | led[15] | High Range | IO_L15P_T2_DQS_34 | OUTPUT | LVCMOS33 | 34 | 12 | SLOW | | FP_VTT_50 | | FIXED | | | | NONE | | | |
+| P3 | | High Range | IO_L14N_T2_SRCC_34 | User IO | | 34 | | | | | | | | | | | | | |
+| P4 | | High Range | IO_L14P_T2_SRCC_34 | User IO | | 34 | | | | | | | | | | | | | |
+| P5 | led[12] | High Range | IO_L13N_T2_MRCC_34 | OUTPUT | LVCMOS33 | 34 | 12 | SLOW | | FP_VTT_50 | | FIXED | | | | NONE | | | |
+| P6 | | High Range | VCCO_34 | VCCO | | 34 | | | | | 3.30 | | | | | | | | |
+| P7 | | Dedicated | INIT_B_0 | Config | | 0 | | | | | | | | | | | | | |
+| P8 | | Dedicated | CFGBVS_0 | Config | | 0 | | | | | | | | | | | | | |
+| P9 | | Dedicated | PROGRAM_B_0 | Config | | 0 | | | | | | | | | | | | | |
+| P10 | | Dedicated | DONE_0 | Config | | 0 | | | | | | | | | | | | | |
+| P11 | | Dedicated | M2_0 | Config | | 0 | | | | | | | | | | | | | |
+| P12 | | Dedicated | M0_0 | Config | | 0 | | | | | | | | | | | | | |
+| P13 | | Dedicated | M1_0 | Config | | 0 | | | | | | | | | | | | | |
+| P14 | | High Range | IO_L8N_T1_D12_14 | User IO | | 14 | | | | | | | | | | | | | |
+| P15 | | High Range | IO_L13P_T2_MRCC_14 | User IO | | 14 | | | | | | | | | | | | | |
+| P16 | | High Range | VCCO_14 | VCCO | | 14 | | | | | any** | | | | | | | | |
+| P17 | | High Range | IO_L12P_T1_MRCC_14 | User IO | | 14 | | | | | | | | | | | | | |
+| P18 | | High Range | IO_L9N_T1_DQS_D13_14 | User IO | | 14 | | | | | | | | | | | | | |
+| R1 | led[11] | High Range | IO_L17P_T2_34 | OUTPUT | LVCMOS33 | 34 | 12 | SLOW | | FP_VTT_50 | | FIXED | | | | NONE | | | |
+| R2 | led[14] | High Range | IO_L15N_T2_DQS_34 | OUTPUT | LVCMOS33 | 34 | 12 | SLOW | | FP_VTT_50 | | FIXED | | | | NONE | | | |
+| R3 | | High Range | IO_L11P_T1_SRCC_34 | User IO | | 34 | | | | | | | | | | | | | |
+| R4 | | | GND | GND | | | | | | | 0.0 | | | | | | | | |
+| R5 | | High Range | IO_L19N_T3_VREF_34 | User IO | | 34 | | | | | | | | | | | | | |
+| R6 | | High Range | IO_L19P_T3_34 | User IO | | 34 | | | | | | | | | | | | | |
+| R7 | | High Range | IO_L23P_T3_34 | User IO | | 34 | | | | | | | | | | | | | |
+| R8 | led[2] | High Range | IO_L24P_T3_34 | OUTPUT | LVCMOS33 | 34 | 12 | SLOW | | FP_VTT_50 | | FIXED | | | | NONE | | | |
+| R9 | | Dedicated | VCCO_0 | VCCO | | 0 | | | | | any** | | | | | | | | |
+| R10 | | High Range | IO_25_14 | User IO | | 14 | | | | | | | | | | | | | |
+| R11 | | High Range | IO_0_14 | User IO | | 14 | | | | | | | | | | | | | |
+| R12 | | High Range | IO_L5P_T0_D06_14 | User IO | | 14 | | | | | | | | | | | | | |
+| R13 | | High Range | IO_L5N_T0_D07_14 | User IO | | 14 | | | | | | | | | | | | | |
+| R14 | | | GND | GND | | | | | | | 0.0 | | | | | | | | |
+| R15 | | High Range | IO_L13N_T2_MRCC_14 | User IO | | 14 | | | | | | | | | | | | | |
+| R16 | | High Range | IO_L15P_T2_DQS_RDWR_B_14 | User IO | | 14 | | | | | | | | | | | | | |
+| R17 | | High Range | IO_L12N_T1_MRCC_14 | User IO | | 14 | | | | | | | | | | | | | |
+| R18 | | High Range | IO_L7P_T1_D09_14 | User IO | | 14 | | | | | | | | | | | | | |
+| T1 | | High Range | IO_L17N_T2_34 | User IO | | 34 | | | | | | | | | | | | | |
+| T2 | | High Range | VCCO_34 | VCCO | | 34 | | | | | 3.30 | | | | | | | | |
+| T3 | | High Range | IO_L11N_T1_SRCC_34 | User IO | | 34 | | | | | | | | | | | | | |
+| T4 | led[5] | High Range | IO_L12N_T1_MRCC_34 | OUTPUT | LVCMOS33 | 34 | 12 | SLOW | | FP_VTT_50 | | FIXED | | | | NONE | | | |
+| T5 | led[4] | High Range | IO_L12P_T1_MRCC_34 | OUTPUT | LVCMOS33 | 34 | 12 | SLOW | | FP_VTT_50 | | FIXED | | | | NONE | | | |
+| T6 | led[3] | High Range | IO_L23N_T3_34 | OUTPUT | LVCMOS33 | 34 | 12 | SLOW | | FP_VTT_50 | | FIXED | | | | NONE | | | |
+| T7 | | | GND | GND | | | | | | | 0.0 | | | | | | | | |
+| T8 | led[0] | High Range | IO_L24N_T3_34 | OUTPUT | LVCMOS33 | 34 | 12 | SLOW | | FP_VTT_50 | | FIXED | | | | NONE | | | |
+| T9 | | High Range | IO_L24P_T3_A01_D17_14 | User IO | | 14 | | | | | | | | | | | | | |
+| T10 | | High Range | IO_L24N_T3_A00_D16_14 | User IO | | 14 | | | | | | | | | | | | | |
+| T11 | | High Range | IO_L19P_T3_A10_D26_14 | User IO | | 14 | | | | | | | | | | | | | |
+| T12 | | High Range | VCCO_14 | VCCO | | 14 | | | | | any** | | | | | | | | |
+| T13 | | High Range | IO_L23P_T3_A03_D19_14 | User IO | | 14 | | | | | | | | | | | | | |
+| T14 | | High Range | IO_L14P_T2_SRCC_14 | User IO | | 14 | | | | | | | | | | | | | |
+| T15 | | High Range | IO_L14N_T2_SRCC_14 | User IO | | 14 | | | | | | | | | | | | | |
+| T16 | | High Range | IO_L15N_T2_DQS_DOUT_CSO_B_14 | User IO | | 14 | | | | | | | | | | | | | |
+| T17 | | | GND | GND | | | | | | | 0.0 | | | | | | | | |
+| T18 | | High Range | IO_L7N_T1_D10_14 | User IO | | 14 | | | | | | | | | | | | | |
+| U1 | led[13] | High Range | IO_L7P_T1_34 | OUTPUT | LVCMOS33 | 34 | 12 | SLOW | | FP_VTT_50 | | FIXED | | | | NONE | | | |
+| U2 | | High Range | IO_L9P_T1_DQS_34 | User IO | | 34 | | | | | | | | | | | | | |
+| U3 | led[9] | High Range | IO_L8N_T1_34 | OUTPUT | LVCMOS33 | 34 | 12 | SLOW | | FP_VTT_50 | | FIXED | | | | NONE | | | |
+| U4 | | High Range | IO_L8P_T1_34 | User IO | | 34 | | | | | | | | | | | | | |
+| U5 | | High Range | VCCO_34 | VCCO | | 34 | | | | | 3.30 | | | | | | | | |
+| U6 | led[7] | High Range | IO_L22N_T3_34 | OUTPUT | LVCMOS33 | 34 | 12 | SLOW | | FP_VTT_50 | | FIXED | | | | NONE | | | |
+| U7 | led[6] | High Range | IO_L22P_T3_34 | OUTPUT | LVCMOS33 | 34 | 12 | SLOW | | FP_VTT_50 | | FIXED | | | | NONE | | | |
+| U8 | | High Range | IO_25_34 | User IO | | 34 | | | | | | | | | | | | | |
+| U9 | | High Range | IO_L21P_T3_DQS_34 | User IO | | 34 | | | | | | | | | | | | | |
+| U10 | | | GND | GND | | | | | | | 0.0 | | | | | | | | |
+| U11 | | High Range | IO_L19N_T3_A09_D25_VREF_14 | User IO | | 14 | | | | | | | | | | | | | |
+| U12 | | High Range | IO_L20P_T3_A08_D24_14 | User IO | | 14 | | | | | | | | | | | | | |
+| U13 | | High Range | IO_L23N_T3_A02_D18_14 | User IO | | 14 | | | | | | | | | | | | | |
+| U14 | | High Range | IO_L22P_T3_A05_D21_14 | User IO | | 14 | | | | | | | | | | | | | |
+| U15 | | High Range | VCCO_14 | VCCO | | 14 | | | | | any** | | | | | | | | |
+| U16 | | High Range | IO_L18P_T2_A12_D28_14 | User IO | | 14 | | | | | | | | | | | | | |
+| U17 | | High Range | IO_L17P_T2_A14_D30_14 | User IO | | 14 | | | | | | | | | | | | | |
+| U18 | | High Range | IO_L17N_T2_A13_D29_14 | User IO | | 14 | | | | | | | | | | | | | |
+| V1 | led[10] | High Range | IO_L7N_T1_34 | OUTPUT | LVCMOS33 | 34 | 12 | SLOW | | FP_VTT_50 | | FIXED | | | | NONE | | | |
+| V2 | | High Range | IO_L9N_T1_DQS_34 | User IO | | 34 | | | | | | | | | | | | | |
+| V3 | | | GND | GND | | | | | | | 0.0 | | | | | | | | |
+| V4 | led[8] | High Range | IO_L10N_T1_34 | OUTPUT | LVCMOS33 | 34 | 12 | SLOW | | FP_VTT_50 | | FIXED | | | | NONE | | | |
+| V5 | | High Range | IO_L10P_T1_34 | User IO | | 34 | | | | | | | | | | | | | |
+| V6 | | High Range | IO_L20N_T3_34 | User IO | | 34 | | | | | | | | | | | | | |
+| V7 | | High Range | IO_L20P_T3_34 | User IO | | 34 | | | | | | | | | | | | | |
+| V8 | | High Range | VCCO_34 | VCCO | | 34 | | | | | 3.30 | | | | | | | | |
+| V9 | led[1] | High Range | IO_L21N_T3_DQS_34 | OUTPUT | LVCMOS33 | 34 | 12 | SLOW | | FP_VTT_50 | | FIXED | | | | NONE | | | |
+| V10 | | High Range | IO_L21P_T3_DQS_14 | User IO | | 14 | | | | | | | | | | | | | |
+| V11 | | High Range | IO_L21N_T3_DQS_A06_D22_14 | User IO | | 14 | | | | | | | | | | | | | |
+| V12 | | High Range | IO_L20N_T3_A07_D23_14 | User IO | | 14 | | | | | | | | | | | | | |
+| V13 | | | GND | GND | | | | | | | 0.0 | | | | | | | | |
+| V14 | | High Range | IO_L22N_T3_A04_D20_14 | User IO | | 14 | | | | | | | | | | | | | |
+| V15 | | High Range | IO_L16P_T2_CSI_B_14 | User IO | | 14 | | | | | | | | | | | | | |
+| V16 | | High Range | IO_L16N_T2_A15_D31_14 | User IO | | 14 | | | | | | | | | | | | | |
+| V17 | | High Range | IO_L18N_T2_A11_D27_14 | User IO | | 14 | | | | | | | | | | | | | |
+| V18 | | High Range | VCCO_14 | VCCO | | 14 | | | | | any** | | | | | | | | |
++------------+-------------+------------+------------------------------+-------------+-------------+---------+------------+------+---------------------+----------------------+---------+------------+-----------+----------+------+------------------+--------------+-------------------+--------------+
+* Default value
+** Special VCCO requirements may apply. Please consult the device family datasheet for specific guideline on VCCO requirements.
+
+
diff --git a/game.runs/impl_1/TopModule_methodology_drc_routed.pb b/game.runs/impl_1/TopModule_methodology_drc_routed.pb
new file mode 100644
index 0000000000000000000000000000000000000000..0c8006f28fb883387ccfdd0a1ebe08ac95e2ccda
Binary files /dev/null and b/game.runs/impl_1/TopModule_methodology_drc_routed.pb differ
diff --git a/game.runs/impl_1/TopModule_methodology_drc_routed.rpt b/game.runs/impl_1/TopModule_methodology_drc_routed.rpt
new file mode 100644
index 0000000000000000000000000000000000000000..0e4eccc46776c24905db1d1e2f550424a9658926
--- /dev/null
+++ b/game.runs/impl_1/TopModule_methodology_drc_routed.rpt
@@ -0,0 +1,56 @@
+Copyright 1986-2022 Xilinx, Inc. All Rights Reserved.
+-----------------------------------------------------------------------------------------------------------------------------------------------------------------
+| Tool Version : Vivado v.2022.2 (lin64) Build 3671981 Fri Oct 14 04:59:54 MDT 2022
+| Date : Tue Feb 28 17:02:41 2023
+| Host : LikeUE06 running 64-bit Linux Mint 20.3
+| Command : report_methodology -file TopModule_methodology_drc_routed.rpt -pb TopModule_methodology_drc_routed.pb -rpx TopModule_methodology_drc_routed.rpx
+| Design : TopModule
+| Device : xc7a100tcsg324-1
+| Speed File : -1
+| Design State : Fully Routed
+-----------------------------------------------------------------------------------------------------------------------------------------------------------------
+
+Report Methodology
+
+Table of Contents
+-----------------
+1. REPORT SUMMARY
+2. REPORT DETAILS
+
+1. REPORT SUMMARY
+-----------------
+ Netlist: netlist
+ Floorplan: design_1
+ Design limits: <entire design considered>
+ Max violations: <unlimited>
+ Violations found: 4
++-----------+------------------+------------------------------------------------------------------+------------+
+| Rule | Severity | Description | Violations |
++-----------+------------------+------------------------------------------------------------------+------------+
+| TIMING-6 | Critical Warning | No common primary clock between related clocks | 2 |
+| TIMING-56 | Warning | Missing logically or physically excluded clock groups constraint | 2 |
++-----------+------------------+------------------------------------------------------------------+------------+
+
+2. REPORT DETAILS
+-----------------
+TIMING-6#1 Critical Warning
+No common primary clock between related clocks
+The clocks clk_out1_clk_wiz_0 and clk_out1_clk_wiz_0_1 are related (timed together) but they have no common primary clock. The design could fail in hardware. To find a timing path between these clocks, run the following command: report_timing -from [get_clocks clk_out1_clk_wiz_0] -to [get_clocks clk_out1_clk_wiz_0_1]
+Related violations: <none>
+
+TIMING-6#2 Critical Warning
+No common primary clock between related clocks
+The clocks clk_out1_clk_wiz_0_1 and clk_out1_clk_wiz_0 are related (timed together) but they have no common primary clock. The design could fail in hardware. To find a timing path between these clocks, run the following command: report_timing -from [get_clocks clk_out1_clk_wiz_0_1] -to [get_clocks clk_out1_clk_wiz_0]
+Related violations: <none>
+
+TIMING-56#1 Warning
+Missing logically or physically excluded clock groups constraint
+Multiple clocks are user generated or auto-derived on the source pin pixelClk/inst/mmcm_adv_inst/CLKFBOUT but are not logically or physically exclusive with respect to one another. To have the static timing analysis match the behavior in hardware, there cannot be multiple clocks generated on the same pin and when such situation occurs, the clocks should be defined as physically or logically exclusive. The list of clocks generated on the source pin is: clkfbout_clk_wiz_0, clkfbout_clk_wiz_0_1
+Related violations: <none>
+
+TIMING-56#2 Warning
+Missing logically or physically excluded clock groups constraint
+Multiple clocks are user generated or auto-derived on the source pin pixelClk/inst/mmcm_adv_inst/CLKOUT0 but are not logically or physically exclusive with respect to one another. To have the static timing analysis match the behavior in hardware, there cannot be multiple clocks generated on the same pin and when such situation occurs, the clocks should be defined as physically or logically exclusive. The list of clocks generated on the source pin is: clk_out1_clk_wiz_0, clk_out1_clk_wiz_0_1
+Related violations: <none>
+
+
diff --git a/game.runs/impl_1/TopModule_methodology_drc_routed.rpx b/game.runs/impl_1/TopModule_methodology_drc_routed.rpx
new file mode 100644
index 0000000000000000000000000000000000000000..ff8de844084902a336445fedc9c8087be1d579e5
Binary files /dev/null and b/game.runs/impl_1/TopModule_methodology_drc_routed.rpx differ
diff --git a/game.runs/impl_1/TopModule_opt.dcp b/game.runs/impl_1/TopModule_opt.dcp
new file mode 100644
index 0000000000000000000000000000000000000000..119c4e057386d12875fa39ad726b6712143fc581
Binary files /dev/null and b/game.runs/impl_1/TopModule_opt.dcp differ
diff --git a/game.runs/impl_1/TopModule_physopt.dcp b/game.runs/impl_1/TopModule_physopt.dcp
new file mode 100644
index 0000000000000000000000000000000000000000..655270c6d9202a7a2f1053f709b6d3c16fd297c9
Binary files /dev/null and b/game.runs/impl_1/TopModule_physopt.dcp differ
diff --git a/game.runs/impl_1/TopModule_placed.dcp b/game.runs/impl_1/TopModule_placed.dcp
new file mode 100644
index 0000000000000000000000000000000000000000..0f5ab92386de212d2c7152f5f8b965832e953d4e
Binary files /dev/null and b/game.runs/impl_1/TopModule_placed.dcp differ
diff --git a/game.runs/impl_1/TopModule_power_routed.rpt b/game.runs/impl_1/TopModule_power_routed.rpt
new file mode 100644
index 0000000000000000000000000000000000000000..9667b00463fada0340046b76ef924fb651166dd4
--- /dev/null
+++ b/game.runs/impl_1/TopModule_power_routed.rpt
@@ -0,0 +1,154 @@
+Copyright 1986-2022 Xilinx, Inc. All Rights Reserved.
+-------------------------------------------------------------------------------------------------------------------------------------------------
+| Tool Version : Vivado v.2022.2 (lin64) Build 3671981 Fri Oct 14 04:59:54 MDT 2022
+| Date : Tue Feb 28 17:02:42 2023
+| Host : LikeUE06 running 64-bit Linux Mint 20.3
+| Command : report_power -file TopModule_power_routed.rpt -pb TopModule_power_summary_routed.pb -rpx TopModule_power_routed.rpx
+| Design : TopModule
+| Device : xc7a100tcsg324-1
+| Design State : routed
+| Grade : commercial
+| Process : typical
+| Characterization : Production
+-------------------------------------------------------------------------------------------------------------------------------------------------
+
+Power Report
+
+Table of Contents
+-----------------
+1. Summary
+1.1 On-Chip Components
+1.2 Power Supply Summary
+1.3 Confidence Level
+2. Settings
+2.1 Environment
+2.2 Clock Constraints
+3. Detailed Reports
+3.1 By Hierarchy
+
+1. Summary
+----------
+
++--------------------------+--------------+
+| Total On-Chip Power (W) | 0.215 |
+| Design Power Budget (W) | Unspecified* |
+| Power Budget Margin (W) | NA |
+| Dynamic (W) | 0.117 |
+| Device Static (W) | 0.097 |
+| Effective TJA (C/W) | 4.6 |
+| Max Ambient (C) | 84.0 |
+| Junction Temperature (C) | 26.0 |
+| Confidence Level | Medium |
+| Setting File | --- |
+| Simulation Activity File | --- |
+| Design Nets Matched | NA |
++--------------------------+--------------+
+* Specify Design Power Budget using, set_operating_conditions -design_power_budget <value in Watts>
+
+
+1.1 On-Chip Components
+----------------------
+
++----------------+-----------+----------+-----------+-----------------+
+| On-Chip | Power (W) | Used | Available | Utilization (%) |
++----------------+-----------+----------+-----------+-----------------+
+| Clocks | <0.001 | 8 | --- | --- |
+| Slice Logic | <0.001 | 616 | --- | --- |
+| LUT as Logic | <0.001 | 325 | 63400 | 0.51 |
+| CARRY4 | <0.001 | 56 | 15850 | 0.35 |
+| Register | <0.001 | 127 | 126800 | 0.10 |
+| Others | 0.000 | 10 | --- | --- |
+| Signals | <0.001 | 381 | --- | --- |
+| MMCM | 0.116 | 1 | 6 | 16.67 |
+| I/O | <0.001 | 33 | 210 | 15.71 |
+| Static Power | 0.097 | | | |
+| Total | 0.215 | | | |
++----------------+-----------+----------+-----------+-----------------+
+
+
+1.2 Power Supply Summary
+------------------------
+
++-----------+-------------+-----------+-------------+------------+-------------+-------------+------------+
+| Source | Voltage (V) | Total (A) | Dynamic (A) | Static (A) | Powerup (A) | Budget (A) | Margin (A) |
++-----------+-------------+-----------+-------------+------------+-------------+-------------+------------+
+| Vccint | 1.000 | 0.016 | 0.001 | 0.015 | NA | Unspecified | NA |
+| Vccaux | 1.800 | 0.082 | 0.064 | 0.018 | NA | Unspecified | NA |
+| Vcco33 | 3.300 | 0.004 | 0.000 | 0.004 | NA | Unspecified | NA |
+| Vcco25 | 2.500 | 0.000 | 0.000 | 0.000 | NA | Unspecified | NA |
+| Vcco18 | 1.800 | 0.000 | 0.000 | 0.000 | NA | Unspecified | NA |
+| Vcco15 | 1.500 | 0.000 | 0.000 | 0.000 | NA | Unspecified | NA |
+| Vcco135 | 1.350 | 0.000 | 0.000 | 0.000 | NA | Unspecified | NA |
+| Vcco12 | 1.200 | 0.000 | 0.000 | 0.000 | NA | Unspecified | NA |
+| Vccaux_io | 1.800 | 0.000 | 0.000 | 0.000 | NA | Unspecified | NA |
+| Vccbram | 1.000 | 0.000 | 0.000 | 0.000 | NA | Unspecified | NA |
+| MGTAVcc | 1.000 | 0.000 | 0.000 | 0.000 | NA | Unspecified | NA |
+| MGTAVtt | 1.200 | 0.000 | 0.000 | 0.000 | NA | Unspecified | NA |
+| Vccadc | 1.800 | 0.020 | 0.000 | 0.020 | NA | Unspecified | NA |
++-----------+-------------+-----------+-------------+------------+-------------+-------------+------------+
+
+
+1.3 Confidence Level
+--------------------
+
++-----------------------------+------------+-------------------------------------------------------+------------------------------------------------------------------------------------------------------------+
+| User Input Data | Confidence | Details | Action |
++-----------------------------+------------+-------------------------------------------------------+------------------------------------------------------------------------------------------------------------+
+| Design implementation state | High | Design is routed | |
+| Clock nodes activity | High | User specified more than 95% of clocks | |
+| I/O nodes activity | Medium | More than 5% of inputs are missing user specification | Provide missing input activity with simulation results or by editing the "By Resource Type -> I/Os" view |
+| Internal nodes activity | Medium | User specified less than 25% of internal nodes | Provide missing internal nodes activity with simulation results or by editing the "By Resource Type" views |
+| Device models | High | Device models are Production | |
+| | | | |
+| Overall confidence level | Medium | | |
++-----------------------------+------------+-------------------------------------------------------+------------------------------------------------------------------------------------------------------------+
+
+
+2. Settings
+-----------
+
+2.1 Environment
+---------------
+
++-----------------------+--------------------------+
+| Ambient Temp (C) | 25.0 |
+| ThetaJA (C/W) | 4.6 |
+| Airflow (LFM) | 250 |
+| Heat Sink | medium (Medium Profile) |
+| ThetaSA (C/W) | 4.6 |
+| Board Selection | medium (10"x10") |
+| # of Board Layers | 12to15 (12 to 15 Layers) |
+| Board Temperature (C) | 25.0 |
++-----------------------+--------------------------+
+
+
+2.2 Clock Constraints
+---------------------
+
++----------------------+----------------------------------+-----------------+
+| Clock | Domain | Constraint (ns) |
++----------------------+----------------------------------+-----------------+
+| clk | clk | 10.0 |
+| clk_out1_clk_wiz_0 | pixelClk/inst/clk_out1_clk_wiz_0 | 40.0 |
+| clk_out1_clk_wiz_0_1 | pixelClk/inst/clk_out1_clk_wiz_0 | 40.0 |
+| clkfbout_clk_wiz_0 | pixelClk/inst/clkfbout_clk_wiz_0 | 10.0 |
+| clkfbout_clk_wiz_0_1 | pixelClk/inst/clkfbout_clk_wiz_0 | 10.0 |
+| sys_clk_pin | clk | 10.0 |
++----------------------+----------------------------------+-----------------+
+
+
+3. Detailed Reports
+-------------------
+
+3.1 By Hierarchy
+----------------
+
++------------+-----------+
+| Name | Power (W) |
++------------+-----------+
+| TopModule | 0.117 |
+| pixelClk | 0.116 |
+| inst | 0.116 |
++------------+-----------+
+
+
diff --git a/game.runs/impl_1/TopModule_power_routed.rpx b/game.runs/impl_1/TopModule_power_routed.rpx
new file mode 100644
index 0000000000000000000000000000000000000000..94aba08621aceb22e66d320b6dc29befe938255a
Binary files /dev/null and b/game.runs/impl_1/TopModule_power_routed.rpx differ
diff --git a/game.runs/impl_1/TopModule_power_summary_routed.pb b/game.runs/impl_1/TopModule_power_summary_routed.pb
new file mode 100644
index 0000000000000000000000000000000000000000..9a0611f65f99f4fe173ece59b7a205caaa296bfb
Binary files /dev/null and b/game.runs/impl_1/TopModule_power_summary_routed.pb differ
diff --git a/game.runs/impl_1/TopModule_route_status.pb b/game.runs/impl_1/TopModule_route_status.pb
new file mode 100644
index 0000000000000000000000000000000000000000..c2fbede3a9328c2bbd087a968836fc50761b5337
Binary files /dev/null and b/game.runs/impl_1/TopModule_route_status.pb differ
diff --git a/game.runs/impl_1/TopModule_route_status.rpt b/game.runs/impl_1/TopModule_route_status.rpt
new file mode 100644
index 0000000000000000000000000000000000000000..72790303ff958311254586c937d639c5dd99eee5
--- /dev/null
+++ b/game.runs/impl_1/TopModule_route_status.rpt
@@ -0,0 +1,11 @@
+Design Route Status
+ : # nets :
+ ------------------------------------------- : ----------- :
+ # of logical nets.......................... : 737 :
+ # of nets not needing routing.......... : 349 :
+ # of internally routed nets........ : 349 :
+ # of routable nets..................... : 388 :
+ # of fully routed nets............. : 388 :
+ # of nets with routing errors.......... : 0 :
+ ------------------------------------------- : ----------- :
+
diff --git a/game.runs/impl_1/TopModule_routed.dcp b/game.runs/impl_1/TopModule_routed.dcp
new file mode 100644
index 0000000000000000000000000000000000000000..b50fc9994d57b340822d433b9794eb5cba3763ed
Binary files /dev/null and b/game.runs/impl_1/TopModule_routed.dcp differ
diff --git a/game.runs/impl_1/TopModule_timing_summary_routed.pb b/game.runs/impl_1/TopModule_timing_summary_routed.pb
new file mode 100644
index 0000000000000000000000000000000000000000..a850bdbc240adb6ac06bf7f87dfdca71928dee2d
Binary files /dev/null and b/game.runs/impl_1/TopModule_timing_summary_routed.pb differ
diff --git a/game.runs/impl_1/TopModule_timing_summary_routed.rpt b/game.runs/impl_1/TopModule_timing_summary_routed.rpt
new file mode 100644
index 0000000000000000000000000000000000000000..a09212b277b87dfd07cf786b1d2e1dc4ba4f793f
--- /dev/null
+++ b/game.runs/impl_1/TopModule_timing_summary_routed.rpt
@@ -0,0 +1,10517 @@
+Copyright 1986-2022 Xilinx, Inc. All Rights Reserved.
+------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
+| Tool Version : Vivado v.2022.2 (lin64) Build 3671981 Fri Oct 14 04:59:54 MDT 2022
+| Date : Tue Feb 28 17:02:42 2023
+| Host : LikeUE06 running 64-bit Linux Mint 20.3
+| Command : report_timing_summary -max_paths 10 -report_unconstrained -file TopModule_timing_summary_routed.rpt -pb TopModule_timing_summary_routed.pb -rpx TopModule_timing_summary_routed.rpx -warn_on_violation
+| Design : TopModule
+| Device : 7a100t-csg324
+| Speed File : -1 PRODUCTION 1.23 2018-06-13
+------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
+
+Timing Summary Report
+
+------------------------------------------------------------------------------------------------
+| Timer Settings
+| --------------
+------------------------------------------------------------------------------------------------
+
+ Enable Multi Corner Analysis : Yes
+ Enable Pessimism Removal : Yes
+ Pessimism Removal Resolution : Nearest Common Node
+ Enable Input Delay Default Clock : No
+ Enable Preset / Clear Arcs : No
+ Disable Flight Delays : No
+ Ignore I/O Paths : No
+ Timing Early Launch at Borrowing Latches : No
+ Borrow Time for Max Delay Exceptions : Yes
+ Merge Timing Exceptions : Yes
+
+ Corner Analyze Analyze
+ Name Max Paths Min Paths
+ ------ --------- ---------
+ Slow Yes Yes
+ Fast Yes Yes
+
+
+------------------------------------------------------------------------------------------------
+| Report Methodology
+| ------------------
+------------------------------------------------------------------------------------------------
+
+Rule Severity Description Violations
+--------- ---------------- ---------------------------------------------------------------- ----------
+TIMING-6 Critical Warning No common primary clock between related clocks 2
+TIMING-56 Warning Missing logically or physically excluded clock groups constraint 2
+
+Note: This report is based on the most recent report_methodology run and may not be up-to-date. Run report_methodology on the current design for the latest report.
+
+
+
+check_timing report
+
+Table of Contents
+-----------------
+1. checking no_clock (0)
+2. checking constant_clock (0)
+3. checking pulse_width_clock (0)
+4. checking unconstrained_internal_endpoints (0)
+5. checking no_input_delay (2)
+6. checking no_output_delay (30)
+7. checking multiple_clock (127)
+8. checking generated_clocks (0)
+9. checking loops (0)
+10. checking partial_input_delay (0)
+11. checking partial_output_delay (0)
+12. checking latch_loops (0)
+
+1. checking no_clock (0)
+------------------------
+ There are 0 register/latch pins with no clock.
+
+
+2. checking constant_clock (0)
+------------------------------
+ There are 0 register/latch pins with constant_clock.
+
+
+3. checking pulse_width_clock (0)
+---------------------------------
+ There are 0 register/latch pins which need pulse_width check
+
+
+4. checking unconstrained_internal_endpoints (0)
+------------------------------------------------
+ There are 0 pins that are not constrained for maximum delay.
+
+ There are 0 pins that are not constrained for maximum delay due to constant clock.
+
+
+5. checking no_input_delay (2)
+------------------------------
+ There are 2 input ports with no input delay specified. (HIGH)
+
+ There are 0 input ports with no input delay but user has a false path constraint.
+
+
+6. checking no_output_delay (30)
+--------------------------------
+ There are 30 ports with no output delay specified. (HIGH)
+
+ There are 0 ports with no output delay but user has a false path constraint
+
+ There are 0 ports with no output delay but with a timing clock defined on it or propagating through it
+
+
+7. checking multiple_clock (127)
+--------------------------------
+ There are 127 register/latch pins with multiple clocks. (HIGH)
+
+
+8. checking generated_clocks (0)
+--------------------------------
+ There are 0 generated clocks that are not connected to a clock source.
+
+
+9. checking loops (0)
+---------------------
+ There are 0 combinational loops in the design.
+
+
+10. checking partial_input_delay (0)
+------------------------------------
+ There are 0 input ports with partial input delay specified.
+
+
+11. checking partial_output_delay (0)
+-------------------------------------
+ There are 0 ports with partial output delay specified.
+
+
+12. checking latch_loops (0)
+----------------------------
+ There are 0 combinational latch loops in the design through latch input
+
+
+
+------------------------------------------------------------------------------------------------
+| Design Timing Summary
+| ---------------------
+------------------------------------------------------------------------------------------------
+
+ WNS(ns) TNS(ns) TNS Failing Endpoints TNS Total Endpoints WHS(ns) THS(ns) THS Failing Endpoints THS Total Endpoints WPWS(ns) TPWS(ns) TPWS Failing Endpoints TPWS Total Endpoints
+ ------- ------- --------------------- ------------------- ------- ------- --------------------- ------------------- -------- -------- ---------------------- --------------------
+ 24.909 0.000 0 248 0.063 0.000 0 248 3.000 0.000 0 133
+
+
+All user specified timing constraints are met.
+
+
+------------------------------------------------------------------------------------------------
+| Clock Summary
+| -------------
+------------------------------------------------------------------------------------------------
+
+Clock Waveform(ns) Period(ns) Frequency(MHz)
+----- ------------ ---------- --------------
+clk {0.000 5.000} 10.000 100.000
+ clk_out1_clk_wiz_0 {0.000 20.000} 40.000 25.000
+ clkfbout_clk_wiz_0 {0.000 5.000} 10.000 100.000
+sys_clk_pin {0.000 5.000} 10.000 100.000
+ clk_out1_clk_wiz_0_1 {0.000 20.000} 40.000 25.000
+ clkfbout_clk_wiz_0_1 {0.000 5.000} 10.000 100.000
+
+
+------------------------------------------------------------------------------------------------
+| Intra Clock Table
+| -----------------
+------------------------------------------------------------------------------------------------
+
+Clock WNS(ns) TNS(ns) TNS Failing Endpoints TNS Total Endpoints WHS(ns) THS(ns) THS Failing Endpoints THS Total Endpoints WPWS(ns) TPWS(ns) TPWS Failing Endpoints TPWS Total Endpoints
+----- ------- ------- --------------------- ------------------- ------- ------- --------------------- ------------------- -------- -------- ---------------------- --------------------
+clk 3.000 0.000 0 1
+ clk_out1_clk_wiz_0 24.909 0.000 0 248 0.161 0.000 0 248 19.500 0.000 0 129
+ clkfbout_clk_wiz_0 7.845 0.000 0 3
+sys_clk_pin 3.000 0.000 0 1
+ clk_out1_clk_wiz_0_1 24.912 0.000 0 248 0.161 0.000 0 248 19.500 0.000 0 129
+ clkfbout_clk_wiz_0_1 7.845 0.000 0 3
+
+
+------------------------------------------------------------------------------------------------
+| Inter Clock Table
+| -----------------
+------------------------------------------------------------------------------------------------
+
+From Clock To Clock WNS(ns) TNS(ns) TNS Failing Endpoints TNS Total Endpoints WHS(ns) THS(ns) THS Failing Endpoints THS Total Endpoints
+---------- -------- ------- ------- --------------------- ------------------- ------- ------- --------------------- -------------------
+clk_out1_clk_wiz_0_1 clk_out1_clk_wiz_0 24.909 0.000 0 248 0.063 0.000 0 248
+clk_out1_clk_wiz_0 clk_out1_clk_wiz_0_1 24.909 0.000 0 248 0.063 0.000 0 248
+
+
+------------------------------------------------------------------------------------------------
+| Other Path Groups Table
+| -----------------------
+------------------------------------------------------------------------------------------------
+
+Path Group From Clock To Clock WNS(ns) TNS(ns) TNS Failing Endpoints TNS Total Endpoints WHS(ns) THS(ns) THS Failing Endpoints THS Total Endpoints
+---------- ---------- -------- ------- ------- --------------------- ------------------- ------- ------- --------------------- -------------------
+
+
+------------------------------------------------------------------------------------------------
+| User Ignored Path Table
+| -----------------------
+------------------------------------------------------------------------------------------------
+
+Path Group From Clock To Clock
+---------- ---------- --------
+
+
+------------------------------------------------------------------------------------------------
+| Unconstrained Path Table
+| ------------------------
+------------------------------------------------------------------------------------------------
+
+Path Group From Clock To Clock
+---------- ---------- --------
+(none) clk_out1_clk_wiz_0
+(none) clk_out1_clk_wiz_0_1
+(none) clkfbout_clk_wiz_0
+(none) clkfbout_clk_wiz_0_1
+(none) clk_out1_clk_wiz_0
+(none) clk_out1_clk_wiz_0_1
+
+
+------------------------------------------------------------------------------------------------
+| Timing Details
+| --------------
+------------------------------------------------------------------------------------------------
+
+
+---------------------------------------------------------------------------------------------------
+From Clock: clk
+ To Clock: clk
+
+Setup : NA Failing Endpoints, Worst Slack NA , Total Violation NA
+Hold : NA Failing Endpoints, Worst Slack NA , Total Violation NA
+PW : 0 Failing Endpoints, Worst Slack 3.000ns, Total Violation 0.000ns
+---------------------------------------------------------------------------------------------------
+
+
+Pulse Width Checks
+--------------------------------------------------------------------------------------
+Clock Name: clk
+Waveform(ns): { 0.000 5.000 }
+Period(ns): 10.000
+Sources: { clk }
+
+Check Type Corner Lib Pin Reference Pin Required(ns) Actual(ns) Slack(ns) Location Pin
+Min Period n/a MMCME2_ADV/CLKIN1 n/a 1.249 10.000 8.751 MMCME2_ADV_X1Y2 pixelClk/inst/mmcm_adv_inst/CLKIN1
+Max Period n/a MMCME2_ADV/CLKIN1 n/a 100.000 10.000 90.000 MMCME2_ADV_X1Y2 pixelClk/inst/mmcm_adv_inst/CLKIN1
+Low Pulse Width Slow MMCME2_ADV/CLKIN1 n/a 2.000 5.000 3.000 MMCME2_ADV_X1Y2 pixelClk/inst/mmcm_adv_inst/CLKIN1
+Low Pulse Width Fast MMCME2_ADV/CLKIN1 n/a 2.000 5.000 3.000 MMCME2_ADV_X1Y2 pixelClk/inst/mmcm_adv_inst/CLKIN1
+High Pulse Width Slow MMCME2_ADV/CLKIN1 n/a 2.000 5.000 3.000 MMCME2_ADV_X1Y2 pixelClk/inst/mmcm_adv_inst/CLKIN1
+High Pulse Width Fast MMCME2_ADV/CLKIN1 n/a 2.000 5.000 3.000 MMCME2_ADV_X1Y2 pixelClk/inst/mmcm_adv_inst/CLKIN1
+
+
+
+---------------------------------------------------------------------------------------------------
+From Clock: clk_out1_clk_wiz_0
+ To Clock: clk_out1_clk_wiz_0
+
+Setup : 0 Failing Endpoints, Worst Slack 24.909ns, Total Violation 0.000ns
+Hold : 0 Failing Endpoints, Worst Slack 0.161ns, Total Violation 0.000ns
+PW : 0 Failing Endpoints, Worst Slack 19.500ns, Total Violation 0.000ns
+---------------------------------------------------------------------------------------------------
+
+
+Max Delay Paths
+--------------------------------------------------------------------------------------
+Slack (MET) : 24.909ns (required time - arrival time)
+ Source: vgaInterface/counter_f_reg[2]/C
+ (rising edge-triggered cell FDCE clocked by clk_out1_clk_wiz_0 {rise@0.000ns fall@20.000ns period=40.000ns})
+ Destination: runnerObject/pos_object_y_target_reg[8]/D
+ (rising edge-triggered cell FDSE clocked by clk_out1_clk_wiz_0 {rise@0.000ns fall@20.000ns period=40.000ns})
+ Path Group: clk_out1_clk_wiz_0
+ Path Type: Setup (Max at Slow Process Corner)
+ Requirement: 40.000ns (clk_out1_clk_wiz_0 rise@40.000ns - clk_out1_clk_wiz_0 rise@0.000ns)
+ Data Path Delay: 15.033ns (logic 5.901ns (39.253%) route 9.132ns (60.747%))
+ Logic Levels: 18 (CARRY4=9 LUT1=2 LUT2=2 LUT4=2 LUT5=1 LUT6=2)
+ Clock Path Skew: -0.039ns (DCD - SCD + CPR)
+ Destination Clock Delay (DCD): -1.419ns = ( 38.581 - 40.000 )
+ Source Clock Delay (SCD): -0.821ns
+ Clock Pessimism Removal (CPR): 0.559ns
+ Clock Uncertainty: 0.098ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE
+ Total System Jitter (TSJ): 0.071ns
+ Discrete Jitter (DJ): 0.182ns
+ Phase Error (PE): 0.000ns
+
+ Location Delay type Incr(ns) Path(ns) Netlist Resource(s)
+ ------------------------------------------------------------------- -------------------
+ (clock clk_out1_clk_wiz_0 rise edge)
+ 0.000 0.000 r
+ E3 0.000 0.000 r clk (IN)
+ net (fo=0) 0.000 0.000 pixelClk/inst/clk_in1
+ E3 IBUF (Prop_ibuf_I_O) 1.482 1.482 r pixelClk/inst/clkin1_ibufg/O
+ net (fo=1, routed) 1.233 2.715 pixelClk/inst/clk_in1_clk_wiz_0
+ MMCME2_ADV_X1Y2 MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKOUT0)
+ -7.070 -4.355 r pixelClk/inst/mmcm_adv_inst/CLKOUT0
+ net (fo=1, routed) 1.719 -2.636 pixelClk/inst/clk_out1_clk_wiz_0
+ BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.096 -2.540 r pixelClk/inst/clkout1_buf/O
+ net (fo=127, routed) 1.719 -0.821 vgaInterface/clk_out1
+ SLICE_X89Y70 FDCE r vgaInterface/counter_f_reg[2]/C
+ ------------------------------------------------------------------- -------------------
+ SLICE_X89Y70 FDCE (Prop_fdce_C_Q) 0.456 -0.365 f vgaInterface/counter_f_reg[2]/Q
+ net (fo=5, routed) 1.006 0.641 vgaInterface/counter_f_reg[2]
+ SLICE_X88Y67 LUT1 (Prop_lut1_I0_O) 0.124 0.765 r vgaInterface/FCounter_17bit_carry_i_3/O
+ net (fo=1, routed) 0.000 0.765 runnerObject/pos_object_y_target6_carry_0[1]
+ SLICE_X88Y67 CARRY4 (Prop_carry4_S[1]_CO[3])
+ 0.533 1.298 r runnerObject/FCounter_17bit_carry/CO[3]
+ net (fo=1, routed) 0.000 1.298 runnerObject/FCounter_17bit_carry_n_0
+ SLICE_X88Y68 CARRY4 (Prop_carry4_CI_O[2])
+ 0.239 1.537 r runnerObject/FCounter_17bit_carry__0/O[2]
+ net (fo=2, routed) 0.987 2.523 runnerObject/FCounter_17bit[7]
+ SLICE_X88Y71 LUT2 (Prop_lut2_I0_O) 0.301 2.824 r runnerObject/pos_object_y_target6_carry__0_i_1/O
+ net (fo=1, routed) 0.000 2.824 runnerObject/pos_object_y_target6_carry__0_i_1_n_0
+ SLICE_X88Y71 CARRY4 (Prop_carry4_S[3]_CO[3])
+ 0.376 3.200 r runnerObject/pos_object_y_target6_carry__0/CO[3]
+ net (fo=1, routed) 0.000 3.200 runnerObject/pos_object_y_target6_carry__0_n_0
+ SLICE_X88Y72 CARRY4 (Prop_carry4_CI_O[1])
+ 0.323 3.523 f runnerObject/pos_object_y_target6_carry__1/O[1]
+ net (fo=5, routed) 0.953 4.477 runnerObject/pos_object_y_target6[9]
+ SLICE_X82Y72 LUT1 (Prop_lut1_I0_O) 0.306 4.783 r runnerObject/i__carry__1_i_13/O
+ net (fo=1, routed) 0.000 4.783 runnerObject/p_0_in[9]
+ SLICE_X82Y72 CARRY4 (Prop_carry4_S[0]_O[2])
+ 0.547 5.330 f runnerObject/i__carry__1_i_9/O[2]
+ net (fo=2, routed) 0.821 6.151 runnerObject/pos_object_y_target9[11]
+ SLICE_X84Y71 LUT4 (Prop_lut4_I3_O) 0.302 6.453 r runnerObject/pos_object_y_target2_carry_i_13/O
+ net (fo=2, routed) 0.420 6.872 runnerObject/pos_object_y_target2_carry_i_13_n_0
+ SLICE_X87Y72 LUT6 (Prop_lut6_I0_O) 0.124 6.996 r runnerObject/pos_object_y_target2_carry_i_10/O
+ net (fo=34, routed) 1.081 8.077 runnerObject/pos_object_y_target2_carry_i_10_n_0
+ SLICE_X84Y70 LUT6 (Prop_lut6_I3_O) 0.124 8.201 r runnerObject/pos_object_y_target2_carry_i_9/O
+ net (fo=1, routed) 0.701 8.903 runnerObject/pos_object_y_target2_carry_i_9_n_0
+ SLICE_X85Y70 CARRY4 (Prop_carry4_S[0]_O[3])
+ 0.730 9.633 f runnerObject/pos_object_y_target2_carry/O[3]
+ net (fo=2, routed) 1.215 10.847 runnerObject/pos_object_y_target2[4]
+ SLICE_X84Y73 LUT2 (Prop_lut2_I1_O) 0.306 11.153 r runnerObject/pos_object_y_target1_carry_i_4/O
+ net (fo=1, routed) 0.000 11.153 runnerObject/pos_object_y_target1_carry_i_4_n_0
+ SLICE_X84Y73 CARRY4 (Prop_carry4_S[2]_CO[3])
+ 0.380 11.533 r runnerObject/pos_object_y_target1_carry/CO[3]
+ net (fo=1, routed) 0.000 11.533 runnerObject/pos_object_y_target1_carry_n_0
+ SLICE_X84Y74 CARRY4 (Prop_carry4_CI_CO[3])
+ 0.117 11.650 r runnerObject/pos_object_y_target1_carry__0/CO[3]
+ net (fo=1, routed) 0.009 11.659 runnerObject/pos_object_y_target1_carry__0_n_0
+ SLICE_X84Y75 CARRY4 (Prop_carry4_CI_CO[1])
+ 0.157 11.816 r runnerObject/pos_object_y_target1_carry__1/CO[1]
+ net (fo=11, routed) 1.258 13.075 runnerObject/pos_object_y_target1
+ SLICE_X88Y80 LUT5 (Prop_lut5_I1_O) 0.332 13.407 r runnerObject/pos_object_y_target[8]_i_4/O
+ net (fo=2, routed) 0.682 14.088 runnerObject/pos_object_y_target[8]_i_4_n_0
+ SLICE_X88Y80 LUT4 (Prop_lut4_I3_O) 0.124 14.212 r runnerObject/pos_object_y_target[8]_i_3/O
+ net (fo=1, routed) 0.000 14.212 runnerObject/pos_object_y_target[8]_i_3_n_0
+ SLICE_X88Y80 FDSE r runnerObject/pos_object_y_target_reg[8]/D
+ ------------------------------------------------------------------- -------------------
+
+ (clock clk_out1_clk_wiz_0 rise edge)
+ 40.000 40.000 r
+ E3 0.000 40.000 r clk (IN)
+ net (fo=0) 0.000 40.000 pixelClk/inst/clk_in1
+ E3 IBUF (Prop_ibuf_I_O) 1.411 41.411 r pixelClk/inst/clkin1_ibufg/O
+ net (fo=1, routed) 1.162 42.573 pixelClk/inst/clk_in1_clk_wiz_0
+ MMCME2_ADV_X1Y2 MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKOUT0)
+ -7.324 35.249 r pixelClk/inst/mmcm_adv_inst/CLKOUT0
+ net (fo=1, routed) 1.639 36.888 pixelClk/inst/clk_out1_clk_wiz_0
+ BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.091 36.979 r pixelClk/inst/clkout1_buf/O
+ net (fo=127, routed) 1.601 38.581 runnerObject/clk_out1
+ SLICE_X88Y80 FDSE r runnerObject/pos_object_y_target_reg[8]/C
+ clock pessimism 0.559 39.140
+ clock uncertainty -0.098 39.043
+ SLICE_X88Y80 FDSE (Setup_fdse_C_D) 0.079 39.122 runnerObject/pos_object_y_target_reg[8]
+ -------------------------------------------------------------------
+ required time 39.122
+ arrival time -14.212
+ -------------------------------------------------------------------
+ slack 24.909
+
+Slack (MET) : 25.045ns (required time - arrival time)
+ Source: vgaInterface/counter_f_reg[2]/C
+ (rising edge-triggered cell FDCE clocked by clk_out1_clk_wiz_0 {rise@0.000ns fall@20.000ns period=40.000ns})
+ Destination: runnerObject/pos_object_y_target_reg[5]/R
+ (rising edge-triggered cell FDRE clocked by clk_out1_clk_wiz_0 {rise@0.000ns fall@20.000ns period=40.000ns})
+ Path Group: clk_out1_clk_wiz_0
+ Path Type: Setup (Max at Slow Process Corner)
+ Requirement: 40.000ns (clk_out1_clk_wiz_0 rise@40.000ns - clk_out1_clk_wiz_0 rise@0.000ns)
+ Data Path Delay: 14.294ns (logic 5.777ns (40.414%) route 8.517ns (59.586%))
+ Logic Levels: 17 (CARRY4=9 LUT1=2 LUT2=2 LUT3=1 LUT4=1 LUT6=2)
+ Clock Path Skew: -0.039ns (DCD - SCD + CPR)
+ Destination Clock Delay (DCD): -1.419ns = ( 38.581 - 40.000 )
+ Source Clock Delay (SCD): -0.821ns
+ Clock Pessimism Removal (CPR): 0.559ns
+ Clock Uncertainty: 0.098ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE
+ Total System Jitter (TSJ): 0.071ns
+ Discrete Jitter (DJ): 0.182ns
+ Phase Error (PE): 0.000ns
+
+ Location Delay type Incr(ns) Path(ns) Netlist Resource(s)
+ ------------------------------------------------------------------- -------------------
+ (clock clk_out1_clk_wiz_0 rise edge)
+ 0.000 0.000 r
+ E3 0.000 0.000 r clk (IN)
+ net (fo=0) 0.000 0.000 pixelClk/inst/clk_in1
+ E3 IBUF (Prop_ibuf_I_O) 1.482 1.482 r pixelClk/inst/clkin1_ibufg/O
+ net (fo=1, routed) 1.233 2.715 pixelClk/inst/clk_in1_clk_wiz_0
+ MMCME2_ADV_X1Y2 MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKOUT0)
+ -7.070 -4.355 r pixelClk/inst/mmcm_adv_inst/CLKOUT0
+ net (fo=1, routed) 1.719 -2.636 pixelClk/inst/clk_out1_clk_wiz_0
+ BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.096 -2.540 r pixelClk/inst/clkout1_buf/O
+ net (fo=127, routed) 1.719 -0.821 vgaInterface/clk_out1
+ SLICE_X89Y70 FDCE r vgaInterface/counter_f_reg[2]/C
+ ------------------------------------------------------------------- -------------------
+ SLICE_X89Y70 FDCE (Prop_fdce_C_Q) 0.456 -0.365 f vgaInterface/counter_f_reg[2]/Q
+ net (fo=5, routed) 1.006 0.641 vgaInterface/counter_f_reg[2]
+ SLICE_X88Y67 LUT1 (Prop_lut1_I0_O) 0.124 0.765 r vgaInterface/FCounter_17bit_carry_i_3/O
+ net (fo=1, routed) 0.000 0.765 runnerObject/pos_object_y_target6_carry_0[1]
+ SLICE_X88Y67 CARRY4 (Prop_carry4_S[1]_CO[3])
+ 0.533 1.298 r runnerObject/FCounter_17bit_carry/CO[3]
+ net (fo=1, routed) 0.000 1.298 runnerObject/FCounter_17bit_carry_n_0
+ SLICE_X88Y68 CARRY4 (Prop_carry4_CI_O[2])
+ 0.239 1.537 r runnerObject/FCounter_17bit_carry__0/O[2]
+ net (fo=2, routed) 0.987 2.523 runnerObject/FCounter_17bit[7]
+ SLICE_X88Y71 LUT2 (Prop_lut2_I0_O) 0.301 2.824 r runnerObject/pos_object_y_target6_carry__0_i_1/O
+ net (fo=1, routed) 0.000 2.824 runnerObject/pos_object_y_target6_carry__0_i_1_n_0
+ SLICE_X88Y71 CARRY4 (Prop_carry4_S[3]_CO[3])
+ 0.376 3.200 r runnerObject/pos_object_y_target6_carry__0/CO[3]
+ net (fo=1, routed) 0.000 3.200 runnerObject/pos_object_y_target6_carry__0_n_0
+ SLICE_X88Y72 CARRY4 (Prop_carry4_CI_O[1])
+ 0.323 3.523 f runnerObject/pos_object_y_target6_carry__1/O[1]
+ net (fo=5, routed) 0.953 4.477 runnerObject/pos_object_y_target6[9]
+ SLICE_X82Y72 LUT1 (Prop_lut1_I0_O) 0.306 4.783 r runnerObject/i__carry__1_i_13/O
+ net (fo=1, routed) 0.000 4.783 runnerObject/p_0_in[9]
+ SLICE_X82Y72 CARRY4 (Prop_carry4_S[0]_O[2])
+ 0.547 5.330 f runnerObject/i__carry__1_i_9/O[2]
+ net (fo=2, routed) 0.821 6.151 runnerObject/pos_object_y_target9[11]
+ SLICE_X84Y71 LUT4 (Prop_lut4_I3_O) 0.302 6.453 r runnerObject/pos_object_y_target2_carry_i_13/O
+ net (fo=2, routed) 0.420 6.872 runnerObject/pos_object_y_target2_carry_i_13_n_0
+ SLICE_X87Y72 LUT6 (Prop_lut6_I0_O) 0.124 6.996 r runnerObject/pos_object_y_target2_carry_i_10/O
+ net (fo=34, routed) 1.081 8.077 runnerObject/pos_object_y_target2_carry_i_10_n_0
+ SLICE_X84Y70 LUT6 (Prop_lut6_I3_O) 0.124 8.201 r runnerObject/pos_object_y_target2_carry_i_9/O
+ net (fo=1, routed) 0.701 8.903 runnerObject/pos_object_y_target2_carry_i_9_n_0
+ SLICE_X85Y70 CARRY4 (Prop_carry4_S[0]_O[3])
+ 0.730 9.633 f runnerObject/pos_object_y_target2_carry/O[3]
+ net (fo=2, routed) 1.215 10.847 runnerObject/pos_object_y_target2[4]
+ SLICE_X84Y73 LUT2 (Prop_lut2_I1_O) 0.306 11.153 r runnerObject/pos_object_y_target1_carry_i_4/O
+ net (fo=1, routed) 0.000 11.153 runnerObject/pos_object_y_target1_carry_i_4_n_0
+ SLICE_X84Y73 CARRY4 (Prop_carry4_S[2]_CO[3])
+ 0.380 11.533 r runnerObject/pos_object_y_target1_carry/CO[3]
+ net (fo=1, routed) 0.000 11.533 runnerObject/pos_object_y_target1_carry_n_0
+ SLICE_X84Y74 CARRY4 (Prop_carry4_CI_CO[3])
+ 0.117 11.650 r runnerObject/pos_object_y_target1_carry__0/CO[3]
+ net (fo=1, routed) 0.009 11.659 runnerObject/pos_object_y_target1_carry__0_n_0
+ SLICE_X84Y75 CARRY4 (Prop_carry4_CI_CO[1])
+ 0.157 11.816 f runnerObject/pos_object_y_target1_carry__1/CO[1]
+ net (fo=11, routed) 0.629 12.445 runnerObject/pos_object_y_target1
+ SLICE_X86Y77 LUT3 (Prop_lut3_I0_O) 0.332 12.777 r runnerObject/pos_object_y_target[8]_i_1/O
+ net (fo=9, routed) 0.697 13.474 runnerObject/pos_object_y_target[8]_i_1_n_0
+ SLICE_X88Y79 FDRE r runnerObject/pos_object_y_target_reg[5]/R
+ ------------------------------------------------------------------- -------------------
+
+ (clock clk_out1_clk_wiz_0 rise edge)
+ 40.000 40.000 r
+ E3 0.000 40.000 r clk (IN)
+ net (fo=0) 0.000 40.000 pixelClk/inst/clk_in1
+ E3 IBUF (Prop_ibuf_I_O) 1.411 41.411 r pixelClk/inst/clkin1_ibufg/O
+ net (fo=1, routed) 1.162 42.573 pixelClk/inst/clk_in1_clk_wiz_0
+ MMCME2_ADV_X1Y2 MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKOUT0)
+ -7.324 35.249 r pixelClk/inst/mmcm_adv_inst/CLKOUT0
+ net (fo=1, routed) 1.639 36.888 pixelClk/inst/clk_out1_clk_wiz_0
+ BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.091 36.979 r pixelClk/inst/clkout1_buf/O
+ net (fo=127, routed) 1.601 38.581 runnerObject/clk_out1
+ SLICE_X88Y79 FDRE r runnerObject/pos_object_y_target_reg[5]/C
+ clock pessimism 0.559 39.140
+ clock uncertainty -0.098 39.043
+ SLICE_X88Y79 FDRE (Setup_fdre_C_R) -0.524 38.519 runnerObject/pos_object_y_target_reg[5]
+ -------------------------------------------------------------------
+ required time 38.519
+ arrival time -13.474
+ -------------------------------------------------------------------
+ slack 25.045
+
+Slack (MET) : 25.102ns (required time - arrival time)
+ Source: vgaInterface/counter_f_reg[2]/C
+ (rising edge-triggered cell FDCE clocked by clk_out1_clk_wiz_0 {rise@0.000ns fall@20.000ns period=40.000ns})
+ Destination: runnerObject/pos_object_y_target_reg[6]/S
+ (rising edge-triggered cell FDSE clocked by clk_out1_clk_wiz_0 {rise@0.000ns fall@20.000ns period=40.000ns})
+ Path Group: clk_out1_clk_wiz_0
+ Path Type: Setup (Max at Slow Process Corner)
+ Requirement: 40.000ns (clk_out1_clk_wiz_0 rise@40.000ns - clk_out1_clk_wiz_0 rise@0.000ns)
+ Data Path Delay: 14.237ns (logic 5.777ns (40.577%) route 8.460ns (59.423%))
+ Logic Levels: 17 (CARRY4=9 LUT1=2 LUT2=2 LUT3=1 LUT4=1 LUT6=2)
+ Clock Path Skew: -0.039ns (DCD - SCD + CPR)
+ Destination Clock Delay (DCD): -1.419ns = ( 38.581 - 40.000 )
+ Source Clock Delay (SCD): -0.821ns
+ Clock Pessimism Removal (CPR): 0.559ns
+ Clock Uncertainty: 0.098ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE
+ Total System Jitter (TSJ): 0.071ns
+ Discrete Jitter (DJ): 0.182ns
+ Phase Error (PE): 0.000ns
+
+ Location Delay type Incr(ns) Path(ns) Netlist Resource(s)
+ ------------------------------------------------------------------- -------------------
+ (clock clk_out1_clk_wiz_0 rise edge)
+ 0.000 0.000 r
+ E3 0.000 0.000 r clk (IN)
+ net (fo=0) 0.000 0.000 pixelClk/inst/clk_in1
+ E3 IBUF (Prop_ibuf_I_O) 1.482 1.482 r pixelClk/inst/clkin1_ibufg/O
+ net (fo=1, routed) 1.233 2.715 pixelClk/inst/clk_in1_clk_wiz_0
+ MMCME2_ADV_X1Y2 MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKOUT0)
+ -7.070 -4.355 r pixelClk/inst/mmcm_adv_inst/CLKOUT0
+ net (fo=1, routed) 1.719 -2.636 pixelClk/inst/clk_out1_clk_wiz_0
+ BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.096 -2.540 r pixelClk/inst/clkout1_buf/O
+ net (fo=127, routed) 1.719 -0.821 vgaInterface/clk_out1
+ SLICE_X89Y70 FDCE r vgaInterface/counter_f_reg[2]/C
+ ------------------------------------------------------------------- -------------------
+ SLICE_X89Y70 FDCE (Prop_fdce_C_Q) 0.456 -0.365 f vgaInterface/counter_f_reg[2]/Q
+ net (fo=5, routed) 1.006 0.641 vgaInterface/counter_f_reg[2]
+ SLICE_X88Y67 LUT1 (Prop_lut1_I0_O) 0.124 0.765 r vgaInterface/FCounter_17bit_carry_i_3/O
+ net (fo=1, routed) 0.000 0.765 runnerObject/pos_object_y_target6_carry_0[1]
+ SLICE_X88Y67 CARRY4 (Prop_carry4_S[1]_CO[3])
+ 0.533 1.298 r runnerObject/FCounter_17bit_carry/CO[3]
+ net (fo=1, routed) 0.000 1.298 runnerObject/FCounter_17bit_carry_n_0
+ SLICE_X88Y68 CARRY4 (Prop_carry4_CI_O[2])
+ 0.239 1.537 r runnerObject/FCounter_17bit_carry__0/O[2]
+ net (fo=2, routed) 0.987 2.523 runnerObject/FCounter_17bit[7]
+ SLICE_X88Y71 LUT2 (Prop_lut2_I0_O) 0.301 2.824 r runnerObject/pos_object_y_target6_carry__0_i_1/O
+ net (fo=1, routed) 0.000 2.824 runnerObject/pos_object_y_target6_carry__0_i_1_n_0
+ SLICE_X88Y71 CARRY4 (Prop_carry4_S[3]_CO[3])
+ 0.376 3.200 r runnerObject/pos_object_y_target6_carry__0/CO[3]
+ net (fo=1, routed) 0.000 3.200 runnerObject/pos_object_y_target6_carry__0_n_0
+ SLICE_X88Y72 CARRY4 (Prop_carry4_CI_O[1])
+ 0.323 3.523 f runnerObject/pos_object_y_target6_carry__1/O[1]
+ net (fo=5, routed) 0.953 4.477 runnerObject/pos_object_y_target6[9]
+ SLICE_X82Y72 LUT1 (Prop_lut1_I0_O) 0.306 4.783 r runnerObject/i__carry__1_i_13/O
+ net (fo=1, routed) 0.000 4.783 runnerObject/p_0_in[9]
+ SLICE_X82Y72 CARRY4 (Prop_carry4_S[0]_O[2])
+ 0.547 5.330 f runnerObject/i__carry__1_i_9/O[2]
+ net (fo=2, routed) 0.821 6.151 runnerObject/pos_object_y_target9[11]
+ SLICE_X84Y71 LUT4 (Prop_lut4_I3_O) 0.302 6.453 r runnerObject/pos_object_y_target2_carry_i_13/O
+ net (fo=2, routed) 0.420 6.872 runnerObject/pos_object_y_target2_carry_i_13_n_0
+ SLICE_X87Y72 LUT6 (Prop_lut6_I0_O) 0.124 6.996 r runnerObject/pos_object_y_target2_carry_i_10/O
+ net (fo=34, routed) 1.081 8.077 runnerObject/pos_object_y_target2_carry_i_10_n_0
+ SLICE_X84Y70 LUT6 (Prop_lut6_I3_O) 0.124 8.201 r runnerObject/pos_object_y_target2_carry_i_9/O
+ net (fo=1, routed) 0.701 8.903 runnerObject/pos_object_y_target2_carry_i_9_n_0
+ SLICE_X85Y70 CARRY4 (Prop_carry4_S[0]_O[3])
+ 0.730 9.633 f runnerObject/pos_object_y_target2_carry/O[3]
+ net (fo=2, routed) 1.215 10.847 runnerObject/pos_object_y_target2[4]
+ SLICE_X84Y73 LUT2 (Prop_lut2_I1_O) 0.306 11.153 r runnerObject/pos_object_y_target1_carry_i_4/O
+ net (fo=1, routed) 0.000 11.153 runnerObject/pos_object_y_target1_carry_i_4_n_0
+ SLICE_X84Y73 CARRY4 (Prop_carry4_S[2]_CO[3])
+ 0.380 11.533 r runnerObject/pos_object_y_target1_carry/CO[3]
+ net (fo=1, routed) 0.000 11.533 runnerObject/pos_object_y_target1_carry_n_0
+ SLICE_X84Y74 CARRY4 (Prop_carry4_CI_CO[3])
+ 0.117 11.650 r runnerObject/pos_object_y_target1_carry__0/CO[3]
+ net (fo=1, routed) 0.009 11.659 runnerObject/pos_object_y_target1_carry__0_n_0
+ SLICE_X84Y75 CARRY4 (Prop_carry4_CI_CO[1])
+ 0.157 11.816 f runnerObject/pos_object_y_target1_carry__1/CO[1]
+ net (fo=11, routed) 0.629 12.445 runnerObject/pos_object_y_target1
+ SLICE_X86Y77 LUT3 (Prop_lut3_I0_O) 0.332 12.777 r runnerObject/pos_object_y_target[8]_i_1/O
+ net (fo=9, routed) 0.639 13.416 runnerObject/pos_object_y_target[8]_i_1_n_0
+ SLICE_X88Y80 FDSE r runnerObject/pos_object_y_target_reg[6]/S
+ ------------------------------------------------------------------- -------------------
+
+ (clock clk_out1_clk_wiz_0 rise edge)
+ 40.000 40.000 r
+ E3 0.000 40.000 r clk (IN)
+ net (fo=0) 0.000 40.000 pixelClk/inst/clk_in1
+ E3 IBUF (Prop_ibuf_I_O) 1.411 41.411 r pixelClk/inst/clkin1_ibufg/O
+ net (fo=1, routed) 1.162 42.573 pixelClk/inst/clk_in1_clk_wiz_0
+ MMCME2_ADV_X1Y2 MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKOUT0)
+ -7.324 35.249 r pixelClk/inst/mmcm_adv_inst/CLKOUT0
+ net (fo=1, routed) 1.639 36.888 pixelClk/inst/clk_out1_clk_wiz_0
+ BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.091 36.979 r pixelClk/inst/clkout1_buf/O
+ net (fo=127, routed) 1.601 38.581 runnerObject/clk_out1
+ SLICE_X88Y80 FDSE r runnerObject/pos_object_y_target_reg[6]/C
+ clock pessimism 0.559 39.140
+ clock uncertainty -0.098 39.043
+ SLICE_X88Y80 FDSE (Setup_fdse_C_S) -0.524 38.519 runnerObject/pos_object_y_target_reg[6]
+ -------------------------------------------------------------------
+ required time 38.519
+ arrival time -13.416
+ -------------------------------------------------------------------
+ slack 25.102
+
+Slack (MET) : 25.102ns (required time - arrival time)
+ Source: vgaInterface/counter_f_reg[2]/C
+ (rising edge-triggered cell FDCE clocked by clk_out1_clk_wiz_0 {rise@0.000ns fall@20.000ns period=40.000ns})
+ Destination: runnerObject/pos_object_y_target_reg[7]/R
+ (rising edge-triggered cell FDRE clocked by clk_out1_clk_wiz_0 {rise@0.000ns fall@20.000ns period=40.000ns})
+ Path Group: clk_out1_clk_wiz_0
+ Path Type: Setup (Max at Slow Process Corner)
+ Requirement: 40.000ns (clk_out1_clk_wiz_0 rise@40.000ns - clk_out1_clk_wiz_0 rise@0.000ns)
+ Data Path Delay: 14.237ns (logic 5.777ns (40.577%) route 8.460ns (59.423%))
+ Logic Levels: 17 (CARRY4=9 LUT1=2 LUT2=2 LUT3=1 LUT4=1 LUT6=2)
+ Clock Path Skew: -0.039ns (DCD - SCD + CPR)
+ Destination Clock Delay (DCD): -1.419ns = ( 38.581 - 40.000 )
+ Source Clock Delay (SCD): -0.821ns
+ Clock Pessimism Removal (CPR): 0.559ns
+ Clock Uncertainty: 0.098ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE
+ Total System Jitter (TSJ): 0.071ns
+ Discrete Jitter (DJ): 0.182ns
+ Phase Error (PE): 0.000ns
+
+ Location Delay type Incr(ns) Path(ns) Netlist Resource(s)
+ ------------------------------------------------------------------- -------------------
+ (clock clk_out1_clk_wiz_0 rise edge)
+ 0.000 0.000 r
+ E3 0.000 0.000 r clk (IN)
+ net (fo=0) 0.000 0.000 pixelClk/inst/clk_in1
+ E3 IBUF (Prop_ibuf_I_O) 1.482 1.482 r pixelClk/inst/clkin1_ibufg/O
+ net (fo=1, routed) 1.233 2.715 pixelClk/inst/clk_in1_clk_wiz_0
+ MMCME2_ADV_X1Y2 MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKOUT0)
+ -7.070 -4.355 r pixelClk/inst/mmcm_adv_inst/CLKOUT0
+ net (fo=1, routed) 1.719 -2.636 pixelClk/inst/clk_out1_clk_wiz_0
+ BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.096 -2.540 r pixelClk/inst/clkout1_buf/O
+ net (fo=127, routed) 1.719 -0.821 vgaInterface/clk_out1
+ SLICE_X89Y70 FDCE r vgaInterface/counter_f_reg[2]/C
+ ------------------------------------------------------------------- -------------------
+ SLICE_X89Y70 FDCE (Prop_fdce_C_Q) 0.456 -0.365 f vgaInterface/counter_f_reg[2]/Q
+ net (fo=5, routed) 1.006 0.641 vgaInterface/counter_f_reg[2]
+ SLICE_X88Y67 LUT1 (Prop_lut1_I0_O) 0.124 0.765 r vgaInterface/FCounter_17bit_carry_i_3/O
+ net (fo=1, routed) 0.000 0.765 runnerObject/pos_object_y_target6_carry_0[1]
+ SLICE_X88Y67 CARRY4 (Prop_carry4_S[1]_CO[3])
+ 0.533 1.298 r runnerObject/FCounter_17bit_carry/CO[3]
+ net (fo=1, routed) 0.000 1.298 runnerObject/FCounter_17bit_carry_n_0
+ SLICE_X88Y68 CARRY4 (Prop_carry4_CI_O[2])
+ 0.239 1.537 r runnerObject/FCounter_17bit_carry__0/O[2]
+ net (fo=2, routed) 0.987 2.523 runnerObject/FCounter_17bit[7]
+ SLICE_X88Y71 LUT2 (Prop_lut2_I0_O) 0.301 2.824 r runnerObject/pos_object_y_target6_carry__0_i_1/O
+ net (fo=1, routed) 0.000 2.824 runnerObject/pos_object_y_target6_carry__0_i_1_n_0
+ SLICE_X88Y71 CARRY4 (Prop_carry4_S[3]_CO[3])
+ 0.376 3.200 r runnerObject/pos_object_y_target6_carry__0/CO[3]
+ net (fo=1, routed) 0.000 3.200 runnerObject/pos_object_y_target6_carry__0_n_0
+ SLICE_X88Y72 CARRY4 (Prop_carry4_CI_O[1])
+ 0.323 3.523 f runnerObject/pos_object_y_target6_carry__1/O[1]
+ net (fo=5, routed) 0.953 4.477 runnerObject/pos_object_y_target6[9]
+ SLICE_X82Y72 LUT1 (Prop_lut1_I0_O) 0.306 4.783 r runnerObject/i__carry__1_i_13/O
+ net (fo=1, routed) 0.000 4.783 runnerObject/p_0_in[9]
+ SLICE_X82Y72 CARRY4 (Prop_carry4_S[0]_O[2])
+ 0.547 5.330 f runnerObject/i__carry__1_i_9/O[2]
+ net (fo=2, routed) 0.821 6.151 runnerObject/pos_object_y_target9[11]
+ SLICE_X84Y71 LUT4 (Prop_lut4_I3_O) 0.302 6.453 r runnerObject/pos_object_y_target2_carry_i_13/O
+ net (fo=2, routed) 0.420 6.872 runnerObject/pos_object_y_target2_carry_i_13_n_0
+ SLICE_X87Y72 LUT6 (Prop_lut6_I0_O) 0.124 6.996 r runnerObject/pos_object_y_target2_carry_i_10/O
+ net (fo=34, routed) 1.081 8.077 runnerObject/pos_object_y_target2_carry_i_10_n_0
+ SLICE_X84Y70 LUT6 (Prop_lut6_I3_O) 0.124 8.201 r runnerObject/pos_object_y_target2_carry_i_9/O
+ net (fo=1, routed) 0.701 8.903 runnerObject/pos_object_y_target2_carry_i_9_n_0
+ SLICE_X85Y70 CARRY4 (Prop_carry4_S[0]_O[3])
+ 0.730 9.633 f runnerObject/pos_object_y_target2_carry/O[3]
+ net (fo=2, routed) 1.215 10.847 runnerObject/pos_object_y_target2[4]
+ SLICE_X84Y73 LUT2 (Prop_lut2_I1_O) 0.306 11.153 r runnerObject/pos_object_y_target1_carry_i_4/O
+ net (fo=1, routed) 0.000 11.153 runnerObject/pos_object_y_target1_carry_i_4_n_0
+ SLICE_X84Y73 CARRY4 (Prop_carry4_S[2]_CO[3])
+ 0.380 11.533 r runnerObject/pos_object_y_target1_carry/CO[3]
+ net (fo=1, routed) 0.000 11.533 runnerObject/pos_object_y_target1_carry_n_0
+ SLICE_X84Y74 CARRY4 (Prop_carry4_CI_CO[3])
+ 0.117 11.650 r runnerObject/pos_object_y_target1_carry__0/CO[3]
+ net (fo=1, routed) 0.009 11.659 runnerObject/pos_object_y_target1_carry__0_n_0
+ SLICE_X84Y75 CARRY4 (Prop_carry4_CI_CO[1])
+ 0.157 11.816 f runnerObject/pos_object_y_target1_carry__1/CO[1]
+ net (fo=11, routed) 0.629 12.445 runnerObject/pos_object_y_target1
+ SLICE_X86Y77 LUT3 (Prop_lut3_I0_O) 0.332 12.777 r runnerObject/pos_object_y_target[8]_i_1/O
+ net (fo=9, routed) 0.639 13.416 runnerObject/pos_object_y_target[8]_i_1_n_0
+ SLICE_X88Y80 FDRE r runnerObject/pos_object_y_target_reg[7]/R
+ ------------------------------------------------------------------- -------------------
+
+ (clock clk_out1_clk_wiz_0 rise edge)
+ 40.000 40.000 r
+ E3 0.000 40.000 r clk (IN)
+ net (fo=0) 0.000 40.000 pixelClk/inst/clk_in1
+ E3 IBUF (Prop_ibuf_I_O) 1.411 41.411 r pixelClk/inst/clkin1_ibufg/O
+ net (fo=1, routed) 1.162 42.573 pixelClk/inst/clk_in1_clk_wiz_0
+ MMCME2_ADV_X1Y2 MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKOUT0)
+ -7.324 35.249 r pixelClk/inst/mmcm_adv_inst/CLKOUT0
+ net (fo=1, routed) 1.639 36.888 pixelClk/inst/clk_out1_clk_wiz_0
+ BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.091 36.979 r pixelClk/inst/clkout1_buf/O
+ net (fo=127, routed) 1.601 38.581 runnerObject/clk_out1
+ SLICE_X88Y80 FDRE r runnerObject/pos_object_y_target_reg[7]/C
+ clock pessimism 0.559 39.140
+ clock uncertainty -0.098 39.043
+ SLICE_X88Y80 FDRE (Setup_fdre_C_R) -0.524 38.519 runnerObject/pos_object_y_target_reg[7]
+ -------------------------------------------------------------------
+ required time 38.519
+ arrival time -13.416
+ -------------------------------------------------------------------
+ slack 25.102
+
+Slack (MET) : 25.102ns (required time - arrival time)
+ Source: vgaInterface/counter_f_reg[2]/C
+ (rising edge-triggered cell FDCE clocked by clk_out1_clk_wiz_0 {rise@0.000ns fall@20.000ns period=40.000ns})
+ Destination: runnerObject/pos_object_y_target_reg[8]/S
+ (rising edge-triggered cell FDSE clocked by clk_out1_clk_wiz_0 {rise@0.000ns fall@20.000ns period=40.000ns})
+ Path Group: clk_out1_clk_wiz_0
+ Path Type: Setup (Max at Slow Process Corner)
+ Requirement: 40.000ns (clk_out1_clk_wiz_0 rise@40.000ns - clk_out1_clk_wiz_0 rise@0.000ns)
+ Data Path Delay: 14.237ns (logic 5.777ns (40.577%) route 8.460ns (59.423%))
+ Logic Levels: 17 (CARRY4=9 LUT1=2 LUT2=2 LUT3=1 LUT4=1 LUT6=2)
+ Clock Path Skew: -0.039ns (DCD - SCD + CPR)
+ Destination Clock Delay (DCD): -1.419ns = ( 38.581 - 40.000 )
+ Source Clock Delay (SCD): -0.821ns
+ Clock Pessimism Removal (CPR): 0.559ns
+ Clock Uncertainty: 0.098ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE
+ Total System Jitter (TSJ): 0.071ns
+ Discrete Jitter (DJ): 0.182ns
+ Phase Error (PE): 0.000ns
+
+ Location Delay type Incr(ns) Path(ns) Netlist Resource(s)
+ ------------------------------------------------------------------- -------------------
+ (clock clk_out1_clk_wiz_0 rise edge)
+ 0.000 0.000 r
+ E3 0.000 0.000 r clk (IN)
+ net (fo=0) 0.000 0.000 pixelClk/inst/clk_in1
+ E3 IBUF (Prop_ibuf_I_O) 1.482 1.482 r pixelClk/inst/clkin1_ibufg/O
+ net (fo=1, routed) 1.233 2.715 pixelClk/inst/clk_in1_clk_wiz_0
+ MMCME2_ADV_X1Y2 MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKOUT0)
+ -7.070 -4.355 r pixelClk/inst/mmcm_adv_inst/CLKOUT0
+ net (fo=1, routed) 1.719 -2.636 pixelClk/inst/clk_out1_clk_wiz_0
+ BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.096 -2.540 r pixelClk/inst/clkout1_buf/O
+ net (fo=127, routed) 1.719 -0.821 vgaInterface/clk_out1
+ SLICE_X89Y70 FDCE r vgaInterface/counter_f_reg[2]/C
+ ------------------------------------------------------------------- -------------------
+ SLICE_X89Y70 FDCE (Prop_fdce_C_Q) 0.456 -0.365 f vgaInterface/counter_f_reg[2]/Q
+ net (fo=5, routed) 1.006 0.641 vgaInterface/counter_f_reg[2]
+ SLICE_X88Y67 LUT1 (Prop_lut1_I0_O) 0.124 0.765 r vgaInterface/FCounter_17bit_carry_i_3/O
+ net (fo=1, routed) 0.000 0.765 runnerObject/pos_object_y_target6_carry_0[1]
+ SLICE_X88Y67 CARRY4 (Prop_carry4_S[1]_CO[3])
+ 0.533 1.298 r runnerObject/FCounter_17bit_carry/CO[3]
+ net (fo=1, routed) 0.000 1.298 runnerObject/FCounter_17bit_carry_n_0
+ SLICE_X88Y68 CARRY4 (Prop_carry4_CI_O[2])
+ 0.239 1.537 r runnerObject/FCounter_17bit_carry__0/O[2]
+ net (fo=2, routed) 0.987 2.523 runnerObject/FCounter_17bit[7]
+ SLICE_X88Y71 LUT2 (Prop_lut2_I0_O) 0.301 2.824 r runnerObject/pos_object_y_target6_carry__0_i_1/O
+ net (fo=1, routed) 0.000 2.824 runnerObject/pos_object_y_target6_carry__0_i_1_n_0
+ SLICE_X88Y71 CARRY4 (Prop_carry4_S[3]_CO[3])
+ 0.376 3.200 r runnerObject/pos_object_y_target6_carry__0/CO[3]
+ net (fo=1, routed) 0.000 3.200 runnerObject/pos_object_y_target6_carry__0_n_0
+ SLICE_X88Y72 CARRY4 (Prop_carry4_CI_O[1])
+ 0.323 3.523 f runnerObject/pos_object_y_target6_carry__1/O[1]
+ net (fo=5, routed) 0.953 4.477 runnerObject/pos_object_y_target6[9]
+ SLICE_X82Y72 LUT1 (Prop_lut1_I0_O) 0.306 4.783 r runnerObject/i__carry__1_i_13/O
+ net (fo=1, routed) 0.000 4.783 runnerObject/p_0_in[9]
+ SLICE_X82Y72 CARRY4 (Prop_carry4_S[0]_O[2])
+ 0.547 5.330 f runnerObject/i__carry__1_i_9/O[2]
+ net (fo=2, routed) 0.821 6.151 runnerObject/pos_object_y_target9[11]
+ SLICE_X84Y71 LUT4 (Prop_lut4_I3_O) 0.302 6.453 r runnerObject/pos_object_y_target2_carry_i_13/O
+ net (fo=2, routed) 0.420 6.872 runnerObject/pos_object_y_target2_carry_i_13_n_0
+ SLICE_X87Y72 LUT6 (Prop_lut6_I0_O) 0.124 6.996 r runnerObject/pos_object_y_target2_carry_i_10/O
+ net (fo=34, routed) 1.081 8.077 runnerObject/pos_object_y_target2_carry_i_10_n_0
+ SLICE_X84Y70 LUT6 (Prop_lut6_I3_O) 0.124 8.201 r runnerObject/pos_object_y_target2_carry_i_9/O
+ net (fo=1, routed) 0.701 8.903 runnerObject/pos_object_y_target2_carry_i_9_n_0
+ SLICE_X85Y70 CARRY4 (Prop_carry4_S[0]_O[3])
+ 0.730 9.633 f runnerObject/pos_object_y_target2_carry/O[3]
+ net (fo=2, routed) 1.215 10.847 runnerObject/pos_object_y_target2[4]
+ SLICE_X84Y73 LUT2 (Prop_lut2_I1_O) 0.306 11.153 r runnerObject/pos_object_y_target1_carry_i_4/O
+ net (fo=1, routed) 0.000 11.153 runnerObject/pos_object_y_target1_carry_i_4_n_0
+ SLICE_X84Y73 CARRY4 (Prop_carry4_S[2]_CO[3])
+ 0.380 11.533 r runnerObject/pos_object_y_target1_carry/CO[3]
+ net (fo=1, routed) 0.000 11.533 runnerObject/pos_object_y_target1_carry_n_0
+ SLICE_X84Y74 CARRY4 (Prop_carry4_CI_CO[3])
+ 0.117 11.650 r runnerObject/pos_object_y_target1_carry__0/CO[3]
+ net (fo=1, routed) 0.009 11.659 runnerObject/pos_object_y_target1_carry__0_n_0
+ SLICE_X84Y75 CARRY4 (Prop_carry4_CI_CO[1])
+ 0.157 11.816 f runnerObject/pos_object_y_target1_carry__1/CO[1]
+ net (fo=11, routed) 0.629 12.445 runnerObject/pos_object_y_target1
+ SLICE_X86Y77 LUT3 (Prop_lut3_I0_O) 0.332 12.777 r runnerObject/pos_object_y_target[8]_i_1/O
+ net (fo=9, routed) 0.639 13.416 runnerObject/pos_object_y_target[8]_i_1_n_0
+ SLICE_X88Y80 FDSE r runnerObject/pos_object_y_target_reg[8]/S
+ ------------------------------------------------------------------- -------------------
+
+ (clock clk_out1_clk_wiz_0 rise edge)
+ 40.000 40.000 r
+ E3 0.000 40.000 r clk (IN)
+ net (fo=0) 0.000 40.000 pixelClk/inst/clk_in1
+ E3 IBUF (Prop_ibuf_I_O) 1.411 41.411 r pixelClk/inst/clkin1_ibufg/O
+ net (fo=1, routed) 1.162 42.573 pixelClk/inst/clk_in1_clk_wiz_0
+ MMCME2_ADV_X1Y2 MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKOUT0)
+ -7.324 35.249 r pixelClk/inst/mmcm_adv_inst/CLKOUT0
+ net (fo=1, routed) 1.639 36.888 pixelClk/inst/clk_out1_clk_wiz_0
+ BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.091 36.979 r pixelClk/inst/clkout1_buf/O
+ net (fo=127, routed) 1.601 38.581 runnerObject/clk_out1
+ SLICE_X88Y80 FDSE r runnerObject/pos_object_y_target_reg[8]/C
+ clock pessimism 0.559 39.140
+ clock uncertainty -0.098 39.043
+ SLICE_X88Y80 FDSE (Setup_fdse_C_S) -0.524 38.519 runnerObject/pos_object_y_target_reg[8]
+ -------------------------------------------------------------------
+ required time 38.519
+ arrival time -13.416
+ -------------------------------------------------------------------
+ slack 25.102
+
+Slack (MET) : 25.140ns (required time - arrival time)
+ Source: vgaInterface/counter_f_reg[2]/C
+ (rising edge-triggered cell FDCE clocked by clk_out1_clk_wiz_0 {rise@0.000ns fall@20.000ns period=40.000ns})
+ Destination: runnerObject/pos_object_y_target_reg[0]/R
+ (rising edge-triggered cell FDRE clocked by clk_out1_clk_wiz_0 {rise@0.000ns fall@20.000ns period=40.000ns})
+ Path Group: clk_out1_clk_wiz_0
+ Path Type: Setup (Max at Slow Process Corner)
+ Requirement: 40.000ns (clk_out1_clk_wiz_0 rise@40.000ns - clk_out1_clk_wiz_0 rise@0.000ns)
+ Data Path Delay: 14.294ns (logic 5.777ns (40.414%) route 8.517ns (59.586%))
+ Logic Levels: 17 (CARRY4=9 LUT1=2 LUT2=2 LUT3=1 LUT4=1 LUT6=2)
+ Clock Path Skew: -0.039ns (DCD - SCD + CPR)
+ Destination Clock Delay (DCD): -1.419ns = ( 38.581 - 40.000 )
+ Source Clock Delay (SCD): -0.821ns
+ Clock Pessimism Removal (CPR): 0.559ns
+ Clock Uncertainty: 0.098ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE
+ Total System Jitter (TSJ): 0.071ns
+ Discrete Jitter (DJ): 0.182ns
+ Phase Error (PE): 0.000ns
+
+ Location Delay type Incr(ns) Path(ns) Netlist Resource(s)
+ ------------------------------------------------------------------- -------------------
+ (clock clk_out1_clk_wiz_0 rise edge)
+ 0.000 0.000 r
+ E3 0.000 0.000 r clk (IN)
+ net (fo=0) 0.000 0.000 pixelClk/inst/clk_in1
+ E3 IBUF (Prop_ibuf_I_O) 1.482 1.482 r pixelClk/inst/clkin1_ibufg/O
+ net (fo=1, routed) 1.233 2.715 pixelClk/inst/clk_in1_clk_wiz_0
+ MMCME2_ADV_X1Y2 MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKOUT0)
+ -7.070 -4.355 r pixelClk/inst/mmcm_adv_inst/CLKOUT0
+ net (fo=1, routed) 1.719 -2.636 pixelClk/inst/clk_out1_clk_wiz_0
+ BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.096 -2.540 r pixelClk/inst/clkout1_buf/O
+ net (fo=127, routed) 1.719 -0.821 vgaInterface/clk_out1
+ SLICE_X89Y70 FDCE r vgaInterface/counter_f_reg[2]/C
+ ------------------------------------------------------------------- -------------------
+ SLICE_X89Y70 FDCE (Prop_fdce_C_Q) 0.456 -0.365 f vgaInterface/counter_f_reg[2]/Q
+ net (fo=5, routed) 1.006 0.641 vgaInterface/counter_f_reg[2]
+ SLICE_X88Y67 LUT1 (Prop_lut1_I0_O) 0.124 0.765 r vgaInterface/FCounter_17bit_carry_i_3/O
+ net (fo=1, routed) 0.000 0.765 runnerObject/pos_object_y_target6_carry_0[1]
+ SLICE_X88Y67 CARRY4 (Prop_carry4_S[1]_CO[3])
+ 0.533 1.298 r runnerObject/FCounter_17bit_carry/CO[3]
+ net (fo=1, routed) 0.000 1.298 runnerObject/FCounter_17bit_carry_n_0
+ SLICE_X88Y68 CARRY4 (Prop_carry4_CI_O[2])
+ 0.239 1.537 r runnerObject/FCounter_17bit_carry__0/O[2]
+ net (fo=2, routed) 0.987 2.523 runnerObject/FCounter_17bit[7]
+ SLICE_X88Y71 LUT2 (Prop_lut2_I0_O) 0.301 2.824 r runnerObject/pos_object_y_target6_carry__0_i_1/O
+ net (fo=1, routed) 0.000 2.824 runnerObject/pos_object_y_target6_carry__0_i_1_n_0
+ SLICE_X88Y71 CARRY4 (Prop_carry4_S[3]_CO[3])
+ 0.376 3.200 r runnerObject/pos_object_y_target6_carry__0/CO[3]
+ net (fo=1, routed) 0.000 3.200 runnerObject/pos_object_y_target6_carry__0_n_0
+ SLICE_X88Y72 CARRY4 (Prop_carry4_CI_O[1])
+ 0.323 3.523 f runnerObject/pos_object_y_target6_carry__1/O[1]
+ net (fo=5, routed) 0.953 4.477 runnerObject/pos_object_y_target6[9]
+ SLICE_X82Y72 LUT1 (Prop_lut1_I0_O) 0.306 4.783 r runnerObject/i__carry__1_i_13/O
+ net (fo=1, routed) 0.000 4.783 runnerObject/p_0_in[9]
+ SLICE_X82Y72 CARRY4 (Prop_carry4_S[0]_O[2])
+ 0.547 5.330 f runnerObject/i__carry__1_i_9/O[2]
+ net (fo=2, routed) 0.821 6.151 runnerObject/pos_object_y_target9[11]
+ SLICE_X84Y71 LUT4 (Prop_lut4_I3_O) 0.302 6.453 r runnerObject/pos_object_y_target2_carry_i_13/O
+ net (fo=2, routed) 0.420 6.872 runnerObject/pos_object_y_target2_carry_i_13_n_0
+ SLICE_X87Y72 LUT6 (Prop_lut6_I0_O) 0.124 6.996 r runnerObject/pos_object_y_target2_carry_i_10/O
+ net (fo=34, routed) 1.081 8.077 runnerObject/pos_object_y_target2_carry_i_10_n_0
+ SLICE_X84Y70 LUT6 (Prop_lut6_I3_O) 0.124 8.201 r runnerObject/pos_object_y_target2_carry_i_9/O
+ net (fo=1, routed) 0.701 8.903 runnerObject/pos_object_y_target2_carry_i_9_n_0
+ SLICE_X85Y70 CARRY4 (Prop_carry4_S[0]_O[3])
+ 0.730 9.633 f runnerObject/pos_object_y_target2_carry/O[3]
+ net (fo=2, routed) 1.215 10.847 runnerObject/pos_object_y_target2[4]
+ SLICE_X84Y73 LUT2 (Prop_lut2_I1_O) 0.306 11.153 r runnerObject/pos_object_y_target1_carry_i_4/O
+ net (fo=1, routed) 0.000 11.153 runnerObject/pos_object_y_target1_carry_i_4_n_0
+ SLICE_X84Y73 CARRY4 (Prop_carry4_S[2]_CO[3])
+ 0.380 11.533 r runnerObject/pos_object_y_target1_carry/CO[3]
+ net (fo=1, routed) 0.000 11.533 runnerObject/pos_object_y_target1_carry_n_0
+ SLICE_X84Y74 CARRY4 (Prop_carry4_CI_CO[3])
+ 0.117 11.650 r runnerObject/pos_object_y_target1_carry__0/CO[3]
+ net (fo=1, routed) 0.009 11.659 runnerObject/pos_object_y_target1_carry__0_n_0
+ SLICE_X84Y75 CARRY4 (Prop_carry4_CI_CO[1])
+ 0.157 11.816 f runnerObject/pos_object_y_target1_carry__1/CO[1]
+ net (fo=11, routed) 0.629 12.445 runnerObject/pos_object_y_target1
+ SLICE_X86Y77 LUT3 (Prop_lut3_I0_O) 0.332 12.777 r runnerObject/pos_object_y_target[8]_i_1/O
+ net (fo=9, routed) 0.697 13.474 runnerObject/pos_object_y_target[8]_i_1_n_0
+ SLICE_X89Y79 FDRE r runnerObject/pos_object_y_target_reg[0]/R
+ ------------------------------------------------------------------- -------------------
+
+ (clock clk_out1_clk_wiz_0 rise edge)
+ 40.000 40.000 r
+ E3 0.000 40.000 r clk (IN)
+ net (fo=0) 0.000 40.000 pixelClk/inst/clk_in1
+ E3 IBUF (Prop_ibuf_I_O) 1.411 41.411 r pixelClk/inst/clkin1_ibufg/O
+ net (fo=1, routed) 1.162 42.573 pixelClk/inst/clk_in1_clk_wiz_0
+ MMCME2_ADV_X1Y2 MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKOUT0)
+ -7.324 35.249 r pixelClk/inst/mmcm_adv_inst/CLKOUT0
+ net (fo=1, routed) 1.639 36.888 pixelClk/inst/clk_out1_clk_wiz_0
+ BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.091 36.979 r pixelClk/inst/clkout1_buf/O
+ net (fo=127, routed) 1.601 38.581 runnerObject/clk_out1
+ SLICE_X89Y79 FDRE r runnerObject/pos_object_y_target_reg[0]/C
+ clock pessimism 0.559 39.140
+ clock uncertainty -0.098 39.043
+ SLICE_X89Y79 FDRE (Setup_fdre_C_R) -0.429 38.614 runnerObject/pos_object_y_target_reg[0]
+ -------------------------------------------------------------------
+ required time 38.614
+ arrival time -13.474
+ -------------------------------------------------------------------
+ slack 25.140
+
+Slack (MET) : 25.140ns (required time - arrival time)
+ Source: vgaInterface/counter_f_reg[2]/C
+ (rising edge-triggered cell FDCE clocked by clk_out1_clk_wiz_0 {rise@0.000ns fall@20.000ns period=40.000ns})
+ Destination: runnerObject/pos_object_y_target_reg[1]/S
+ (rising edge-triggered cell FDSE clocked by clk_out1_clk_wiz_0 {rise@0.000ns fall@20.000ns period=40.000ns})
+ Path Group: clk_out1_clk_wiz_0
+ Path Type: Setup (Max at Slow Process Corner)
+ Requirement: 40.000ns (clk_out1_clk_wiz_0 rise@40.000ns - clk_out1_clk_wiz_0 rise@0.000ns)
+ Data Path Delay: 14.294ns (logic 5.777ns (40.414%) route 8.517ns (59.586%))
+ Logic Levels: 17 (CARRY4=9 LUT1=2 LUT2=2 LUT3=1 LUT4=1 LUT6=2)
+ Clock Path Skew: -0.039ns (DCD - SCD + CPR)
+ Destination Clock Delay (DCD): -1.419ns = ( 38.581 - 40.000 )
+ Source Clock Delay (SCD): -0.821ns
+ Clock Pessimism Removal (CPR): 0.559ns
+ Clock Uncertainty: 0.098ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE
+ Total System Jitter (TSJ): 0.071ns
+ Discrete Jitter (DJ): 0.182ns
+ Phase Error (PE): 0.000ns
+
+ Location Delay type Incr(ns) Path(ns) Netlist Resource(s)
+ ------------------------------------------------------------------- -------------------
+ (clock clk_out1_clk_wiz_0 rise edge)
+ 0.000 0.000 r
+ E3 0.000 0.000 r clk (IN)
+ net (fo=0) 0.000 0.000 pixelClk/inst/clk_in1
+ E3 IBUF (Prop_ibuf_I_O) 1.482 1.482 r pixelClk/inst/clkin1_ibufg/O
+ net (fo=1, routed) 1.233 2.715 pixelClk/inst/clk_in1_clk_wiz_0
+ MMCME2_ADV_X1Y2 MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKOUT0)
+ -7.070 -4.355 r pixelClk/inst/mmcm_adv_inst/CLKOUT0
+ net (fo=1, routed) 1.719 -2.636 pixelClk/inst/clk_out1_clk_wiz_0
+ BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.096 -2.540 r pixelClk/inst/clkout1_buf/O
+ net (fo=127, routed) 1.719 -0.821 vgaInterface/clk_out1
+ SLICE_X89Y70 FDCE r vgaInterface/counter_f_reg[2]/C
+ ------------------------------------------------------------------- -------------------
+ SLICE_X89Y70 FDCE (Prop_fdce_C_Q) 0.456 -0.365 f vgaInterface/counter_f_reg[2]/Q
+ net (fo=5, routed) 1.006 0.641 vgaInterface/counter_f_reg[2]
+ SLICE_X88Y67 LUT1 (Prop_lut1_I0_O) 0.124 0.765 r vgaInterface/FCounter_17bit_carry_i_3/O
+ net (fo=1, routed) 0.000 0.765 runnerObject/pos_object_y_target6_carry_0[1]
+ SLICE_X88Y67 CARRY4 (Prop_carry4_S[1]_CO[3])
+ 0.533 1.298 r runnerObject/FCounter_17bit_carry/CO[3]
+ net (fo=1, routed) 0.000 1.298 runnerObject/FCounter_17bit_carry_n_0
+ SLICE_X88Y68 CARRY4 (Prop_carry4_CI_O[2])
+ 0.239 1.537 r runnerObject/FCounter_17bit_carry__0/O[2]
+ net (fo=2, routed) 0.987 2.523 runnerObject/FCounter_17bit[7]
+ SLICE_X88Y71 LUT2 (Prop_lut2_I0_O) 0.301 2.824 r runnerObject/pos_object_y_target6_carry__0_i_1/O
+ net (fo=1, routed) 0.000 2.824 runnerObject/pos_object_y_target6_carry__0_i_1_n_0
+ SLICE_X88Y71 CARRY4 (Prop_carry4_S[3]_CO[3])
+ 0.376 3.200 r runnerObject/pos_object_y_target6_carry__0/CO[3]
+ net (fo=1, routed) 0.000 3.200 runnerObject/pos_object_y_target6_carry__0_n_0
+ SLICE_X88Y72 CARRY4 (Prop_carry4_CI_O[1])
+ 0.323 3.523 f runnerObject/pos_object_y_target6_carry__1/O[1]
+ net (fo=5, routed) 0.953 4.477 runnerObject/pos_object_y_target6[9]
+ SLICE_X82Y72 LUT1 (Prop_lut1_I0_O) 0.306 4.783 r runnerObject/i__carry__1_i_13/O
+ net (fo=1, routed) 0.000 4.783 runnerObject/p_0_in[9]
+ SLICE_X82Y72 CARRY4 (Prop_carry4_S[0]_O[2])
+ 0.547 5.330 f runnerObject/i__carry__1_i_9/O[2]
+ net (fo=2, routed) 0.821 6.151 runnerObject/pos_object_y_target9[11]
+ SLICE_X84Y71 LUT4 (Prop_lut4_I3_O) 0.302 6.453 r runnerObject/pos_object_y_target2_carry_i_13/O
+ net (fo=2, routed) 0.420 6.872 runnerObject/pos_object_y_target2_carry_i_13_n_0
+ SLICE_X87Y72 LUT6 (Prop_lut6_I0_O) 0.124 6.996 r runnerObject/pos_object_y_target2_carry_i_10/O
+ net (fo=34, routed) 1.081 8.077 runnerObject/pos_object_y_target2_carry_i_10_n_0
+ SLICE_X84Y70 LUT6 (Prop_lut6_I3_O) 0.124 8.201 r runnerObject/pos_object_y_target2_carry_i_9/O
+ net (fo=1, routed) 0.701 8.903 runnerObject/pos_object_y_target2_carry_i_9_n_0
+ SLICE_X85Y70 CARRY4 (Prop_carry4_S[0]_O[3])
+ 0.730 9.633 f runnerObject/pos_object_y_target2_carry/O[3]
+ net (fo=2, routed) 1.215 10.847 runnerObject/pos_object_y_target2[4]
+ SLICE_X84Y73 LUT2 (Prop_lut2_I1_O) 0.306 11.153 r runnerObject/pos_object_y_target1_carry_i_4/O
+ net (fo=1, routed) 0.000 11.153 runnerObject/pos_object_y_target1_carry_i_4_n_0
+ SLICE_X84Y73 CARRY4 (Prop_carry4_S[2]_CO[3])
+ 0.380 11.533 r runnerObject/pos_object_y_target1_carry/CO[3]
+ net (fo=1, routed) 0.000 11.533 runnerObject/pos_object_y_target1_carry_n_0
+ SLICE_X84Y74 CARRY4 (Prop_carry4_CI_CO[3])
+ 0.117 11.650 r runnerObject/pos_object_y_target1_carry__0/CO[3]
+ net (fo=1, routed) 0.009 11.659 runnerObject/pos_object_y_target1_carry__0_n_0
+ SLICE_X84Y75 CARRY4 (Prop_carry4_CI_CO[1])
+ 0.157 11.816 f runnerObject/pos_object_y_target1_carry__1/CO[1]
+ net (fo=11, routed) 0.629 12.445 runnerObject/pos_object_y_target1
+ SLICE_X86Y77 LUT3 (Prop_lut3_I0_O) 0.332 12.777 r runnerObject/pos_object_y_target[8]_i_1/O
+ net (fo=9, routed) 0.697 13.474 runnerObject/pos_object_y_target[8]_i_1_n_0
+ SLICE_X89Y79 FDSE r runnerObject/pos_object_y_target_reg[1]/S
+ ------------------------------------------------------------------- -------------------
+
+ (clock clk_out1_clk_wiz_0 rise edge)
+ 40.000 40.000 r
+ E3 0.000 40.000 r clk (IN)
+ net (fo=0) 0.000 40.000 pixelClk/inst/clk_in1
+ E3 IBUF (Prop_ibuf_I_O) 1.411 41.411 r pixelClk/inst/clkin1_ibufg/O
+ net (fo=1, routed) 1.162 42.573 pixelClk/inst/clk_in1_clk_wiz_0
+ MMCME2_ADV_X1Y2 MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKOUT0)
+ -7.324 35.249 r pixelClk/inst/mmcm_adv_inst/CLKOUT0
+ net (fo=1, routed) 1.639 36.888 pixelClk/inst/clk_out1_clk_wiz_0
+ BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.091 36.979 r pixelClk/inst/clkout1_buf/O
+ net (fo=127, routed) 1.601 38.581 runnerObject/clk_out1
+ SLICE_X89Y79 FDSE r runnerObject/pos_object_y_target_reg[1]/C
+ clock pessimism 0.559 39.140
+ clock uncertainty -0.098 39.043
+ SLICE_X89Y79 FDSE (Setup_fdse_C_S) -0.429 38.614 runnerObject/pos_object_y_target_reg[1]
+ -------------------------------------------------------------------
+ required time 38.614
+ arrival time -13.474
+ -------------------------------------------------------------------
+ slack 25.140
+
+Slack (MET) : 25.140ns (required time - arrival time)
+ Source: vgaInterface/counter_f_reg[2]/C
+ (rising edge-triggered cell FDCE clocked by clk_out1_clk_wiz_0 {rise@0.000ns fall@20.000ns period=40.000ns})
+ Destination: runnerObject/pos_object_y_target_reg[2]/S
+ (rising edge-triggered cell FDSE clocked by clk_out1_clk_wiz_0 {rise@0.000ns fall@20.000ns period=40.000ns})
+ Path Group: clk_out1_clk_wiz_0
+ Path Type: Setup (Max at Slow Process Corner)
+ Requirement: 40.000ns (clk_out1_clk_wiz_0 rise@40.000ns - clk_out1_clk_wiz_0 rise@0.000ns)
+ Data Path Delay: 14.294ns (logic 5.777ns (40.414%) route 8.517ns (59.586%))
+ Logic Levels: 17 (CARRY4=9 LUT1=2 LUT2=2 LUT3=1 LUT4=1 LUT6=2)
+ Clock Path Skew: -0.039ns (DCD - SCD + CPR)
+ Destination Clock Delay (DCD): -1.419ns = ( 38.581 - 40.000 )
+ Source Clock Delay (SCD): -0.821ns
+ Clock Pessimism Removal (CPR): 0.559ns
+ Clock Uncertainty: 0.098ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE
+ Total System Jitter (TSJ): 0.071ns
+ Discrete Jitter (DJ): 0.182ns
+ Phase Error (PE): 0.000ns
+
+ Location Delay type Incr(ns) Path(ns) Netlist Resource(s)
+ ------------------------------------------------------------------- -------------------
+ (clock clk_out1_clk_wiz_0 rise edge)
+ 0.000 0.000 r
+ E3 0.000 0.000 r clk (IN)
+ net (fo=0) 0.000 0.000 pixelClk/inst/clk_in1
+ E3 IBUF (Prop_ibuf_I_O) 1.482 1.482 r pixelClk/inst/clkin1_ibufg/O
+ net (fo=1, routed) 1.233 2.715 pixelClk/inst/clk_in1_clk_wiz_0
+ MMCME2_ADV_X1Y2 MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKOUT0)
+ -7.070 -4.355 r pixelClk/inst/mmcm_adv_inst/CLKOUT0
+ net (fo=1, routed) 1.719 -2.636 pixelClk/inst/clk_out1_clk_wiz_0
+ BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.096 -2.540 r pixelClk/inst/clkout1_buf/O
+ net (fo=127, routed) 1.719 -0.821 vgaInterface/clk_out1
+ SLICE_X89Y70 FDCE r vgaInterface/counter_f_reg[2]/C
+ ------------------------------------------------------------------- -------------------
+ SLICE_X89Y70 FDCE (Prop_fdce_C_Q) 0.456 -0.365 f vgaInterface/counter_f_reg[2]/Q
+ net (fo=5, routed) 1.006 0.641 vgaInterface/counter_f_reg[2]
+ SLICE_X88Y67 LUT1 (Prop_lut1_I0_O) 0.124 0.765 r vgaInterface/FCounter_17bit_carry_i_3/O
+ net (fo=1, routed) 0.000 0.765 runnerObject/pos_object_y_target6_carry_0[1]
+ SLICE_X88Y67 CARRY4 (Prop_carry4_S[1]_CO[3])
+ 0.533 1.298 r runnerObject/FCounter_17bit_carry/CO[3]
+ net (fo=1, routed) 0.000 1.298 runnerObject/FCounter_17bit_carry_n_0
+ SLICE_X88Y68 CARRY4 (Prop_carry4_CI_O[2])
+ 0.239 1.537 r runnerObject/FCounter_17bit_carry__0/O[2]
+ net (fo=2, routed) 0.987 2.523 runnerObject/FCounter_17bit[7]
+ SLICE_X88Y71 LUT2 (Prop_lut2_I0_O) 0.301 2.824 r runnerObject/pos_object_y_target6_carry__0_i_1/O
+ net (fo=1, routed) 0.000 2.824 runnerObject/pos_object_y_target6_carry__0_i_1_n_0
+ SLICE_X88Y71 CARRY4 (Prop_carry4_S[3]_CO[3])
+ 0.376 3.200 r runnerObject/pos_object_y_target6_carry__0/CO[3]
+ net (fo=1, routed) 0.000 3.200 runnerObject/pos_object_y_target6_carry__0_n_0
+ SLICE_X88Y72 CARRY4 (Prop_carry4_CI_O[1])
+ 0.323 3.523 f runnerObject/pos_object_y_target6_carry__1/O[1]
+ net (fo=5, routed) 0.953 4.477 runnerObject/pos_object_y_target6[9]
+ SLICE_X82Y72 LUT1 (Prop_lut1_I0_O) 0.306 4.783 r runnerObject/i__carry__1_i_13/O
+ net (fo=1, routed) 0.000 4.783 runnerObject/p_0_in[9]
+ SLICE_X82Y72 CARRY4 (Prop_carry4_S[0]_O[2])
+ 0.547 5.330 f runnerObject/i__carry__1_i_9/O[2]
+ net (fo=2, routed) 0.821 6.151 runnerObject/pos_object_y_target9[11]
+ SLICE_X84Y71 LUT4 (Prop_lut4_I3_O) 0.302 6.453 r runnerObject/pos_object_y_target2_carry_i_13/O
+ net (fo=2, routed) 0.420 6.872 runnerObject/pos_object_y_target2_carry_i_13_n_0
+ SLICE_X87Y72 LUT6 (Prop_lut6_I0_O) 0.124 6.996 r runnerObject/pos_object_y_target2_carry_i_10/O
+ net (fo=34, routed) 1.081 8.077 runnerObject/pos_object_y_target2_carry_i_10_n_0
+ SLICE_X84Y70 LUT6 (Prop_lut6_I3_O) 0.124 8.201 r runnerObject/pos_object_y_target2_carry_i_9/O
+ net (fo=1, routed) 0.701 8.903 runnerObject/pos_object_y_target2_carry_i_9_n_0
+ SLICE_X85Y70 CARRY4 (Prop_carry4_S[0]_O[3])
+ 0.730 9.633 f runnerObject/pos_object_y_target2_carry/O[3]
+ net (fo=2, routed) 1.215 10.847 runnerObject/pos_object_y_target2[4]
+ SLICE_X84Y73 LUT2 (Prop_lut2_I1_O) 0.306 11.153 r runnerObject/pos_object_y_target1_carry_i_4/O
+ net (fo=1, routed) 0.000 11.153 runnerObject/pos_object_y_target1_carry_i_4_n_0
+ SLICE_X84Y73 CARRY4 (Prop_carry4_S[2]_CO[3])
+ 0.380 11.533 r runnerObject/pos_object_y_target1_carry/CO[3]
+ net (fo=1, routed) 0.000 11.533 runnerObject/pos_object_y_target1_carry_n_0
+ SLICE_X84Y74 CARRY4 (Prop_carry4_CI_CO[3])
+ 0.117 11.650 r runnerObject/pos_object_y_target1_carry__0/CO[3]
+ net (fo=1, routed) 0.009 11.659 runnerObject/pos_object_y_target1_carry__0_n_0
+ SLICE_X84Y75 CARRY4 (Prop_carry4_CI_CO[1])
+ 0.157 11.816 f runnerObject/pos_object_y_target1_carry__1/CO[1]
+ net (fo=11, routed) 0.629 12.445 runnerObject/pos_object_y_target1
+ SLICE_X86Y77 LUT3 (Prop_lut3_I0_O) 0.332 12.777 r runnerObject/pos_object_y_target[8]_i_1/O
+ net (fo=9, routed) 0.697 13.474 runnerObject/pos_object_y_target[8]_i_1_n_0
+ SLICE_X89Y79 FDSE r runnerObject/pos_object_y_target_reg[2]/S
+ ------------------------------------------------------------------- -------------------
+
+ (clock clk_out1_clk_wiz_0 rise edge)
+ 40.000 40.000 r
+ E3 0.000 40.000 r clk (IN)
+ net (fo=0) 0.000 40.000 pixelClk/inst/clk_in1
+ E3 IBUF (Prop_ibuf_I_O) 1.411 41.411 r pixelClk/inst/clkin1_ibufg/O
+ net (fo=1, routed) 1.162 42.573 pixelClk/inst/clk_in1_clk_wiz_0
+ MMCME2_ADV_X1Y2 MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKOUT0)
+ -7.324 35.249 r pixelClk/inst/mmcm_adv_inst/CLKOUT0
+ net (fo=1, routed) 1.639 36.888 pixelClk/inst/clk_out1_clk_wiz_0
+ BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.091 36.979 r pixelClk/inst/clkout1_buf/O
+ net (fo=127, routed) 1.601 38.581 runnerObject/clk_out1
+ SLICE_X89Y79 FDSE r runnerObject/pos_object_y_target_reg[2]/C
+ clock pessimism 0.559 39.140
+ clock uncertainty -0.098 39.043
+ SLICE_X89Y79 FDSE (Setup_fdse_C_S) -0.429 38.614 runnerObject/pos_object_y_target_reg[2]
+ -------------------------------------------------------------------
+ required time 38.614
+ arrival time -13.474
+ -------------------------------------------------------------------
+ slack 25.140
+
+Slack (MET) : 25.140ns (required time - arrival time)
+ Source: vgaInterface/counter_f_reg[2]/C
+ (rising edge-triggered cell FDCE clocked by clk_out1_clk_wiz_0 {rise@0.000ns fall@20.000ns period=40.000ns})
+ Destination: runnerObject/pos_object_y_target_reg[3]/S
+ (rising edge-triggered cell FDSE clocked by clk_out1_clk_wiz_0 {rise@0.000ns fall@20.000ns period=40.000ns})
+ Path Group: clk_out1_clk_wiz_0
+ Path Type: Setup (Max at Slow Process Corner)
+ Requirement: 40.000ns (clk_out1_clk_wiz_0 rise@40.000ns - clk_out1_clk_wiz_0 rise@0.000ns)
+ Data Path Delay: 14.294ns (logic 5.777ns (40.414%) route 8.517ns (59.586%))
+ Logic Levels: 17 (CARRY4=9 LUT1=2 LUT2=2 LUT3=1 LUT4=1 LUT6=2)
+ Clock Path Skew: -0.039ns (DCD - SCD + CPR)
+ Destination Clock Delay (DCD): -1.419ns = ( 38.581 - 40.000 )
+ Source Clock Delay (SCD): -0.821ns
+ Clock Pessimism Removal (CPR): 0.559ns
+ Clock Uncertainty: 0.098ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE
+ Total System Jitter (TSJ): 0.071ns
+ Discrete Jitter (DJ): 0.182ns
+ Phase Error (PE): 0.000ns
+
+ Location Delay type Incr(ns) Path(ns) Netlist Resource(s)
+ ------------------------------------------------------------------- -------------------
+ (clock clk_out1_clk_wiz_0 rise edge)
+ 0.000 0.000 r
+ E3 0.000 0.000 r clk (IN)
+ net (fo=0) 0.000 0.000 pixelClk/inst/clk_in1
+ E3 IBUF (Prop_ibuf_I_O) 1.482 1.482 r pixelClk/inst/clkin1_ibufg/O
+ net (fo=1, routed) 1.233 2.715 pixelClk/inst/clk_in1_clk_wiz_0
+ MMCME2_ADV_X1Y2 MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKOUT0)
+ -7.070 -4.355 r pixelClk/inst/mmcm_adv_inst/CLKOUT0
+ net (fo=1, routed) 1.719 -2.636 pixelClk/inst/clk_out1_clk_wiz_0
+ BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.096 -2.540 r pixelClk/inst/clkout1_buf/O
+ net (fo=127, routed) 1.719 -0.821 vgaInterface/clk_out1
+ SLICE_X89Y70 FDCE r vgaInterface/counter_f_reg[2]/C
+ ------------------------------------------------------------------- -------------------
+ SLICE_X89Y70 FDCE (Prop_fdce_C_Q) 0.456 -0.365 f vgaInterface/counter_f_reg[2]/Q
+ net (fo=5, routed) 1.006 0.641 vgaInterface/counter_f_reg[2]
+ SLICE_X88Y67 LUT1 (Prop_lut1_I0_O) 0.124 0.765 r vgaInterface/FCounter_17bit_carry_i_3/O
+ net (fo=1, routed) 0.000 0.765 runnerObject/pos_object_y_target6_carry_0[1]
+ SLICE_X88Y67 CARRY4 (Prop_carry4_S[1]_CO[3])
+ 0.533 1.298 r runnerObject/FCounter_17bit_carry/CO[3]
+ net (fo=1, routed) 0.000 1.298 runnerObject/FCounter_17bit_carry_n_0
+ SLICE_X88Y68 CARRY4 (Prop_carry4_CI_O[2])
+ 0.239 1.537 r runnerObject/FCounter_17bit_carry__0/O[2]
+ net (fo=2, routed) 0.987 2.523 runnerObject/FCounter_17bit[7]
+ SLICE_X88Y71 LUT2 (Prop_lut2_I0_O) 0.301 2.824 r runnerObject/pos_object_y_target6_carry__0_i_1/O
+ net (fo=1, routed) 0.000 2.824 runnerObject/pos_object_y_target6_carry__0_i_1_n_0
+ SLICE_X88Y71 CARRY4 (Prop_carry4_S[3]_CO[3])
+ 0.376 3.200 r runnerObject/pos_object_y_target6_carry__0/CO[3]
+ net (fo=1, routed) 0.000 3.200 runnerObject/pos_object_y_target6_carry__0_n_0
+ SLICE_X88Y72 CARRY4 (Prop_carry4_CI_O[1])
+ 0.323 3.523 f runnerObject/pos_object_y_target6_carry__1/O[1]
+ net (fo=5, routed) 0.953 4.477 runnerObject/pos_object_y_target6[9]
+ SLICE_X82Y72 LUT1 (Prop_lut1_I0_O) 0.306 4.783 r runnerObject/i__carry__1_i_13/O
+ net (fo=1, routed) 0.000 4.783 runnerObject/p_0_in[9]
+ SLICE_X82Y72 CARRY4 (Prop_carry4_S[0]_O[2])
+ 0.547 5.330 f runnerObject/i__carry__1_i_9/O[2]
+ net (fo=2, routed) 0.821 6.151 runnerObject/pos_object_y_target9[11]
+ SLICE_X84Y71 LUT4 (Prop_lut4_I3_O) 0.302 6.453 r runnerObject/pos_object_y_target2_carry_i_13/O
+ net (fo=2, routed) 0.420 6.872 runnerObject/pos_object_y_target2_carry_i_13_n_0
+ SLICE_X87Y72 LUT6 (Prop_lut6_I0_O) 0.124 6.996 r runnerObject/pos_object_y_target2_carry_i_10/O
+ net (fo=34, routed) 1.081 8.077 runnerObject/pos_object_y_target2_carry_i_10_n_0
+ SLICE_X84Y70 LUT6 (Prop_lut6_I3_O) 0.124 8.201 r runnerObject/pos_object_y_target2_carry_i_9/O
+ net (fo=1, routed) 0.701 8.903 runnerObject/pos_object_y_target2_carry_i_9_n_0
+ SLICE_X85Y70 CARRY4 (Prop_carry4_S[0]_O[3])
+ 0.730 9.633 f runnerObject/pos_object_y_target2_carry/O[3]
+ net (fo=2, routed) 1.215 10.847 runnerObject/pos_object_y_target2[4]
+ SLICE_X84Y73 LUT2 (Prop_lut2_I1_O) 0.306 11.153 r runnerObject/pos_object_y_target1_carry_i_4/O
+ net (fo=1, routed) 0.000 11.153 runnerObject/pos_object_y_target1_carry_i_4_n_0
+ SLICE_X84Y73 CARRY4 (Prop_carry4_S[2]_CO[3])
+ 0.380 11.533 r runnerObject/pos_object_y_target1_carry/CO[3]
+ net (fo=1, routed) 0.000 11.533 runnerObject/pos_object_y_target1_carry_n_0
+ SLICE_X84Y74 CARRY4 (Prop_carry4_CI_CO[3])
+ 0.117 11.650 r runnerObject/pos_object_y_target1_carry__0/CO[3]
+ net (fo=1, routed) 0.009 11.659 runnerObject/pos_object_y_target1_carry__0_n_0
+ SLICE_X84Y75 CARRY4 (Prop_carry4_CI_CO[1])
+ 0.157 11.816 f runnerObject/pos_object_y_target1_carry__1/CO[1]
+ net (fo=11, routed) 0.629 12.445 runnerObject/pos_object_y_target1
+ SLICE_X86Y77 LUT3 (Prop_lut3_I0_O) 0.332 12.777 r runnerObject/pos_object_y_target[8]_i_1/O
+ net (fo=9, routed) 0.697 13.474 runnerObject/pos_object_y_target[8]_i_1_n_0
+ SLICE_X89Y79 FDSE r runnerObject/pos_object_y_target_reg[3]/S
+ ------------------------------------------------------------------- -------------------
+
+ (clock clk_out1_clk_wiz_0 rise edge)
+ 40.000 40.000 r
+ E3 0.000 40.000 r clk (IN)
+ net (fo=0) 0.000 40.000 pixelClk/inst/clk_in1
+ E3 IBUF (Prop_ibuf_I_O) 1.411 41.411 r pixelClk/inst/clkin1_ibufg/O
+ net (fo=1, routed) 1.162 42.573 pixelClk/inst/clk_in1_clk_wiz_0
+ MMCME2_ADV_X1Y2 MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKOUT0)
+ -7.324 35.249 r pixelClk/inst/mmcm_adv_inst/CLKOUT0
+ net (fo=1, routed) 1.639 36.888 pixelClk/inst/clk_out1_clk_wiz_0
+ BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.091 36.979 r pixelClk/inst/clkout1_buf/O
+ net (fo=127, routed) 1.601 38.581 runnerObject/clk_out1
+ SLICE_X89Y79 FDSE r runnerObject/pos_object_y_target_reg[3]/C
+ clock pessimism 0.559 39.140
+ clock uncertainty -0.098 39.043
+ SLICE_X89Y79 FDSE (Setup_fdse_C_S) -0.429 38.614 runnerObject/pos_object_y_target_reg[3]
+ -------------------------------------------------------------------
+ required time 38.614
+ arrival time -13.474
+ -------------------------------------------------------------------
+ slack 25.140
+
+Slack (MET) : 25.140ns (required time - arrival time)
+ Source: vgaInterface/counter_f_reg[2]/C
+ (rising edge-triggered cell FDCE clocked by clk_out1_clk_wiz_0 {rise@0.000ns fall@20.000ns period=40.000ns})
+ Destination: runnerObject/pos_object_y_target_reg[4]/S
+ (rising edge-triggered cell FDSE clocked by clk_out1_clk_wiz_0 {rise@0.000ns fall@20.000ns period=40.000ns})
+ Path Group: clk_out1_clk_wiz_0
+ Path Type: Setup (Max at Slow Process Corner)
+ Requirement: 40.000ns (clk_out1_clk_wiz_0 rise@40.000ns - clk_out1_clk_wiz_0 rise@0.000ns)
+ Data Path Delay: 14.294ns (logic 5.777ns (40.414%) route 8.517ns (59.586%))
+ Logic Levels: 17 (CARRY4=9 LUT1=2 LUT2=2 LUT3=1 LUT4=1 LUT6=2)
+ Clock Path Skew: -0.039ns (DCD - SCD + CPR)
+ Destination Clock Delay (DCD): -1.419ns = ( 38.581 - 40.000 )
+ Source Clock Delay (SCD): -0.821ns
+ Clock Pessimism Removal (CPR): 0.559ns
+ Clock Uncertainty: 0.098ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE
+ Total System Jitter (TSJ): 0.071ns
+ Discrete Jitter (DJ): 0.182ns
+ Phase Error (PE): 0.000ns
+
+ Location Delay type Incr(ns) Path(ns) Netlist Resource(s)
+ ------------------------------------------------------------------- -------------------
+ (clock clk_out1_clk_wiz_0 rise edge)
+ 0.000 0.000 r
+ E3 0.000 0.000 r clk (IN)
+ net (fo=0) 0.000 0.000 pixelClk/inst/clk_in1
+ E3 IBUF (Prop_ibuf_I_O) 1.482 1.482 r pixelClk/inst/clkin1_ibufg/O
+ net (fo=1, routed) 1.233 2.715 pixelClk/inst/clk_in1_clk_wiz_0
+ MMCME2_ADV_X1Y2 MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKOUT0)
+ -7.070 -4.355 r pixelClk/inst/mmcm_adv_inst/CLKOUT0
+ net (fo=1, routed) 1.719 -2.636 pixelClk/inst/clk_out1_clk_wiz_0
+ BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.096 -2.540 r pixelClk/inst/clkout1_buf/O
+ net (fo=127, routed) 1.719 -0.821 vgaInterface/clk_out1
+ SLICE_X89Y70 FDCE r vgaInterface/counter_f_reg[2]/C
+ ------------------------------------------------------------------- -------------------
+ SLICE_X89Y70 FDCE (Prop_fdce_C_Q) 0.456 -0.365 f vgaInterface/counter_f_reg[2]/Q
+ net (fo=5, routed) 1.006 0.641 vgaInterface/counter_f_reg[2]
+ SLICE_X88Y67 LUT1 (Prop_lut1_I0_O) 0.124 0.765 r vgaInterface/FCounter_17bit_carry_i_3/O
+ net (fo=1, routed) 0.000 0.765 runnerObject/pos_object_y_target6_carry_0[1]
+ SLICE_X88Y67 CARRY4 (Prop_carry4_S[1]_CO[3])
+ 0.533 1.298 r runnerObject/FCounter_17bit_carry/CO[3]
+ net (fo=1, routed) 0.000 1.298 runnerObject/FCounter_17bit_carry_n_0
+ SLICE_X88Y68 CARRY4 (Prop_carry4_CI_O[2])
+ 0.239 1.537 r runnerObject/FCounter_17bit_carry__0/O[2]
+ net (fo=2, routed) 0.987 2.523 runnerObject/FCounter_17bit[7]
+ SLICE_X88Y71 LUT2 (Prop_lut2_I0_O) 0.301 2.824 r runnerObject/pos_object_y_target6_carry__0_i_1/O
+ net (fo=1, routed) 0.000 2.824 runnerObject/pos_object_y_target6_carry__0_i_1_n_0
+ SLICE_X88Y71 CARRY4 (Prop_carry4_S[3]_CO[3])
+ 0.376 3.200 r runnerObject/pos_object_y_target6_carry__0/CO[3]
+ net (fo=1, routed) 0.000 3.200 runnerObject/pos_object_y_target6_carry__0_n_0
+ SLICE_X88Y72 CARRY4 (Prop_carry4_CI_O[1])
+ 0.323 3.523 f runnerObject/pos_object_y_target6_carry__1/O[1]
+ net (fo=5, routed) 0.953 4.477 runnerObject/pos_object_y_target6[9]
+ SLICE_X82Y72 LUT1 (Prop_lut1_I0_O) 0.306 4.783 r runnerObject/i__carry__1_i_13/O
+ net (fo=1, routed) 0.000 4.783 runnerObject/p_0_in[9]
+ SLICE_X82Y72 CARRY4 (Prop_carry4_S[0]_O[2])
+ 0.547 5.330 f runnerObject/i__carry__1_i_9/O[2]
+ net (fo=2, routed) 0.821 6.151 runnerObject/pos_object_y_target9[11]
+ SLICE_X84Y71 LUT4 (Prop_lut4_I3_O) 0.302 6.453 r runnerObject/pos_object_y_target2_carry_i_13/O
+ net (fo=2, routed) 0.420 6.872 runnerObject/pos_object_y_target2_carry_i_13_n_0
+ SLICE_X87Y72 LUT6 (Prop_lut6_I0_O) 0.124 6.996 r runnerObject/pos_object_y_target2_carry_i_10/O
+ net (fo=34, routed) 1.081 8.077 runnerObject/pos_object_y_target2_carry_i_10_n_0
+ SLICE_X84Y70 LUT6 (Prop_lut6_I3_O) 0.124 8.201 r runnerObject/pos_object_y_target2_carry_i_9/O
+ net (fo=1, routed) 0.701 8.903 runnerObject/pos_object_y_target2_carry_i_9_n_0
+ SLICE_X85Y70 CARRY4 (Prop_carry4_S[0]_O[3])
+ 0.730 9.633 f runnerObject/pos_object_y_target2_carry/O[3]
+ net (fo=2, routed) 1.215 10.847 runnerObject/pos_object_y_target2[4]
+ SLICE_X84Y73 LUT2 (Prop_lut2_I1_O) 0.306 11.153 r runnerObject/pos_object_y_target1_carry_i_4/O
+ net (fo=1, routed) 0.000 11.153 runnerObject/pos_object_y_target1_carry_i_4_n_0
+ SLICE_X84Y73 CARRY4 (Prop_carry4_S[2]_CO[3])
+ 0.380 11.533 r runnerObject/pos_object_y_target1_carry/CO[3]
+ net (fo=1, routed) 0.000 11.533 runnerObject/pos_object_y_target1_carry_n_0
+ SLICE_X84Y74 CARRY4 (Prop_carry4_CI_CO[3])
+ 0.117 11.650 r runnerObject/pos_object_y_target1_carry__0/CO[3]
+ net (fo=1, routed) 0.009 11.659 runnerObject/pos_object_y_target1_carry__0_n_0
+ SLICE_X84Y75 CARRY4 (Prop_carry4_CI_CO[1])
+ 0.157 11.816 f runnerObject/pos_object_y_target1_carry__1/CO[1]
+ net (fo=11, routed) 0.629 12.445 runnerObject/pos_object_y_target1
+ SLICE_X86Y77 LUT3 (Prop_lut3_I0_O) 0.332 12.777 r runnerObject/pos_object_y_target[8]_i_1/O
+ net (fo=9, routed) 0.697 13.474 runnerObject/pos_object_y_target[8]_i_1_n_0
+ SLICE_X89Y79 FDSE r runnerObject/pos_object_y_target_reg[4]/S
+ ------------------------------------------------------------------- -------------------
+
+ (clock clk_out1_clk_wiz_0 rise edge)
+ 40.000 40.000 r
+ E3 0.000 40.000 r clk (IN)
+ net (fo=0) 0.000 40.000 pixelClk/inst/clk_in1
+ E3 IBUF (Prop_ibuf_I_O) 1.411 41.411 r pixelClk/inst/clkin1_ibufg/O
+ net (fo=1, routed) 1.162 42.573 pixelClk/inst/clk_in1_clk_wiz_0
+ MMCME2_ADV_X1Y2 MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKOUT0)
+ -7.324 35.249 r pixelClk/inst/mmcm_adv_inst/CLKOUT0
+ net (fo=1, routed) 1.639 36.888 pixelClk/inst/clk_out1_clk_wiz_0
+ BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.091 36.979 r pixelClk/inst/clkout1_buf/O
+ net (fo=127, routed) 1.601 38.581 runnerObject/clk_out1
+ SLICE_X89Y79 FDSE r runnerObject/pos_object_y_target_reg[4]/C
+ clock pessimism 0.559 39.140
+ clock uncertainty -0.098 39.043
+ SLICE_X89Y79 FDSE (Setup_fdse_C_S) -0.429 38.614 runnerObject/pos_object_y_target_reg[4]
+ -------------------------------------------------------------------
+ required time 38.614
+ arrival time -13.474
+ -------------------------------------------------------------------
+ slack 25.140
+
+
+
+
+
+Min Delay Paths
+--------------------------------------------------------------------------------------
+Slack (MET) : 0.161ns (arrival time - required time)
+ Source: vgaInterface/counter_f_reg[3]/C
+ (rising edge-triggered cell FDCE clocked by clk_out1_clk_wiz_0 {rise@0.000ns fall@20.000ns period=40.000ns})
+ Destination: runnerObject/fcount_edge_reg[3]/D
+ (rising edge-triggered cell FDCE clocked by clk_out1_clk_wiz_0 {rise@0.000ns fall@20.000ns period=40.000ns})
+ Path Group: clk_out1_clk_wiz_0
+ Path Type: Hold (Min at Fast Process Corner)
+ Requirement: 0.000ns (clk_out1_clk_wiz_0 rise@0.000ns - clk_out1_clk_wiz_0 rise@0.000ns)
+ Data Path Delay: 0.257ns (logic 0.141ns (54.962%) route 0.116ns (45.038%))
+ Logic Levels: 0
+ Clock Path Skew: 0.013ns (DCD - SCD - CPR)
+ Destination Clock Delay (DCD): -0.805ns
+ Source Clock Delay (SCD): -0.566ns
+ Clock Pessimism Removal (CPR): -0.252ns
+
+ Location Delay type Incr(ns) Path(ns) Netlist Resource(s)
+ ------------------------------------------------------------------- -------------------
+ (clock clk_out1_clk_wiz_0 rise edge)
+ 0.000 0.000 r
+ E3 0.000 0.000 r clk (IN)
+ net (fo=0) 0.000 0.000 pixelClk/inst/clk_in1
+ E3 IBUF (Prop_ibuf_I_O) 0.250 0.250 r pixelClk/inst/clkin1_ibufg/O
+ net (fo=1, routed) 0.440 0.690 pixelClk/inst/clk_in1_clk_wiz_0
+ MMCME2_ADV_X1Y2 MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKOUT0)
+ -2.379 -1.689 r pixelClk/inst/mmcm_adv_inst/CLKOUT0
+ net (fo=1, routed) 0.499 -1.190 pixelClk/inst/clk_out1_clk_wiz_0
+ BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.026 -1.164 r pixelClk/inst/clkout1_buf/O
+ net (fo=127, routed) 0.598 -0.566 vgaInterface/clk_out1
+ SLICE_X89Y70 FDCE r vgaInterface/counter_f_reg[3]/C
+ ------------------------------------------------------------------- -------------------
+ SLICE_X89Y70 FDCE (Prop_fdce_C_Q) 0.141 -0.425 r vgaInterface/counter_f_reg[3]/Q
+ net (fo=5, routed) 0.116 -0.310 runnerObject/counter_f_reg[3]
+ SLICE_X88Y70 FDCE r runnerObject/fcount_edge_reg[3]/D
+ ------------------------------------------------------------------- -------------------
+
+ (clock clk_out1_clk_wiz_0 rise edge)
+ 0.000 0.000 r
+ E3 0.000 0.000 r clk (IN)
+ net (fo=0) 0.000 0.000 pixelClk/inst/clk_in1
+ E3 IBUF (Prop_ibuf_I_O) 0.438 0.438 r pixelClk/inst/clkin1_ibufg/O
+ net (fo=1, routed) 0.480 0.918 pixelClk/inst/clk_in1_clk_wiz_0
+ MMCME2_ADV_X1Y2 MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKOUT0)
+ -3.163 -2.245 r pixelClk/inst/mmcm_adv_inst/CLKOUT0
+ net (fo=1, routed) 0.544 -1.702 pixelClk/inst/clk_out1_clk_wiz_0
+ BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.029 -1.673 r pixelClk/inst/clkout1_buf/O
+ net (fo=127, routed) 0.868 -0.805 runnerObject/clk_out1
+ SLICE_X88Y70 FDCE r runnerObject/fcount_edge_reg[3]/C
+ clock pessimism 0.252 -0.553
+ SLICE_X88Y70 FDCE (Hold_fdce_C_D) 0.083 -0.470 runnerObject/fcount_edge_reg[3]
+ -------------------------------------------------------------------
+ required time 0.470
+ arrival time -0.310
+ -------------------------------------------------------------------
+ slack 0.161
+
+Slack (MET) : 0.161ns (arrival time - required time)
+ Source: vgaInterface/counter_f_reg[7]/C
+ (rising edge-triggered cell FDCE clocked by clk_out1_clk_wiz_0 {rise@0.000ns fall@20.000ns period=40.000ns})
+ Destination: runnerObject/fcount_edge_reg[7]/D
+ (rising edge-triggered cell FDCE clocked by clk_out1_clk_wiz_0 {rise@0.000ns fall@20.000ns period=40.000ns})
+ Path Group: clk_out1_clk_wiz_0
+ Path Type: Hold (Min at Fast Process Corner)
+ Requirement: 0.000ns (clk_out1_clk_wiz_0 rise@0.000ns - clk_out1_clk_wiz_0 rise@0.000ns)
+ Data Path Delay: 0.257ns (logic 0.141ns (54.948%) route 0.116ns (45.052%))
+ Logic Levels: 0
+ Clock Path Skew: 0.013ns (DCD - SCD - CPR)
+ Destination Clock Delay (DCD): -0.806ns
+ Source Clock Delay (SCD): -0.567ns
+ Clock Pessimism Removal (CPR): -0.252ns
+
+ Location Delay type Incr(ns) Path(ns) Netlist Resource(s)
+ ------------------------------------------------------------------- -------------------
+ (clock clk_out1_clk_wiz_0 rise edge)
+ 0.000 0.000 r
+ E3 0.000 0.000 r clk (IN)
+ net (fo=0) 0.000 0.000 pixelClk/inst/clk_in1
+ E3 IBUF (Prop_ibuf_I_O) 0.250 0.250 r pixelClk/inst/clkin1_ibufg/O
+ net (fo=1, routed) 0.440 0.690 pixelClk/inst/clk_in1_clk_wiz_0
+ MMCME2_ADV_X1Y2 MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKOUT0)
+ -2.379 -1.689 r pixelClk/inst/mmcm_adv_inst/CLKOUT0
+ net (fo=1, routed) 0.499 -1.190 pixelClk/inst/clk_out1_clk_wiz_0
+ BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.026 -1.164 r pixelClk/inst/clkout1_buf/O
+ net (fo=127, routed) 0.597 -0.567 vgaInterface/clk_out1
+ SLICE_X89Y71 FDCE r vgaInterface/counter_f_reg[7]/C
+ ------------------------------------------------------------------- -------------------
+ SLICE_X89Y71 FDCE (Prop_fdce_C_Q) 0.141 -0.426 r vgaInterface/counter_f_reg[7]/Q
+ net (fo=5, routed) 0.116 -0.311 runnerObject/counter_f_reg[7]
+ SLICE_X88Y71 FDCE r runnerObject/fcount_edge_reg[7]/D
+ ------------------------------------------------------------------- -------------------
+
+ (clock clk_out1_clk_wiz_0 rise edge)
+ 0.000 0.000 r
+ E3 0.000 0.000 r clk (IN)
+ net (fo=0) 0.000 0.000 pixelClk/inst/clk_in1
+ E3 IBUF (Prop_ibuf_I_O) 0.438 0.438 r pixelClk/inst/clkin1_ibufg/O
+ net (fo=1, routed) 0.480 0.918 pixelClk/inst/clk_in1_clk_wiz_0
+ MMCME2_ADV_X1Y2 MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKOUT0)
+ -3.163 -2.245 r pixelClk/inst/mmcm_adv_inst/CLKOUT0
+ net (fo=1, routed) 0.544 -1.702 pixelClk/inst/clk_out1_clk_wiz_0
+ BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.029 -1.673 r pixelClk/inst/clkout1_buf/O
+ net (fo=127, routed) 0.867 -0.806 runnerObject/clk_out1
+ SLICE_X88Y71 FDCE r runnerObject/fcount_edge_reg[7]/C
+ clock pessimism 0.252 -0.554
+ SLICE_X88Y71 FDCE (Hold_fdce_C_D) 0.083 -0.471 runnerObject/fcount_edge_reg[7]
+ -------------------------------------------------------------------
+ required time 0.471
+ arrival time -0.311
+ -------------------------------------------------------------------
+ slack 0.161
+
+Slack (MET) : 0.166ns (arrival time - required time)
+ Source: vgaInterface/counter_f_reg[4]/C
+ (rising edge-triggered cell FDCE clocked by clk_out1_clk_wiz_0 {rise@0.000ns fall@20.000ns period=40.000ns})
+ Destination: runnerObject/fcount_edge_reg[4]/D
+ (rising edge-triggered cell FDCE clocked by clk_out1_clk_wiz_0 {rise@0.000ns fall@20.000ns period=40.000ns})
+ Path Group: clk_out1_clk_wiz_0
+ Path Type: Hold (Min at Fast Process Corner)
+ Requirement: 0.000ns (clk_out1_clk_wiz_0 rise@0.000ns - clk_out1_clk_wiz_0 rise@0.000ns)
+ Data Path Delay: 0.264ns (logic 0.141ns (53.502%) route 0.123ns (46.498%))
+ Logic Levels: 0
+ Clock Path Skew: 0.013ns (DCD - SCD - CPR)
+ Destination Clock Delay (DCD): -0.806ns
+ Source Clock Delay (SCD): -0.567ns
+ Clock Pessimism Removal (CPR): -0.252ns
+
+ Location Delay type Incr(ns) Path(ns) Netlist Resource(s)
+ ------------------------------------------------------------------- -------------------
+ (clock clk_out1_clk_wiz_0 rise edge)
+ 0.000 0.000 r
+ E3 0.000 0.000 r clk (IN)
+ net (fo=0) 0.000 0.000 pixelClk/inst/clk_in1
+ E3 IBUF (Prop_ibuf_I_O) 0.250 0.250 r pixelClk/inst/clkin1_ibufg/O
+ net (fo=1, routed) 0.440 0.690 pixelClk/inst/clk_in1_clk_wiz_0
+ MMCME2_ADV_X1Y2 MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKOUT0)
+ -2.379 -1.689 r pixelClk/inst/mmcm_adv_inst/CLKOUT0
+ net (fo=1, routed) 0.499 -1.190 pixelClk/inst/clk_out1_clk_wiz_0
+ BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.026 -1.164 r pixelClk/inst/clkout1_buf/O
+ net (fo=127, routed) 0.597 -0.567 vgaInterface/clk_out1
+ SLICE_X89Y71 FDCE r vgaInterface/counter_f_reg[4]/C
+ ------------------------------------------------------------------- -------------------
+ SLICE_X89Y71 FDCE (Prop_fdce_C_Q) 0.141 -0.426 r vgaInterface/counter_f_reg[4]/Q
+ net (fo=5, routed) 0.123 -0.304 runnerObject/counter_f_reg[4]
+ SLICE_X88Y71 FDCE r runnerObject/fcount_edge_reg[4]/D
+ ------------------------------------------------------------------- -------------------
+
+ (clock clk_out1_clk_wiz_0 rise edge)
+ 0.000 0.000 r
+ E3 0.000 0.000 r clk (IN)
+ net (fo=0) 0.000 0.000 pixelClk/inst/clk_in1
+ E3 IBUF (Prop_ibuf_I_O) 0.438 0.438 r pixelClk/inst/clkin1_ibufg/O
+ net (fo=1, routed) 0.480 0.918 pixelClk/inst/clk_in1_clk_wiz_0
+ MMCME2_ADV_X1Y2 MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKOUT0)
+ -3.163 -2.245 r pixelClk/inst/mmcm_adv_inst/CLKOUT0
+ net (fo=1, routed) 0.544 -1.702 pixelClk/inst/clk_out1_clk_wiz_0
+ BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.029 -1.673 r pixelClk/inst/clkout1_buf/O
+ net (fo=127, routed) 0.867 -0.806 runnerObject/clk_out1
+ SLICE_X88Y71 FDCE r runnerObject/fcount_edge_reg[4]/C
+ clock pessimism 0.252 -0.554
+ SLICE_X88Y71 FDCE (Hold_fdce_C_D) 0.085 -0.469 runnerObject/fcount_edge_reg[4]
+ -------------------------------------------------------------------
+ required time 0.469
+ arrival time -0.304
+ -------------------------------------------------------------------
+ slack 0.166
+
+Slack (MET) : 0.179ns (arrival time - required time)
+ Source: runnerObject/pos_object_y_target_reg[4]/C
+ (rising edge-triggered cell FDSE clocked by clk_out1_clk_wiz_0 {rise@0.000ns fall@20.000ns period=40.000ns})
+ Destination: runnerObject/pos_object_y_actual_reg[4]/D
+ (rising edge-triggered cell FDRE clocked by clk_out1_clk_wiz_0 {rise@0.000ns fall@20.000ns period=40.000ns})
+ Path Group: clk_out1_clk_wiz_0
+ Path Type: Hold (Min at Fast Process Corner)
+ Requirement: 0.000ns (clk_out1_clk_wiz_0 rise@0.000ns - clk_out1_clk_wiz_0 rise@0.000ns)
+ Data Path Delay: 0.263ns (logic 0.141ns (53.569%) route 0.122ns (46.431%))
+ Logic Levels: 0
+ Clock Path Skew: 0.014ns (DCD - SCD - CPR)
+ Destination Clock Delay (DCD): -0.805ns
+ Source Clock Delay (SCD): -0.566ns
+ Clock Pessimism Removal (CPR): -0.253ns
+
+ Location Delay type Incr(ns) Path(ns) Netlist Resource(s)
+ ------------------------------------------------------------------- -------------------
+ (clock clk_out1_clk_wiz_0 rise edge)
+ 0.000 0.000 r
+ E3 0.000 0.000 r clk (IN)
+ net (fo=0) 0.000 0.000 pixelClk/inst/clk_in1
+ E3 IBUF (Prop_ibuf_I_O) 0.250 0.250 r pixelClk/inst/clkin1_ibufg/O
+ net (fo=1, routed) 0.440 0.690 pixelClk/inst/clk_in1_clk_wiz_0
+ MMCME2_ADV_X1Y2 MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKOUT0)
+ -2.379 -1.689 r pixelClk/inst/mmcm_adv_inst/CLKOUT0
+ net (fo=1, routed) 0.499 -1.190 pixelClk/inst/clk_out1_clk_wiz_0
+ BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.026 -1.164 r pixelClk/inst/clkout1_buf/O
+ net (fo=127, routed) 0.598 -0.566 runnerObject/clk_out1
+ SLICE_X89Y79 FDSE r runnerObject/pos_object_y_target_reg[4]/C
+ ------------------------------------------------------------------- -------------------
+ SLICE_X89Y79 FDSE (Prop_fdse_C_Q) 0.141 -0.425 r runnerObject/pos_object_y_target_reg[4]/Q
+ net (fo=4, routed) 0.122 -0.303 runnerObject/pos_object_y_target[4]
+ SLICE_X87Y79 FDRE r runnerObject/pos_object_y_actual_reg[4]/D
+ ------------------------------------------------------------------- -------------------
+
+ (clock clk_out1_clk_wiz_0 rise edge)
+ 0.000 0.000 r
+ E3 0.000 0.000 r clk (IN)
+ net (fo=0) 0.000 0.000 pixelClk/inst/clk_in1
+ E3 IBUF (Prop_ibuf_I_O) 0.438 0.438 r pixelClk/inst/clkin1_ibufg/O
+ net (fo=1, routed) 0.480 0.918 pixelClk/inst/clk_in1_clk_wiz_0
+ MMCME2_ADV_X1Y2 MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKOUT0)
+ -3.163 -2.245 r pixelClk/inst/mmcm_adv_inst/CLKOUT0
+ net (fo=1, routed) 0.544 -1.702 pixelClk/inst/clk_out1_clk_wiz_0
+ BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.029 -1.673 r pixelClk/inst/clkout1_buf/O
+ net (fo=127, routed) 0.868 -0.805 runnerObject/clk_out1
+ SLICE_X87Y79 FDRE r runnerObject/pos_object_y_actual_reg[4]/C
+ clock pessimism 0.253 -0.552
+ SLICE_X87Y79 FDRE (Hold_fdre_C_D) 0.070 -0.482 runnerObject/pos_object_y_actual_reg[4]
+ -------------------------------------------------------------------
+ required time 0.482
+ arrival time -0.303
+ -------------------------------------------------------------------
+ slack 0.179
+
+Slack (MET) : 0.189ns (arrival time - required time)
+ Source: largeObstacle/pos_object_x_target_reg[0]/C
+ (rising edge-triggered cell FDCE clocked by clk_out1_clk_wiz_0 {rise@0.000ns fall@20.000ns period=40.000ns})
+ Destination: largeObstacle/pos_object_x_actual_reg[0]/D
+ (rising edge-triggered cell FDRE clocked by clk_out1_clk_wiz_0 {rise@0.000ns fall@20.000ns period=40.000ns})
+ Path Group: clk_out1_clk_wiz_0
+ Path Type: Hold (Min at Fast Process Corner)
+ Requirement: 0.000ns (clk_out1_clk_wiz_0 rise@0.000ns - clk_out1_clk_wiz_0 rise@0.000ns)
+ Data Path Delay: 0.272ns (logic 0.141ns (51.925%) route 0.131ns (48.075%))
+ Logic Levels: 0
+ Clock Path Skew: 0.013ns (DCD - SCD - CPR)
+ Destination Clock Delay (DCD): -0.805ns
+ Source Clock Delay (SCD): -0.565ns
+ Clock Pessimism Removal (CPR): -0.253ns
+
+ Location Delay type Incr(ns) Path(ns) Netlist Resource(s)
+ ------------------------------------------------------------------- -------------------
+ (clock clk_out1_clk_wiz_0 rise edge)
+ 0.000 0.000 r
+ E3 0.000 0.000 r clk (IN)
+ net (fo=0) 0.000 0.000 pixelClk/inst/clk_in1
+ E3 IBUF (Prop_ibuf_I_O) 0.250 0.250 r pixelClk/inst/clkin1_ibufg/O
+ net (fo=1, routed) 0.440 0.690 pixelClk/inst/clk_in1_clk_wiz_0
+ MMCME2_ADV_X1Y2 MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKOUT0)
+ -2.379 -1.689 r pixelClk/inst/mmcm_adv_inst/CLKOUT0
+ net (fo=1, routed) 0.499 -1.190 pixelClk/inst/clk_out1_clk_wiz_0
+ BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.026 -1.164 r pixelClk/inst/clkout1_buf/O
+ net (fo=127, routed) 0.599 -0.565 largeObstacle/CLK
+ SLICE_X82Y81 FDCE r largeObstacle/pos_object_x_target_reg[0]/C
+ ------------------------------------------------------------------- -------------------
+ SLICE_X82Y81 FDCE (Prop_fdce_C_Q) 0.141 -0.424 r largeObstacle/pos_object_x_target_reg[0]/Q
+ net (fo=2, routed) 0.131 -0.294 largeObstacle/pos_object_x_target_reg[0]
+ SLICE_X82Y80 FDRE r largeObstacle/pos_object_x_actual_reg[0]/D
+ ------------------------------------------------------------------- -------------------
+
+ (clock clk_out1_clk_wiz_0 rise edge)
+ 0.000 0.000 r
+ E3 0.000 0.000 r clk (IN)
+ net (fo=0) 0.000 0.000 pixelClk/inst/clk_in1
+ E3 IBUF (Prop_ibuf_I_O) 0.438 0.438 r pixelClk/inst/clkin1_ibufg/O
+ net (fo=1, routed) 0.480 0.918 pixelClk/inst/clk_in1_clk_wiz_0
+ MMCME2_ADV_X1Y2 MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKOUT0)
+ -3.163 -2.245 r pixelClk/inst/mmcm_adv_inst/CLKOUT0
+ net (fo=1, routed) 0.544 -1.702 pixelClk/inst/clk_out1_clk_wiz_0
+ BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.029 -1.673 r pixelClk/inst/clkout1_buf/O
+ net (fo=127, routed) 0.868 -0.805 largeObstacle/CLK
+ SLICE_X82Y80 FDRE r largeObstacle/pos_object_x_actual_reg[0]/C
+ clock pessimism 0.253 -0.552
+ SLICE_X82Y80 FDRE (Hold_fdre_C_D) 0.070 -0.482 largeObstacle/pos_object_x_actual_reg[0]
+ -------------------------------------------------------------------
+ required time 0.482
+ arrival time -0.294
+ -------------------------------------------------------------------
+ slack 0.189
+
+Slack (MET) : 0.198ns (arrival time - required time)
+ Source: runnerObject/pos_object_y_target_reg[2]/C
+ (rising edge-triggered cell FDSE clocked by clk_out1_clk_wiz_0 {rise@0.000ns fall@20.000ns period=40.000ns})
+ Destination: runnerObject/pos_object_y_actual_reg[2]/D
+ (rising edge-triggered cell FDRE clocked by clk_out1_clk_wiz_0 {rise@0.000ns fall@20.000ns period=40.000ns})
+ Path Group: clk_out1_clk_wiz_0
+ Path Type: Hold (Min at Fast Process Corner)
+ Requirement: 0.000ns (clk_out1_clk_wiz_0 rise@0.000ns - clk_out1_clk_wiz_0 rise@0.000ns)
+ Data Path Delay: 0.282ns (logic 0.141ns (49.964%) route 0.141ns (50.036%))
+ Logic Levels: 0
+ Clock Path Skew: 0.014ns (DCD - SCD - CPR)
+ Destination Clock Delay (DCD): -0.805ns
+ Source Clock Delay (SCD): -0.566ns
+ Clock Pessimism Removal (CPR): -0.253ns
+
+ Location Delay type Incr(ns) Path(ns) Netlist Resource(s)
+ ------------------------------------------------------------------- -------------------
+ (clock clk_out1_clk_wiz_0 rise edge)
+ 0.000 0.000 r
+ E3 0.000 0.000 r clk (IN)
+ net (fo=0) 0.000 0.000 pixelClk/inst/clk_in1
+ E3 IBUF (Prop_ibuf_I_O) 0.250 0.250 r pixelClk/inst/clkin1_ibufg/O
+ net (fo=1, routed) 0.440 0.690 pixelClk/inst/clk_in1_clk_wiz_0
+ MMCME2_ADV_X1Y2 MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKOUT0)
+ -2.379 -1.689 r pixelClk/inst/mmcm_adv_inst/CLKOUT0
+ net (fo=1, routed) 0.499 -1.190 pixelClk/inst/clk_out1_clk_wiz_0
+ BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.026 -1.164 r pixelClk/inst/clkout1_buf/O
+ net (fo=127, routed) 0.598 -0.566 runnerObject/clk_out1
+ SLICE_X89Y79 FDSE r runnerObject/pos_object_y_target_reg[2]/C
+ ------------------------------------------------------------------- -------------------
+ SLICE_X89Y79 FDSE (Prop_fdse_C_Q) 0.141 -0.425 r runnerObject/pos_object_y_target_reg[2]/Q
+ net (fo=6, routed) 0.141 -0.284 runnerObject/pos_object_y_target[2]
+ SLICE_X86Y79 FDRE r runnerObject/pos_object_y_actual_reg[2]/D
+ ------------------------------------------------------------------- -------------------
+
+ (clock clk_out1_clk_wiz_0 rise edge)
+ 0.000 0.000 r
+ E3 0.000 0.000 r clk (IN)
+ net (fo=0) 0.000 0.000 pixelClk/inst/clk_in1
+ E3 IBUF (Prop_ibuf_I_O) 0.438 0.438 r pixelClk/inst/clkin1_ibufg/O
+ net (fo=1, routed) 0.480 0.918 pixelClk/inst/clk_in1_clk_wiz_0
+ MMCME2_ADV_X1Y2 MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKOUT0)
+ -3.163 -2.245 r pixelClk/inst/mmcm_adv_inst/CLKOUT0
+ net (fo=1, routed) 0.544 -1.702 pixelClk/inst/clk_out1_clk_wiz_0
+ BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.029 -1.673 r pixelClk/inst/clkout1_buf/O
+ net (fo=127, routed) 0.868 -0.805 runnerObject/clk_out1
+ SLICE_X86Y79 FDRE r runnerObject/pos_object_y_actual_reg[2]/C
+ clock pessimism 0.253 -0.552
+ SLICE_X86Y79 FDRE (Hold_fdre_C_D) 0.070 -0.482 runnerObject/pos_object_y_actual_reg[2]
+ -------------------------------------------------------------------
+ required time 0.482
+ arrival time -0.284
+ -------------------------------------------------------------------
+ slack 0.198
+
+Slack (MET) : 0.201ns (arrival time - required time)
+ Source: runnerObject/pos_object_y_target_reg[0]/C
+ (rising edge-triggered cell FDRE clocked by clk_out1_clk_wiz_0 {rise@0.000ns fall@20.000ns period=40.000ns})
+ Destination: runnerObject/pos_object_y_actual_reg[0]/D
+ (rising edge-triggered cell FDRE clocked by clk_out1_clk_wiz_0 {rise@0.000ns fall@20.000ns period=40.000ns})
+ Path Group: clk_out1_clk_wiz_0
+ Path Type: Hold (Min at Fast Process Corner)
+ Requirement: 0.000ns (clk_out1_clk_wiz_0 rise@0.000ns - clk_out1_clk_wiz_0 rise@0.000ns)
+ Data Path Delay: 0.285ns (logic 0.141ns (49.436%) route 0.144ns (50.564%))
+ Logic Levels: 0
+ Clock Path Skew: 0.014ns (DCD - SCD - CPR)
+ Destination Clock Delay (DCD): -0.805ns
+ Source Clock Delay (SCD): -0.566ns
+ Clock Pessimism Removal (CPR): -0.253ns
+
+ Location Delay type Incr(ns) Path(ns) Netlist Resource(s)
+ ------------------------------------------------------------------- -------------------
+ (clock clk_out1_clk_wiz_0 rise edge)
+ 0.000 0.000 r
+ E3 0.000 0.000 r clk (IN)
+ net (fo=0) 0.000 0.000 pixelClk/inst/clk_in1
+ E3 IBUF (Prop_ibuf_I_O) 0.250 0.250 r pixelClk/inst/clkin1_ibufg/O
+ net (fo=1, routed) 0.440 0.690 pixelClk/inst/clk_in1_clk_wiz_0
+ MMCME2_ADV_X1Y2 MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKOUT0)
+ -2.379 -1.689 r pixelClk/inst/mmcm_adv_inst/CLKOUT0
+ net (fo=1, routed) 0.499 -1.190 pixelClk/inst/clk_out1_clk_wiz_0
+ BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.026 -1.164 r pixelClk/inst/clkout1_buf/O
+ net (fo=127, routed) 0.598 -0.566 runnerObject/clk_out1
+ SLICE_X89Y79 FDRE r runnerObject/pos_object_y_target_reg[0]/C
+ ------------------------------------------------------------------- -------------------
+ SLICE_X89Y79 FDRE (Prop_fdre_C_Q) 0.141 -0.425 r runnerObject/pos_object_y_target_reg[0]/Q
+ net (fo=8, routed) 0.144 -0.281 runnerObject/pos_object_y_target[0]
+ SLICE_X87Y79 FDRE r runnerObject/pos_object_y_actual_reg[0]/D
+ ------------------------------------------------------------------- -------------------
+
+ (clock clk_out1_clk_wiz_0 rise edge)
+ 0.000 0.000 r
+ E3 0.000 0.000 r clk (IN)
+ net (fo=0) 0.000 0.000 pixelClk/inst/clk_in1
+ E3 IBUF (Prop_ibuf_I_O) 0.438 0.438 r pixelClk/inst/clkin1_ibufg/O
+ net (fo=1, routed) 0.480 0.918 pixelClk/inst/clk_in1_clk_wiz_0
+ MMCME2_ADV_X1Y2 MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKOUT0)
+ -3.163 -2.245 r pixelClk/inst/mmcm_adv_inst/CLKOUT0
+ net (fo=1, routed) 0.544 -1.702 pixelClk/inst/clk_out1_clk_wiz_0
+ BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.029 -1.673 r pixelClk/inst/clkout1_buf/O
+ net (fo=127, routed) 0.868 -0.805 runnerObject/clk_out1
+ SLICE_X87Y79 FDRE r runnerObject/pos_object_y_actual_reg[0]/C
+ clock pessimism 0.253 -0.552
+ SLICE_X87Y79 FDRE (Hold_fdre_C_D) 0.070 -0.482 runnerObject/pos_object_y_actual_reg[0]
+ -------------------------------------------------------------------
+ required time 0.482
+ arrival time -0.281
+ -------------------------------------------------------------------
+ slack 0.201
+
+Slack (MET) : 0.204ns (arrival time - required time)
+ Source: vgaInterface/counter_f_reg[1]/C
+ (rising edge-triggered cell FDCE clocked by clk_out1_clk_wiz_0 {rise@0.000ns fall@20.000ns period=40.000ns})
+ Destination: runnerObject/fcount_edge_reg[1]/D
+ (rising edge-triggered cell FDCE clocked by clk_out1_clk_wiz_0 {rise@0.000ns fall@20.000ns period=40.000ns})
+ Path Group: clk_out1_clk_wiz_0
+ Path Type: Hold (Min at Fast Process Corner)
+ Requirement: 0.000ns (clk_out1_clk_wiz_0 rise@0.000ns - clk_out1_clk_wiz_0 rise@0.000ns)
+ Data Path Delay: 0.303ns (logic 0.141ns (46.482%) route 0.162ns (53.518%))
+ Logic Levels: 0
+ Clock Path Skew: 0.013ns (DCD - SCD - CPR)
+ Destination Clock Delay (DCD): -0.805ns
+ Source Clock Delay (SCD): -0.566ns
+ Clock Pessimism Removal (CPR): -0.252ns
+
+ Location Delay type Incr(ns) Path(ns) Netlist Resource(s)
+ ------------------------------------------------------------------- -------------------
+ (clock clk_out1_clk_wiz_0 rise edge)
+ 0.000 0.000 r
+ E3 0.000 0.000 r clk (IN)
+ net (fo=0) 0.000 0.000 pixelClk/inst/clk_in1
+ E3 IBUF (Prop_ibuf_I_O) 0.250 0.250 r pixelClk/inst/clkin1_ibufg/O
+ net (fo=1, routed) 0.440 0.690 pixelClk/inst/clk_in1_clk_wiz_0
+ MMCME2_ADV_X1Y2 MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKOUT0)
+ -2.379 -1.689 r pixelClk/inst/mmcm_adv_inst/CLKOUT0
+ net (fo=1, routed) 0.499 -1.190 pixelClk/inst/clk_out1_clk_wiz_0
+ BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.026 -1.164 r pixelClk/inst/clkout1_buf/O
+ net (fo=127, routed) 0.598 -0.566 vgaInterface/clk_out1
+ SLICE_X89Y70 FDCE r vgaInterface/counter_f_reg[1]/C
+ ------------------------------------------------------------------- -------------------
+ SLICE_X89Y70 FDCE (Prop_fdce_C_Q) 0.141 -0.425 r vgaInterface/counter_f_reg[1]/Q
+ net (fo=5, routed) 0.162 -0.263 runnerObject/counter_f_reg[1]
+ SLICE_X88Y70 FDCE r runnerObject/fcount_edge_reg[1]/D
+ ------------------------------------------------------------------- -------------------
+
+ (clock clk_out1_clk_wiz_0 rise edge)
+ 0.000 0.000 r
+ E3 0.000 0.000 r clk (IN)
+ net (fo=0) 0.000 0.000 pixelClk/inst/clk_in1
+ E3 IBUF (Prop_ibuf_I_O) 0.438 0.438 r pixelClk/inst/clkin1_ibufg/O
+ net (fo=1, routed) 0.480 0.918 pixelClk/inst/clk_in1_clk_wiz_0
+ MMCME2_ADV_X1Y2 MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKOUT0)
+ -3.163 -2.245 r pixelClk/inst/mmcm_adv_inst/CLKOUT0
+ net (fo=1, routed) 0.544 -1.702 pixelClk/inst/clk_out1_clk_wiz_0
+ BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.029 -1.673 r pixelClk/inst/clkout1_buf/O
+ net (fo=127, routed) 0.868 -0.805 runnerObject/clk_out1
+ SLICE_X88Y70 FDCE r runnerObject/fcount_edge_reg[1]/C
+ clock pessimism 0.252 -0.553
+ SLICE_X88Y70 FDCE (Hold_fdce_C_D) 0.086 -0.467 runnerObject/fcount_edge_reg[1]
+ -------------------------------------------------------------------
+ required time 0.467
+ arrival time -0.263
+ -------------------------------------------------------------------
+ slack 0.204
+
+Slack (MET) : 0.204ns (arrival time - required time)
+ Source: vgaInterface/counter_f_reg[5]/C
+ (rising edge-triggered cell FDCE clocked by clk_out1_clk_wiz_0 {rise@0.000ns fall@20.000ns period=40.000ns})
+ Destination: runnerObject/fcount_edge_reg[5]/D
+ (rising edge-triggered cell FDCE clocked by clk_out1_clk_wiz_0 {rise@0.000ns fall@20.000ns period=40.000ns})
+ Path Group: clk_out1_clk_wiz_0
+ Path Type: Hold (Min at Fast Process Corner)
+ Requirement: 0.000ns (clk_out1_clk_wiz_0 rise@0.000ns - clk_out1_clk_wiz_0 rise@0.000ns)
+ Data Path Delay: 0.303ns (logic 0.141ns (46.472%) route 0.162ns (53.528%))
+ Logic Levels: 0
+ Clock Path Skew: 0.013ns (DCD - SCD - CPR)
+ Destination Clock Delay (DCD): -0.806ns
+ Source Clock Delay (SCD): -0.567ns
+ Clock Pessimism Removal (CPR): -0.252ns
+
+ Location Delay type Incr(ns) Path(ns) Netlist Resource(s)
+ ------------------------------------------------------------------- -------------------
+ (clock clk_out1_clk_wiz_0 rise edge)
+ 0.000 0.000 r
+ E3 0.000 0.000 r clk (IN)
+ net (fo=0) 0.000 0.000 pixelClk/inst/clk_in1
+ E3 IBUF (Prop_ibuf_I_O) 0.250 0.250 r pixelClk/inst/clkin1_ibufg/O
+ net (fo=1, routed) 0.440 0.690 pixelClk/inst/clk_in1_clk_wiz_0
+ MMCME2_ADV_X1Y2 MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKOUT0)
+ -2.379 -1.689 r pixelClk/inst/mmcm_adv_inst/CLKOUT0
+ net (fo=1, routed) 0.499 -1.190 pixelClk/inst/clk_out1_clk_wiz_0
+ BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.026 -1.164 r pixelClk/inst/clkout1_buf/O
+ net (fo=127, routed) 0.597 -0.567 vgaInterface/clk_out1
+ SLICE_X89Y71 FDCE r vgaInterface/counter_f_reg[5]/C
+ ------------------------------------------------------------------- -------------------
+ SLICE_X89Y71 FDCE (Prop_fdce_C_Q) 0.141 -0.426 r vgaInterface/counter_f_reg[5]/Q
+ net (fo=5, routed) 0.162 -0.264 runnerObject/counter_f_reg[5]
+ SLICE_X88Y71 FDCE r runnerObject/fcount_edge_reg[5]/D
+ ------------------------------------------------------------------- -------------------
+
+ (clock clk_out1_clk_wiz_0 rise edge)
+ 0.000 0.000 r
+ E3 0.000 0.000 r clk (IN)
+ net (fo=0) 0.000 0.000 pixelClk/inst/clk_in1
+ E3 IBUF (Prop_ibuf_I_O) 0.438 0.438 r pixelClk/inst/clkin1_ibufg/O
+ net (fo=1, routed) 0.480 0.918 pixelClk/inst/clk_in1_clk_wiz_0
+ MMCME2_ADV_X1Y2 MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKOUT0)
+ -3.163 -2.245 r pixelClk/inst/mmcm_adv_inst/CLKOUT0
+ net (fo=1, routed) 0.544 -1.702 pixelClk/inst/clk_out1_clk_wiz_0
+ BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.029 -1.673 r pixelClk/inst/clkout1_buf/O
+ net (fo=127, routed) 0.867 -0.806 runnerObject/clk_out1
+ SLICE_X88Y71 FDCE r runnerObject/fcount_edge_reg[5]/C
+ clock pessimism 0.252 -0.554
+ SLICE_X88Y71 FDCE (Hold_fdce_C_D) 0.086 -0.468 runnerObject/fcount_edge_reg[5]
+ -------------------------------------------------------------------
+ required time 0.468
+ arrival time -0.264
+ -------------------------------------------------------------------
+ slack 0.204
+
+Slack (MET) : 0.214ns (arrival time - required time)
+ Source: largeObstacle/pos_object_x_target_reg[4]/C
+ (rising edge-triggered cell FDCE clocked by clk_out1_clk_wiz_0 {rise@0.000ns fall@20.000ns period=40.000ns})
+ Destination: largeObstacle/pos_object_x_actual_reg[4]/D
+ (rising edge-triggered cell FDRE clocked by clk_out1_clk_wiz_0 {rise@0.000ns fall@20.000ns period=40.000ns})
+ Path Group: clk_out1_clk_wiz_0
+ Path Type: Hold (Min at Fast Process Corner)
+ Requirement: 0.000ns (clk_out1_clk_wiz_0 rise@0.000ns - clk_out1_clk_wiz_0 rise@0.000ns)
+ Data Path Delay: 0.288ns (logic 0.164ns (56.904%) route 0.124ns (43.096%))
+ Logic Levels: 0
+ Clock Path Skew: 0.015ns (DCD - SCD - CPR)
+ Destination Clock Delay (DCD): -0.810ns
+ Source Clock Delay (SCD): -0.572ns
+ Clock Pessimism Removal (CPR): -0.253ns
+
+ Location Delay type Incr(ns) Path(ns) Netlist Resource(s)
+ ------------------------------------------------------------------- -------------------
+ (clock clk_out1_clk_wiz_0 rise edge)
+ 0.000 0.000 r
+ E3 0.000 0.000 r clk (IN)
+ net (fo=0) 0.000 0.000 pixelClk/inst/clk_in1
+ E3 IBUF (Prop_ibuf_I_O) 0.250 0.250 r pixelClk/inst/clkin1_ibufg/O
+ net (fo=1, routed) 0.440 0.690 pixelClk/inst/clk_in1_clk_wiz_0
+ MMCME2_ADV_X1Y2 MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKOUT0)
+ -2.379 -1.689 r pixelClk/inst/mmcm_adv_inst/CLKOUT0
+ net (fo=1, routed) 0.499 -1.190 pixelClk/inst/clk_out1_clk_wiz_0
+ BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.026 -1.164 r pixelClk/inst/clkout1_buf/O
+ net (fo=127, routed) 0.592 -0.572 largeObstacle/CLK
+ SLICE_X80Y78 FDCE r largeObstacle/pos_object_x_target_reg[4]/C
+ ------------------------------------------------------------------- -------------------
+ SLICE_X80Y78 FDCE (Prop_fdce_C_Q) 0.164 -0.408 r largeObstacle/pos_object_x_target_reg[4]/Q
+ net (fo=5, routed) 0.124 -0.284 largeObstacle/pos_object_x_target_reg[4]
+ SLICE_X80Y79 FDRE r largeObstacle/pos_object_x_actual_reg[4]/D
+ ------------------------------------------------------------------- -------------------
+
+ (clock clk_out1_clk_wiz_0 rise edge)
+ 0.000 0.000 r
+ E3 0.000 0.000 r clk (IN)
+ net (fo=0) 0.000 0.000 pixelClk/inst/clk_in1
+ E3 IBUF (Prop_ibuf_I_O) 0.438 0.438 r pixelClk/inst/clkin1_ibufg/O
+ net (fo=1, routed) 0.480 0.918 pixelClk/inst/clk_in1_clk_wiz_0
+ MMCME2_ADV_X1Y2 MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKOUT0)
+ -3.163 -2.245 r pixelClk/inst/mmcm_adv_inst/CLKOUT0
+ net (fo=1, routed) 0.544 -1.702 pixelClk/inst/clk_out1_clk_wiz_0
+ BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.029 -1.673 r pixelClk/inst/clkout1_buf/O
+ net (fo=127, routed) 0.863 -0.810 largeObstacle/CLK
+ SLICE_X80Y79 FDRE r largeObstacle/pos_object_x_actual_reg[4]/C
+ clock pessimism 0.253 -0.557
+ SLICE_X80Y79 FDRE (Hold_fdre_C_D) 0.059 -0.498 largeObstacle/pos_object_x_actual_reg[4]
+ -------------------------------------------------------------------
+ required time 0.498
+ arrival time -0.284
+ -------------------------------------------------------------------
+ slack 0.214
+
+
+
+
+
+Pulse Width Checks
+--------------------------------------------------------------------------------------
+Clock Name: clk_out1_clk_wiz_0
+Waveform(ns): { 0.000 20.000 }
+Period(ns): 40.000
+Sources: { pixelClk/inst/mmcm_adv_inst/CLKOUT0 }
+
+Check Type Corner Lib Pin Reference Pin Required(ns) Actual(ns) Slack(ns) Location Pin
+Min Period n/a BUFG/I n/a 2.155 40.000 37.845 BUFGCTRL_X0Y16 pixelClk/inst/clkout1_buf/I
+Min Period n/a MMCME2_ADV/CLKOUT0 n/a 1.249 40.000 38.751 MMCME2_ADV_X1Y2 pixelClk/inst/mmcm_adv_inst/CLKOUT0
+Min Period n/a FDCE/C n/a 1.000 40.000 39.000 SLICE_X89Y67 collisionDetection/collision_cnt_reg[0]/C
+Min Period n/a FDCE/C n/a 1.000 40.000 39.000 SLICE_X88Y69 collisionDetection/collision_cnt_reg[10]/C
+Min Period n/a FDCE/C n/a 1.000 40.000 39.000 SLICE_X89Y69 collisionDetection/collision_cnt_reg[10]_lopt_replica/C
+Min Period n/a FDCE/C n/a 1.000 40.000 39.000 SLICE_X88Y67 collisionDetection/collision_cnt_reg[11]/C
+Min Period n/a FDCE/C n/a 1.000 40.000 39.000 SLICE_X89Y69 collisionDetection/collision_cnt_reg[12]/C
+Min Period n/a FDCE/C n/a 1.000 40.000 39.000 SLICE_X89Y69 collisionDetection/collision_cnt_reg[13]/C
+Min Period n/a FDCE/C n/a 1.000 40.000 39.000 SLICE_X89Y69 collisionDetection/collision_cnt_reg[14]/C
+Min Period n/a FDCE/C n/a 1.000 40.000 39.000 SLICE_X88Y69 collisionDetection/collision_cnt_reg[15]/C
+Max Period n/a MMCME2_ADV/CLKOUT0 n/a 213.360 40.000 173.360 MMCME2_ADV_X1Y2 pixelClk/inst/mmcm_adv_inst/CLKOUT0
+Low Pulse Width Slow FDCE/C n/a 0.500 20.000 19.500 SLICE_X89Y67 collisionDetection/collision_cnt_reg[0]/C
+Low Pulse Width Fast FDCE/C n/a 0.500 20.000 19.500 SLICE_X89Y67 collisionDetection/collision_cnt_reg[0]/C
+Low Pulse Width Slow FDCE/C n/a 0.500 20.000 19.500 SLICE_X88Y69 collisionDetection/collision_cnt_reg[10]/C
+Low Pulse Width Fast FDCE/C n/a 0.500 20.000 19.500 SLICE_X88Y69 collisionDetection/collision_cnt_reg[10]/C
+Low Pulse Width Slow FDCE/C n/a 0.500 20.000 19.500 SLICE_X89Y69 collisionDetection/collision_cnt_reg[10]_lopt_replica/C
+Low Pulse Width Fast FDCE/C n/a 0.500 20.000 19.500 SLICE_X89Y69 collisionDetection/collision_cnt_reg[10]_lopt_replica/C
+Low Pulse Width Slow FDCE/C n/a 0.500 20.000 19.500 SLICE_X88Y67 collisionDetection/collision_cnt_reg[11]/C
+Low Pulse Width Fast FDCE/C n/a 0.500 20.000 19.500 SLICE_X88Y67 collisionDetection/collision_cnt_reg[11]/C
+Low Pulse Width Slow FDCE/C n/a 0.500 20.000 19.500 SLICE_X89Y69 collisionDetection/collision_cnt_reg[12]/C
+Low Pulse Width Fast FDCE/C n/a 0.500 20.000 19.500 SLICE_X89Y69 collisionDetection/collision_cnt_reg[12]/C
+High Pulse Width Slow FDCE/C n/a 0.500 20.000 19.500 SLICE_X89Y67 collisionDetection/collision_cnt_reg[0]/C
+High Pulse Width Fast FDCE/C n/a 0.500 20.000 19.500 SLICE_X89Y67 collisionDetection/collision_cnt_reg[0]/C
+High Pulse Width Slow FDCE/C n/a 0.500 20.000 19.500 SLICE_X88Y69 collisionDetection/collision_cnt_reg[10]/C
+High Pulse Width Fast FDCE/C n/a 0.500 20.000 19.500 SLICE_X88Y69 collisionDetection/collision_cnt_reg[10]/C
+High Pulse Width Slow FDCE/C n/a 0.500 20.000 19.500 SLICE_X89Y69 collisionDetection/collision_cnt_reg[10]_lopt_replica/C
+High Pulse Width Fast FDCE/C n/a 0.500 20.000 19.500 SLICE_X89Y69 collisionDetection/collision_cnt_reg[10]_lopt_replica/C
+High Pulse Width Slow FDCE/C n/a 0.500 20.000 19.500 SLICE_X88Y67 collisionDetection/collision_cnt_reg[11]/C
+High Pulse Width Fast FDCE/C n/a 0.500 20.000 19.500 SLICE_X88Y67 collisionDetection/collision_cnt_reg[11]/C
+High Pulse Width Slow FDCE/C n/a 0.500 20.000 19.500 SLICE_X89Y69 collisionDetection/collision_cnt_reg[12]/C
+High Pulse Width Fast FDCE/C n/a 0.500 20.000 19.500 SLICE_X89Y69 collisionDetection/collision_cnt_reg[12]/C
+
+
+
+---------------------------------------------------------------------------------------------------
+From Clock: clkfbout_clk_wiz_0
+ To Clock: clkfbout_clk_wiz_0
+
+Setup : NA Failing Endpoints, Worst Slack NA , Total Violation NA
+Hold : NA Failing Endpoints, Worst Slack NA , Total Violation NA
+PW : 0 Failing Endpoints, Worst Slack 7.845ns, Total Violation 0.000ns
+---------------------------------------------------------------------------------------------------
+
+
+Pulse Width Checks
+--------------------------------------------------------------------------------------
+Clock Name: clkfbout_clk_wiz_0
+Waveform(ns): { 0.000 5.000 }
+Period(ns): 10.000
+Sources: { pixelClk/inst/mmcm_adv_inst/CLKFBOUT }
+
+Check Type Corner Lib Pin Reference Pin Required(ns) Actual(ns) Slack(ns) Location Pin
+Min Period n/a BUFG/I n/a 2.155 10.000 7.845 BUFGCTRL_X0Y17 pixelClk/inst/clkf_buf/I
+Min Period n/a MMCME2_ADV/CLKFBOUT n/a 1.249 10.000 8.751 MMCME2_ADV_X1Y2 pixelClk/inst/mmcm_adv_inst/CLKFBOUT
+Min Period n/a MMCME2_ADV/CLKFBIN n/a 1.249 10.000 8.751 MMCME2_ADV_X1Y2 pixelClk/inst/mmcm_adv_inst/CLKFBIN
+Max Period n/a MMCME2_ADV/CLKFBIN n/a 100.000 10.000 90.000 MMCME2_ADV_X1Y2 pixelClk/inst/mmcm_adv_inst/CLKFBIN
+Max Period n/a MMCME2_ADV/CLKFBOUT n/a 213.360 10.000 203.360 MMCME2_ADV_X1Y2 pixelClk/inst/mmcm_adv_inst/CLKFBOUT
+
+
+
+---------------------------------------------------------------------------------------------------
+From Clock: sys_clk_pin
+ To Clock: sys_clk_pin
+
+Setup : NA Failing Endpoints, Worst Slack NA , Total Violation NA
+Hold : NA Failing Endpoints, Worst Slack NA , Total Violation NA
+PW : 0 Failing Endpoints, Worst Slack 3.000ns, Total Violation 0.000ns
+---------------------------------------------------------------------------------------------------
+
+
+Pulse Width Checks
+--------------------------------------------------------------------------------------
+Clock Name: sys_clk_pin
+Waveform(ns): { 0.000 5.000 }
+Period(ns): 10.000
+Sources: { clk }
+
+Check Type Corner Lib Pin Reference Pin Required(ns) Actual(ns) Slack(ns) Location Pin
+Min Period n/a MMCME2_ADV/CLKIN1 n/a 1.249 10.000 8.751 MMCME2_ADV_X1Y2 pixelClk/inst/mmcm_adv_inst/CLKIN1
+Max Period n/a MMCME2_ADV/CLKIN1 n/a 100.000 10.000 90.000 MMCME2_ADV_X1Y2 pixelClk/inst/mmcm_adv_inst/CLKIN1
+Low Pulse Width Slow MMCME2_ADV/CLKIN1 n/a 2.000 5.000 3.000 MMCME2_ADV_X1Y2 pixelClk/inst/mmcm_adv_inst/CLKIN1
+Low Pulse Width Fast MMCME2_ADV/CLKIN1 n/a 2.000 5.000 3.000 MMCME2_ADV_X1Y2 pixelClk/inst/mmcm_adv_inst/CLKIN1
+High Pulse Width Slow MMCME2_ADV/CLKIN1 n/a 2.000 5.000 3.000 MMCME2_ADV_X1Y2 pixelClk/inst/mmcm_adv_inst/CLKIN1
+High Pulse Width Fast MMCME2_ADV/CLKIN1 n/a 2.000 5.000 3.000 MMCME2_ADV_X1Y2 pixelClk/inst/mmcm_adv_inst/CLKIN1
+
+
+
+---------------------------------------------------------------------------------------------------
+From Clock: clk_out1_clk_wiz_0_1
+ To Clock: clk_out1_clk_wiz_0_1
+
+Setup : 0 Failing Endpoints, Worst Slack 24.912ns, Total Violation 0.000ns
+Hold : 0 Failing Endpoints, Worst Slack 0.161ns, Total Violation 0.000ns
+PW : 0 Failing Endpoints, Worst Slack 19.500ns, Total Violation 0.000ns
+---------------------------------------------------------------------------------------------------
+
+
+Max Delay Paths
+--------------------------------------------------------------------------------------
+Slack (MET) : 24.912ns (required time - arrival time)
+ Source: vgaInterface/counter_f_reg[2]/C
+ (rising edge-triggered cell FDCE clocked by clk_out1_clk_wiz_0_1 {rise@0.000ns fall@20.000ns period=40.000ns})
+ Destination: runnerObject/pos_object_y_target_reg[8]/D
+ (rising edge-triggered cell FDSE clocked by clk_out1_clk_wiz_0_1 {rise@0.000ns fall@20.000ns period=40.000ns})
+ Path Group: clk_out1_clk_wiz_0_1
+ Path Type: Setup (Max at Slow Process Corner)
+ Requirement: 40.000ns (clk_out1_clk_wiz_0_1 rise@40.000ns - clk_out1_clk_wiz_0_1 rise@0.000ns)
+ Data Path Delay: 15.033ns (logic 5.901ns (39.253%) route 9.132ns (60.747%))
+ Logic Levels: 18 (CARRY4=9 LUT1=2 LUT2=2 LUT4=2 LUT5=1 LUT6=2)
+ Clock Path Skew: -0.039ns (DCD - SCD + CPR)
+ Destination Clock Delay (DCD): -1.419ns = ( 38.581 - 40.000 )
+ Source Clock Delay (SCD): -0.821ns
+ Clock Pessimism Removal (CPR): 0.559ns
+ Clock Uncertainty: 0.094ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE
+ Total System Jitter (TSJ): 0.071ns
+ Discrete Jitter (DJ): 0.175ns
+ Phase Error (PE): 0.000ns
+
+ Location Delay type Incr(ns) Path(ns) Netlist Resource(s)
+ ------------------------------------------------------------------- -------------------
+ (clock clk_out1_clk_wiz_0_1 rise edge)
+ 0.000 0.000 r
+ E3 0.000 0.000 r clk (IN)
+ net (fo=0) 0.000 0.000 pixelClk/inst/clk_in1
+ E3 IBUF (Prop_ibuf_I_O) 1.482 1.482 r pixelClk/inst/clkin1_ibufg/O
+ net (fo=1, routed) 1.233 2.715 pixelClk/inst/clk_in1_clk_wiz_0
+ MMCME2_ADV_X1Y2 MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKOUT0)
+ -7.070 -4.355 r pixelClk/inst/mmcm_adv_inst/CLKOUT0
+ net (fo=1, routed) 1.719 -2.636 pixelClk/inst/clk_out1_clk_wiz_0
+ BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.096 -2.540 r pixelClk/inst/clkout1_buf/O
+ net (fo=127, routed) 1.719 -0.821 vgaInterface/clk_out1
+ SLICE_X89Y70 FDCE r vgaInterface/counter_f_reg[2]/C
+ ------------------------------------------------------------------- -------------------
+ SLICE_X89Y70 FDCE (Prop_fdce_C_Q) 0.456 -0.365 f vgaInterface/counter_f_reg[2]/Q
+ net (fo=5, routed) 1.006 0.641 vgaInterface/counter_f_reg[2]
+ SLICE_X88Y67 LUT1 (Prop_lut1_I0_O) 0.124 0.765 r vgaInterface/FCounter_17bit_carry_i_3/O
+ net (fo=1, routed) 0.000 0.765 runnerObject/pos_object_y_target6_carry_0[1]
+ SLICE_X88Y67 CARRY4 (Prop_carry4_S[1]_CO[3])
+ 0.533 1.298 r runnerObject/FCounter_17bit_carry/CO[3]
+ net (fo=1, routed) 0.000 1.298 runnerObject/FCounter_17bit_carry_n_0
+ SLICE_X88Y68 CARRY4 (Prop_carry4_CI_O[2])
+ 0.239 1.537 r runnerObject/FCounter_17bit_carry__0/O[2]
+ net (fo=2, routed) 0.987 2.523 runnerObject/FCounter_17bit[7]
+ SLICE_X88Y71 LUT2 (Prop_lut2_I0_O) 0.301 2.824 r runnerObject/pos_object_y_target6_carry__0_i_1/O
+ net (fo=1, routed) 0.000 2.824 runnerObject/pos_object_y_target6_carry__0_i_1_n_0
+ SLICE_X88Y71 CARRY4 (Prop_carry4_S[3]_CO[3])
+ 0.376 3.200 r runnerObject/pos_object_y_target6_carry__0/CO[3]
+ net (fo=1, routed) 0.000 3.200 runnerObject/pos_object_y_target6_carry__0_n_0
+ SLICE_X88Y72 CARRY4 (Prop_carry4_CI_O[1])
+ 0.323 3.523 f runnerObject/pos_object_y_target6_carry__1/O[1]
+ net (fo=5, routed) 0.953 4.477 runnerObject/pos_object_y_target6[9]
+ SLICE_X82Y72 LUT1 (Prop_lut1_I0_O) 0.306 4.783 r runnerObject/i__carry__1_i_13/O
+ net (fo=1, routed) 0.000 4.783 runnerObject/p_0_in[9]
+ SLICE_X82Y72 CARRY4 (Prop_carry4_S[0]_O[2])
+ 0.547 5.330 f runnerObject/i__carry__1_i_9/O[2]
+ net (fo=2, routed) 0.821 6.151 runnerObject/pos_object_y_target9[11]
+ SLICE_X84Y71 LUT4 (Prop_lut4_I3_O) 0.302 6.453 r runnerObject/pos_object_y_target2_carry_i_13/O
+ net (fo=2, routed) 0.420 6.872 runnerObject/pos_object_y_target2_carry_i_13_n_0
+ SLICE_X87Y72 LUT6 (Prop_lut6_I0_O) 0.124 6.996 r runnerObject/pos_object_y_target2_carry_i_10/O
+ net (fo=34, routed) 1.081 8.077 runnerObject/pos_object_y_target2_carry_i_10_n_0
+ SLICE_X84Y70 LUT6 (Prop_lut6_I3_O) 0.124 8.201 r runnerObject/pos_object_y_target2_carry_i_9/O
+ net (fo=1, routed) 0.701 8.903 runnerObject/pos_object_y_target2_carry_i_9_n_0
+ SLICE_X85Y70 CARRY4 (Prop_carry4_S[0]_O[3])
+ 0.730 9.633 f runnerObject/pos_object_y_target2_carry/O[3]
+ net (fo=2, routed) 1.215 10.847 runnerObject/pos_object_y_target2[4]
+ SLICE_X84Y73 LUT2 (Prop_lut2_I1_O) 0.306 11.153 r runnerObject/pos_object_y_target1_carry_i_4/O
+ net (fo=1, routed) 0.000 11.153 runnerObject/pos_object_y_target1_carry_i_4_n_0
+ SLICE_X84Y73 CARRY4 (Prop_carry4_S[2]_CO[3])
+ 0.380 11.533 r runnerObject/pos_object_y_target1_carry/CO[3]
+ net (fo=1, routed) 0.000 11.533 runnerObject/pos_object_y_target1_carry_n_0
+ SLICE_X84Y74 CARRY4 (Prop_carry4_CI_CO[3])
+ 0.117 11.650 r runnerObject/pos_object_y_target1_carry__0/CO[3]
+ net (fo=1, routed) 0.009 11.659 runnerObject/pos_object_y_target1_carry__0_n_0
+ SLICE_X84Y75 CARRY4 (Prop_carry4_CI_CO[1])
+ 0.157 11.816 r runnerObject/pos_object_y_target1_carry__1/CO[1]
+ net (fo=11, routed) 1.258 13.075 runnerObject/pos_object_y_target1
+ SLICE_X88Y80 LUT5 (Prop_lut5_I1_O) 0.332 13.407 r runnerObject/pos_object_y_target[8]_i_4/O
+ net (fo=2, routed) 0.682 14.088 runnerObject/pos_object_y_target[8]_i_4_n_0
+ SLICE_X88Y80 LUT4 (Prop_lut4_I3_O) 0.124 14.212 r runnerObject/pos_object_y_target[8]_i_3/O
+ net (fo=1, routed) 0.000 14.212 runnerObject/pos_object_y_target[8]_i_3_n_0
+ SLICE_X88Y80 FDSE r runnerObject/pos_object_y_target_reg[8]/D
+ ------------------------------------------------------------------- -------------------
+
+ (clock clk_out1_clk_wiz_0_1 rise edge)
+ 40.000 40.000 r
+ E3 0.000 40.000 r clk (IN)
+ net (fo=0) 0.000 40.000 pixelClk/inst/clk_in1
+ E3 IBUF (Prop_ibuf_I_O) 1.411 41.411 r pixelClk/inst/clkin1_ibufg/O
+ net (fo=1, routed) 1.162 42.573 pixelClk/inst/clk_in1_clk_wiz_0
+ MMCME2_ADV_X1Y2 MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKOUT0)
+ -7.324 35.249 r pixelClk/inst/mmcm_adv_inst/CLKOUT0
+ net (fo=1, routed) 1.639 36.888 pixelClk/inst/clk_out1_clk_wiz_0
+ BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.091 36.979 r pixelClk/inst/clkout1_buf/O
+ net (fo=127, routed) 1.601 38.581 runnerObject/clk_out1
+ SLICE_X88Y80 FDSE r runnerObject/pos_object_y_target_reg[8]/C
+ clock pessimism 0.559 39.140
+ clock uncertainty -0.094 39.046
+ SLICE_X88Y80 FDSE (Setup_fdse_C_D) 0.079 39.125 runnerObject/pos_object_y_target_reg[8]
+ -------------------------------------------------------------------
+ required time 39.125
+ arrival time -14.212
+ -------------------------------------------------------------------
+ slack 24.912
+
+Slack (MET) : 25.048ns (required time - arrival time)
+ Source: vgaInterface/counter_f_reg[2]/C
+ (rising edge-triggered cell FDCE clocked by clk_out1_clk_wiz_0_1 {rise@0.000ns fall@20.000ns period=40.000ns})
+ Destination: runnerObject/pos_object_y_target_reg[5]/R
+ (rising edge-triggered cell FDRE clocked by clk_out1_clk_wiz_0_1 {rise@0.000ns fall@20.000ns period=40.000ns})
+ Path Group: clk_out1_clk_wiz_0_1
+ Path Type: Setup (Max at Slow Process Corner)
+ Requirement: 40.000ns (clk_out1_clk_wiz_0_1 rise@40.000ns - clk_out1_clk_wiz_0_1 rise@0.000ns)
+ Data Path Delay: 14.294ns (logic 5.777ns (40.414%) route 8.517ns (59.586%))
+ Logic Levels: 17 (CARRY4=9 LUT1=2 LUT2=2 LUT3=1 LUT4=1 LUT6=2)
+ Clock Path Skew: -0.039ns (DCD - SCD + CPR)
+ Destination Clock Delay (DCD): -1.419ns = ( 38.581 - 40.000 )
+ Source Clock Delay (SCD): -0.821ns
+ Clock Pessimism Removal (CPR): 0.559ns
+ Clock Uncertainty: 0.094ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE
+ Total System Jitter (TSJ): 0.071ns
+ Discrete Jitter (DJ): 0.175ns
+ Phase Error (PE): 0.000ns
+
+ Location Delay type Incr(ns) Path(ns) Netlist Resource(s)
+ ------------------------------------------------------------------- -------------------
+ (clock clk_out1_clk_wiz_0_1 rise edge)
+ 0.000 0.000 r
+ E3 0.000 0.000 r clk (IN)
+ net (fo=0) 0.000 0.000 pixelClk/inst/clk_in1
+ E3 IBUF (Prop_ibuf_I_O) 1.482 1.482 r pixelClk/inst/clkin1_ibufg/O
+ net (fo=1, routed) 1.233 2.715 pixelClk/inst/clk_in1_clk_wiz_0
+ MMCME2_ADV_X1Y2 MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKOUT0)
+ -7.070 -4.355 r pixelClk/inst/mmcm_adv_inst/CLKOUT0
+ net (fo=1, routed) 1.719 -2.636 pixelClk/inst/clk_out1_clk_wiz_0
+ BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.096 -2.540 r pixelClk/inst/clkout1_buf/O
+ net (fo=127, routed) 1.719 -0.821 vgaInterface/clk_out1
+ SLICE_X89Y70 FDCE r vgaInterface/counter_f_reg[2]/C
+ ------------------------------------------------------------------- -------------------
+ SLICE_X89Y70 FDCE (Prop_fdce_C_Q) 0.456 -0.365 f vgaInterface/counter_f_reg[2]/Q
+ net (fo=5, routed) 1.006 0.641 vgaInterface/counter_f_reg[2]
+ SLICE_X88Y67 LUT1 (Prop_lut1_I0_O) 0.124 0.765 r vgaInterface/FCounter_17bit_carry_i_3/O
+ net (fo=1, routed) 0.000 0.765 runnerObject/pos_object_y_target6_carry_0[1]
+ SLICE_X88Y67 CARRY4 (Prop_carry4_S[1]_CO[3])
+ 0.533 1.298 r runnerObject/FCounter_17bit_carry/CO[3]
+ net (fo=1, routed) 0.000 1.298 runnerObject/FCounter_17bit_carry_n_0
+ SLICE_X88Y68 CARRY4 (Prop_carry4_CI_O[2])
+ 0.239 1.537 r runnerObject/FCounter_17bit_carry__0/O[2]
+ net (fo=2, routed) 0.987 2.523 runnerObject/FCounter_17bit[7]
+ SLICE_X88Y71 LUT2 (Prop_lut2_I0_O) 0.301 2.824 r runnerObject/pos_object_y_target6_carry__0_i_1/O
+ net (fo=1, routed) 0.000 2.824 runnerObject/pos_object_y_target6_carry__0_i_1_n_0
+ SLICE_X88Y71 CARRY4 (Prop_carry4_S[3]_CO[3])
+ 0.376 3.200 r runnerObject/pos_object_y_target6_carry__0/CO[3]
+ net (fo=1, routed) 0.000 3.200 runnerObject/pos_object_y_target6_carry__0_n_0
+ SLICE_X88Y72 CARRY4 (Prop_carry4_CI_O[1])
+ 0.323 3.523 f runnerObject/pos_object_y_target6_carry__1/O[1]
+ net (fo=5, routed) 0.953 4.477 runnerObject/pos_object_y_target6[9]
+ SLICE_X82Y72 LUT1 (Prop_lut1_I0_O) 0.306 4.783 r runnerObject/i__carry__1_i_13/O
+ net (fo=1, routed) 0.000 4.783 runnerObject/p_0_in[9]
+ SLICE_X82Y72 CARRY4 (Prop_carry4_S[0]_O[2])
+ 0.547 5.330 f runnerObject/i__carry__1_i_9/O[2]
+ net (fo=2, routed) 0.821 6.151 runnerObject/pos_object_y_target9[11]
+ SLICE_X84Y71 LUT4 (Prop_lut4_I3_O) 0.302 6.453 r runnerObject/pos_object_y_target2_carry_i_13/O
+ net (fo=2, routed) 0.420 6.872 runnerObject/pos_object_y_target2_carry_i_13_n_0
+ SLICE_X87Y72 LUT6 (Prop_lut6_I0_O) 0.124 6.996 r runnerObject/pos_object_y_target2_carry_i_10/O
+ net (fo=34, routed) 1.081 8.077 runnerObject/pos_object_y_target2_carry_i_10_n_0
+ SLICE_X84Y70 LUT6 (Prop_lut6_I3_O) 0.124 8.201 r runnerObject/pos_object_y_target2_carry_i_9/O
+ net (fo=1, routed) 0.701 8.903 runnerObject/pos_object_y_target2_carry_i_9_n_0
+ SLICE_X85Y70 CARRY4 (Prop_carry4_S[0]_O[3])
+ 0.730 9.633 f runnerObject/pos_object_y_target2_carry/O[3]
+ net (fo=2, routed) 1.215 10.847 runnerObject/pos_object_y_target2[4]
+ SLICE_X84Y73 LUT2 (Prop_lut2_I1_O) 0.306 11.153 r runnerObject/pos_object_y_target1_carry_i_4/O
+ net (fo=1, routed) 0.000 11.153 runnerObject/pos_object_y_target1_carry_i_4_n_0
+ SLICE_X84Y73 CARRY4 (Prop_carry4_S[2]_CO[3])
+ 0.380 11.533 r runnerObject/pos_object_y_target1_carry/CO[3]
+ net (fo=1, routed) 0.000 11.533 runnerObject/pos_object_y_target1_carry_n_0
+ SLICE_X84Y74 CARRY4 (Prop_carry4_CI_CO[3])
+ 0.117 11.650 r runnerObject/pos_object_y_target1_carry__0/CO[3]
+ net (fo=1, routed) 0.009 11.659 runnerObject/pos_object_y_target1_carry__0_n_0
+ SLICE_X84Y75 CARRY4 (Prop_carry4_CI_CO[1])
+ 0.157 11.816 f runnerObject/pos_object_y_target1_carry__1/CO[1]
+ net (fo=11, routed) 0.629 12.445 runnerObject/pos_object_y_target1
+ SLICE_X86Y77 LUT3 (Prop_lut3_I0_O) 0.332 12.777 r runnerObject/pos_object_y_target[8]_i_1/O
+ net (fo=9, routed) 0.697 13.474 runnerObject/pos_object_y_target[8]_i_1_n_0
+ SLICE_X88Y79 FDRE r runnerObject/pos_object_y_target_reg[5]/R
+ ------------------------------------------------------------------- -------------------
+
+ (clock clk_out1_clk_wiz_0_1 rise edge)
+ 40.000 40.000 r
+ E3 0.000 40.000 r clk (IN)
+ net (fo=0) 0.000 40.000 pixelClk/inst/clk_in1
+ E3 IBUF (Prop_ibuf_I_O) 1.411 41.411 r pixelClk/inst/clkin1_ibufg/O
+ net (fo=1, routed) 1.162 42.573 pixelClk/inst/clk_in1_clk_wiz_0
+ MMCME2_ADV_X1Y2 MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKOUT0)
+ -7.324 35.249 r pixelClk/inst/mmcm_adv_inst/CLKOUT0
+ net (fo=1, routed) 1.639 36.888 pixelClk/inst/clk_out1_clk_wiz_0
+ BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.091 36.979 r pixelClk/inst/clkout1_buf/O
+ net (fo=127, routed) 1.601 38.581 runnerObject/clk_out1
+ SLICE_X88Y79 FDRE r runnerObject/pos_object_y_target_reg[5]/C
+ clock pessimism 0.559 39.140
+ clock uncertainty -0.094 39.046
+ SLICE_X88Y79 FDRE (Setup_fdre_C_R) -0.524 38.522 runnerObject/pos_object_y_target_reg[5]
+ -------------------------------------------------------------------
+ required time 38.522
+ arrival time -13.474
+ -------------------------------------------------------------------
+ slack 25.048
+
+Slack (MET) : 25.106ns (required time - arrival time)
+ Source: vgaInterface/counter_f_reg[2]/C
+ (rising edge-triggered cell FDCE clocked by clk_out1_clk_wiz_0_1 {rise@0.000ns fall@20.000ns period=40.000ns})
+ Destination: runnerObject/pos_object_y_target_reg[6]/S
+ (rising edge-triggered cell FDSE clocked by clk_out1_clk_wiz_0_1 {rise@0.000ns fall@20.000ns period=40.000ns})
+ Path Group: clk_out1_clk_wiz_0_1
+ Path Type: Setup (Max at Slow Process Corner)
+ Requirement: 40.000ns (clk_out1_clk_wiz_0_1 rise@40.000ns - clk_out1_clk_wiz_0_1 rise@0.000ns)
+ Data Path Delay: 14.237ns (logic 5.777ns (40.577%) route 8.460ns (59.423%))
+ Logic Levels: 17 (CARRY4=9 LUT1=2 LUT2=2 LUT3=1 LUT4=1 LUT6=2)
+ Clock Path Skew: -0.039ns (DCD - SCD + CPR)
+ Destination Clock Delay (DCD): -1.419ns = ( 38.581 - 40.000 )
+ Source Clock Delay (SCD): -0.821ns
+ Clock Pessimism Removal (CPR): 0.559ns
+ Clock Uncertainty: 0.094ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE
+ Total System Jitter (TSJ): 0.071ns
+ Discrete Jitter (DJ): 0.175ns
+ Phase Error (PE): 0.000ns
+
+ Location Delay type Incr(ns) Path(ns) Netlist Resource(s)
+ ------------------------------------------------------------------- -------------------
+ (clock clk_out1_clk_wiz_0_1 rise edge)
+ 0.000 0.000 r
+ E3 0.000 0.000 r clk (IN)
+ net (fo=0) 0.000 0.000 pixelClk/inst/clk_in1
+ E3 IBUF (Prop_ibuf_I_O) 1.482 1.482 r pixelClk/inst/clkin1_ibufg/O
+ net (fo=1, routed) 1.233 2.715 pixelClk/inst/clk_in1_clk_wiz_0
+ MMCME2_ADV_X1Y2 MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKOUT0)
+ -7.070 -4.355 r pixelClk/inst/mmcm_adv_inst/CLKOUT0
+ net (fo=1, routed) 1.719 -2.636 pixelClk/inst/clk_out1_clk_wiz_0
+ BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.096 -2.540 r pixelClk/inst/clkout1_buf/O
+ net (fo=127, routed) 1.719 -0.821 vgaInterface/clk_out1
+ SLICE_X89Y70 FDCE r vgaInterface/counter_f_reg[2]/C
+ ------------------------------------------------------------------- -------------------
+ SLICE_X89Y70 FDCE (Prop_fdce_C_Q) 0.456 -0.365 f vgaInterface/counter_f_reg[2]/Q
+ net (fo=5, routed) 1.006 0.641 vgaInterface/counter_f_reg[2]
+ SLICE_X88Y67 LUT1 (Prop_lut1_I0_O) 0.124 0.765 r vgaInterface/FCounter_17bit_carry_i_3/O
+ net (fo=1, routed) 0.000 0.765 runnerObject/pos_object_y_target6_carry_0[1]
+ SLICE_X88Y67 CARRY4 (Prop_carry4_S[1]_CO[3])
+ 0.533 1.298 r runnerObject/FCounter_17bit_carry/CO[3]
+ net (fo=1, routed) 0.000 1.298 runnerObject/FCounter_17bit_carry_n_0
+ SLICE_X88Y68 CARRY4 (Prop_carry4_CI_O[2])
+ 0.239 1.537 r runnerObject/FCounter_17bit_carry__0/O[2]
+ net (fo=2, routed) 0.987 2.523 runnerObject/FCounter_17bit[7]
+ SLICE_X88Y71 LUT2 (Prop_lut2_I0_O) 0.301 2.824 r runnerObject/pos_object_y_target6_carry__0_i_1/O
+ net (fo=1, routed) 0.000 2.824 runnerObject/pos_object_y_target6_carry__0_i_1_n_0
+ SLICE_X88Y71 CARRY4 (Prop_carry4_S[3]_CO[3])
+ 0.376 3.200 r runnerObject/pos_object_y_target6_carry__0/CO[3]
+ net (fo=1, routed) 0.000 3.200 runnerObject/pos_object_y_target6_carry__0_n_0
+ SLICE_X88Y72 CARRY4 (Prop_carry4_CI_O[1])
+ 0.323 3.523 f runnerObject/pos_object_y_target6_carry__1/O[1]
+ net (fo=5, routed) 0.953 4.477 runnerObject/pos_object_y_target6[9]
+ SLICE_X82Y72 LUT1 (Prop_lut1_I0_O) 0.306 4.783 r runnerObject/i__carry__1_i_13/O
+ net (fo=1, routed) 0.000 4.783 runnerObject/p_0_in[9]
+ SLICE_X82Y72 CARRY4 (Prop_carry4_S[0]_O[2])
+ 0.547 5.330 f runnerObject/i__carry__1_i_9/O[2]
+ net (fo=2, routed) 0.821 6.151 runnerObject/pos_object_y_target9[11]
+ SLICE_X84Y71 LUT4 (Prop_lut4_I3_O) 0.302 6.453 r runnerObject/pos_object_y_target2_carry_i_13/O
+ net (fo=2, routed) 0.420 6.872 runnerObject/pos_object_y_target2_carry_i_13_n_0
+ SLICE_X87Y72 LUT6 (Prop_lut6_I0_O) 0.124 6.996 r runnerObject/pos_object_y_target2_carry_i_10/O
+ net (fo=34, routed) 1.081 8.077 runnerObject/pos_object_y_target2_carry_i_10_n_0
+ SLICE_X84Y70 LUT6 (Prop_lut6_I3_O) 0.124 8.201 r runnerObject/pos_object_y_target2_carry_i_9/O
+ net (fo=1, routed) 0.701 8.903 runnerObject/pos_object_y_target2_carry_i_9_n_0
+ SLICE_X85Y70 CARRY4 (Prop_carry4_S[0]_O[3])
+ 0.730 9.633 f runnerObject/pos_object_y_target2_carry/O[3]
+ net (fo=2, routed) 1.215 10.847 runnerObject/pos_object_y_target2[4]
+ SLICE_X84Y73 LUT2 (Prop_lut2_I1_O) 0.306 11.153 r runnerObject/pos_object_y_target1_carry_i_4/O
+ net (fo=1, routed) 0.000 11.153 runnerObject/pos_object_y_target1_carry_i_4_n_0
+ SLICE_X84Y73 CARRY4 (Prop_carry4_S[2]_CO[3])
+ 0.380 11.533 r runnerObject/pos_object_y_target1_carry/CO[3]
+ net (fo=1, routed) 0.000 11.533 runnerObject/pos_object_y_target1_carry_n_0
+ SLICE_X84Y74 CARRY4 (Prop_carry4_CI_CO[3])
+ 0.117 11.650 r runnerObject/pos_object_y_target1_carry__0/CO[3]
+ net (fo=1, routed) 0.009 11.659 runnerObject/pos_object_y_target1_carry__0_n_0
+ SLICE_X84Y75 CARRY4 (Prop_carry4_CI_CO[1])
+ 0.157 11.816 f runnerObject/pos_object_y_target1_carry__1/CO[1]
+ net (fo=11, routed) 0.629 12.445 runnerObject/pos_object_y_target1
+ SLICE_X86Y77 LUT3 (Prop_lut3_I0_O) 0.332 12.777 r runnerObject/pos_object_y_target[8]_i_1/O
+ net (fo=9, routed) 0.639 13.416 runnerObject/pos_object_y_target[8]_i_1_n_0
+ SLICE_X88Y80 FDSE r runnerObject/pos_object_y_target_reg[6]/S
+ ------------------------------------------------------------------- -------------------
+
+ (clock clk_out1_clk_wiz_0_1 rise edge)
+ 40.000 40.000 r
+ E3 0.000 40.000 r clk (IN)
+ net (fo=0) 0.000 40.000 pixelClk/inst/clk_in1
+ E3 IBUF (Prop_ibuf_I_O) 1.411 41.411 r pixelClk/inst/clkin1_ibufg/O
+ net (fo=1, routed) 1.162 42.573 pixelClk/inst/clk_in1_clk_wiz_0
+ MMCME2_ADV_X1Y2 MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKOUT0)
+ -7.324 35.249 r pixelClk/inst/mmcm_adv_inst/CLKOUT0
+ net (fo=1, routed) 1.639 36.888 pixelClk/inst/clk_out1_clk_wiz_0
+ BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.091 36.979 r pixelClk/inst/clkout1_buf/O
+ net (fo=127, routed) 1.601 38.581 runnerObject/clk_out1
+ SLICE_X88Y80 FDSE r runnerObject/pos_object_y_target_reg[6]/C
+ clock pessimism 0.559 39.140
+ clock uncertainty -0.094 39.046
+ SLICE_X88Y80 FDSE (Setup_fdse_C_S) -0.524 38.522 runnerObject/pos_object_y_target_reg[6]
+ -------------------------------------------------------------------
+ required time 38.522
+ arrival time -13.416
+ -------------------------------------------------------------------
+ slack 25.106
+
+Slack (MET) : 25.106ns (required time - arrival time)
+ Source: vgaInterface/counter_f_reg[2]/C
+ (rising edge-triggered cell FDCE clocked by clk_out1_clk_wiz_0_1 {rise@0.000ns fall@20.000ns period=40.000ns})
+ Destination: runnerObject/pos_object_y_target_reg[7]/R
+ (rising edge-triggered cell FDRE clocked by clk_out1_clk_wiz_0_1 {rise@0.000ns fall@20.000ns period=40.000ns})
+ Path Group: clk_out1_clk_wiz_0_1
+ Path Type: Setup (Max at Slow Process Corner)
+ Requirement: 40.000ns (clk_out1_clk_wiz_0_1 rise@40.000ns - clk_out1_clk_wiz_0_1 rise@0.000ns)
+ Data Path Delay: 14.237ns (logic 5.777ns (40.577%) route 8.460ns (59.423%))
+ Logic Levels: 17 (CARRY4=9 LUT1=2 LUT2=2 LUT3=1 LUT4=1 LUT6=2)
+ Clock Path Skew: -0.039ns (DCD - SCD + CPR)
+ Destination Clock Delay (DCD): -1.419ns = ( 38.581 - 40.000 )
+ Source Clock Delay (SCD): -0.821ns
+ Clock Pessimism Removal (CPR): 0.559ns
+ Clock Uncertainty: 0.094ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE
+ Total System Jitter (TSJ): 0.071ns
+ Discrete Jitter (DJ): 0.175ns
+ Phase Error (PE): 0.000ns
+
+ Location Delay type Incr(ns) Path(ns) Netlist Resource(s)
+ ------------------------------------------------------------------- -------------------
+ (clock clk_out1_clk_wiz_0_1 rise edge)
+ 0.000 0.000 r
+ E3 0.000 0.000 r clk (IN)
+ net (fo=0) 0.000 0.000 pixelClk/inst/clk_in1
+ E3 IBUF (Prop_ibuf_I_O) 1.482 1.482 r pixelClk/inst/clkin1_ibufg/O
+ net (fo=1, routed) 1.233 2.715 pixelClk/inst/clk_in1_clk_wiz_0
+ MMCME2_ADV_X1Y2 MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKOUT0)
+ -7.070 -4.355 r pixelClk/inst/mmcm_adv_inst/CLKOUT0
+ net (fo=1, routed) 1.719 -2.636 pixelClk/inst/clk_out1_clk_wiz_0
+ BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.096 -2.540 r pixelClk/inst/clkout1_buf/O
+ net (fo=127, routed) 1.719 -0.821 vgaInterface/clk_out1
+ SLICE_X89Y70 FDCE r vgaInterface/counter_f_reg[2]/C
+ ------------------------------------------------------------------- -------------------
+ SLICE_X89Y70 FDCE (Prop_fdce_C_Q) 0.456 -0.365 f vgaInterface/counter_f_reg[2]/Q
+ net (fo=5, routed) 1.006 0.641 vgaInterface/counter_f_reg[2]
+ SLICE_X88Y67 LUT1 (Prop_lut1_I0_O) 0.124 0.765 r vgaInterface/FCounter_17bit_carry_i_3/O
+ net (fo=1, routed) 0.000 0.765 runnerObject/pos_object_y_target6_carry_0[1]
+ SLICE_X88Y67 CARRY4 (Prop_carry4_S[1]_CO[3])
+ 0.533 1.298 r runnerObject/FCounter_17bit_carry/CO[3]
+ net (fo=1, routed) 0.000 1.298 runnerObject/FCounter_17bit_carry_n_0
+ SLICE_X88Y68 CARRY4 (Prop_carry4_CI_O[2])
+ 0.239 1.537 r runnerObject/FCounter_17bit_carry__0/O[2]
+ net (fo=2, routed) 0.987 2.523 runnerObject/FCounter_17bit[7]
+ SLICE_X88Y71 LUT2 (Prop_lut2_I0_O) 0.301 2.824 r runnerObject/pos_object_y_target6_carry__0_i_1/O
+ net (fo=1, routed) 0.000 2.824 runnerObject/pos_object_y_target6_carry__0_i_1_n_0
+ SLICE_X88Y71 CARRY4 (Prop_carry4_S[3]_CO[3])
+ 0.376 3.200 r runnerObject/pos_object_y_target6_carry__0/CO[3]
+ net (fo=1, routed) 0.000 3.200 runnerObject/pos_object_y_target6_carry__0_n_0
+ SLICE_X88Y72 CARRY4 (Prop_carry4_CI_O[1])
+ 0.323 3.523 f runnerObject/pos_object_y_target6_carry__1/O[1]
+ net (fo=5, routed) 0.953 4.477 runnerObject/pos_object_y_target6[9]
+ SLICE_X82Y72 LUT1 (Prop_lut1_I0_O) 0.306 4.783 r runnerObject/i__carry__1_i_13/O
+ net (fo=1, routed) 0.000 4.783 runnerObject/p_0_in[9]
+ SLICE_X82Y72 CARRY4 (Prop_carry4_S[0]_O[2])
+ 0.547 5.330 f runnerObject/i__carry__1_i_9/O[2]
+ net (fo=2, routed) 0.821 6.151 runnerObject/pos_object_y_target9[11]
+ SLICE_X84Y71 LUT4 (Prop_lut4_I3_O) 0.302 6.453 r runnerObject/pos_object_y_target2_carry_i_13/O
+ net (fo=2, routed) 0.420 6.872 runnerObject/pos_object_y_target2_carry_i_13_n_0
+ SLICE_X87Y72 LUT6 (Prop_lut6_I0_O) 0.124 6.996 r runnerObject/pos_object_y_target2_carry_i_10/O
+ net (fo=34, routed) 1.081 8.077 runnerObject/pos_object_y_target2_carry_i_10_n_0
+ SLICE_X84Y70 LUT6 (Prop_lut6_I3_O) 0.124 8.201 r runnerObject/pos_object_y_target2_carry_i_9/O
+ net (fo=1, routed) 0.701 8.903 runnerObject/pos_object_y_target2_carry_i_9_n_0
+ SLICE_X85Y70 CARRY4 (Prop_carry4_S[0]_O[3])
+ 0.730 9.633 f runnerObject/pos_object_y_target2_carry/O[3]
+ net (fo=2, routed) 1.215 10.847 runnerObject/pos_object_y_target2[4]
+ SLICE_X84Y73 LUT2 (Prop_lut2_I1_O) 0.306 11.153 r runnerObject/pos_object_y_target1_carry_i_4/O
+ net (fo=1, routed) 0.000 11.153 runnerObject/pos_object_y_target1_carry_i_4_n_0
+ SLICE_X84Y73 CARRY4 (Prop_carry4_S[2]_CO[3])
+ 0.380 11.533 r runnerObject/pos_object_y_target1_carry/CO[3]
+ net (fo=1, routed) 0.000 11.533 runnerObject/pos_object_y_target1_carry_n_0
+ SLICE_X84Y74 CARRY4 (Prop_carry4_CI_CO[3])
+ 0.117 11.650 r runnerObject/pos_object_y_target1_carry__0/CO[3]
+ net (fo=1, routed) 0.009 11.659 runnerObject/pos_object_y_target1_carry__0_n_0
+ SLICE_X84Y75 CARRY4 (Prop_carry4_CI_CO[1])
+ 0.157 11.816 f runnerObject/pos_object_y_target1_carry__1/CO[1]
+ net (fo=11, routed) 0.629 12.445 runnerObject/pos_object_y_target1
+ SLICE_X86Y77 LUT3 (Prop_lut3_I0_O) 0.332 12.777 r runnerObject/pos_object_y_target[8]_i_1/O
+ net (fo=9, routed) 0.639 13.416 runnerObject/pos_object_y_target[8]_i_1_n_0
+ SLICE_X88Y80 FDRE r runnerObject/pos_object_y_target_reg[7]/R
+ ------------------------------------------------------------------- -------------------
+
+ (clock clk_out1_clk_wiz_0_1 rise edge)
+ 40.000 40.000 r
+ E3 0.000 40.000 r clk (IN)
+ net (fo=0) 0.000 40.000 pixelClk/inst/clk_in1
+ E3 IBUF (Prop_ibuf_I_O) 1.411 41.411 r pixelClk/inst/clkin1_ibufg/O
+ net (fo=1, routed) 1.162 42.573 pixelClk/inst/clk_in1_clk_wiz_0
+ MMCME2_ADV_X1Y2 MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKOUT0)
+ -7.324 35.249 r pixelClk/inst/mmcm_adv_inst/CLKOUT0
+ net (fo=1, routed) 1.639 36.888 pixelClk/inst/clk_out1_clk_wiz_0
+ BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.091 36.979 r pixelClk/inst/clkout1_buf/O
+ net (fo=127, routed) 1.601 38.581 runnerObject/clk_out1
+ SLICE_X88Y80 FDRE r runnerObject/pos_object_y_target_reg[7]/C
+ clock pessimism 0.559 39.140
+ clock uncertainty -0.094 39.046
+ SLICE_X88Y80 FDRE (Setup_fdre_C_R) -0.524 38.522 runnerObject/pos_object_y_target_reg[7]
+ -------------------------------------------------------------------
+ required time 38.522
+ arrival time -13.416
+ -------------------------------------------------------------------
+ slack 25.106
+
+Slack (MET) : 25.106ns (required time - arrival time)
+ Source: vgaInterface/counter_f_reg[2]/C
+ (rising edge-triggered cell FDCE clocked by clk_out1_clk_wiz_0_1 {rise@0.000ns fall@20.000ns period=40.000ns})
+ Destination: runnerObject/pos_object_y_target_reg[8]/S
+ (rising edge-triggered cell FDSE clocked by clk_out1_clk_wiz_0_1 {rise@0.000ns fall@20.000ns period=40.000ns})
+ Path Group: clk_out1_clk_wiz_0_1
+ Path Type: Setup (Max at Slow Process Corner)
+ Requirement: 40.000ns (clk_out1_clk_wiz_0_1 rise@40.000ns - clk_out1_clk_wiz_0_1 rise@0.000ns)
+ Data Path Delay: 14.237ns (logic 5.777ns (40.577%) route 8.460ns (59.423%))
+ Logic Levels: 17 (CARRY4=9 LUT1=2 LUT2=2 LUT3=1 LUT4=1 LUT6=2)
+ Clock Path Skew: -0.039ns (DCD - SCD + CPR)
+ Destination Clock Delay (DCD): -1.419ns = ( 38.581 - 40.000 )
+ Source Clock Delay (SCD): -0.821ns
+ Clock Pessimism Removal (CPR): 0.559ns
+ Clock Uncertainty: 0.094ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE
+ Total System Jitter (TSJ): 0.071ns
+ Discrete Jitter (DJ): 0.175ns
+ Phase Error (PE): 0.000ns
+
+ Location Delay type Incr(ns) Path(ns) Netlist Resource(s)
+ ------------------------------------------------------------------- -------------------
+ (clock clk_out1_clk_wiz_0_1 rise edge)
+ 0.000 0.000 r
+ E3 0.000 0.000 r clk (IN)
+ net (fo=0) 0.000 0.000 pixelClk/inst/clk_in1
+ E3 IBUF (Prop_ibuf_I_O) 1.482 1.482 r pixelClk/inst/clkin1_ibufg/O
+ net (fo=1, routed) 1.233 2.715 pixelClk/inst/clk_in1_clk_wiz_0
+ MMCME2_ADV_X1Y2 MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKOUT0)
+ -7.070 -4.355 r pixelClk/inst/mmcm_adv_inst/CLKOUT0
+ net (fo=1, routed) 1.719 -2.636 pixelClk/inst/clk_out1_clk_wiz_0
+ BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.096 -2.540 r pixelClk/inst/clkout1_buf/O
+ net (fo=127, routed) 1.719 -0.821 vgaInterface/clk_out1
+ SLICE_X89Y70 FDCE r vgaInterface/counter_f_reg[2]/C
+ ------------------------------------------------------------------- -------------------
+ SLICE_X89Y70 FDCE (Prop_fdce_C_Q) 0.456 -0.365 f vgaInterface/counter_f_reg[2]/Q
+ net (fo=5, routed) 1.006 0.641 vgaInterface/counter_f_reg[2]
+ SLICE_X88Y67 LUT1 (Prop_lut1_I0_O) 0.124 0.765 r vgaInterface/FCounter_17bit_carry_i_3/O
+ net (fo=1, routed) 0.000 0.765 runnerObject/pos_object_y_target6_carry_0[1]
+ SLICE_X88Y67 CARRY4 (Prop_carry4_S[1]_CO[3])
+ 0.533 1.298 r runnerObject/FCounter_17bit_carry/CO[3]
+ net (fo=1, routed) 0.000 1.298 runnerObject/FCounter_17bit_carry_n_0
+ SLICE_X88Y68 CARRY4 (Prop_carry4_CI_O[2])
+ 0.239 1.537 r runnerObject/FCounter_17bit_carry__0/O[2]
+ net (fo=2, routed) 0.987 2.523 runnerObject/FCounter_17bit[7]
+ SLICE_X88Y71 LUT2 (Prop_lut2_I0_O) 0.301 2.824 r runnerObject/pos_object_y_target6_carry__0_i_1/O
+ net (fo=1, routed) 0.000 2.824 runnerObject/pos_object_y_target6_carry__0_i_1_n_0
+ SLICE_X88Y71 CARRY4 (Prop_carry4_S[3]_CO[3])
+ 0.376 3.200 r runnerObject/pos_object_y_target6_carry__0/CO[3]
+ net (fo=1, routed) 0.000 3.200 runnerObject/pos_object_y_target6_carry__0_n_0
+ SLICE_X88Y72 CARRY4 (Prop_carry4_CI_O[1])
+ 0.323 3.523 f runnerObject/pos_object_y_target6_carry__1/O[1]
+ net (fo=5, routed) 0.953 4.477 runnerObject/pos_object_y_target6[9]
+ SLICE_X82Y72 LUT1 (Prop_lut1_I0_O) 0.306 4.783 r runnerObject/i__carry__1_i_13/O
+ net (fo=1, routed) 0.000 4.783 runnerObject/p_0_in[9]
+ SLICE_X82Y72 CARRY4 (Prop_carry4_S[0]_O[2])
+ 0.547 5.330 f runnerObject/i__carry__1_i_9/O[2]
+ net (fo=2, routed) 0.821 6.151 runnerObject/pos_object_y_target9[11]
+ SLICE_X84Y71 LUT4 (Prop_lut4_I3_O) 0.302 6.453 r runnerObject/pos_object_y_target2_carry_i_13/O
+ net (fo=2, routed) 0.420 6.872 runnerObject/pos_object_y_target2_carry_i_13_n_0
+ SLICE_X87Y72 LUT6 (Prop_lut6_I0_O) 0.124 6.996 r runnerObject/pos_object_y_target2_carry_i_10/O
+ net (fo=34, routed) 1.081 8.077 runnerObject/pos_object_y_target2_carry_i_10_n_0
+ SLICE_X84Y70 LUT6 (Prop_lut6_I3_O) 0.124 8.201 r runnerObject/pos_object_y_target2_carry_i_9/O
+ net (fo=1, routed) 0.701 8.903 runnerObject/pos_object_y_target2_carry_i_9_n_0
+ SLICE_X85Y70 CARRY4 (Prop_carry4_S[0]_O[3])
+ 0.730 9.633 f runnerObject/pos_object_y_target2_carry/O[3]
+ net (fo=2, routed) 1.215 10.847 runnerObject/pos_object_y_target2[4]
+ SLICE_X84Y73 LUT2 (Prop_lut2_I1_O) 0.306 11.153 r runnerObject/pos_object_y_target1_carry_i_4/O
+ net (fo=1, routed) 0.000 11.153 runnerObject/pos_object_y_target1_carry_i_4_n_0
+ SLICE_X84Y73 CARRY4 (Prop_carry4_S[2]_CO[3])
+ 0.380 11.533 r runnerObject/pos_object_y_target1_carry/CO[3]
+ net (fo=1, routed) 0.000 11.533 runnerObject/pos_object_y_target1_carry_n_0
+ SLICE_X84Y74 CARRY4 (Prop_carry4_CI_CO[3])
+ 0.117 11.650 r runnerObject/pos_object_y_target1_carry__0/CO[3]
+ net (fo=1, routed) 0.009 11.659 runnerObject/pos_object_y_target1_carry__0_n_0
+ SLICE_X84Y75 CARRY4 (Prop_carry4_CI_CO[1])
+ 0.157 11.816 f runnerObject/pos_object_y_target1_carry__1/CO[1]
+ net (fo=11, routed) 0.629 12.445 runnerObject/pos_object_y_target1
+ SLICE_X86Y77 LUT3 (Prop_lut3_I0_O) 0.332 12.777 r runnerObject/pos_object_y_target[8]_i_1/O
+ net (fo=9, routed) 0.639 13.416 runnerObject/pos_object_y_target[8]_i_1_n_0
+ SLICE_X88Y80 FDSE r runnerObject/pos_object_y_target_reg[8]/S
+ ------------------------------------------------------------------- -------------------
+
+ (clock clk_out1_clk_wiz_0_1 rise edge)
+ 40.000 40.000 r
+ E3 0.000 40.000 r clk (IN)
+ net (fo=0) 0.000 40.000 pixelClk/inst/clk_in1
+ E3 IBUF (Prop_ibuf_I_O) 1.411 41.411 r pixelClk/inst/clkin1_ibufg/O
+ net (fo=1, routed) 1.162 42.573 pixelClk/inst/clk_in1_clk_wiz_0
+ MMCME2_ADV_X1Y2 MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKOUT0)
+ -7.324 35.249 r pixelClk/inst/mmcm_adv_inst/CLKOUT0
+ net (fo=1, routed) 1.639 36.888 pixelClk/inst/clk_out1_clk_wiz_0
+ BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.091 36.979 r pixelClk/inst/clkout1_buf/O
+ net (fo=127, routed) 1.601 38.581 runnerObject/clk_out1
+ SLICE_X88Y80 FDSE r runnerObject/pos_object_y_target_reg[8]/C
+ clock pessimism 0.559 39.140
+ clock uncertainty -0.094 39.046
+ SLICE_X88Y80 FDSE (Setup_fdse_C_S) -0.524 38.522 runnerObject/pos_object_y_target_reg[8]
+ -------------------------------------------------------------------
+ required time 38.522
+ arrival time -13.416
+ -------------------------------------------------------------------
+ slack 25.106
+
+Slack (MET) : 25.143ns (required time - arrival time)
+ Source: vgaInterface/counter_f_reg[2]/C
+ (rising edge-triggered cell FDCE clocked by clk_out1_clk_wiz_0_1 {rise@0.000ns fall@20.000ns period=40.000ns})
+ Destination: runnerObject/pos_object_y_target_reg[0]/R
+ (rising edge-triggered cell FDRE clocked by clk_out1_clk_wiz_0_1 {rise@0.000ns fall@20.000ns period=40.000ns})
+ Path Group: clk_out1_clk_wiz_0_1
+ Path Type: Setup (Max at Slow Process Corner)
+ Requirement: 40.000ns (clk_out1_clk_wiz_0_1 rise@40.000ns - clk_out1_clk_wiz_0_1 rise@0.000ns)
+ Data Path Delay: 14.294ns (logic 5.777ns (40.414%) route 8.517ns (59.586%))
+ Logic Levels: 17 (CARRY4=9 LUT1=2 LUT2=2 LUT3=1 LUT4=1 LUT6=2)
+ Clock Path Skew: -0.039ns (DCD - SCD + CPR)
+ Destination Clock Delay (DCD): -1.419ns = ( 38.581 - 40.000 )
+ Source Clock Delay (SCD): -0.821ns
+ Clock Pessimism Removal (CPR): 0.559ns
+ Clock Uncertainty: 0.094ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE
+ Total System Jitter (TSJ): 0.071ns
+ Discrete Jitter (DJ): 0.175ns
+ Phase Error (PE): 0.000ns
+
+ Location Delay type Incr(ns) Path(ns) Netlist Resource(s)
+ ------------------------------------------------------------------- -------------------
+ (clock clk_out1_clk_wiz_0_1 rise edge)
+ 0.000 0.000 r
+ E3 0.000 0.000 r clk (IN)
+ net (fo=0) 0.000 0.000 pixelClk/inst/clk_in1
+ E3 IBUF (Prop_ibuf_I_O) 1.482 1.482 r pixelClk/inst/clkin1_ibufg/O
+ net (fo=1, routed) 1.233 2.715 pixelClk/inst/clk_in1_clk_wiz_0
+ MMCME2_ADV_X1Y2 MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKOUT0)
+ -7.070 -4.355 r pixelClk/inst/mmcm_adv_inst/CLKOUT0
+ net (fo=1, routed) 1.719 -2.636 pixelClk/inst/clk_out1_clk_wiz_0
+ BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.096 -2.540 r pixelClk/inst/clkout1_buf/O
+ net (fo=127, routed) 1.719 -0.821 vgaInterface/clk_out1
+ SLICE_X89Y70 FDCE r vgaInterface/counter_f_reg[2]/C
+ ------------------------------------------------------------------- -------------------
+ SLICE_X89Y70 FDCE (Prop_fdce_C_Q) 0.456 -0.365 f vgaInterface/counter_f_reg[2]/Q
+ net (fo=5, routed) 1.006 0.641 vgaInterface/counter_f_reg[2]
+ SLICE_X88Y67 LUT1 (Prop_lut1_I0_O) 0.124 0.765 r vgaInterface/FCounter_17bit_carry_i_3/O
+ net (fo=1, routed) 0.000 0.765 runnerObject/pos_object_y_target6_carry_0[1]
+ SLICE_X88Y67 CARRY4 (Prop_carry4_S[1]_CO[3])
+ 0.533 1.298 r runnerObject/FCounter_17bit_carry/CO[3]
+ net (fo=1, routed) 0.000 1.298 runnerObject/FCounter_17bit_carry_n_0
+ SLICE_X88Y68 CARRY4 (Prop_carry4_CI_O[2])
+ 0.239 1.537 r runnerObject/FCounter_17bit_carry__0/O[2]
+ net (fo=2, routed) 0.987 2.523 runnerObject/FCounter_17bit[7]
+ SLICE_X88Y71 LUT2 (Prop_lut2_I0_O) 0.301 2.824 r runnerObject/pos_object_y_target6_carry__0_i_1/O
+ net (fo=1, routed) 0.000 2.824 runnerObject/pos_object_y_target6_carry__0_i_1_n_0
+ SLICE_X88Y71 CARRY4 (Prop_carry4_S[3]_CO[3])
+ 0.376 3.200 r runnerObject/pos_object_y_target6_carry__0/CO[3]
+ net (fo=1, routed) 0.000 3.200 runnerObject/pos_object_y_target6_carry__0_n_0
+ SLICE_X88Y72 CARRY4 (Prop_carry4_CI_O[1])
+ 0.323 3.523 f runnerObject/pos_object_y_target6_carry__1/O[1]
+ net (fo=5, routed) 0.953 4.477 runnerObject/pos_object_y_target6[9]
+ SLICE_X82Y72 LUT1 (Prop_lut1_I0_O) 0.306 4.783 r runnerObject/i__carry__1_i_13/O
+ net (fo=1, routed) 0.000 4.783 runnerObject/p_0_in[9]
+ SLICE_X82Y72 CARRY4 (Prop_carry4_S[0]_O[2])
+ 0.547 5.330 f runnerObject/i__carry__1_i_9/O[2]
+ net (fo=2, routed) 0.821 6.151 runnerObject/pos_object_y_target9[11]
+ SLICE_X84Y71 LUT4 (Prop_lut4_I3_O) 0.302 6.453 r runnerObject/pos_object_y_target2_carry_i_13/O
+ net (fo=2, routed) 0.420 6.872 runnerObject/pos_object_y_target2_carry_i_13_n_0
+ SLICE_X87Y72 LUT6 (Prop_lut6_I0_O) 0.124 6.996 r runnerObject/pos_object_y_target2_carry_i_10/O
+ net (fo=34, routed) 1.081 8.077 runnerObject/pos_object_y_target2_carry_i_10_n_0
+ SLICE_X84Y70 LUT6 (Prop_lut6_I3_O) 0.124 8.201 r runnerObject/pos_object_y_target2_carry_i_9/O
+ net (fo=1, routed) 0.701 8.903 runnerObject/pos_object_y_target2_carry_i_9_n_0
+ SLICE_X85Y70 CARRY4 (Prop_carry4_S[0]_O[3])
+ 0.730 9.633 f runnerObject/pos_object_y_target2_carry/O[3]
+ net (fo=2, routed) 1.215 10.847 runnerObject/pos_object_y_target2[4]
+ SLICE_X84Y73 LUT2 (Prop_lut2_I1_O) 0.306 11.153 r runnerObject/pos_object_y_target1_carry_i_4/O
+ net (fo=1, routed) 0.000 11.153 runnerObject/pos_object_y_target1_carry_i_4_n_0
+ SLICE_X84Y73 CARRY4 (Prop_carry4_S[2]_CO[3])
+ 0.380 11.533 r runnerObject/pos_object_y_target1_carry/CO[3]
+ net (fo=1, routed) 0.000 11.533 runnerObject/pos_object_y_target1_carry_n_0
+ SLICE_X84Y74 CARRY4 (Prop_carry4_CI_CO[3])
+ 0.117 11.650 r runnerObject/pos_object_y_target1_carry__0/CO[3]
+ net (fo=1, routed) 0.009 11.659 runnerObject/pos_object_y_target1_carry__0_n_0
+ SLICE_X84Y75 CARRY4 (Prop_carry4_CI_CO[1])
+ 0.157 11.816 f runnerObject/pos_object_y_target1_carry__1/CO[1]
+ net (fo=11, routed) 0.629 12.445 runnerObject/pos_object_y_target1
+ SLICE_X86Y77 LUT3 (Prop_lut3_I0_O) 0.332 12.777 r runnerObject/pos_object_y_target[8]_i_1/O
+ net (fo=9, routed) 0.697 13.474 runnerObject/pos_object_y_target[8]_i_1_n_0
+ SLICE_X89Y79 FDRE r runnerObject/pos_object_y_target_reg[0]/R
+ ------------------------------------------------------------------- -------------------
+
+ (clock clk_out1_clk_wiz_0_1 rise edge)
+ 40.000 40.000 r
+ E3 0.000 40.000 r clk (IN)
+ net (fo=0) 0.000 40.000 pixelClk/inst/clk_in1
+ E3 IBUF (Prop_ibuf_I_O) 1.411 41.411 r pixelClk/inst/clkin1_ibufg/O
+ net (fo=1, routed) 1.162 42.573 pixelClk/inst/clk_in1_clk_wiz_0
+ MMCME2_ADV_X1Y2 MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKOUT0)
+ -7.324 35.249 r pixelClk/inst/mmcm_adv_inst/CLKOUT0
+ net (fo=1, routed) 1.639 36.888 pixelClk/inst/clk_out1_clk_wiz_0
+ BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.091 36.979 r pixelClk/inst/clkout1_buf/O
+ net (fo=127, routed) 1.601 38.581 runnerObject/clk_out1
+ SLICE_X89Y79 FDRE r runnerObject/pos_object_y_target_reg[0]/C
+ clock pessimism 0.559 39.140
+ clock uncertainty -0.094 39.046
+ SLICE_X89Y79 FDRE (Setup_fdre_C_R) -0.429 38.617 runnerObject/pos_object_y_target_reg[0]
+ -------------------------------------------------------------------
+ required time 38.617
+ arrival time -13.474
+ -------------------------------------------------------------------
+ slack 25.143
+
+Slack (MET) : 25.143ns (required time - arrival time)
+ Source: vgaInterface/counter_f_reg[2]/C
+ (rising edge-triggered cell FDCE clocked by clk_out1_clk_wiz_0_1 {rise@0.000ns fall@20.000ns period=40.000ns})
+ Destination: runnerObject/pos_object_y_target_reg[1]/S
+ (rising edge-triggered cell FDSE clocked by clk_out1_clk_wiz_0_1 {rise@0.000ns fall@20.000ns period=40.000ns})
+ Path Group: clk_out1_clk_wiz_0_1
+ Path Type: Setup (Max at Slow Process Corner)
+ Requirement: 40.000ns (clk_out1_clk_wiz_0_1 rise@40.000ns - clk_out1_clk_wiz_0_1 rise@0.000ns)
+ Data Path Delay: 14.294ns (logic 5.777ns (40.414%) route 8.517ns (59.586%))
+ Logic Levels: 17 (CARRY4=9 LUT1=2 LUT2=2 LUT3=1 LUT4=1 LUT6=2)
+ Clock Path Skew: -0.039ns (DCD - SCD + CPR)
+ Destination Clock Delay (DCD): -1.419ns = ( 38.581 - 40.000 )
+ Source Clock Delay (SCD): -0.821ns
+ Clock Pessimism Removal (CPR): 0.559ns
+ Clock Uncertainty: 0.094ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE
+ Total System Jitter (TSJ): 0.071ns
+ Discrete Jitter (DJ): 0.175ns
+ Phase Error (PE): 0.000ns
+
+ Location Delay type Incr(ns) Path(ns) Netlist Resource(s)
+ ------------------------------------------------------------------- -------------------
+ (clock clk_out1_clk_wiz_0_1 rise edge)
+ 0.000 0.000 r
+ E3 0.000 0.000 r clk (IN)
+ net (fo=0) 0.000 0.000 pixelClk/inst/clk_in1
+ E3 IBUF (Prop_ibuf_I_O) 1.482 1.482 r pixelClk/inst/clkin1_ibufg/O
+ net (fo=1, routed) 1.233 2.715 pixelClk/inst/clk_in1_clk_wiz_0
+ MMCME2_ADV_X1Y2 MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKOUT0)
+ -7.070 -4.355 r pixelClk/inst/mmcm_adv_inst/CLKOUT0
+ net (fo=1, routed) 1.719 -2.636 pixelClk/inst/clk_out1_clk_wiz_0
+ BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.096 -2.540 r pixelClk/inst/clkout1_buf/O
+ net (fo=127, routed) 1.719 -0.821 vgaInterface/clk_out1
+ SLICE_X89Y70 FDCE r vgaInterface/counter_f_reg[2]/C
+ ------------------------------------------------------------------- -------------------
+ SLICE_X89Y70 FDCE (Prop_fdce_C_Q) 0.456 -0.365 f vgaInterface/counter_f_reg[2]/Q
+ net (fo=5, routed) 1.006 0.641 vgaInterface/counter_f_reg[2]
+ SLICE_X88Y67 LUT1 (Prop_lut1_I0_O) 0.124 0.765 r vgaInterface/FCounter_17bit_carry_i_3/O
+ net (fo=1, routed) 0.000 0.765 runnerObject/pos_object_y_target6_carry_0[1]
+ SLICE_X88Y67 CARRY4 (Prop_carry4_S[1]_CO[3])
+ 0.533 1.298 r runnerObject/FCounter_17bit_carry/CO[3]
+ net (fo=1, routed) 0.000 1.298 runnerObject/FCounter_17bit_carry_n_0
+ SLICE_X88Y68 CARRY4 (Prop_carry4_CI_O[2])
+ 0.239 1.537 r runnerObject/FCounter_17bit_carry__0/O[2]
+ net (fo=2, routed) 0.987 2.523 runnerObject/FCounter_17bit[7]
+ SLICE_X88Y71 LUT2 (Prop_lut2_I0_O) 0.301 2.824 r runnerObject/pos_object_y_target6_carry__0_i_1/O
+ net (fo=1, routed) 0.000 2.824 runnerObject/pos_object_y_target6_carry__0_i_1_n_0
+ SLICE_X88Y71 CARRY4 (Prop_carry4_S[3]_CO[3])
+ 0.376 3.200 r runnerObject/pos_object_y_target6_carry__0/CO[3]
+ net (fo=1, routed) 0.000 3.200 runnerObject/pos_object_y_target6_carry__0_n_0
+ SLICE_X88Y72 CARRY4 (Prop_carry4_CI_O[1])
+ 0.323 3.523 f runnerObject/pos_object_y_target6_carry__1/O[1]
+ net (fo=5, routed) 0.953 4.477 runnerObject/pos_object_y_target6[9]
+ SLICE_X82Y72 LUT1 (Prop_lut1_I0_O) 0.306 4.783 r runnerObject/i__carry__1_i_13/O
+ net (fo=1, routed) 0.000 4.783 runnerObject/p_0_in[9]
+ SLICE_X82Y72 CARRY4 (Prop_carry4_S[0]_O[2])
+ 0.547 5.330 f runnerObject/i__carry__1_i_9/O[2]
+ net (fo=2, routed) 0.821 6.151 runnerObject/pos_object_y_target9[11]
+ SLICE_X84Y71 LUT4 (Prop_lut4_I3_O) 0.302 6.453 r runnerObject/pos_object_y_target2_carry_i_13/O
+ net (fo=2, routed) 0.420 6.872 runnerObject/pos_object_y_target2_carry_i_13_n_0
+ SLICE_X87Y72 LUT6 (Prop_lut6_I0_O) 0.124 6.996 r runnerObject/pos_object_y_target2_carry_i_10/O
+ net (fo=34, routed) 1.081 8.077 runnerObject/pos_object_y_target2_carry_i_10_n_0
+ SLICE_X84Y70 LUT6 (Prop_lut6_I3_O) 0.124 8.201 r runnerObject/pos_object_y_target2_carry_i_9/O
+ net (fo=1, routed) 0.701 8.903 runnerObject/pos_object_y_target2_carry_i_9_n_0
+ SLICE_X85Y70 CARRY4 (Prop_carry4_S[0]_O[3])
+ 0.730 9.633 f runnerObject/pos_object_y_target2_carry/O[3]
+ net (fo=2, routed) 1.215 10.847 runnerObject/pos_object_y_target2[4]
+ SLICE_X84Y73 LUT2 (Prop_lut2_I1_O) 0.306 11.153 r runnerObject/pos_object_y_target1_carry_i_4/O
+ net (fo=1, routed) 0.000 11.153 runnerObject/pos_object_y_target1_carry_i_4_n_0
+ SLICE_X84Y73 CARRY4 (Prop_carry4_S[2]_CO[3])
+ 0.380 11.533 r runnerObject/pos_object_y_target1_carry/CO[3]
+ net (fo=1, routed) 0.000 11.533 runnerObject/pos_object_y_target1_carry_n_0
+ SLICE_X84Y74 CARRY4 (Prop_carry4_CI_CO[3])
+ 0.117 11.650 r runnerObject/pos_object_y_target1_carry__0/CO[3]
+ net (fo=1, routed) 0.009 11.659 runnerObject/pos_object_y_target1_carry__0_n_0
+ SLICE_X84Y75 CARRY4 (Prop_carry4_CI_CO[1])
+ 0.157 11.816 f runnerObject/pos_object_y_target1_carry__1/CO[1]
+ net (fo=11, routed) 0.629 12.445 runnerObject/pos_object_y_target1
+ SLICE_X86Y77 LUT3 (Prop_lut3_I0_O) 0.332 12.777 r runnerObject/pos_object_y_target[8]_i_1/O
+ net (fo=9, routed) 0.697 13.474 runnerObject/pos_object_y_target[8]_i_1_n_0
+ SLICE_X89Y79 FDSE r runnerObject/pos_object_y_target_reg[1]/S
+ ------------------------------------------------------------------- -------------------
+
+ (clock clk_out1_clk_wiz_0_1 rise edge)
+ 40.000 40.000 r
+ E3 0.000 40.000 r clk (IN)
+ net (fo=0) 0.000 40.000 pixelClk/inst/clk_in1
+ E3 IBUF (Prop_ibuf_I_O) 1.411 41.411 r pixelClk/inst/clkin1_ibufg/O
+ net (fo=1, routed) 1.162 42.573 pixelClk/inst/clk_in1_clk_wiz_0
+ MMCME2_ADV_X1Y2 MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKOUT0)
+ -7.324 35.249 r pixelClk/inst/mmcm_adv_inst/CLKOUT0
+ net (fo=1, routed) 1.639 36.888 pixelClk/inst/clk_out1_clk_wiz_0
+ BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.091 36.979 r pixelClk/inst/clkout1_buf/O
+ net (fo=127, routed) 1.601 38.581 runnerObject/clk_out1
+ SLICE_X89Y79 FDSE r runnerObject/pos_object_y_target_reg[1]/C
+ clock pessimism 0.559 39.140
+ clock uncertainty -0.094 39.046
+ SLICE_X89Y79 FDSE (Setup_fdse_C_S) -0.429 38.617 runnerObject/pos_object_y_target_reg[1]
+ -------------------------------------------------------------------
+ required time 38.617
+ arrival time -13.474
+ -------------------------------------------------------------------
+ slack 25.143
+
+Slack (MET) : 25.143ns (required time - arrival time)
+ Source: vgaInterface/counter_f_reg[2]/C
+ (rising edge-triggered cell FDCE clocked by clk_out1_clk_wiz_0_1 {rise@0.000ns fall@20.000ns period=40.000ns})
+ Destination: runnerObject/pos_object_y_target_reg[2]/S
+ (rising edge-triggered cell FDSE clocked by clk_out1_clk_wiz_0_1 {rise@0.000ns fall@20.000ns period=40.000ns})
+ Path Group: clk_out1_clk_wiz_0_1
+ Path Type: Setup (Max at Slow Process Corner)
+ Requirement: 40.000ns (clk_out1_clk_wiz_0_1 rise@40.000ns - clk_out1_clk_wiz_0_1 rise@0.000ns)
+ Data Path Delay: 14.294ns (logic 5.777ns (40.414%) route 8.517ns (59.586%))
+ Logic Levels: 17 (CARRY4=9 LUT1=2 LUT2=2 LUT3=1 LUT4=1 LUT6=2)
+ Clock Path Skew: -0.039ns (DCD - SCD + CPR)
+ Destination Clock Delay (DCD): -1.419ns = ( 38.581 - 40.000 )
+ Source Clock Delay (SCD): -0.821ns
+ Clock Pessimism Removal (CPR): 0.559ns
+ Clock Uncertainty: 0.094ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE
+ Total System Jitter (TSJ): 0.071ns
+ Discrete Jitter (DJ): 0.175ns
+ Phase Error (PE): 0.000ns
+
+ Location Delay type Incr(ns) Path(ns) Netlist Resource(s)
+ ------------------------------------------------------------------- -------------------
+ (clock clk_out1_clk_wiz_0_1 rise edge)
+ 0.000 0.000 r
+ E3 0.000 0.000 r clk (IN)
+ net (fo=0) 0.000 0.000 pixelClk/inst/clk_in1
+ E3 IBUF (Prop_ibuf_I_O) 1.482 1.482 r pixelClk/inst/clkin1_ibufg/O
+ net (fo=1, routed) 1.233 2.715 pixelClk/inst/clk_in1_clk_wiz_0
+ MMCME2_ADV_X1Y2 MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKOUT0)
+ -7.070 -4.355 r pixelClk/inst/mmcm_adv_inst/CLKOUT0
+ net (fo=1, routed) 1.719 -2.636 pixelClk/inst/clk_out1_clk_wiz_0
+ BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.096 -2.540 r pixelClk/inst/clkout1_buf/O
+ net (fo=127, routed) 1.719 -0.821 vgaInterface/clk_out1
+ SLICE_X89Y70 FDCE r vgaInterface/counter_f_reg[2]/C
+ ------------------------------------------------------------------- -------------------
+ SLICE_X89Y70 FDCE (Prop_fdce_C_Q) 0.456 -0.365 f vgaInterface/counter_f_reg[2]/Q
+ net (fo=5, routed) 1.006 0.641 vgaInterface/counter_f_reg[2]
+ SLICE_X88Y67 LUT1 (Prop_lut1_I0_O) 0.124 0.765 r vgaInterface/FCounter_17bit_carry_i_3/O
+ net (fo=1, routed) 0.000 0.765 runnerObject/pos_object_y_target6_carry_0[1]
+ SLICE_X88Y67 CARRY4 (Prop_carry4_S[1]_CO[3])
+ 0.533 1.298 r runnerObject/FCounter_17bit_carry/CO[3]
+ net (fo=1, routed) 0.000 1.298 runnerObject/FCounter_17bit_carry_n_0
+ SLICE_X88Y68 CARRY4 (Prop_carry4_CI_O[2])
+ 0.239 1.537 r runnerObject/FCounter_17bit_carry__0/O[2]
+ net (fo=2, routed) 0.987 2.523 runnerObject/FCounter_17bit[7]
+ SLICE_X88Y71 LUT2 (Prop_lut2_I0_O) 0.301 2.824 r runnerObject/pos_object_y_target6_carry__0_i_1/O
+ net (fo=1, routed) 0.000 2.824 runnerObject/pos_object_y_target6_carry__0_i_1_n_0
+ SLICE_X88Y71 CARRY4 (Prop_carry4_S[3]_CO[3])
+ 0.376 3.200 r runnerObject/pos_object_y_target6_carry__0/CO[3]
+ net (fo=1, routed) 0.000 3.200 runnerObject/pos_object_y_target6_carry__0_n_0
+ SLICE_X88Y72 CARRY4 (Prop_carry4_CI_O[1])
+ 0.323 3.523 f runnerObject/pos_object_y_target6_carry__1/O[1]
+ net (fo=5, routed) 0.953 4.477 runnerObject/pos_object_y_target6[9]
+ SLICE_X82Y72 LUT1 (Prop_lut1_I0_O) 0.306 4.783 r runnerObject/i__carry__1_i_13/O
+ net (fo=1, routed) 0.000 4.783 runnerObject/p_0_in[9]
+ SLICE_X82Y72 CARRY4 (Prop_carry4_S[0]_O[2])
+ 0.547 5.330 f runnerObject/i__carry__1_i_9/O[2]
+ net (fo=2, routed) 0.821 6.151 runnerObject/pos_object_y_target9[11]
+ SLICE_X84Y71 LUT4 (Prop_lut4_I3_O) 0.302 6.453 r runnerObject/pos_object_y_target2_carry_i_13/O
+ net (fo=2, routed) 0.420 6.872 runnerObject/pos_object_y_target2_carry_i_13_n_0
+ SLICE_X87Y72 LUT6 (Prop_lut6_I0_O) 0.124 6.996 r runnerObject/pos_object_y_target2_carry_i_10/O
+ net (fo=34, routed) 1.081 8.077 runnerObject/pos_object_y_target2_carry_i_10_n_0
+ SLICE_X84Y70 LUT6 (Prop_lut6_I3_O) 0.124 8.201 r runnerObject/pos_object_y_target2_carry_i_9/O
+ net (fo=1, routed) 0.701 8.903 runnerObject/pos_object_y_target2_carry_i_9_n_0
+ SLICE_X85Y70 CARRY4 (Prop_carry4_S[0]_O[3])
+ 0.730 9.633 f runnerObject/pos_object_y_target2_carry/O[3]
+ net (fo=2, routed) 1.215 10.847 runnerObject/pos_object_y_target2[4]
+ SLICE_X84Y73 LUT2 (Prop_lut2_I1_O) 0.306 11.153 r runnerObject/pos_object_y_target1_carry_i_4/O
+ net (fo=1, routed) 0.000 11.153 runnerObject/pos_object_y_target1_carry_i_4_n_0
+ SLICE_X84Y73 CARRY4 (Prop_carry4_S[2]_CO[3])
+ 0.380 11.533 r runnerObject/pos_object_y_target1_carry/CO[3]
+ net (fo=1, routed) 0.000 11.533 runnerObject/pos_object_y_target1_carry_n_0
+ SLICE_X84Y74 CARRY4 (Prop_carry4_CI_CO[3])
+ 0.117 11.650 r runnerObject/pos_object_y_target1_carry__0/CO[3]
+ net (fo=1, routed) 0.009 11.659 runnerObject/pos_object_y_target1_carry__0_n_0
+ SLICE_X84Y75 CARRY4 (Prop_carry4_CI_CO[1])
+ 0.157 11.816 f runnerObject/pos_object_y_target1_carry__1/CO[1]
+ net (fo=11, routed) 0.629 12.445 runnerObject/pos_object_y_target1
+ SLICE_X86Y77 LUT3 (Prop_lut3_I0_O) 0.332 12.777 r runnerObject/pos_object_y_target[8]_i_1/O
+ net (fo=9, routed) 0.697 13.474 runnerObject/pos_object_y_target[8]_i_1_n_0
+ SLICE_X89Y79 FDSE r runnerObject/pos_object_y_target_reg[2]/S
+ ------------------------------------------------------------------- -------------------
+
+ (clock clk_out1_clk_wiz_0_1 rise edge)
+ 40.000 40.000 r
+ E3 0.000 40.000 r clk (IN)
+ net (fo=0) 0.000 40.000 pixelClk/inst/clk_in1
+ E3 IBUF (Prop_ibuf_I_O) 1.411 41.411 r pixelClk/inst/clkin1_ibufg/O
+ net (fo=1, routed) 1.162 42.573 pixelClk/inst/clk_in1_clk_wiz_0
+ MMCME2_ADV_X1Y2 MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKOUT0)
+ -7.324 35.249 r pixelClk/inst/mmcm_adv_inst/CLKOUT0
+ net (fo=1, routed) 1.639 36.888 pixelClk/inst/clk_out1_clk_wiz_0
+ BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.091 36.979 r pixelClk/inst/clkout1_buf/O
+ net (fo=127, routed) 1.601 38.581 runnerObject/clk_out1
+ SLICE_X89Y79 FDSE r runnerObject/pos_object_y_target_reg[2]/C
+ clock pessimism 0.559 39.140
+ clock uncertainty -0.094 39.046
+ SLICE_X89Y79 FDSE (Setup_fdse_C_S) -0.429 38.617 runnerObject/pos_object_y_target_reg[2]
+ -------------------------------------------------------------------
+ required time 38.617
+ arrival time -13.474
+ -------------------------------------------------------------------
+ slack 25.143
+
+Slack (MET) : 25.143ns (required time - arrival time)
+ Source: vgaInterface/counter_f_reg[2]/C
+ (rising edge-triggered cell FDCE clocked by clk_out1_clk_wiz_0_1 {rise@0.000ns fall@20.000ns period=40.000ns})
+ Destination: runnerObject/pos_object_y_target_reg[3]/S
+ (rising edge-triggered cell FDSE clocked by clk_out1_clk_wiz_0_1 {rise@0.000ns fall@20.000ns period=40.000ns})
+ Path Group: clk_out1_clk_wiz_0_1
+ Path Type: Setup (Max at Slow Process Corner)
+ Requirement: 40.000ns (clk_out1_clk_wiz_0_1 rise@40.000ns - clk_out1_clk_wiz_0_1 rise@0.000ns)
+ Data Path Delay: 14.294ns (logic 5.777ns (40.414%) route 8.517ns (59.586%))
+ Logic Levels: 17 (CARRY4=9 LUT1=2 LUT2=2 LUT3=1 LUT4=1 LUT6=2)
+ Clock Path Skew: -0.039ns (DCD - SCD + CPR)
+ Destination Clock Delay (DCD): -1.419ns = ( 38.581 - 40.000 )
+ Source Clock Delay (SCD): -0.821ns
+ Clock Pessimism Removal (CPR): 0.559ns
+ Clock Uncertainty: 0.094ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE
+ Total System Jitter (TSJ): 0.071ns
+ Discrete Jitter (DJ): 0.175ns
+ Phase Error (PE): 0.000ns
+
+ Location Delay type Incr(ns) Path(ns) Netlist Resource(s)
+ ------------------------------------------------------------------- -------------------
+ (clock clk_out1_clk_wiz_0_1 rise edge)
+ 0.000 0.000 r
+ E3 0.000 0.000 r clk (IN)
+ net (fo=0) 0.000 0.000 pixelClk/inst/clk_in1
+ E3 IBUF (Prop_ibuf_I_O) 1.482 1.482 r pixelClk/inst/clkin1_ibufg/O
+ net (fo=1, routed) 1.233 2.715 pixelClk/inst/clk_in1_clk_wiz_0
+ MMCME2_ADV_X1Y2 MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKOUT0)
+ -7.070 -4.355 r pixelClk/inst/mmcm_adv_inst/CLKOUT0
+ net (fo=1, routed) 1.719 -2.636 pixelClk/inst/clk_out1_clk_wiz_0
+ BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.096 -2.540 r pixelClk/inst/clkout1_buf/O
+ net (fo=127, routed) 1.719 -0.821 vgaInterface/clk_out1
+ SLICE_X89Y70 FDCE r vgaInterface/counter_f_reg[2]/C
+ ------------------------------------------------------------------- -------------------
+ SLICE_X89Y70 FDCE (Prop_fdce_C_Q) 0.456 -0.365 f vgaInterface/counter_f_reg[2]/Q
+ net (fo=5, routed) 1.006 0.641 vgaInterface/counter_f_reg[2]
+ SLICE_X88Y67 LUT1 (Prop_lut1_I0_O) 0.124 0.765 r vgaInterface/FCounter_17bit_carry_i_3/O
+ net (fo=1, routed) 0.000 0.765 runnerObject/pos_object_y_target6_carry_0[1]
+ SLICE_X88Y67 CARRY4 (Prop_carry4_S[1]_CO[3])
+ 0.533 1.298 r runnerObject/FCounter_17bit_carry/CO[3]
+ net (fo=1, routed) 0.000 1.298 runnerObject/FCounter_17bit_carry_n_0
+ SLICE_X88Y68 CARRY4 (Prop_carry4_CI_O[2])
+ 0.239 1.537 r runnerObject/FCounter_17bit_carry__0/O[2]
+ net (fo=2, routed) 0.987 2.523 runnerObject/FCounter_17bit[7]
+ SLICE_X88Y71 LUT2 (Prop_lut2_I0_O) 0.301 2.824 r runnerObject/pos_object_y_target6_carry__0_i_1/O
+ net (fo=1, routed) 0.000 2.824 runnerObject/pos_object_y_target6_carry__0_i_1_n_0
+ SLICE_X88Y71 CARRY4 (Prop_carry4_S[3]_CO[3])
+ 0.376 3.200 r runnerObject/pos_object_y_target6_carry__0/CO[3]
+ net (fo=1, routed) 0.000 3.200 runnerObject/pos_object_y_target6_carry__0_n_0
+ SLICE_X88Y72 CARRY4 (Prop_carry4_CI_O[1])
+ 0.323 3.523 f runnerObject/pos_object_y_target6_carry__1/O[1]
+ net (fo=5, routed) 0.953 4.477 runnerObject/pos_object_y_target6[9]
+ SLICE_X82Y72 LUT1 (Prop_lut1_I0_O) 0.306 4.783 r runnerObject/i__carry__1_i_13/O
+ net (fo=1, routed) 0.000 4.783 runnerObject/p_0_in[9]
+ SLICE_X82Y72 CARRY4 (Prop_carry4_S[0]_O[2])
+ 0.547 5.330 f runnerObject/i__carry__1_i_9/O[2]
+ net (fo=2, routed) 0.821 6.151 runnerObject/pos_object_y_target9[11]
+ SLICE_X84Y71 LUT4 (Prop_lut4_I3_O) 0.302 6.453 r runnerObject/pos_object_y_target2_carry_i_13/O
+ net (fo=2, routed) 0.420 6.872 runnerObject/pos_object_y_target2_carry_i_13_n_0
+ SLICE_X87Y72 LUT6 (Prop_lut6_I0_O) 0.124 6.996 r runnerObject/pos_object_y_target2_carry_i_10/O
+ net (fo=34, routed) 1.081 8.077 runnerObject/pos_object_y_target2_carry_i_10_n_0
+ SLICE_X84Y70 LUT6 (Prop_lut6_I3_O) 0.124 8.201 r runnerObject/pos_object_y_target2_carry_i_9/O
+ net (fo=1, routed) 0.701 8.903 runnerObject/pos_object_y_target2_carry_i_9_n_0
+ SLICE_X85Y70 CARRY4 (Prop_carry4_S[0]_O[3])
+ 0.730 9.633 f runnerObject/pos_object_y_target2_carry/O[3]
+ net (fo=2, routed) 1.215 10.847 runnerObject/pos_object_y_target2[4]
+ SLICE_X84Y73 LUT2 (Prop_lut2_I1_O) 0.306 11.153 r runnerObject/pos_object_y_target1_carry_i_4/O
+ net (fo=1, routed) 0.000 11.153 runnerObject/pos_object_y_target1_carry_i_4_n_0
+ SLICE_X84Y73 CARRY4 (Prop_carry4_S[2]_CO[3])
+ 0.380 11.533 r runnerObject/pos_object_y_target1_carry/CO[3]
+ net (fo=1, routed) 0.000 11.533 runnerObject/pos_object_y_target1_carry_n_0
+ SLICE_X84Y74 CARRY4 (Prop_carry4_CI_CO[3])
+ 0.117 11.650 r runnerObject/pos_object_y_target1_carry__0/CO[3]
+ net (fo=1, routed) 0.009 11.659 runnerObject/pos_object_y_target1_carry__0_n_0
+ SLICE_X84Y75 CARRY4 (Prop_carry4_CI_CO[1])
+ 0.157 11.816 f runnerObject/pos_object_y_target1_carry__1/CO[1]
+ net (fo=11, routed) 0.629 12.445 runnerObject/pos_object_y_target1
+ SLICE_X86Y77 LUT3 (Prop_lut3_I0_O) 0.332 12.777 r runnerObject/pos_object_y_target[8]_i_1/O
+ net (fo=9, routed) 0.697 13.474 runnerObject/pos_object_y_target[8]_i_1_n_0
+ SLICE_X89Y79 FDSE r runnerObject/pos_object_y_target_reg[3]/S
+ ------------------------------------------------------------------- -------------------
+
+ (clock clk_out1_clk_wiz_0_1 rise edge)
+ 40.000 40.000 r
+ E3 0.000 40.000 r clk (IN)
+ net (fo=0) 0.000 40.000 pixelClk/inst/clk_in1
+ E3 IBUF (Prop_ibuf_I_O) 1.411 41.411 r pixelClk/inst/clkin1_ibufg/O
+ net (fo=1, routed) 1.162 42.573 pixelClk/inst/clk_in1_clk_wiz_0
+ MMCME2_ADV_X1Y2 MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKOUT0)
+ -7.324 35.249 r pixelClk/inst/mmcm_adv_inst/CLKOUT0
+ net (fo=1, routed) 1.639 36.888 pixelClk/inst/clk_out1_clk_wiz_0
+ BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.091 36.979 r pixelClk/inst/clkout1_buf/O
+ net (fo=127, routed) 1.601 38.581 runnerObject/clk_out1
+ SLICE_X89Y79 FDSE r runnerObject/pos_object_y_target_reg[3]/C
+ clock pessimism 0.559 39.140
+ clock uncertainty -0.094 39.046
+ SLICE_X89Y79 FDSE (Setup_fdse_C_S) -0.429 38.617 runnerObject/pos_object_y_target_reg[3]
+ -------------------------------------------------------------------
+ required time 38.617
+ arrival time -13.474
+ -------------------------------------------------------------------
+ slack 25.143
+
+Slack (MET) : 25.143ns (required time - arrival time)
+ Source: vgaInterface/counter_f_reg[2]/C
+ (rising edge-triggered cell FDCE clocked by clk_out1_clk_wiz_0_1 {rise@0.000ns fall@20.000ns period=40.000ns})
+ Destination: runnerObject/pos_object_y_target_reg[4]/S
+ (rising edge-triggered cell FDSE clocked by clk_out1_clk_wiz_0_1 {rise@0.000ns fall@20.000ns period=40.000ns})
+ Path Group: clk_out1_clk_wiz_0_1
+ Path Type: Setup (Max at Slow Process Corner)
+ Requirement: 40.000ns (clk_out1_clk_wiz_0_1 rise@40.000ns - clk_out1_clk_wiz_0_1 rise@0.000ns)
+ Data Path Delay: 14.294ns (logic 5.777ns (40.414%) route 8.517ns (59.586%))
+ Logic Levels: 17 (CARRY4=9 LUT1=2 LUT2=2 LUT3=1 LUT4=1 LUT6=2)
+ Clock Path Skew: -0.039ns (DCD - SCD + CPR)
+ Destination Clock Delay (DCD): -1.419ns = ( 38.581 - 40.000 )
+ Source Clock Delay (SCD): -0.821ns
+ Clock Pessimism Removal (CPR): 0.559ns
+ Clock Uncertainty: 0.094ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE
+ Total System Jitter (TSJ): 0.071ns
+ Discrete Jitter (DJ): 0.175ns
+ Phase Error (PE): 0.000ns
+
+ Location Delay type Incr(ns) Path(ns) Netlist Resource(s)
+ ------------------------------------------------------------------- -------------------
+ (clock clk_out1_clk_wiz_0_1 rise edge)
+ 0.000 0.000 r
+ E3 0.000 0.000 r clk (IN)
+ net (fo=0) 0.000 0.000 pixelClk/inst/clk_in1
+ E3 IBUF (Prop_ibuf_I_O) 1.482 1.482 r pixelClk/inst/clkin1_ibufg/O
+ net (fo=1, routed) 1.233 2.715 pixelClk/inst/clk_in1_clk_wiz_0
+ MMCME2_ADV_X1Y2 MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKOUT0)
+ -7.070 -4.355 r pixelClk/inst/mmcm_adv_inst/CLKOUT0
+ net (fo=1, routed) 1.719 -2.636 pixelClk/inst/clk_out1_clk_wiz_0
+ BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.096 -2.540 r pixelClk/inst/clkout1_buf/O
+ net (fo=127, routed) 1.719 -0.821 vgaInterface/clk_out1
+ SLICE_X89Y70 FDCE r vgaInterface/counter_f_reg[2]/C
+ ------------------------------------------------------------------- -------------------
+ SLICE_X89Y70 FDCE (Prop_fdce_C_Q) 0.456 -0.365 f vgaInterface/counter_f_reg[2]/Q
+ net (fo=5, routed) 1.006 0.641 vgaInterface/counter_f_reg[2]
+ SLICE_X88Y67 LUT1 (Prop_lut1_I0_O) 0.124 0.765 r vgaInterface/FCounter_17bit_carry_i_3/O
+ net (fo=1, routed) 0.000 0.765 runnerObject/pos_object_y_target6_carry_0[1]
+ SLICE_X88Y67 CARRY4 (Prop_carry4_S[1]_CO[3])
+ 0.533 1.298 r runnerObject/FCounter_17bit_carry/CO[3]
+ net (fo=1, routed) 0.000 1.298 runnerObject/FCounter_17bit_carry_n_0
+ SLICE_X88Y68 CARRY4 (Prop_carry4_CI_O[2])
+ 0.239 1.537 r runnerObject/FCounter_17bit_carry__0/O[2]
+ net (fo=2, routed) 0.987 2.523 runnerObject/FCounter_17bit[7]
+ SLICE_X88Y71 LUT2 (Prop_lut2_I0_O) 0.301 2.824 r runnerObject/pos_object_y_target6_carry__0_i_1/O
+ net (fo=1, routed) 0.000 2.824 runnerObject/pos_object_y_target6_carry__0_i_1_n_0
+ SLICE_X88Y71 CARRY4 (Prop_carry4_S[3]_CO[3])
+ 0.376 3.200 r runnerObject/pos_object_y_target6_carry__0/CO[3]
+ net (fo=1, routed) 0.000 3.200 runnerObject/pos_object_y_target6_carry__0_n_0
+ SLICE_X88Y72 CARRY4 (Prop_carry4_CI_O[1])
+ 0.323 3.523 f runnerObject/pos_object_y_target6_carry__1/O[1]
+ net (fo=5, routed) 0.953 4.477 runnerObject/pos_object_y_target6[9]
+ SLICE_X82Y72 LUT1 (Prop_lut1_I0_O) 0.306 4.783 r runnerObject/i__carry__1_i_13/O
+ net (fo=1, routed) 0.000 4.783 runnerObject/p_0_in[9]
+ SLICE_X82Y72 CARRY4 (Prop_carry4_S[0]_O[2])
+ 0.547 5.330 f runnerObject/i__carry__1_i_9/O[2]
+ net (fo=2, routed) 0.821 6.151 runnerObject/pos_object_y_target9[11]
+ SLICE_X84Y71 LUT4 (Prop_lut4_I3_O) 0.302 6.453 r runnerObject/pos_object_y_target2_carry_i_13/O
+ net (fo=2, routed) 0.420 6.872 runnerObject/pos_object_y_target2_carry_i_13_n_0
+ SLICE_X87Y72 LUT6 (Prop_lut6_I0_O) 0.124 6.996 r runnerObject/pos_object_y_target2_carry_i_10/O
+ net (fo=34, routed) 1.081 8.077 runnerObject/pos_object_y_target2_carry_i_10_n_0
+ SLICE_X84Y70 LUT6 (Prop_lut6_I3_O) 0.124 8.201 r runnerObject/pos_object_y_target2_carry_i_9/O
+ net (fo=1, routed) 0.701 8.903 runnerObject/pos_object_y_target2_carry_i_9_n_0
+ SLICE_X85Y70 CARRY4 (Prop_carry4_S[0]_O[3])
+ 0.730 9.633 f runnerObject/pos_object_y_target2_carry/O[3]
+ net (fo=2, routed) 1.215 10.847 runnerObject/pos_object_y_target2[4]
+ SLICE_X84Y73 LUT2 (Prop_lut2_I1_O) 0.306 11.153 r runnerObject/pos_object_y_target1_carry_i_4/O
+ net (fo=1, routed) 0.000 11.153 runnerObject/pos_object_y_target1_carry_i_4_n_0
+ SLICE_X84Y73 CARRY4 (Prop_carry4_S[2]_CO[3])
+ 0.380 11.533 r runnerObject/pos_object_y_target1_carry/CO[3]
+ net (fo=1, routed) 0.000 11.533 runnerObject/pos_object_y_target1_carry_n_0
+ SLICE_X84Y74 CARRY4 (Prop_carry4_CI_CO[3])
+ 0.117 11.650 r runnerObject/pos_object_y_target1_carry__0/CO[3]
+ net (fo=1, routed) 0.009 11.659 runnerObject/pos_object_y_target1_carry__0_n_0
+ SLICE_X84Y75 CARRY4 (Prop_carry4_CI_CO[1])
+ 0.157 11.816 f runnerObject/pos_object_y_target1_carry__1/CO[1]
+ net (fo=11, routed) 0.629 12.445 runnerObject/pos_object_y_target1
+ SLICE_X86Y77 LUT3 (Prop_lut3_I0_O) 0.332 12.777 r runnerObject/pos_object_y_target[8]_i_1/O
+ net (fo=9, routed) 0.697 13.474 runnerObject/pos_object_y_target[8]_i_1_n_0
+ SLICE_X89Y79 FDSE r runnerObject/pos_object_y_target_reg[4]/S
+ ------------------------------------------------------------------- -------------------
+
+ (clock clk_out1_clk_wiz_0_1 rise edge)
+ 40.000 40.000 r
+ E3 0.000 40.000 r clk (IN)
+ net (fo=0) 0.000 40.000 pixelClk/inst/clk_in1
+ E3 IBUF (Prop_ibuf_I_O) 1.411 41.411 r pixelClk/inst/clkin1_ibufg/O
+ net (fo=1, routed) 1.162 42.573 pixelClk/inst/clk_in1_clk_wiz_0
+ MMCME2_ADV_X1Y2 MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKOUT0)
+ -7.324 35.249 r pixelClk/inst/mmcm_adv_inst/CLKOUT0
+ net (fo=1, routed) 1.639 36.888 pixelClk/inst/clk_out1_clk_wiz_0
+ BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.091 36.979 r pixelClk/inst/clkout1_buf/O
+ net (fo=127, routed) 1.601 38.581 runnerObject/clk_out1
+ SLICE_X89Y79 FDSE r runnerObject/pos_object_y_target_reg[4]/C
+ clock pessimism 0.559 39.140
+ clock uncertainty -0.094 39.046
+ SLICE_X89Y79 FDSE (Setup_fdse_C_S) -0.429 38.617 runnerObject/pos_object_y_target_reg[4]
+ -------------------------------------------------------------------
+ required time 38.617
+ arrival time -13.474
+ -------------------------------------------------------------------
+ slack 25.143
+
+
+
+
+
+Min Delay Paths
+--------------------------------------------------------------------------------------
+Slack (MET) : 0.161ns (arrival time - required time)
+ Source: vgaInterface/counter_f_reg[3]/C
+ (rising edge-triggered cell FDCE clocked by clk_out1_clk_wiz_0_1 {rise@0.000ns fall@20.000ns period=40.000ns})
+ Destination: runnerObject/fcount_edge_reg[3]/D
+ (rising edge-triggered cell FDCE clocked by clk_out1_clk_wiz_0_1 {rise@0.000ns fall@20.000ns period=40.000ns})
+ Path Group: clk_out1_clk_wiz_0_1
+ Path Type: Hold (Min at Fast Process Corner)
+ Requirement: 0.000ns (clk_out1_clk_wiz_0_1 rise@0.000ns - clk_out1_clk_wiz_0_1 rise@0.000ns)
+ Data Path Delay: 0.257ns (logic 0.141ns (54.962%) route 0.116ns (45.038%))
+ Logic Levels: 0
+ Clock Path Skew: 0.013ns (DCD - SCD - CPR)
+ Destination Clock Delay (DCD): -0.805ns
+ Source Clock Delay (SCD): -0.566ns
+ Clock Pessimism Removal (CPR): -0.252ns
+
+ Location Delay type Incr(ns) Path(ns) Netlist Resource(s)
+ ------------------------------------------------------------------- -------------------
+ (clock clk_out1_clk_wiz_0_1 rise edge)
+ 0.000 0.000 r
+ E3 0.000 0.000 r clk (IN)
+ net (fo=0) 0.000 0.000 pixelClk/inst/clk_in1
+ E3 IBUF (Prop_ibuf_I_O) 0.250 0.250 r pixelClk/inst/clkin1_ibufg/O
+ net (fo=1, routed) 0.440 0.690 pixelClk/inst/clk_in1_clk_wiz_0
+ MMCME2_ADV_X1Y2 MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKOUT0)
+ -2.379 -1.689 r pixelClk/inst/mmcm_adv_inst/CLKOUT0
+ net (fo=1, routed) 0.499 -1.190 pixelClk/inst/clk_out1_clk_wiz_0
+ BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.026 -1.164 r pixelClk/inst/clkout1_buf/O
+ net (fo=127, routed) 0.598 -0.566 vgaInterface/clk_out1
+ SLICE_X89Y70 FDCE r vgaInterface/counter_f_reg[3]/C
+ ------------------------------------------------------------------- -------------------
+ SLICE_X89Y70 FDCE (Prop_fdce_C_Q) 0.141 -0.425 r vgaInterface/counter_f_reg[3]/Q
+ net (fo=5, routed) 0.116 -0.310 runnerObject/counter_f_reg[3]
+ SLICE_X88Y70 FDCE r runnerObject/fcount_edge_reg[3]/D
+ ------------------------------------------------------------------- -------------------
+
+ (clock clk_out1_clk_wiz_0_1 rise edge)
+ 0.000 0.000 r
+ E3 0.000 0.000 r clk (IN)
+ net (fo=0) 0.000 0.000 pixelClk/inst/clk_in1
+ E3 IBUF (Prop_ibuf_I_O) 0.438 0.438 r pixelClk/inst/clkin1_ibufg/O
+ net (fo=1, routed) 0.480 0.918 pixelClk/inst/clk_in1_clk_wiz_0
+ MMCME2_ADV_X1Y2 MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKOUT0)
+ -3.163 -2.245 r pixelClk/inst/mmcm_adv_inst/CLKOUT0
+ net (fo=1, routed) 0.544 -1.702 pixelClk/inst/clk_out1_clk_wiz_0
+ BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.029 -1.673 r pixelClk/inst/clkout1_buf/O
+ net (fo=127, routed) 0.868 -0.805 runnerObject/clk_out1
+ SLICE_X88Y70 FDCE r runnerObject/fcount_edge_reg[3]/C
+ clock pessimism 0.252 -0.553
+ SLICE_X88Y70 FDCE (Hold_fdce_C_D) 0.083 -0.470 runnerObject/fcount_edge_reg[3]
+ -------------------------------------------------------------------
+ required time 0.470
+ arrival time -0.310
+ -------------------------------------------------------------------
+ slack 0.161
+
+Slack (MET) : 0.161ns (arrival time - required time)
+ Source: vgaInterface/counter_f_reg[7]/C
+ (rising edge-triggered cell FDCE clocked by clk_out1_clk_wiz_0_1 {rise@0.000ns fall@20.000ns period=40.000ns})
+ Destination: runnerObject/fcount_edge_reg[7]/D
+ (rising edge-triggered cell FDCE clocked by clk_out1_clk_wiz_0_1 {rise@0.000ns fall@20.000ns period=40.000ns})
+ Path Group: clk_out1_clk_wiz_0_1
+ Path Type: Hold (Min at Fast Process Corner)
+ Requirement: 0.000ns (clk_out1_clk_wiz_0_1 rise@0.000ns - clk_out1_clk_wiz_0_1 rise@0.000ns)
+ Data Path Delay: 0.257ns (logic 0.141ns (54.948%) route 0.116ns (45.052%))
+ Logic Levels: 0
+ Clock Path Skew: 0.013ns (DCD - SCD - CPR)
+ Destination Clock Delay (DCD): -0.806ns
+ Source Clock Delay (SCD): -0.567ns
+ Clock Pessimism Removal (CPR): -0.252ns
+
+ Location Delay type Incr(ns) Path(ns) Netlist Resource(s)
+ ------------------------------------------------------------------- -------------------
+ (clock clk_out1_clk_wiz_0_1 rise edge)
+ 0.000 0.000 r
+ E3 0.000 0.000 r clk (IN)
+ net (fo=0) 0.000 0.000 pixelClk/inst/clk_in1
+ E3 IBUF (Prop_ibuf_I_O) 0.250 0.250 r pixelClk/inst/clkin1_ibufg/O
+ net (fo=1, routed) 0.440 0.690 pixelClk/inst/clk_in1_clk_wiz_0
+ MMCME2_ADV_X1Y2 MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKOUT0)
+ -2.379 -1.689 r pixelClk/inst/mmcm_adv_inst/CLKOUT0
+ net (fo=1, routed) 0.499 -1.190 pixelClk/inst/clk_out1_clk_wiz_0
+ BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.026 -1.164 r pixelClk/inst/clkout1_buf/O
+ net (fo=127, routed) 0.597 -0.567 vgaInterface/clk_out1
+ SLICE_X89Y71 FDCE r vgaInterface/counter_f_reg[7]/C
+ ------------------------------------------------------------------- -------------------
+ SLICE_X89Y71 FDCE (Prop_fdce_C_Q) 0.141 -0.426 r vgaInterface/counter_f_reg[7]/Q
+ net (fo=5, routed) 0.116 -0.311 runnerObject/counter_f_reg[7]
+ SLICE_X88Y71 FDCE r runnerObject/fcount_edge_reg[7]/D
+ ------------------------------------------------------------------- -------------------
+
+ (clock clk_out1_clk_wiz_0_1 rise edge)
+ 0.000 0.000 r
+ E3 0.000 0.000 r clk (IN)
+ net (fo=0) 0.000 0.000 pixelClk/inst/clk_in1
+ E3 IBUF (Prop_ibuf_I_O) 0.438 0.438 r pixelClk/inst/clkin1_ibufg/O
+ net (fo=1, routed) 0.480 0.918 pixelClk/inst/clk_in1_clk_wiz_0
+ MMCME2_ADV_X1Y2 MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKOUT0)
+ -3.163 -2.245 r pixelClk/inst/mmcm_adv_inst/CLKOUT0
+ net (fo=1, routed) 0.544 -1.702 pixelClk/inst/clk_out1_clk_wiz_0
+ BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.029 -1.673 r pixelClk/inst/clkout1_buf/O
+ net (fo=127, routed) 0.867 -0.806 runnerObject/clk_out1
+ SLICE_X88Y71 FDCE r runnerObject/fcount_edge_reg[7]/C
+ clock pessimism 0.252 -0.554
+ SLICE_X88Y71 FDCE (Hold_fdce_C_D) 0.083 -0.471 runnerObject/fcount_edge_reg[7]
+ -------------------------------------------------------------------
+ required time 0.471
+ arrival time -0.311
+ -------------------------------------------------------------------
+ slack 0.161
+
+Slack (MET) : 0.166ns (arrival time - required time)
+ Source: vgaInterface/counter_f_reg[4]/C
+ (rising edge-triggered cell FDCE clocked by clk_out1_clk_wiz_0_1 {rise@0.000ns fall@20.000ns period=40.000ns})
+ Destination: runnerObject/fcount_edge_reg[4]/D
+ (rising edge-triggered cell FDCE clocked by clk_out1_clk_wiz_0_1 {rise@0.000ns fall@20.000ns period=40.000ns})
+ Path Group: clk_out1_clk_wiz_0_1
+ Path Type: Hold (Min at Fast Process Corner)
+ Requirement: 0.000ns (clk_out1_clk_wiz_0_1 rise@0.000ns - clk_out1_clk_wiz_0_1 rise@0.000ns)
+ Data Path Delay: 0.264ns (logic 0.141ns (53.502%) route 0.123ns (46.498%))
+ Logic Levels: 0
+ Clock Path Skew: 0.013ns (DCD - SCD - CPR)
+ Destination Clock Delay (DCD): -0.806ns
+ Source Clock Delay (SCD): -0.567ns
+ Clock Pessimism Removal (CPR): -0.252ns
+
+ Location Delay type Incr(ns) Path(ns) Netlist Resource(s)
+ ------------------------------------------------------------------- -------------------
+ (clock clk_out1_clk_wiz_0_1 rise edge)
+ 0.000 0.000 r
+ E3 0.000 0.000 r clk (IN)
+ net (fo=0) 0.000 0.000 pixelClk/inst/clk_in1
+ E3 IBUF (Prop_ibuf_I_O) 0.250 0.250 r pixelClk/inst/clkin1_ibufg/O
+ net (fo=1, routed) 0.440 0.690 pixelClk/inst/clk_in1_clk_wiz_0
+ MMCME2_ADV_X1Y2 MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKOUT0)
+ -2.379 -1.689 r pixelClk/inst/mmcm_adv_inst/CLKOUT0
+ net (fo=1, routed) 0.499 -1.190 pixelClk/inst/clk_out1_clk_wiz_0
+ BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.026 -1.164 r pixelClk/inst/clkout1_buf/O
+ net (fo=127, routed) 0.597 -0.567 vgaInterface/clk_out1
+ SLICE_X89Y71 FDCE r vgaInterface/counter_f_reg[4]/C
+ ------------------------------------------------------------------- -------------------
+ SLICE_X89Y71 FDCE (Prop_fdce_C_Q) 0.141 -0.426 r vgaInterface/counter_f_reg[4]/Q
+ net (fo=5, routed) 0.123 -0.304 runnerObject/counter_f_reg[4]
+ SLICE_X88Y71 FDCE r runnerObject/fcount_edge_reg[4]/D
+ ------------------------------------------------------------------- -------------------
+
+ (clock clk_out1_clk_wiz_0_1 rise edge)
+ 0.000 0.000 r
+ E3 0.000 0.000 r clk (IN)
+ net (fo=0) 0.000 0.000 pixelClk/inst/clk_in1
+ E3 IBUF (Prop_ibuf_I_O) 0.438 0.438 r pixelClk/inst/clkin1_ibufg/O
+ net (fo=1, routed) 0.480 0.918 pixelClk/inst/clk_in1_clk_wiz_0
+ MMCME2_ADV_X1Y2 MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKOUT0)
+ -3.163 -2.245 r pixelClk/inst/mmcm_adv_inst/CLKOUT0
+ net (fo=1, routed) 0.544 -1.702 pixelClk/inst/clk_out1_clk_wiz_0
+ BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.029 -1.673 r pixelClk/inst/clkout1_buf/O
+ net (fo=127, routed) 0.867 -0.806 runnerObject/clk_out1
+ SLICE_X88Y71 FDCE r runnerObject/fcount_edge_reg[4]/C
+ clock pessimism 0.252 -0.554
+ SLICE_X88Y71 FDCE (Hold_fdce_C_D) 0.085 -0.469 runnerObject/fcount_edge_reg[4]
+ -------------------------------------------------------------------
+ required time 0.469
+ arrival time -0.304
+ -------------------------------------------------------------------
+ slack 0.166
+
+Slack (MET) : 0.179ns (arrival time - required time)
+ Source: runnerObject/pos_object_y_target_reg[4]/C
+ (rising edge-triggered cell FDSE clocked by clk_out1_clk_wiz_0_1 {rise@0.000ns fall@20.000ns period=40.000ns})
+ Destination: runnerObject/pos_object_y_actual_reg[4]/D
+ (rising edge-triggered cell FDRE clocked by clk_out1_clk_wiz_0_1 {rise@0.000ns fall@20.000ns period=40.000ns})
+ Path Group: clk_out1_clk_wiz_0_1
+ Path Type: Hold (Min at Fast Process Corner)
+ Requirement: 0.000ns (clk_out1_clk_wiz_0_1 rise@0.000ns - clk_out1_clk_wiz_0_1 rise@0.000ns)
+ Data Path Delay: 0.263ns (logic 0.141ns (53.569%) route 0.122ns (46.431%))
+ Logic Levels: 0
+ Clock Path Skew: 0.014ns (DCD - SCD - CPR)
+ Destination Clock Delay (DCD): -0.805ns
+ Source Clock Delay (SCD): -0.566ns
+ Clock Pessimism Removal (CPR): -0.253ns
+
+ Location Delay type Incr(ns) Path(ns) Netlist Resource(s)
+ ------------------------------------------------------------------- -------------------
+ (clock clk_out1_clk_wiz_0_1 rise edge)
+ 0.000 0.000 r
+ E3 0.000 0.000 r clk (IN)
+ net (fo=0) 0.000 0.000 pixelClk/inst/clk_in1
+ E3 IBUF (Prop_ibuf_I_O) 0.250 0.250 r pixelClk/inst/clkin1_ibufg/O
+ net (fo=1, routed) 0.440 0.690 pixelClk/inst/clk_in1_clk_wiz_0
+ MMCME2_ADV_X1Y2 MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKOUT0)
+ -2.379 -1.689 r pixelClk/inst/mmcm_adv_inst/CLKOUT0
+ net (fo=1, routed) 0.499 -1.190 pixelClk/inst/clk_out1_clk_wiz_0
+ BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.026 -1.164 r pixelClk/inst/clkout1_buf/O
+ net (fo=127, routed) 0.598 -0.566 runnerObject/clk_out1
+ SLICE_X89Y79 FDSE r runnerObject/pos_object_y_target_reg[4]/C
+ ------------------------------------------------------------------- -------------------
+ SLICE_X89Y79 FDSE (Prop_fdse_C_Q) 0.141 -0.425 r runnerObject/pos_object_y_target_reg[4]/Q
+ net (fo=4, routed) 0.122 -0.303 runnerObject/pos_object_y_target[4]
+ SLICE_X87Y79 FDRE r runnerObject/pos_object_y_actual_reg[4]/D
+ ------------------------------------------------------------------- -------------------
+
+ (clock clk_out1_clk_wiz_0_1 rise edge)
+ 0.000 0.000 r
+ E3 0.000 0.000 r clk (IN)
+ net (fo=0) 0.000 0.000 pixelClk/inst/clk_in1
+ E3 IBUF (Prop_ibuf_I_O) 0.438 0.438 r pixelClk/inst/clkin1_ibufg/O
+ net (fo=1, routed) 0.480 0.918 pixelClk/inst/clk_in1_clk_wiz_0
+ MMCME2_ADV_X1Y2 MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKOUT0)
+ -3.163 -2.245 r pixelClk/inst/mmcm_adv_inst/CLKOUT0
+ net (fo=1, routed) 0.544 -1.702 pixelClk/inst/clk_out1_clk_wiz_0
+ BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.029 -1.673 r pixelClk/inst/clkout1_buf/O
+ net (fo=127, routed) 0.868 -0.805 runnerObject/clk_out1
+ SLICE_X87Y79 FDRE r runnerObject/pos_object_y_actual_reg[4]/C
+ clock pessimism 0.253 -0.552
+ SLICE_X87Y79 FDRE (Hold_fdre_C_D) 0.070 -0.482 runnerObject/pos_object_y_actual_reg[4]
+ -------------------------------------------------------------------
+ required time 0.482
+ arrival time -0.303
+ -------------------------------------------------------------------
+ slack 0.179
+
+Slack (MET) : 0.189ns (arrival time - required time)
+ Source: largeObstacle/pos_object_x_target_reg[0]/C
+ (rising edge-triggered cell FDCE clocked by clk_out1_clk_wiz_0_1 {rise@0.000ns fall@20.000ns period=40.000ns})
+ Destination: largeObstacle/pos_object_x_actual_reg[0]/D
+ (rising edge-triggered cell FDRE clocked by clk_out1_clk_wiz_0_1 {rise@0.000ns fall@20.000ns period=40.000ns})
+ Path Group: clk_out1_clk_wiz_0_1
+ Path Type: Hold (Min at Fast Process Corner)
+ Requirement: 0.000ns (clk_out1_clk_wiz_0_1 rise@0.000ns - clk_out1_clk_wiz_0_1 rise@0.000ns)
+ Data Path Delay: 0.272ns (logic 0.141ns (51.925%) route 0.131ns (48.075%))
+ Logic Levels: 0
+ Clock Path Skew: 0.013ns (DCD - SCD - CPR)
+ Destination Clock Delay (DCD): -0.805ns
+ Source Clock Delay (SCD): -0.565ns
+ Clock Pessimism Removal (CPR): -0.253ns
+
+ Location Delay type Incr(ns) Path(ns) Netlist Resource(s)
+ ------------------------------------------------------------------- -------------------
+ (clock clk_out1_clk_wiz_0_1 rise edge)
+ 0.000 0.000 r
+ E3 0.000 0.000 r clk (IN)
+ net (fo=0) 0.000 0.000 pixelClk/inst/clk_in1
+ E3 IBUF (Prop_ibuf_I_O) 0.250 0.250 r pixelClk/inst/clkin1_ibufg/O
+ net (fo=1, routed) 0.440 0.690 pixelClk/inst/clk_in1_clk_wiz_0
+ MMCME2_ADV_X1Y2 MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKOUT0)
+ -2.379 -1.689 r pixelClk/inst/mmcm_adv_inst/CLKOUT0
+ net (fo=1, routed) 0.499 -1.190 pixelClk/inst/clk_out1_clk_wiz_0
+ BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.026 -1.164 r pixelClk/inst/clkout1_buf/O
+ net (fo=127, routed) 0.599 -0.565 largeObstacle/CLK
+ SLICE_X82Y81 FDCE r largeObstacle/pos_object_x_target_reg[0]/C
+ ------------------------------------------------------------------- -------------------
+ SLICE_X82Y81 FDCE (Prop_fdce_C_Q) 0.141 -0.424 r largeObstacle/pos_object_x_target_reg[0]/Q
+ net (fo=2, routed) 0.131 -0.294 largeObstacle/pos_object_x_target_reg[0]
+ SLICE_X82Y80 FDRE r largeObstacle/pos_object_x_actual_reg[0]/D
+ ------------------------------------------------------------------- -------------------
+
+ (clock clk_out1_clk_wiz_0_1 rise edge)
+ 0.000 0.000 r
+ E3 0.000 0.000 r clk (IN)
+ net (fo=0) 0.000 0.000 pixelClk/inst/clk_in1
+ E3 IBUF (Prop_ibuf_I_O) 0.438 0.438 r pixelClk/inst/clkin1_ibufg/O
+ net (fo=1, routed) 0.480 0.918 pixelClk/inst/clk_in1_clk_wiz_0
+ MMCME2_ADV_X1Y2 MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKOUT0)
+ -3.163 -2.245 r pixelClk/inst/mmcm_adv_inst/CLKOUT0
+ net (fo=1, routed) 0.544 -1.702 pixelClk/inst/clk_out1_clk_wiz_0
+ BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.029 -1.673 r pixelClk/inst/clkout1_buf/O
+ net (fo=127, routed) 0.868 -0.805 largeObstacle/CLK
+ SLICE_X82Y80 FDRE r largeObstacle/pos_object_x_actual_reg[0]/C
+ clock pessimism 0.253 -0.552
+ SLICE_X82Y80 FDRE (Hold_fdre_C_D) 0.070 -0.482 largeObstacle/pos_object_x_actual_reg[0]
+ -------------------------------------------------------------------
+ required time 0.482
+ arrival time -0.294
+ -------------------------------------------------------------------
+ slack 0.189
+
+Slack (MET) : 0.198ns (arrival time - required time)
+ Source: runnerObject/pos_object_y_target_reg[2]/C
+ (rising edge-triggered cell FDSE clocked by clk_out1_clk_wiz_0_1 {rise@0.000ns fall@20.000ns period=40.000ns})
+ Destination: runnerObject/pos_object_y_actual_reg[2]/D
+ (rising edge-triggered cell FDRE clocked by clk_out1_clk_wiz_0_1 {rise@0.000ns fall@20.000ns period=40.000ns})
+ Path Group: clk_out1_clk_wiz_0_1
+ Path Type: Hold (Min at Fast Process Corner)
+ Requirement: 0.000ns (clk_out1_clk_wiz_0_1 rise@0.000ns - clk_out1_clk_wiz_0_1 rise@0.000ns)
+ Data Path Delay: 0.282ns (logic 0.141ns (49.964%) route 0.141ns (50.036%))
+ Logic Levels: 0
+ Clock Path Skew: 0.014ns (DCD - SCD - CPR)
+ Destination Clock Delay (DCD): -0.805ns
+ Source Clock Delay (SCD): -0.566ns
+ Clock Pessimism Removal (CPR): -0.253ns
+
+ Location Delay type Incr(ns) Path(ns) Netlist Resource(s)
+ ------------------------------------------------------------------- -------------------
+ (clock clk_out1_clk_wiz_0_1 rise edge)
+ 0.000 0.000 r
+ E3 0.000 0.000 r clk (IN)
+ net (fo=0) 0.000 0.000 pixelClk/inst/clk_in1
+ E3 IBUF (Prop_ibuf_I_O) 0.250 0.250 r pixelClk/inst/clkin1_ibufg/O
+ net (fo=1, routed) 0.440 0.690 pixelClk/inst/clk_in1_clk_wiz_0
+ MMCME2_ADV_X1Y2 MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKOUT0)
+ -2.379 -1.689 r pixelClk/inst/mmcm_adv_inst/CLKOUT0
+ net (fo=1, routed) 0.499 -1.190 pixelClk/inst/clk_out1_clk_wiz_0
+ BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.026 -1.164 r pixelClk/inst/clkout1_buf/O
+ net (fo=127, routed) 0.598 -0.566 runnerObject/clk_out1
+ SLICE_X89Y79 FDSE r runnerObject/pos_object_y_target_reg[2]/C
+ ------------------------------------------------------------------- -------------------
+ SLICE_X89Y79 FDSE (Prop_fdse_C_Q) 0.141 -0.425 r runnerObject/pos_object_y_target_reg[2]/Q
+ net (fo=6, routed) 0.141 -0.284 runnerObject/pos_object_y_target[2]
+ SLICE_X86Y79 FDRE r runnerObject/pos_object_y_actual_reg[2]/D
+ ------------------------------------------------------------------- -------------------
+
+ (clock clk_out1_clk_wiz_0_1 rise edge)
+ 0.000 0.000 r
+ E3 0.000 0.000 r clk (IN)
+ net (fo=0) 0.000 0.000 pixelClk/inst/clk_in1
+ E3 IBUF (Prop_ibuf_I_O) 0.438 0.438 r pixelClk/inst/clkin1_ibufg/O
+ net (fo=1, routed) 0.480 0.918 pixelClk/inst/clk_in1_clk_wiz_0
+ MMCME2_ADV_X1Y2 MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKOUT0)
+ -3.163 -2.245 r pixelClk/inst/mmcm_adv_inst/CLKOUT0
+ net (fo=1, routed) 0.544 -1.702 pixelClk/inst/clk_out1_clk_wiz_0
+ BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.029 -1.673 r pixelClk/inst/clkout1_buf/O
+ net (fo=127, routed) 0.868 -0.805 runnerObject/clk_out1
+ SLICE_X86Y79 FDRE r runnerObject/pos_object_y_actual_reg[2]/C
+ clock pessimism 0.253 -0.552
+ SLICE_X86Y79 FDRE (Hold_fdre_C_D) 0.070 -0.482 runnerObject/pos_object_y_actual_reg[2]
+ -------------------------------------------------------------------
+ required time 0.482
+ arrival time -0.284
+ -------------------------------------------------------------------
+ slack 0.198
+
+Slack (MET) : 0.201ns (arrival time - required time)
+ Source: runnerObject/pos_object_y_target_reg[0]/C
+ (rising edge-triggered cell FDRE clocked by clk_out1_clk_wiz_0_1 {rise@0.000ns fall@20.000ns period=40.000ns})
+ Destination: runnerObject/pos_object_y_actual_reg[0]/D
+ (rising edge-triggered cell FDRE clocked by clk_out1_clk_wiz_0_1 {rise@0.000ns fall@20.000ns period=40.000ns})
+ Path Group: clk_out1_clk_wiz_0_1
+ Path Type: Hold (Min at Fast Process Corner)
+ Requirement: 0.000ns (clk_out1_clk_wiz_0_1 rise@0.000ns - clk_out1_clk_wiz_0_1 rise@0.000ns)
+ Data Path Delay: 0.285ns (logic 0.141ns (49.436%) route 0.144ns (50.564%))
+ Logic Levels: 0
+ Clock Path Skew: 0.014ns (DCD - SCD - CPR)
+ Destination Clock Delay (DCD): -0.805ns
+ Source Clock Delay (SCD): -0.566ns
+ Clock Pessimism Removal (CPR): -0.253ns
+
+ Location Delay type Incr(ns) Path(ns) Netlist Resource(s)
+ ------------------------------------------------------------------- -------------------
+ (clock clk_out1_clk_wiz_0_1 rise edge)
+ 0.000 0.000 r
+ E3 0.000 0.000 r clk (IN)
+ net (fo=0) 0.000 0.000 pixelClk/inst/clk_in1
+ E3 IBUF (Prop_ibuf_I_O) 0.250 0.250 r pixelClk/inst/clkin1_ibufg/O
+ net (fo=1, routed) 0.440 0.690 pixelClk/inst/clk_in1_clk_wiz_0
+ MMCME2_ADV_X1Y2 MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKOUT0)
+ -2.379 -1.689 r pixelClk/inst/mmcm_adv_inst/CLKOUT0
+ net (fo=1, routed) 0.499 -1.190 pixelClk/inst/clk_out1_clk_wiz_0
+ BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.026 -1.164 r pixelClk/inst/clkout1_buf/O
+ net (fo=127, routed) 0.598 -0.566 runnerObject/clk_out1
+ SLICE_X89Y79 FDRE r runnerObject/pos_object_y_target_reg[0]/C
+ ------------------------------------------------------------------- -------------------
+ SLICE_X89Y79 FDRE (Prop_fdre_C_Q) 0.141 -0.425 r runnerObject/pos_object_y_target_reg[0]/Q
+ net (fo=8, routed) 0.144 -0.281 runnerObject/pos_object_y_target[0]
+ SLICE_X87Y79 FDRE r runnerObject/pos_object_y_actual_reg[0]/D
+ ------------------------------------------------------------------- -------------------
+
+ (clock clk_out1_clk_wiz_0_1 rise edge)
+ 0.000 0.000 r
+ E3 0.000 0.000 r clk (IN)
+ net (fo=0) 0.000 0.000 pixelClk/inst/clk_in1
+ E3 IBUF (Prop_ibuf_I_O) 0.438 0.438 r pixelClk/inst/clkin1_ibufg/O
+ net (fo=1, routed) 0.480 0.918 pixelClk/inst/clk_in1_clk_wiz_0
+ MMCME2_ADV_X1Y2 MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKOUT0)
+ -3.163 -2.245 r pixelClk/inst/mmcm_adv_inst/CLKOUT0
+ net (fo=1, routed) 0.544 -1.702 pixelClk/inst/clk_out1_clk_wiz_0
+ BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.029 -1.673 r pixelClk/inst/clkout1_buf/O
+ net (fo=127, routed) 0.868 -0.805 runnerObject/clk_out1
+ SLICE_X87Y79 FDRE r runnerObject/pos_object_y_actual_reg[0]/C
+ clock pessimism 0.253 -0.552
+ SLICE_X87Y79 FDRE (Hold_fdre_C_D) 0.070 -0.482 runnerObject/pos_object_y_actual_reg[0]
+ -------------------------------------------------------------------
+ required time 0.482
+ arrival time -0.281
+ -------------------------------------------------------------------
+ slack 0.201
+
+Slack (MET) : 0.204ns (arrival time - required time)
+ Source: vgaInterface/counter_f_reg[1]/C
+ (rising edge-triggered cell FDCE clocked by clk_out1_clk_wiz_0_1 {rise@0.000ns fall@20.000ns period=40.000ns})
+ Destination: runnerObject/fcount_edge_reg[1]/D
+ (rising edge-triggered cell FDCE clocked by clk_out1_clk_wiz_0_1 {rise@0.000ns fall@20.000ns period=40.000ns})
+ Path Group: clk_out1_clk_wiz_0_1
+ Path Type: Hold (Min at Fast Process Corner)
+ Requirement: 0.000ns (clk_out1_clk_wiz_0_1 rise@0.000ns - clk_out1_clk_wiz_0_1 rise@0.000ns)
+ Data Path Delay: 0.303ns (logic 0.141ns (46.482%) route 0.162ns (53.518%))
+ Logic Levels: 0
+ Clock Path Skew: 0.013ns (DCD - SCD - CPR)
+ Destination Clock Delay (DCD): -0.805ns
+ Source Clock Delay (SCD): -0.566ns
+ Clock Pessimism Removal (CPR): -0.252ns
+
+ Location Delay type Incr(ns) Path(ns) Netlist Resource(s)
+ ------------------------------------------------------------------- -------------------
+ (clock clk_out1_clk_wiz_0_1 rise edge)
+ 0.000 0.000 r
+ E3 0.000 0.000 r clk (IN)
+ net (fo=0) 0.000 0.000 pixelClk/inst/clk_in1
+ E3 IBUF (Prop_ibuf_I_O) 0.250 0.250 r pixelClk/inst/clkin1_ibufg/O
+ net (fo=1, routed) 0.440 0.690 pixelClk/inst/clk_in1_clk_wiz_0
+ MMCME2_ADV_X1Y2 MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKOUT0)
+ -2.379 -1.689 r pixelClk/inst/mmcm_adv_inst/CLKOUT0
+ net (fo=1, routed) 0.499 -1.190 pixelClk/inst/clk_out1_clk_wiz_0
+ BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.026 -1.164 r pixelClk/inst/clkout1_buf/O
+ net (fo=127, routed) 0.598 -0.566 vgaInterface/clk_out1
+ SLICE_X89Y70 FDCE r vgaInterface/counter_f_reg[1]/C
+ ------------------------------------------------------------------- -------------------
+ SLICE_X89Y70 FDCE (Prop_fdce_C_Q) 0.141 -0.425 r vgaInterface/counter_f_reg[1]/Q
+ net (fo=5, routed) 0.162 -0.263 runnerObject/counter_f_reg[1]
+ SLICE_X88Y70 FDCE r runnerObject/fcount_edge_reg[1]/D
+ ------------------------------------------------------------------- -------------------
+
+ (clock clk_out1_clk_wiz_0_1 rise edge)
+ 0.000 0.000 r
+ E3 0.000 0.000 r clk (IN)
+ net (fo=0) 0.000 0.000 pixelClk/inst/clk_in1
+ E3 IBUF (Prop_ibuf_I_O) 0.438 0.438 r pixelClk/inst/clkin1_ibufg/O
+ net (fo=1, routed) 0.480 0.918 pixelClk/inst/clk_in1_clk_wiz_0
+ MMCME2_ADV_X1Y2 MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKOUT0)
+ -3.163 -2.245 r pixelClk/inst/mmcm_adv_inst/CLKOUT0
+ net (fo=1, routed) 0.544 -1.702 pixelClk/inst/clk_out1_clk_wiz_0
+ BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.029 -1.673 r pixelClk/inst/clkout1_buf/O
+ net (fo=127, routed) 0.868 -0.805 runnerObject/clk_out1
+ SLICE_X88Y70 FDCE r runnerObject/fcount_edge_reg[1]/C
+ clock pessimism 0.252 -0.553
+ SLICE_X88Y70 FDCE (Hold_fdce_C_D) 0.086 -0.467 runnerObject/fcount_edge_reg[1]
+ -------------------------------------------------------------------
+ required time 0.467
+ arrival time -0.263
+ -------------------------------------------------------------------
+ slack 0.204
+
+Slack (MET) : 0.204ns (arrival time - required time)
+ Source: vgaInterface/counter_f_reg[5]/C
+ (rising edge-triggered cell FDCE clocked by clk_out1_clk_wiz_0_1 {rise@0.000ns fall@20.000ns period=40.000ns})
+ Destination: runnerObject/fcount_edge_reg[5]/D
+ (rising edge-triggered cell FDCE clocked by clk_out1_clk_wiz_0_1 {rise@0.000ns fall@20.000ns period=40.000ns})
+ Path Group: clk_out1_clk_wiz_0_1
+ Path Type: Hold (Min at Fast Process Corner)
+ Requirement: 0.000ns (clk_out1_clk_wiz_0_1 rise@0.000ns - clk_out1_clk_wiz_0_1 rise@0.000ns)
+ Data Path Delay: 0.303ns (logic 0.141ns (46.472%) route 0.162ns (53.528%))
+ Logic Levels: 0
+ Clock Path Skew: 0.013ns (DCD - SCD - CPR)
+ Destination Clock Delay (DCD): -0.806ns
+ Source Clock Delay (SCD): -0.567ns
+ Clock Pessimism Removal (CPR): -0.252ns
+
+ Location Delay type Incr(ns) Path(ns) Netlist Resource(s)
+ ------------------------------------------------------------------- -------------------
+ (clock clk_out1_clk_wiz_0_1 rise edge)
+ 0.000 0.000 r
+ E3 0.000 0.000 r clk (IN)
+ net (fo=0) 0.000 0.000 pixelClk/inst/clk_in1
+ E3 IBUF (Prop_ibuf_I_O) 0.250 0.250 r pixelClk/inst/clkin1_ibufg/O
+ net (fo=1, routed) 0.440 0.690 pixelClk/inst/clk_in1_clk_wiz_0
+ MMCME2_ADV_X1Y2 MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKOUT0)
+ -2.379 -1.689 r pixelClk/inst/mmcm_adv_inst/CLKOUT0
+ net (fo=1, routed) 0.499 -1.190 pixelClk/inst/clk_out1_clk_wiz_0
+ BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.026 -1.164 r pixelClk/inst/clkout1_buf/O
+ net (fo=127, routed) 0.597 -0.567 vgaInterface/clk_out1
+ SLICE_X89Y71 FDCE r vgaInterface/counter_f_reg[5]/C
+ ------------------------------------------------------------------- -------------------
+ SLICE_X89Y71 FDCE (Prop_fdce_C_Q) 0.141 -0.426 r vgaInterface/counter_f_reg[5]/Q
+ net (fo=5, routed) 0.162 -0.264 runnerObject/counter_f_reg[5]
+ SLICE_X88Y71 FDCE r runnerObject/fcount_edge_reg[5]/D
+ ------------------------------------------------------------------- -------------------
+
+ (clock clk_out1_clk_wiz_0_1 rise edge)
+ 0.000 0.000 r
+ E3 0.000 0.000 r clk (IN)
+ net (fo=0) 0.000 0.000 pixelClk/inst/clk_in1
+ E3 IBUF (Prop_ibuf_I_O) 0.438 0.438 r pixelClk/inst/clkin1_ibufg/O
+ net (fo=1, routed) 0.480 0.918 pixelClk/inst/clk_in1_clk_wiz_0
+ MMCME2_ADV_X1Y2 MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKOUT0)
+ -3.163 -2.245 r pixelClk/inst/mmcm_adv_inst/CLKOUT0
+ net (fo=1, routed) 0.544 -1.702 pixelClk/inst/clk_out1_clk_wiz_0
+ BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.029 -1.673 r pixelClk/inst/clkout1_buf/O
+ net (fo=127, routed) 0.867 -0.806 runnerObject/clk_out1
+ SLICE_X88Y71 FDCE r runnerObject/fcount_edge_reg[5]/C
+ clock pessimism 0.252 -0.554
+ SLICE_X88Y71 FDCE (Hold_fdce_C_D) 0.086 -0.468 runnerObject/fcount_edge_reg[5]
+ -------------------------------------------------------------------
+ required time 0.468
+ arrival time -0.264
+ -------------------------------------------------------------------
+ slack 0.204
+
+Slack (MET) : 0.214ns (arrival time - required time)
+ Source: largeObstacle/pos_object_x_target_reg[4]/C
+ (rising edge-triggered cell FDCE clocked by clk_out1_clk_wiz_0_1 {rise@0.000ns fall@20.000ns period=40.000ns})
+ Destination: largeObstacle/pos_object_x_actual_reg[4]/D
+ (rising edge-triggered cell FDRE clocked by clk_out1_clk_wiz_0_1 {rise@0.000ns fall@20.000ns period=40.000ns})
+ Path Group: clk_out1_clk_wiz_0_1
+ Path Type: Hold (Min at Fast Process Corner)
+ Requirement: 0.000ns (clk_out1_clk_wiz_0_1 rise@0.000ns - clk_out1_clk_wiz_0_1 rise@0.000ns)
+ Data Path Delay: 0.288ns (logic 0.164ns (56.904%) route 0.124ns (43.096%))
+ Logic Levels: 0
+ Clock Path Skew: 0.015ns (DCD - SCD - CPR)
+ Destination Clock Delay (DCD): -0.810ns
+ Source Clock Delay (SCD): -0.572ns
+ Clock Pessimism Removal (CPR): -0.253ns
+
+ Location Delay type Incr(ns) Path(ns) Netlist Resource(s)
+ ------------------------------------------------------------------- -------------------
+ (clock clk_out1_clk_wiz_0_1 rise edge)
+ 0.000 0.000 r
+ E3 0.000 0.000 r clk (IN)
+ net (fo=0) 0.000 0.000 pixelClk/inst/clk_in1
+ E3 IBUF (Prop_ibuf_I_O) 0.250 0.250 r pixelClk/inst/clkin1_ibufg/O
+ net (fo=1, routed) 0.440 0.690 pixelClk/inst/clk_in1_clk_wiz_0
+ MMCME2_ADV_X1Y2 MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKOUT0)
+ -2.379 -1.689 r pixelClk/inst/mmcm_adv_inst/CLKOUT0
+ net (fo=1, routed) 0.499 -1.190 pixelClk/inst/clk_out1_clk_wiz_0
+ BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.026 -1.164 r pixelClk/inst/clkout1_buf/O
+ net (fo=127, routed) 0.592 -0.572 largeObstacle/CLK
+ SLICE_X80Y78 FDCE r largeObstacle/pos_object_x_target_reg[4]/C
+ ------------------------------------------------------------------- -------------------
+ SLICE_X80Y78 FDCE (Prop_fdce_C_Q) 0.164 -0.408 r largeObstacle/pos_object_x_target_reg[4]/Q
+ net (fo=5, routed) 0.124 -0.284 largeObstacle/pos_object_x_target_reg[4]
+ SLICE_X80Y79 FDRE r largeObstacle/pos_object_x_actual_reg[4]/D
+ ------------------------------------------------------------------- -------------------
+
+ (clock clk_out1_clk_wiz_0_1 rise edge)
+ 0.000 0.000 r
+ E3 0.000 0.000 r clk (IN)
+ net (fo=0) 0.000 0.000 pixelClk/inst/clk_in1
+ E3 IBUF (Prop_ibuf_I_O) 0.438 0.438 r pixelClk/inst/clkin1_ibufg/O
+ net (fo=1, routed) 0.480 0.918 pixelClk/inst/clk_in1_clk_wiz_0
+ MMCME2_ADV_X1Y2 MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKOUT0)
+ -3.163 -2.245 r pixelClk/inst/mmcm_adv_inst/CLKOUT0
+ net (fo=1, routed) 0.544 -1.702 pixelClk/inst/clk_out1_clk_wiz_0
+ BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.029 -1.673 r pixelClk/inst/clkout1_buf/O
+ net (fo=127, routed) 0.863 -0.810 largeObstacle/CLK
+ SLICE_X80Y79 FDRE r largeObstacle/pos_object_x_actual_reg[4]/C
+ clock pessimism 0.253 -0.557
+ SLICE_X80Y79 FDRE (Hold_fdre_C_D) 0.059 -0.498 largeObstacle/pos_object_x_actual_reg[4]
+ -------------------------------------------------------------------
+ required time 0.498
+ arrival time -0.284
+ -------------------------------------------------------------------
+ slack 0.214
+
+
+
+
+
+Pulse Width Checks
+--------------------------------------------------------------------------------------
+Clock Name: clk_out1_clk_wiz_0_1
+Waveform(ns): { 0.000 20.000 }
+Period(ns): 40.000
+Sources: { pixelClk/inst/mmcm_adv_inst/CLKOUT0 }
+
+Check Type Corner Lib Pin Reference Pin Required(ns) Actual(ns) Slack(ns) Location Pin
+Min Period n/a BUFG/I n/a 2.155 40.000 37.845 BUFGCTRL_X0Y16 pixelClk/inst/clkout1_buf/I
+Min Period n/a MMCME2_ADV/CLKOUT0 n/a 1.249 40.000 38.751 MMCME2_ADV_X1Y2 pixelClk/inst/mmcm_adv_inst/CLKOUT0
+Min Period n/a FDCE/C n/a 1.000 40.000 39.000 SLICE_X89Y67 collisionDetection/collision_cnt_reg[0]/C
+Min Period n/a FDCE/C n/a 1.000 40.000 39.000 SLICE_X88Y69 collisionDetection/collision_cnt_reg[10]/C
+Min Period n/a FDCE/C n/a 1.000 40.000 39.000 SLICE_X89Y69 collisionDetection/collision_cnt_reg[10]_lopt_replica/C
+Min Period n/a FDCE/C n/a 1.000 40.000 39.000 SLICE_X88Y67 collisionDetection/collision_cnt_reg[11]/C
+Min Period n/a FDCE/C n/a 1.000 40.000 39.000 SLICE_X89Y69 collisionDetection/collision_cnt_reg[12]/C
+Min Period n/a FDCE/C n/a 1.000 40.000 39.000 SLICE_X89Y69 collisionDetection/collision_cnt_reg[13]/C
+Min Period n/a FDCE/C n/a 1.000 40.000 39.000 SLICE_X89Y69 collisionDetection/collision_cnt_reg[14]/C
+Min Period n/a FDCE/C n/a 1.000 40.000 39.000 SLICE_X88Y69 collisionDetection/collision_cnt_reg[15]/C
+Max Period n/a MMCME2_ADV/CLKOUT0 n/a 213.360 40.000 173.360 MMCME2_ADV_X1Y2 pixelClk/inst/mmcm_adv_inst/CLKOUT0
+Low Pulse Width Slow FDCE/C n/a 0.500 20.000 19.500 SLICE_X89Y67 collisionDetection/collision_cnt_reg[0]/C
+Low Pulse Width Fast FDCE/C n/a 0.500 20.000 19.500 SLICE_X89Y67 collisionDetection/collision_cnt_reg[0]/C
+Low Pulse Width Slow FDCE/C n/a 0.500 20.000 19.500 SLICE_X88Y69 collisionDetection/collision_cnt_reg[10]/C
+Low Pulse Width Fast FDCE/C n/a 0.500 20.000 19.500 SLICE_X88Y69 collisionDetection/collision_cnt_reg[10]/C
+Low Pulse Width Slow FDCE/C n/a 0.500 20.000 19.500 SLICE_X89Y69 collisionDetection/collision_cnt_reg[10]_lopt_replica/C
+Low Pulse Width Fast FDCE/C n/a 0.500 20.000 19.500 SLICE_X89Y69 collisionDetection/collision_cnt_reg[10]_lopt_replica/C
+Low Pulse Width Slow FDCE/C n/a 0.500 20.000 19.500 SLICE_X88Y67 collisionDetection/collision_cnt_reg[11]/C
+Low Pulse Width Fast FDCE/C n/a 0.500 20.000 19.500 SLICE_X88Y67 collisionDetection/collision_cnt_reg[11]/C
+Low Pulse Width Slow FDCE/C n/a 0.500 20.000 19.500 SLICE_X89Y69 collisionDetection/collision_cnt_reg[12]/C
+Low Pulse Width Fast FDCE/C n/a 0.500 20.000 19.500 SLICE_X89Y69 collisionDetection/collision_cnt_reg[12]/C
+High Pulse Width Slow FDCE/C n/a 0.500 20.000 19.500 SLICE_X89Y67 collisionDetection/collision_cnt_reg[0]/C
+High Pulse Width Fast FDCE/C n/a 0.500 20.000 19.500 SLICE_X89Y67 collisionDetection/collision_cnt_reg[0]/C
+High Pulse Width Slow FDCE/C n/a 0.500 20.000 19.500 SLICE_X88Y69 collisionDetection/collision_cnt_reg[10]/C
+High Pulse Width Fast FDCE/C n/a 0.500 20.000 19.500 SLICE_X88Y69 collisionDetection/collision_cnt_reg[10]/C
+High Pulse Width Slow FDCE/C n/a 0.500 20.000 19.500 SLICE_X89Y69 collisionDetection/collision_cnt_reg[10]_lopt_replica/C
+High Pulse Width Fast FDCE/C n/a 0.500 20.000 19.500 SLICE_X89Y69 collisionDetection/collision_cnt_reg[10]_lopt_replica/C
+High Pulse Width Slow FDCE/C n/a 0.500 20.000 19.500 SLICE_X88Y67 collisionDetection/collision_cnt_reg[11]/C
+High Pulse Width Fast FDCE/C n/a 0.500 20.000 19.500 SLICE_X88Y67 collisionDetection/collision_cnt_reg[11]/C
+High Pulse Width Slow FDCE/C n/a 0.500 20.000 19.500 SLICE_X89Y69 collisionDetection/collision_cnt_reg[12]/C
+High Pulse Width Fast FDCE/C n/a 0.500 20.000 19.500 SLICE_X89Y69 collisionDetection/collision_cnt_reg[12]/C
+
+
+
+---------------------------------------------------------------------------------------------------
+From Clock: clkfbout_clk_wiz_0_1
+ To Clock: clkfbout_clk_wiz_0_1
+
+Setup : NA Failing Endpoints, Worst Slack NA , Total Violation NA
+Hold : NA Failing Endpoints, Worst Slack NA , Total Violation NA
+PW : 0 Failing Endpoints, Worst Slack 7.845ns, Total Violation 0.000ns
+---------------------------------------------------------------------------------------------------
+
+
+Pulse Width Checks
+--------------------------------------------------------------------------------------
+Clock Name: clkfbout_clk_wiz_0_1
+Waveform(ns): { 0.000 5.000 }
+Period(ns): 10.000
+Sources: { pixelClk/inst/mmcm_adv_inst/CLKFBOUT }
+
+Check Type Corner Lib Pin Reference Pin Required(ns) Actual(ns) Slack(ns) Location Pin
+Min Period n/a BUFG/I n/a 2.155 10.000 7.845 BUFGCTRL_X0Y17 pixelClk/inst/clkf_buf/I
+Min Period n/a MMCME2_ADV/CLKFBOUT n/a 1.249 10.000 8.751 MMCME2_ADV_X1Y2 pixelClk/inst/mmcm_adv_inst/CLKFBOUT
+Min Period n/a MMCME2_ADV/CLKFBIN n/a 1.249 10.000 8.751 MMCME2_ADV_X1Y2 pixelClk/inst/mmcm_adv_inst/CLKFBIN
+Max Period n/a MMCME2_ADV/CLKFBIN n/a 100.000 10.000 90.000 MMCME2_ADV_X1Y2 pixelClk/inst/mmcm_adv_inst/CLKFBIN
+Max Period n/a MMCME2_ADV/CLKFBOUT n/a 213.360 10.000 203.360 MMCME2_ADV_X1Y2 pixelClk/inst/mmcm_adv_inst/CLKFBOUT
+
+
+
+---------------------------------------------------------------------------------------------------
+From Clock: clk_out1_clk_wiz_0_1
+ To Clock: clk_out1_clk_wiz_0
+
+Setup : 0 Failing Endpoints, Worst Slack 24.909ns, Total Violation 0.000ns
+Hold : 0 Failing Endpoints, Worst Slack 0.063ns, Total Violation 0.000ns
+---------------------------------------------------------------------------------------------------
+
+
+Max Delay Paths
+--------------------------------------------------------------------------------------
+Slack (MET) : 24.909ns (required time - arrival time)
+ Source: vgaInterface/counter_f_reg[2]/C
+ (rising edge-triggered cell FDCE clocked by clk_out1_clk_wiz_0_1 {rise@0.000ns fall@20.000ns period=40.000ns})
+ Destination: runnerObject/pos_object_y_target_reg[8]/D
+ (rising edge-triggered cell FDSE clocked by clk_out1_clk_wiz_0 {rise@0.000ns fall@20.000ns period=40.000ns})
+ Path Group: clk_out1_clk_wiz_0
+ Path Type: Setup (Max at Slow Process Corner)
+ Requirement: 40.000ns (clk_out1_clk_wiz_0 rise@40.000ns - clk_out1_clk_wiz_0_1 rise@0.000ns)
+ Data Path Delay: 15.033ns (logic 5.901ns (39.253%) route 9.132ns (60.747%))
+ Logic Levels: 18 (CARRY4=9 LUT1=2 LUT2=2 LUT4=2 LUT5=1 LUT6=2)
+ Clock Path Skew: -0.039ns (DCD - SCD + CPR)
+ Destination Clock Delay (DCD): -1.419ns = ( 38.581 - 40.000 )
+ Source Clock Delay (SCD): -0.821ns
+ Clock Pessimism Removal (CPR): 0.559ns
+ Clock Uncertainty: 0.098ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE
+ Total System Jitter (TSJ): 0.071ns
+ Discrete Jitter (DJ): 0.182ns
+ Phase Error (PE): 0.000ns
+ Clock Domain Crossing: Inter clock paths are considered valid unless explicitly excluded by timing constraints such as set_clock_groups or set_false_path.
+
+ Location Delay type Incr(ns) Path(ns) Netlist Resource(s)
+ ------------------------------------------------------------------- -------------------
+ (clock clk_out1_clk_wiz_0_1 rise edge)
+ 0.000 0.000 r
+ E3 0.000 0.000 r clk (IN)
+ net (fo=0) 0.000 0.000 pixelClk/inst/clk_in1
+ E3 IBUF (Prop_ibuf_I_O) 1.482 1.482 r pixelClk/inst/clkin1_ibufg/O
+ net (fo=1, routed) 1.233 2.715 pixelClk/inst/clk_in1_clk_wiz_0
+ MMCME2_ADV_X1Y2 MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKOUT0)
+ -7.070 -4.355 r pixelClk/inst/mmcm_adv_inst/CLKOUT0
+ net (fo=1, routed) 1.719 -2.636 pixelClk/inst/clk_out1_clk_wiz_0
+ BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.096 -2.540 r pixelClk/inst/clkout1_buf/O
+ net (fo=127, routed) 1.719 -0.821 vgaInterface/clk_out1
+ SLICE_X89Y70 FDCE r vgaInterface/counter_f_reg[2]/C
+ ------------------------------------------------------------------- -------------------
+ SLICE_X89Y70 FDCE (Prop_fdce_C_Q) 0.456 -0.365 f vgaInterface/counter_f_reg[2]/Q
+ net (fo=5, routed) 1.006 0.641 vgaInterface/counter_f_reg[2]
+ SLICE_X88Y67 LUT1 (Prop_lut1_I0_O) 0.124 0.765 r vgaInterface/FCounter_17bit_carry_i_3/O
+ net (fo=1, routed) 0.000 0.765 runnerObject/pos_object_y_target6_carry_0[1]
+ SLICE_X88Y67 CARRY4 (Prop_carry4_S[1]_CO[3])
+ 0.533 1.298 r runnerObject/FCounter_17bit_carry/CO[3]
+ net (fo=1, routed) 0.000 1.298 runnerObject/FCounter_17bit_carry_n_0
+ SLICE_X88Y68 CARRY4 (Prop_carry4_CI_O[2])
+ 0.239 1.537 r runnerObject/FCounter_17bit_carry__0/O[2]
+ net (fo=2, routed) 0.987 2.523 runnerObject/FCounter_17bit[7]
+ SLICE_X88Y71 LUT2 (Prop_lut2_I0_O) 0.301 2.824 r runnerObject/pos_object_y_target6_carry__0_i_1/O
+ net (fo=1, routed) 0.000 2.824 runnerObject/pos_object_y_target6_carry__0_i_1_n_0
+ SLICE_X88Y71 CARRY4 (Prop_carry4_S[3]_CO[3])
+ 0.376 3.200 r runnerObject/pos_object_y_target6_carry__0/CO[3]
+ net (fo=1, routed) 0.000 3.200 runnerObject/pos_object_y_target6_carry__0_n_0
+ SLICE_X88Y72 CARRY4 (Prop_carry4_CI_O[1])
+ 0.323 3.523 f runnerObject/pos_object_y_target6_carry__1/O[1]
+ net (fo=5, routed) 0.953 4.477 runnerObject/pos_object_y_target6[9]
+ SLICE_X82Y72 LUT1 (Prop_lut1_I0_O) 0.306 4.783 r runnerObject/i__carry__1_i_13/O
+ net (fo=1, routed) 0.000 4.783 runnerObject/p_0_in[9]
+ SLICE_X82Y72 CARRY4 (Prop_carry4_S[0]_O[2])
+ 0.547 5.330 f runnerObject/i__carry__1_i_9/O[2]
+ net (fo=2, routed) 0.821 6.151 runnerObject/pos_object_y_target9[11]
+ SLICE_X84Y71 LUT4 (Prop_lut4_I3_O) 0.302 6.453 r runnerObject/pos_object_y_target2_carry_i_13/O
+ net (fo=2, routed) 0.420 6.872 runnerObject/pos_object_y_target2_carry_i_13_n_0
+ SLICE_X87Y72 LUT6 (Prop_lut6_I0_O) 0.124 6.996 r runnerObject/pos_object_y_target2_carry_i_10/O
+ net (fo=34, routed) 1.081 8.077 runnerObject/pos_object_y_target2_carry_i_10_n_0
+ SLICE_X84Y70 LUT6 (Prop_lut6_I3_O) 0.124 8.201 r runnerObject/pos_object_y_target2_carry_i_9/O
+ net (fo=1, routed) 0.701 8.903 runnerObject/pos_object_y_target2_carry_i_9_n_0
+ SLICE_X85Y70 CARRY4 (Prop_carry4_S[0]_O[3])
+ 0.730 9.633 f runnerObject/pos_object_y_target2_carry/O[3]
+ net (fo=2, routed) 1.215 10.847 runnerObject/pos_object_y_target2[4]
+ SLICE_X84Y73 LUT2 (Prop_lut2_I1_O) 0.306 11.153 r runnerObject/pos_object_y_target1_carry_i_4/O
+ net (fo=1, routed) 0.000 11.153 runnerObject/pos_object_y_target1_carry_i_4_n_0
+ SLICE_X84Y73 CARRY4 (Prop_carry4_S[2]_CO[3])
+ 0.380 11.533 r runnerObject/pos_object_y_target1_carry/CO[3]
+ net (fo=1, routed) 0.000 11.533 runnerObject/pos_object_y_target1_carry_n_0
+ SLICE_X84Y74 CARRY4 (Prop_carry4_CI_CO[3])
+ 0.117 11.650 r runnerObject/pos_object_y_target1_carry__0/CO[3]
+ net (fo=1, routed) 0.009 11.659 runnerObject/pos_object_y_target1_carry__0_n_0
+ SLICE_X84Y75 CARRY4 (Prop_carry4_CI_CO[1])
+ 0.157 11.816 r runnerObject/pos_object_y_target1_carry__1/CO[1]
+ net (fo=11, routed) 1.258 13.075 runnerObject/pos_object_y_target1
+ SLICE_X88Y80 LUT5 (Prop_lut5_I1_O) 0.332 13.407 r runnerObject/pos_object_y_target[8]_i_4/O
+ net (fo=2, routed) 0.682 14.088 runnerObject/pos_object_y_target[8]_i_4_n_0
+ SLICE_X88Y80 LUT4 (Prop_lut4_I3_O) 0.124 14.212 r runnerObject/pos_object_y_target[8]_i_3/O
+ net (fo=1, routed) 0.000 14.212 runnerObject/pos_object_y_target[8]_i_3_n_0
+ SLICE_X88Y80 FDSE r runnerObject/pos_object_y_target_reg[8]/D
+ ------------------------------------------------------------------- -------------------
+
+ (clock clk_out1_clk_wiz_0 rise edge)
+ 40.000 40.000 r
+ E3 0.000 40.000 r clk (IN)
+ net (fo=0) 0.000 40.000 pixelClk/inst/clk_in1
+ E3 IBUF (Prop_ibuf_I_O) 1.411 41.411 r pixelClk/inst/clkin1_ibufg/O
+ net (fo=1, routed) 1.162 42.573 pixelClk/inst/clk_in1_clk_wiz_0
+ MMCME2_ADV_X1Y2 MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKOUT0)
+ -7.324 35.249 r pixelClk/inst/mmcm_adv_inst/CLKOUT0
+ net (fo=1, routed) 1.639 36.888 pixelClk/inst/clk_out1_clk_wiz_0
+ BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.091 36.979 r pixelClk/inst/clkout1_buf/O
+ net (fo=127, routed) 1.601 38.581 runnerObject/clk_out1
+ SLICE_X88Y80 FDSE r runnerObject/pos_object_y_target_reg[8]/C
+ clock pessimism 0.559 39.140
+ clock uncertainty -0.098 39.043
+ SLICE_X88Y80 FDSE (Setup_fdse_C_D) 0.079 39.122 runnerObject/pos_object_y_target_reg[8]
+ -------------------------------------------------------------------
+ required time 39.122
+ arrival time -14.212
+ -------------------------------------------------------------------
+ slack 24.909
+
+Slack (MET) : 25.045ns (required time - arrival time)
+ Source: vgaInterface/counter_f_reg[2]/C
+ (rising edge-triggered cell FDCE clocked by clk_out1_clk_wiz_0_1 {rise@0.000ns fall@20.000ns period=40.000ns})
+ Destination: runnerObject/pos_object_y_target_reg[5]/R
+ (rising edge-triggered cell FDRE clocked by clk_out1_clk_wiz_0 {rise@0.000ns fall@20.000ns period=40.000ns})
+ Path Group: clk_out1_clk_wiz_0
+ Path Type: Setup (Max at Slow Process Corner)
+ Requirement: 40.000ns (clk_out1_clk_wiz_0 rise@40.000ns - clk_out1_clk_wiz_0_1 rise@0.000ns)
+ Data Path Delay: 14.294ns (logic 5.777ns (40.414%) route 8.517ns (59.586%))
+ Logic Levels: 17 (CARRY4=9 LUT1=2 LUT2=2 LUT3=1 LUT4=1 LUT6=2)
+ Clock Path Skew: -0.039ns (DCD - SCD + CPR)
+ Destination Clock Delay (DCD): -1.419ns = ( 38.581 - 40.000 )
+ Source Clock Delay (SCD): -0.821ns
+ Clock Pessimism Removal (CPR): 0.559ns
+ Clock Uncertainty: 0.098ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE
+ Total System Jitter (TSJ): 0.071ns
+ Discrete Jitter (DJ): 0.182ns
+ Phase Error (PE): 0.000ns
+ Clock Domain Crossing: Inter clock paths are considered valid unless explicitly excluded by timing constraints such as set_clock_groups or set_false_path.
+
+ Location Delay type Incr(ns) Path(ns) Netlist Resource(s)
+ ------------------------------------------------------------------- -------------------
+ (clock clk_out1_clk_wiz_0_1 rise edge)
+ 0.000 0.000 r
+ E3 0.000 0.000 r clk (IN)
+ net (fo=0) 0.000 0.000 pixelClk/inst/clk_in1
+ E3 IBUF (Prop_ibuf_I_O) 1.482 1.482 r pixelClk/inst/clkin1_ibufg/O
+ net (fo=1, routed) 1.233 2.715 pixelClk/inst/clk_in1_clk_wiz_0
+ MMCME2_ADV_X1Y2 MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKOUT0)
+ -7.070 -4.355 r pixelClk/inst/mmcm_adv_inst/CLKOUT0
+ net (fo=1, routed) 1.719 -2.636 pixelClk/inst/clk_out1_clk_wiz_0
+ BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.096 -2.540 r pixelClk/inst/clkout1_buf/O
+ net (fo=127, routed) 1.719 -0.821 vgaInterface/clk_out1
+ SLICE_X89Y70 FDCE r vgaInterface/counter_f_reg[2]/C
+ ------------------------------------------------------------------- -------------------
+ SLICE_X89Y70 FDCE (Prop_fdce_C_Q) 0.456 -0.365 f vgaInterface/counter_f_reg[2]/Q
+ net (fo=5, routed) 1.006 0.641 vgaInterface/counter_f_reg[2]
+ SLICE_X88Y67 LUT1 (Prop_lut1_I0_O) 0.124 0.765 r vgaInterface/FCounter_17bit_carry_i_3/O
+ net (fo=1, routed) 0.000 0.765 runnerObject/pos_object_y_target6_carry_0[1]
+ SLICE_X88Y67 CARRY4 (Prop_carry4_S[1]_CO[3])
+ 0.533 1.298 r runnerObject/FCounter_17bit_carry/CO[3]
+ net (fo=1, routed) 0.000 1.298 runnerObject/FCounter_17bit_carry_n_0
+ SLICE_X88Y68 CARRY4 (Prop_carry4_CI_O[2])
+ 0.239 1.537 r runnerObject/FCounter_17bit_carry__0/O[2]
+ net (fo=2, routed) 0.987 2.523 runnerObject/FCounter_17bit[7]
+ SLICE_X88Y71 LUT2 (Prop_lut2_I0_O) 0.301 2.824 r runnerObject/pos_object_y_target6_carry__0_i_1/O
+ net (fo=1, routed) 0.000 2.824 runnerObject/pos_object_y_target6_carry__0_i_1_n_0
+ SLICE_X88Y71 CARRY4 (Prop_carry4_S[3]_CO[3])
+ 0.376 3.200 r runnerObject/pos_object_y_target6_carry__0/CO[3]
+ net (fo=1, routed) 0.000 3.200 runnerObject/pos_object_y_target6_carry__0_n_0
+ SLICE_X88Y72 CARRY4 (Prop_carry4_CI_O[1])
+ 0.323 3.523 f runnerObject/pos_object_y_target6_carry__1/O[1]
+ net (fo=5, routed) 0.953 4.477 runnerObject/pos_object_y_target6[9]
+ SLICE_X82Y72 LUT1 (Prop_lut1_I0_O) 0.306 4.783 r runnerObject/i__carry__1_i_13/O
+ net (fo=1, routed) 0.000 4.783 runnerObject/p_0_in[9]
+ SLICE_X82Y72 CARRY4 (Prop_carry4_S[0]_O[2])
+ 0.547 5.330 f runnerObject/i__carry__1_i_9/O[2]
+ net (fo=2, routed) 0.821 6.151 runnerObject/pos_object_y_target9[11]
+ SLICE_X84Y71 LUT4 (Prop_lut4_I3_O) 0.302 6.453 r runnerObject/pos_object_y_target2_carry_i_13/O
+ net (fo=2, routed) 0.420 6.872 runnerObject/pos_object_y_target2_carry_i_13_n_0
+ SLICE_X87Y72 LUT6 (Prop_lut6_I0_O) 0.124 6.996 r runnerObject/pos_object_y_target2_carry_i_10/O
+ net (fo=34, routed) 1.081 8.077 runnerObject/pos_object_y_target2_carry_i_10_n_0
+ SLICE_X84Y70 LUT6 (Prop_lut6_I3_O) 0.124 8.201 r runnerObject/pos_object_y_target2_carry_i_9/O
+ net (fo=1, routed) 0.701 8.903 runnerObject/pos_object_y_target2_carry_i_9_n_0
+ SLICE_X85Y70 CARRY4 (Prop_carry4_S[0]_O[3])
+ 0.730 9.633 f runnerObject/pos_object_y_target2_carry/O[3]
+ net (fo=2, routed) 1.215 10.847 runnerObject/pos_object_y_target2[4]
+ SLICE_X84Y73 LUT2 (Prop_lut2_I1_O) 0.306 11.153 r runnerObject/pos_object_y_target1_carry_i_4/O
+ net (fo=1, routed) 0.000 11.153 runnerObject/pos_object_y_target1_carry_i_4_n_0
+ SLICE_X84Y73 CARRY4 (Prop_carry4_S[2]_CO[3])
+ 0.380 11.533 r runnerObject/pos_object_y_target1_carry/CO[3]
+ net (fo=1, routed) 0.000 11.533 runnerObject/pos_object_y_target1_carry_n_0
+ SLICE_X84Y74 CARRY4 (Prop_carry4_CI_CO[3])
+ 0.117 11.650 r runnerObject/pos_object_y_target1_carry__0/CO[3]
+ net (fo=1, routed) 0.009 11.659 runnerObject/pos_object_y_target1_carry__0_n_0
+ SLICE_X84Y75 CARRY4 (Prop_carry4_CI_CO[1])
+ 0.157 11.816 f runnerObject/pos_object_y_target1_carry__1/CO[1]
+ net (fo=11, routed) 0.629 12.445 runnerObject/pos_object_y_target1
+ SLICE_X86Y77 LUT3 (Prop_lut3_I0_O) 0.332 12.777 r runnerObject/pos_object_y_target[8]_i_1/O
+ net (fo=9, routed) 0.697 13.474 runnerObject/pos_object_y_target[8]_i_1_n_0
+ SLICE_X88Y79 FDRE r runnerObject/pos_object_y_target_reg[5]/R
+ ------------------------------------------------------------------- -------------------
+
+ (clock clk_out1_clk_wiz_0 rise edge)
+ 40.000 40.000 r
+ E3 0.000 40.000 r clk (IN)
+ net (fo=0) 0.000 40.000 pixelClk/inst/clk_in1
+ E3 IBUF (Prop_ibuf_I_O) 1.411 41.411 r pixelClk/inst/clkin1_ibufg/O
+ net (fo=1, routed) 1.162 42.573 pixelClk/inst/clk_in1_clk_wiz_0
+ MMCME2_ADV_X1Y2 MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKOUT0)
+ -7.324 35.249 r pixelClk/inst/mmcm_adv_inst/CLKOUT0
+ net (fo=1, routed) 1.639 36.888 pixelClk/inst/clk_out1_clk_wiz_0
+ BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.091 36.979 r pixelClk/inst/clkout1_buf/O
+ net (fo=127, routed) 1.601 38.581 runnerObject/clk_out1
+ SLICE_X88Y79 FDRE r runnerObject/pos_object_y_target_reg[5]/C
+ clock pessimism 0.559 39.140
+ clock uncertainty -0.098 39.043
+ SLICE_X88Y79 FDRE (Setup_fdre_C_R) -0.524 38.519 runnerObject/pos_object_y_target_reg[5]
+ -------------------------------------------------------------------
+ required time 38.519
+ arrival time -13.474
+ -------------------------------------------------------------------
+ slack 25.045
+
+Slack (MET) : 25.102ns (required time - arrival time)
+ Source: vgaInterface/counter_f_reg[2]/C
+ (rising edge-triggered cell FDCE clocked by clk_out1_clk_wiz_0_1 {rise@0.000ns fall@20.000ns period=40.000ns})
+ Destination: runnerObject/pos_object_y_target_reg[6]/S
+ (rising edge-triggered cell FDSE clocked by clk_out1_clk_wiz_0 {rise@0.000ns fall@20.000ns period=40.000ns})
+ Path Group: clk_out1_clk_wiz_0
+ Path Type: Setup (Max at Slow Process Corner)
+ Requirement: 40.000ns (clk_out1_clk_wiz_0 rise@40.000ns - clk_out1_clk_wiz_0_1 rise@0.000ns)
+ Data Path Delay: 14.237ns (logic 5.777ns (40.577%) route 8.460ns (59.423%))
+ Logic Levels: 17 (CARRY4=9 LUT1=2 LUT2=2 LUT3=1 LUT4=1 LUT6=2)
+ Clock Path Skew: -0.039ns (DCD - SCD + CPR)
+ Destination Clock Delay (DCD): -1.419ns = ( 38.581 - 40.000 )
+ Source Clock Delay (SCD): -0.821ns
+ Clock Pessimism Removal (CPR): 0.559ns
+ Clock Uncertainty: 0.098ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE
+ Total System Jitter (TSJ): 0.071ns
+ Discrete Jitter (DJ): 0.182ns
+ Phase Error (PE): 0.000ns
+ Clock Domain Crossing: Inter clock paths are considered valid unless explicitly excluded by timing constraints such as set_clock_groups or set_false_path.
+
+ Location Delay type Incr(ns) Path(ns) Netlist Resource(s)
+ ------------------------------------------------------------------- -------------------
+ (clock clk_out1_clk_wiz_0_1 rise edge)
+ 0.000 0.000 r
+ E3 0.000 0.000 r clk (IN)
+ net (fo=0) 0.000 0.000 pixelClk/inst/clk_in1
+ E3 IBUF (Prop_ibuf_I_O) 1.482 1.482 r pixelClk/inst/clkin1_ibufg/O
+ net (fo=1, routed) 1.233 2.715 pixelClk/inst/clk_in1_clk_wiz_0
+ MMCME2_ADV_X1Y2 MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKOUT0)
+ -7.070 -4.355 r pixelClk/inst/mmcm_adv_inst/CLKOUT0
+ net (fo=1, routed) 1.719 -2.636 pixelClk/inst/clk_out1_clk_wiz_0
+ BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.096 -2.540 r pixelClk/inst/clkout1_buf/O
+ net (fo=127, routed) 1.719 -0.821 vgaInterface/clk_out1
+ SLICE_X89Y70 FDCE r vgaInterface/counter_f_reg[2]/C
+ ------------------------------------------------------------------- -------------------
+ SLICE_X89Y70 FDCE (Prop_fdce_C_Q) 0.456 -0.365 f vgaInterface/counter_f_reg[2]/Q
+ net (fo=5, routed) 1.006 0.641 vgaInterface/counter_f_reg[2]
+ SLICE_X88Y67 LUT1 (Prop_lut1_I0_O) 0.124 0.765 r vgaInterface/FCounter_17bit_carry_i_3/O
+ net (fo=1, routed) 0.000 0.765 runnerObject/pos_object_y_target6_carry_0[1]
+ SLICE_X88Y67 CARRY4 (Prop_carry4_S[1]_CO[3])
+ 0.533 1.298 r runnerObject/FCounter_17bit_carry/CO[3]
+ net (fo=1, routed) 0.000 1.298 runnerObject/FCounter_17bit_carry_n_0
+ SLICE_X88Y68 CARRY4 (Prop_carry4_CI_O[2])
+ 0.239 1.537 r runnerObject/FCounter_17bit_carry__0/O[2]
+ net (fo=2, routed) 0.987 2.523 runnerObject/FCounter_17bit[7]
+ SLICE_X88Y71 LUT2 (Prop_lut2_I0_O) 0.301 2.824 r runnerObject/pos_object_y_target6_carry__0_i_1/O
+ net (fo=1, routed) 0.000 2.824 runnerObject/pos_object_y_target6_carry__0_i_1_n_0
+ SLICE_X88Y71 CARRY4 (Prop_carry4_S[3]_CO[3])
+ 0.376 3.200 r runnerObject/pos_object_y_target6_carry__0/CO[3]
+ net (fo=1, routed) 0.000 3.200 runnerObject/pos_object_y_target6_carry__0_n_0
+ SLICE_X88Y72 CARRY4 (Prop_carry4_CI_O[1])
+ 0.323 3.523 f runnerObject/pos_object_y_target6_carry__1/O[1]
+ net (fo=5, routed) 0.953 4.477 runnerObject/pos_object_y_target6[9]
+ SLICE_X82Y72 LUT1 (Prop_lut1_I0_O) 0.306 4.783 r runnerObject/i__carry__1_i_13/O
+ net (fo=1, routed) 0.000 4.783 runnerObject/p_0_in[9]
+ SLICE_X82Y72 CARRY4 (Prop_carry4_S[0]_O[2])
+ 0.547 5.330 f runnerObject/i__carry__1_i_9/O[2]
+ net (fo=2, routed) 0.821 6.151 runnerObject/pos_object_y_target9[11]
+ SLICE_X84Y71 LUT4 (Prop_lut4_I3_O) 0.302 6.453 r runnerObject/pos_object_y_target2_carry_i_13/O
+ net (fo=2, routed) 0.420 6.872 runnerObject/pos_object_y_target2_carry_i_13_n_0
+ SLICE_X87Y72 LUT6 (Prop_lut6_I0_O) 0.124 6.996 r runnerObject/pos_object_y_target2_carry_i_10/O
+ net (fo=34, routed) 1.081 8.077 runnerObject/pos_object_y_target2_carry_i_10_n_0
+ SLICE_X84Y70 LUT6 (Prop_lut6_I3_O) 0.124 8.201 r runnerObject/pos_object_y_target2_carry_i_9/O
+ net (fo=1, routed) 0.701 8.903 runnerObject/pos_object_y_target2_carry_i_9_n_0
+ SLICE_X85Y70 CARRY4 (Prop_carry4_S[0]_O[3])
+ 0.730 9.633 f runnerObject/pos_object_y_target2_carry/O[3]
+ net (fo=2, routed) 1.215 10.847 runnerObject/pos_object_y_target2[4]
+ SLICE_X84Y73 LUT2 (Prop_lut2_I1_O) 0.306 11.153 r runnerObject/pos_object_y_target1_carry_i_4/O
+ net (fo=1, routed) 0.000 11.153 runnerObject/pos_object_y_target1_carry_i_4_n_0
+ SLICE_X84Y73 CARRY4 (Prop_carry4_S[2]_CO[3])
+ 0.380 11.533 r runnerObject/pos_object_y_target1_carry/CO[3]
+ net (fo=1, routed) 0.000 11.533 runnerObject/pos_object_y_target1_carry_n_0
+ SLICE_X84Y74 CARRY4 (Prop_carry4_CI_CO[3])
+ 0.117 11.650 r runnerObject/pos_object_y_target1_carry__0/CO[3]
+ net (fo=1, routed) 0.009 11.659 runnerObject/pos_object_y_target1_carry__0_n_0
+ SLICE_X84Y75 CARRY4 (Prop_carry4_CI_CO[1])
+ 0.157 11.816 f runnerObject/pos_object_y_target1_carry__1/CO[1]
+ net (fo=11, routed) 0.629 12.445 runnerObject/pos_object_y_target1
+ SLICE_X86Y77 LUT3 (Prop_lut3_I0_O) 0.332 12.777 r runnerObject/pos_object_y_target[8]_i_1/O
+ net (fo=9, routed) 0.639 13.416 runnerObject/pos_object_y_target[8]_i_1_n_0
+ SLICE_X88Y80 FDSE r runnerObject/pos_object_y_target_reg[6]/S
+ ------------------------------------------------------------------- -------------------
+
+ (clock clk_out1_clk_wiz_0 rise edge)
+ 40.000 40.000 r
+ E3 0.000 40.000 r clk (IN)
+ net (fo=0) 0.000 40.000 pixelClk/inst/clk_in1
+ E3 IBUF (Prop_ibuf_I_O) 1.411 41.411 r pixelClk/inst/clkin1_ibufg/O
+ net (fo=1, routed) 1.162 42.573 pixelClk/inst/clk_in1_clk_wiz_0
+ MMCME2_ADV_X1Y2 MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKOUT0)
+ -7.324 35.249 r pixelClk/inst/mmcm_adv_inst/CLKOUT0
+ net (fo=1, routed) 1.639 36.888 pixelClk/inst/clk_out1_clk_wiz_0
+ BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.091 36.979 r pixelClk/inst/clkout1_buf/O
+ net (fo=127, routed) 1.601 38.581 runnerObject/clk_out1
+ SLICE_X88Y80 FDSE r runnerObject/pos_object_y_target_reg[6]/C
+ clock pessimism 0.559 39.140
+ clock uncertainty -0.098 39.043
+ SLICE_X88Y80 FDSE (Setup_fdse_C_S) -0.524 38.519 runnerObject/pos_object_y_target_reg[6]
+ -------------------------------------------------------------------
+ required time 38.519
+ arrival time -13.416
+ -------------------------------------------------------------------
+ slack 25.102
+
+Slack (MET) : 25.102ns (required time - arrival time)
+ Source: vgaInterface/counter_f_reg[2]/C
+ (rising edge-triggered cell FDCE clocked by clk_out1_clk_wiz_0_1 {rise@0.000ns fall@20.000ns period=40.000ns})
+ Destination: runnerObject/pos_object_y_target_reg[7]/R
+ (rising edge-triggered cell FDRE clocked by clk_out1_clk_wiz_0 {rise@0.000ns fall@20.000ns period=40.000ns})
+ Path Group: clk_out1_clk_wiz_0
+ Path Type: Setup (Max at Slow Process Corner)
+ Requirement: 40.000ns (clk_out1_clk_wiz_0 rise@40.000ns - clk_out1_clk_wiz_0_1 rise@0.000ns)
+ Data Path Delay: 14.237ns (logic 5.777ns (40.577%) route 8.460ns (59.423%))
+ Logic Levels: 17 (CARRY4=9 LUT1=2 LUT2=2 LUT3=1 LUT4=1 LUT6=2)
+ Clock Path Skew: -0.039ns (DCD - SCD + CPR)
+ Destination Clock Delay (DCD): -1.419ns = ( 38.581 - 40.000 )
+ Source Clock Delay (SCD): -0.821ns
+ Clock Pessimism Removal (CPR): 0.559ns
+ Clock Uncertainty: 0.098ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE
+ Total System Jitter (TSJ): 0.071ns
+ Discrete Jitter (DJ): 0.182ns
+ Phase Error (PE): 0.000ns
+ Clock Domain Crossing: Inter clock paths are considered valid unless explicitly excluded by timing constraints such as set_clock_groups or set_false_path.
+
+ Location Delay type Incr(ns) Path(ns) Netlist Resource(s)
+ ------------------------------------------------------------------- -------------------
+ (clock clk_out1_clk_wiz_0_1 rise edge)
+ 0.000 0.000 r
+ E3 0.000 0.000 r clk (IN)
+ net (fo=0) 0.000 0.000 pixelClk/inst/clk_in1
+ E3 IBUF (Prop_ibuf_I_O) 1.482 1.482 r pixelClk/inst/clkin1_ibufg/O
+ net (fo=1, routed) 1.233 2.715 pixelClk/inst/clk_in1_clk_wiz_0
+ MMCME2_ADV_X1Y2 MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKOUT0)
+ -7.070 -4.355 r pixelClk/inst/mmcm_adv_inst/CLKOUT0
+ net (fo=1, routed) 1.719 -2.636 pixelClk/inst/clk_out1_clk_wiz_0
+ BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.096 -2.540 r pixelClk/inst/clkout1_buf/O
+ net (fo=127, routed) 1.719 -0.821 vgaInterface/clk_out1
+ SLICE_X89Y70 FDCE r vgaInterface/counter_f_reg[2]/C
+ ------------------------------------------------------------------- -------------------
+ SLICE_X89Y70 FDCE (Prop_fdce_C_Q) 0.456 -0.365 f vgaInterface/counter_f_reg[2]/Q
+ net (fo=5, routed) 1.006 0.641 vgaInterface/counter_f_reg[2]
+ SLICE_X88Y67 LUT1 (Prop_lut1_I0_O) 0.124 0.765 r vgaInterface/FCounter_17bit_carry_i_3/O
+ net (fo=1, routed) 0.000 0.765 runnerObject/pos_object_y_target6_carry_0[1]
+ SLICE_X88Y67 CARRY4 (Prop_carry4_S[1]_CO[3])
+ 0.533 1.298 r runnerObject/FCounter_17bit_carry/CO[3]
+ net (fo=1, routed) 0.000 1.298 runnerObject/FCounter_17bit_carry_n_0
+ SLICE_X88Y68 CARRY4 (Prop_carry4_CI_O[2])
+ 0.239 1.537 r runnerObject/FCounter_17bit_carry__0/O[2]
+ net (fo=2, routed) 0.987 2.523 runnerObject/FCounter_17bit[7]
+ SLICE_X88Y71 LUT2 (Prop_lut2_I0_O) 0.301 2.824 r runnerObject/pos_object_y_target6_carry__0_i_1/O
+ net (fo=1, routed) 0.000 2.824 runnerObject/pos_object_y_target6_carry__0_i_1_n_0
+ SLICE_X88Y71 CARRY4 (Prop_carry4_S[3]_CO[3])
+ 0.376 3.200 r runnerObject/pos_object_y_target6_carry__0/CO[3]
+ net (fo=1, routed) 0.000 3.200 runnerObject/pos_object_y_target6_carry__0_n_0
+ SLICE_X88Y72 CARRY4 (Prop_carry4_CI_O[1])
+ 0.323 3.523 f runnerObject/pos_object_y_target6_carry__1/O[1]
+ net (fo=5, routed) 0.953 4.477 runnerObject/pos_object_y_target6[9]
+ SLICE_X82Y72 LUT1 (Prop_lut1_I0_O) 0.306 4.783 r runnerObject/i__carry__1_i_13/O
+ net (fo=1, routed) 0.000 4.783 runnerObject/p_0_in[9]
+ SLICE_X82Y72 CARRY4 (Prop_carry4_S[0]_O[2])
+ 0.547 5.330 f runnerObject/i__carry__1_i_9/O[2]
+ net (fo=2, routed) 0.821 6.151 runnerObject/pos_object_y_target9[11]
+ SLICE_X84Y71 LUT4 (Prop_lut4_I3_O) 0.302 6.453 r runnerObject/pos_object_y_target2_carry_i_13/O
+ net (fo=2, routed) 0.420 6.872 runnerObject/pos_object_y_target2_carry_i_13_n_0
+ SLICE_X87Y72 LUT6 (Prop_lut6_I0_O) 0.124 6.996 r runnerObject/pos_object_y_target2_carry_i_10/O
+ net (fo=34, routed) 1.081 8.077 runnerObject/pos_object_y_target2_carry_i_10_n_0
+ SLICE_X84Y70 LUT6 (Prop_lut6_I3_O) 0.124 8.201 r runnerObject/pos_object_y_target2_carry_i_9/O
+ net (fo=1, routed) 0.701 8.903 runnerObject/pos_object_y_target2_carry_i_9_n_0
+ SLICE_X85Y70 CARRY4 (Prop_carry4_S[0]_O[3])
+ 0.730 9.633 f runnerObject/pos_object_y_target2_carry/O[3]
+ net (fo=2, routed) 1.215 10.847 runnerObject/pos_object_y_target2[4]
+ SLICE_X84Y73 LUT2 (Prop_lut2_I1_O) 0.306 11.153 r runnerObject/pos_object_y_target1_carry_i_4/O
+ net (fo=1, routed) 0.000 11.153 runnerObject/pos_object_y_target1_carry_i_4_n_0
+ SLICE_X84Y73 CARRY4 (Prop_carry4_S[2]_CO[3])
+ 0.380 11.533 r runnerObject/pos_object_y_target1_carry/CO[3]
+ net (fo=1, routed) 0.000 11.533 runnerObject/pos_object_y_target1_carry_n_0
+ SLICE_X84Y74 CARRY4 (Prop_carry4_CI_CO[3])
+ 0.117 11.650 r runnerObject/pos_object_y_target1_carry__0/CO[3]
+ net (fo=1, routed) 0.009 11.659 runnerObject/pos_object_y_target1_carry__0_n_0
+ SLICE_X84Y75 CARRY4 (Prop_carry4_CI_CO[1])
+ 0.157 11.816 f runnerObject/pos_object_y_target1_carry__1/CO[1]
+ net (fo=11, routed) 0.629 12.445 runnerObject/pos_object_y_target1
+ SLICE_X86Y77 LUT3 (Prop_lut3_I0_O) 0.332 12.777 r runnerObject/pos_object_y_target[8]_i_1/O
+ net (fo=9, routed) 0.639 13.416 runnerObject/pos_object_y_target[8]_i_1_n_0
+ SLICE_X88Y80 FDRE r runnerObject/pos_object_y_target_reg[7]/R
+ ------------------------------------------------------------------- -------------------
+
+ (clock clk_out1_clk_wiz_0 rise edge)
+ 40.000 40.000 r
+ E3 0.000 40.000 r clk (IN)
+ net (fo=0) 0.000 40.000 pixelClk/inst/clk_in1
+ E3 IBUF (Prop_ibuf_I_O) 1.411 41.411 r pixelClk/inst/clkin1_ibufg/O
+ net (fo=1, routed) 1.162 42.573 pixelClk/inst/clk_in1_clk_wiz_0
+ MMCME2_ADV_X1Y2 MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKOUT0)
+ -7.324 35.249 r pixelClk/inst/mmcm_adv_inst/CLKOUT0
+ net (fo=1, routed) 1.639 36.888 pixelClk/inst/clk_out1_clk_wiz_0
+ BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.091 36.979 r pixelClk/inst/clkout1_buf/O
+ net (fo=127, routed) 1.601 38.581 runnerObject/clk_out1
+ SLICE_X88Y80 FDRE r runnerObject/pos_object_y_target_reg[7]/C
+ clock pessimism 0.559 39.140
+ clock uncertainty -0.098 39.043
+ SLICE_X88Y80 FDRE (Setup_fdre_C_R) -0.524 38.519 runnerObject/pos_object_y_target_reg[7]
+ -------------------------------------------------------------------
+ required time 38.519
+ arrival time -13.416
+ -------------------------------------------------------------------
+ slack 25.102
+
+Slack (MET) : 25.102ns (required time - arrival time)
+ Source: vgaInterface/counter_f_reg[2]/C
+ (rising edge-triggered cell FDCE clocked by clk_out1_clk_wiz_0_1 {rise@0.000ns fall@20.000ns period=40.000ns})
+ Destination: runnerObject/pos_object_y_target_reg[8]/S
+ (rising edge-triggered cell FDSE clocked by clk_out1_clk_wiz_0 {rise@0.000ns fall@20.000ns period=40.000ns})
+ Path Group: clk_out1_clk_wiz_0
+ Path Type: Setup (Max at Slow Process Corner)
+ Requirement: 40.000ns (clk_out1_clk_wiz_0 rise@40.000ns - clk_out1_clk_wiz_0_1 rise@0.000ns)
+ Data Path Delay: 14.237ns (logic 5.777ns (40.577%) route 8.460ns (59.423%))
+ Logic Levels: 17 (CARRY4=9 LUT1=2 LUT2=2 LUT3=1 LUT4=1 LUT6=2)
+ Clock Path Skew: -0.039ns (DCD - SCD + CPR)
+ Destination Clock Delay (DCD): -1.419ns = ( 38.581 - 40.000 )
+ Source Clock Delay (SCD): -0.821ns
+ Clock Pessimism Removal (CPR): 0.559ns
+ Clock Uncertainty: 0.098ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE
+ Total System Jitter (TSJ): 0.071ns
+ Discrete Jitter (DJ): 0.182ns
+ Phase Error (PE): 0.000ns
+ Clock Domain Crossing: Inter clock paths are considered valid unless explicitly excluded by timing constraints such as set_clock_groups or set_false_path.
+
+ Location Delay type Incr(ns) Path(ns) Netlist Resource(s)
+ ------------------------------------------------------------------- -------------------
+ (clock clk_out1_clk_wiz_0_1 rise edge)
+ 0.000 0.000 r
+ E3 0.000 0.000 r clk (IN)
+ net (fo=0) 0.000 0.000 pixelClk/inst/clk_in1
+ E3 IBUF (Prop_ibuf_I_O) 1.482 1.482 r pixelClk/inst/clkin1_ibufg/O
+ net (fo=1, routed) 1.233 2.715 pixelClk/inst/clk_in1_clk_wiz_0
+ MMCME2_ADV_X1Y2 MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKOUT0)
+ -7.070 -4.355 r pixelClk/inst/mmcm_adv_inst/CLKOUT0
+ net (fo=1, routed) 1.719 -2.636 pixelClk/inst/clk_out1_clk_wiz_0
+ BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.096 -2.540 r pixelClk/inst/clkout1_buf/O
+ net (fo=127, routed) 1.719 -0.821 vgaInterface/clk_out1
+ SLICE_X89Y70 FDCE r vgaInterface/counter_f_reg[2]/C
+ ------------------------------------------------------------------- -------------------
+ SLICE_X89Y70 FDCE (Prop_fdce_C_Q) 0.456 -0.365 f vgaInterface/counter_f_reg[2]/Q
+ net (fo=5, routed) 1.006 0.641 vgaInterface/counter_f_reg[2]
+ SLICE_X88Y67 LUT1 (Prop_lut1_I0_O) 0.124 0.765 r vgaInterface/FCounter_17bit_carry_i_3/O
+ net (fo=1, routed) 0.000 0.765 runnerObject/pos_object_y_target6_carry_0[1]
+ SLICE_X88Y67 CARRY4 (Prop_carry4_S[1]_CO[3])
+ 0.533 1.298 r runnerObject/FCounter_17bit_carry/CO[3]
+ net (fo=1, routed) 0.000 1.298 runnerObject/FCounter_17bit_carry_n_0
+ SLICE_X88Y68 CARRY4 (Prop_carry4_CI_O[2])
+ 0.239 1.537 r runnerObject/FCounter_17bit_carry__0/O[2]
+ net (fo=2, routed) 0.987 2.523 runnerObject/FCounter_17bit[7]
+ SLICE_X88Y71 LUT2 (Prop_lut2_I0_O) 0.301 2.824 r runnerObject/pos_object_y_target6_carry__0_i_1/O
+ net (fo=1, routed) 0.000 2.824 runnerObject/pos_object_y_target6_carry__0_i_1_n_0
+ SLICE_X88Y71 CARRY4 (Prop_carry4_S[3]_CO[3])
+ 0.376 3.200 r runnerObject/pos_object_y_target6_carry__0/CO[3]
+ net (fo=1, routed) 0.000 3.200 runnerObject/pos_object_y_target6_carry__0_n_0
+ SLICE_X88Y72 CARRY4 (Prop_carry4_CI_O[1])
+ 0.323 3.523 f runnerObject/pos_object_y_target6_carry__1/O[1]
+ net (fo=5, routed) 0.953 4.477 runnerObject/pos_object_y_target6[9]
+ SLICE_X82Y72 LUT1 (Prop_lut1_I0_O) 0.306 4.783 r runnerObject/i__carry__1_i_13/O
+ net (fo=1, routed) 0.000 4.783 runnerObject/p_0_in[9]
+ SLICE_X82Y72 CARRY4 (Prop_carry4_S[0]_O[2])
+ 0.547 5.330 f runnerObject/i__carry__1_i_9/O[2]
+ net (fo=2, routed) 0.821 6.151 runnerObject/pos_object_y_target9[11]
+ SLICE_X84Y71 LUT4 (Prop_lut4_I3_O) 0.302 6.453 r runnerObject/pos_object_y_target2_carry_i_13/O
+ net (fo=2, routed) 0.420 6.872 runnerObject/pos_object_y_target2_carry_i_13_n_0
+ SLICE_X87Y72 LUT6 (Prop_lut6_I0_O) 0.124 6.996 r runnerObject/pos_object_y_target2_carry_i_10/O
+ net (fo=34, routed) 1.081 8.077 runnerObject/pos_object_y_target2_carry_i_10_n_0
+ SLICE_X84Y70 LUT6 (Prop_lut6_I3_O) 0.124 8.201 r runnerObject/pos_object_y_target2_carry_i_9/O
+ net (fo=1, routed) 0.701 8.903 runnerObject/pos_object_y_target2_carry_i_9_n_0
+ SLICE_X85Y70 CARRY4 (Prop_carry4_S[0]_O[3])
+ 0.730 9.633 f runnerObject/pos_object_y_target2_carry/O[3]
+ net (fo=2, routed) 1.215 10.847 runnerObject/pos_object_y_target2[4]
+ SLICE_X84Y73 LUT2 (Prop_lut2_I1_O) 0.306 11.153 r runnerObject/pos_object_y_target1_carry_i_4/O
+ net (fo=1, routed) 0.000 11.153 runnerObject/pos_object_y_target1_carry_i_4_n_0
+ SLICE_X84Y73 CARRY4 (Prop_carry4_S[2]_CO[3])
+ 0.380 11.533 r runnerObject/pos_object_y_target1_carry/CO[3]
+ net (fo=1, routed) 0.000 11.533 runnerObject/pos_object_y_target1_carry_n_0
+ SLICE_X84Y74 CARRY4 (Prop_carry4_CI_CO[3])
+ 0.117 11.650 r runnerObject/pos_object_y_target1_carry__0/CO[3]
+ net (fo=1, routed) 0.009 11.659 runnerObject/pos_object_y_target1_carry__0_n_0
+ SLICE_X84Y75 CARRY4 (Prop_carry4_CI_CO[1])
+ 0.157 11.816 f runnerObject/pos_object_y_target1_carry__1/CO[1]
+ net (fo=11, routed) 0.629 12.445 runnerObject/pos_object_y_target1
+ SLICE_X86Y77 LUT3 (Prop_lut3_I0_O) 0.332 12.777 r runnerObject/pos_object_y_target[8]_i_1/O
+ net (fo=9, routed) 0.639 13.416 runnerObject/pos_object_y_target[8]_i_1_n_0
+ SLICE_X88Y80 FDSE r runnerObject/pos_object_y_target_reg[8]/S
+ ------------------------------------------------------------------- -------------------
+
+ (clock clk_out1_clk_wiz_0 rise edge)
+ 40.000 40.000 r
+ E3 0.000 40.000 r clk (IN)
+ net (fo=0) 0.000 40.000 pixelClk/inst/clk_in1
+ E3 IBUF (Prop_ibuf_I_O) 1.411 41.411 r pixelClk/inst/clkin1_ibufg/O
+ net (fo=1, routed) 1.162 42.573 pixelClk/inst/clk_in1_clk_wiz_0
+ MMCME2_ADV_X1Y2 MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKOUT0)
+ -7.324 35.249 r pixelClk/inst/mmcm_adv_inst/CLKOUT0
+ net (fo=1, routed) 1.639 36.888 pixelClk/inst/clk_out1_clk_wiz_0
+ BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.091 36.979 r pixelClk/inst/clkout1_buf/O
+ net (fo=127, routed) 1.601 38.581 runnerObject/clk_out1
+ SLICE_X88Y80 FDSE r runnerObject/pos_object_y_target_reg[8]/C
+ clock pessimism 0.559 39.140
+ clock uncertainty -0.098 39.043
+ SLICE_X88Y80 FDSE (Setup_fdse_C_S) -0.524 38.519 runnerObject/pos_object_y_target_reg[8]
+ -------------------------------------------------------------------
+ required time 38.519
+ arrival time -13.416
+ -------------------------------------------------------------------
+ slack 25.102
+
+Slack (MET) : 25.140ns (required time - arrival time)
+ Source: vgaInterface/counter_f_reg[2]/C
+ (rising edge-triggered cell FDCE clocked by clk_out1_clk_wiz_0_1 {rise@0.000ns fall@20.000ns period=40.000ns})
+ Destination: runnerObject/pos_object_y_target_reg[0]/R
+ (rising edge-triggered cell FDRE clocked by clk_out1_clk_wiz_0 {rise@0.000ns fall@20.000ns period=40.000ns})
+ Path Group: clk_out1_clk_wiz_0
+ Path Type: Setup (Max at Slow Process Corner)
+ Requirement: 40.000ns (clk_out1_clk_wiz_0 rise@40.000ns - clk_out1_clk_wiz_0_1 rise@0.000ns)
+ Data Path Delay: 14.294ns (logic 5.777ns (40.414%) route 8.517ns (59.586%))
+ Logic Levels: 17 (CARRY4=9 LUT1=2 LUT2=2 LUT3=1 LUT4=1 LUT6=2)
+ Clock Path Skew: -0.039ns (DCD - SCD + CPR)
+ Destination Clock Delay (DCD): -1.419ns = ( 38.581 - 40.000 )
+ Source Clock Delay (SCD): -0.821ns
+ Clock Pessimism Removal (CPR): 0.559ns
+ Clock Uncertainty: 0.098ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE
+ Total System Jitter (TSJ): 0.071ns
+ Discrete Jitter (DJ): 0.182ns
+ Phase Error (PE): 0.000ns
+ Clock Domain Crossing: Inter clock paths are considered valid unless explicitly excluded by timing constraints such as set_clock_groups or set_false_path.
+
+ Location Delay type Incr(ns) Path(ns) Netlist Resource(s)
+ ------------------------------------------------------------------- -------------------
+ (clock clk_out1_clk_wiz_0_1 rise edge)
+ 0.000 0.000 r
+ E3 0.000 0.000 r clk (IN)
+ net (fo=0) 0.000 0.000 pixelClk/inst/clk_in1
+ E3 IBUF (Prop_ibuf_I_O) 1.482 1.482 r pixelClk/inst/clkin1_ibufg/O
+ net (fo=1, routed) 1.233 2.715 pixelClk/inst/clk_in1_clk_wiz_0
+ MMCME2_ADV_X1Y2 MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKOUT0)
+ -7.070 -4.355 r pixelClk/inst/mmcm_adv_inst/CLKOUT0
+ net (fo=1, routed) 1.719 -2.636 pixelClk/inst/clk_out1_clk_wiz_0
+ BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.096 -2.540 r pixelClk/inst/clkout1_buf/O
+ net (fo=127, routed) 1.719 -0.821 vgaInterface/clk_out1
+ SLICE_X89Y70 FDCE r vgaInterface/counter_f_reg[2]/C
+ ------------------------------------------------------------------- -------------------
+ SLICE_X89Y70 FDCE (Prop_fdce_C_Q) 0.456 -0.365 f vgaInterface/counter_f_reg[2]/Q
+ net (fo=5, routed) 1.006 0.641 vgaInterface/counter_f_reg[2]
+ SLICE_X88Y67 LUT1 (Prop_lut1_I0_O) 0.124 0.765 r vgaInterface/FCounter_17bit_carry_i_3/O
+ net (fo=1, routed) 0.000 0.765 runnerObject/pos_object_y_target6_carry_0[1]
+ SLICE_X88Y67 CARRY4 (Prop_carry4_S[1]_CO[3])
+ 0.533 1.298 r runnerObject/FCounter_17bit_carry/CO[3]
+ net (fo=1, routed) 0.000 1.298 runnerObject/FCounter_17bit_carry_n_0
+ SLICE_X88Y68 CARRY4 (Prop_carry4_CI_O[2])
+ 0.239 1.537 r runnerObject/FCounter_17bit_carry__0/O[2]
+ net (fo=2, routed) 0.987 2.523 runnerObject/FCounter_17bit[7]
+ SLICE_X88Y71 LUT2 (Prop_lut2_I0_O) 0.301 2.824 r runnerObject/pos_object_y_target6_carry__0_i_1/O
+ net (fo=1, routed) 0.000 2.824 runnerObject/pos_object_y_target6_carry__0_i_1_n_0
+ SLICE_X88Y71 CARRY4 (Prop_carry4_S[3]_CO[3])
+ 0.376 3.200 r runnerObject/pos_object_y_target6_carry__0/CO[3]
+ net (fo=1, routed) 0.000 3.200 runnerObject/pos_object_y_target6_carry__0_n_0
+ SLICE_X88Y72 CARRY4 (Prop_carry4_CI_O[1])
+ 0.323 3.523 f runnerObject/pos_object_y_target6_carry__1/O[1]
+ net (fo=5, routed) 0.953 4.477 runnerObject/pos_object_y_target6[9]
+ SLICE_X82Y72 LUT1 (Prop_lut1_I0_O) 0.306 4.783 r runnerObject/i__carry__1_i_13/O
+ net (fo=1, routed) 0.000 4.783 runnerObject/p_0_in[9]
+ SLICE_X82Y72 CARRY4 (Prop_carry4_S[0]_O[2])
+ 0.547 5.330 f runnerObject/i__carry__1_i_9/O[2]
+ net (fo=2, routed) 0.821 6.151 runnerObject/pos_object_y_target9[11]
+ SLICE_X84Y71 LUT4 (Prop_lut4_I3_O) 0.302 6.453 r runnerObject/pos_object_y_target2_carry_i_13/O
+ net (fo=2, routed) 0.420 6.872 runnerObject/pos_object_y_target2_carry_i_13_n_0
+ SLICE_X87Y72 LUT6 (Prop_lut6_I0_O) 0.124 6.996 r runnerObject/pos_object_y_target2_carry_i_10/O
+ net (fo=34, routed) 1.081 8.077 runnerObject/pos_object_y_target2_carry_i_10_n_0
+ SLICE_X84Y70 LUT6 (Prop_lut6_I3_O) 0.124 8.201 r runnerObject/pos_object_y_target2_carry_i_9/O
+ net (fo=1, routed) 0.701 8.903 runnerObject/pos_object_y_target2_carry_i_9_n_0
+ SLICE_X85Y70 CARRY4 (Prop_carry4_S[0]_O[3])
+ 0.730 9.633 f runnerObject/pos_object_y_target2_carry/O[3]
+ net (fo=2, routed) 1.215 10.847 runnerObject/pos_object_y_target2[4]
+ SLICE_X84Y73 LUT2 (Prop_lut2_I1_O) 0.306 11.153 r runnerObject/pos_object_y_target1_carry_i_4/O
+ net (fo=1, routed) 0.000 11.153 runnerObject/pos_object_y_target1_carry_i_4_n_0
+ SLICE_X84Y73 CARRY4 (Prop_carry4_S[2]_CO[3])
+ 0.380 11.533 r runnerObject/pos_object_y_target1_carry/CO[3]
+ net (fo=1, routed) 0.000 11.533 runnerObject/pos_object_y_target1_carry_n_0
+ SLICE_X84Y74 CARRY4 (Prop_carry4_CI_CO[3])
+ 0.117 11.650 r runnerObject/pos_object_y_target1_carry__0/CO[3]
+ net (fo=1, routed) 0.009 11.659 runnerObject/pos_object_y_target1_carry__0_n_0
+ SLICE_X84Y75 CARRY4 (Prop_carry4_CI_CO[1])
+ 0.157 11.816 f runnerObject/pos_object_y_target1_carry__1/CO[1]
+ net (fo=11, routed) 0.629 12.445 runnerObject/pos_object_y_target1
+ SLICE_X86Y77 LUT3 (Prop_lut3_I0_O) 0.332 12.777 r runnerObject/pos_object_y_target[8]_i_1/O
+ net (fo=9, routed) 0.697 13.474 runnerObject/pos_object_y_target[8]_i_1_n_0
+ SLICE_X89Y79 FDRE r runnerObject/pos_object_y_target_reg[0]/R
+ ------------------------------------------------------------------- -------------------
+
+ (clock clk_out1_clk_wiz_0 rise edge)
+ 40.000 40.000 r
+ E3 0.000 40.000 r clk (IN)
+ net (fo=0) 0.000 40.000 pixelClk/inst/clk_in1
+ E3 IBUF (Prop_ibuf_I_O) 1.411 41.411 r pixelClk/inst/clkin1_ibufg/O
+ net (fo=1, routed) 1.162 42.573 pixelClk/inst/clk_in1_clk_wiz_0
+ MMCME2_ADV_X1Y2 MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKOUT0)
+ -7.324 35.249 r pixelClk/inst/mmcm_adv_inst/CLKOUT0
+ net (fo=1, routed) 1.639 36.888 pixelClk/inst/clk_out1_clk_wiz_0
+ BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.091 36.979 r pixelClk/inst/clkout1_buf/O
+ net (fo=127, routed) 1.601 38.581 runnerObject/clk_out1
+ SLICE_X89Y79 FDRE r runnerObject/pos_object_y_target_reg[0]/C
+ clock pessimism 0.559 39.140
+ clock uncertainty -0.098 39.043
+ SLICE_X89Y79 FDRE (Setup_fdre_C_R) -0.429 38.614 runnerObject/pos_object_y_target_reg[0]
+ -------------------------------------------------------------------
+ required time 38.614
+ arrival time -13.474
+ -------------------------------------------------------------------
+ slack 25.140
+
+Slack (MET) : 25.140ns (required time - arrival time)
+ Source: vgaInterface/counter_f_reg[2]/C
+ (rising edge-triggered cell FDCE clocked by clk_out1_clk_wiz_0_1 {rise@0.000ns fall@20.000ns period=40.000ns})
+ Destination: runnerObject/pos_object_y_target_reg[1]/S
+ (rising edge-triggered cell FDSE clocked by clk_out1_clk_wiz_0 {rise@0.000ns fall@20.000ns period=40.000ns})
+ Path Group: clk_out1_clk_wiz_0
+ Path Type: Setup (Max at Slow Process Corner)
+ Requirement: 40.000ns (clk_out1_clk_wiz_0 rise@40.000ns - clk_out1_clk_wiz_0_1 rise@0.000ns)
+ Data Path Delay: 14.294ns (logic 5.777ns (40.414%) route 8.517ns (59.586%))
+ Logic Levels: 17 (CARRY4=9 LUT1=2 LUT2=2 LUT3=1 LUT4=1 LUT6=2)
+ Clock Path Skew: -0.039ns (DCD - SCD + CPR)
+ Destination Clock Delay (DCD): -1.419ns = ( 38.581 - 40.000 )
+ Source Clock Delay (SCD): -0.821ns
+ Clock Pessimism Removal (CPR): 0.559ns
+ Clock Uncertainty: 0.098ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE
+ Total System Jitter (TSJ): 0.071ns
+ Discrete Jitter (DJ): 0.182ns
+ Phase Error (PE): 0.000ns
+ Clock Domain Crossing: Inter clock paths are considered valid unless explicitly excluded by timing constraints such as set_clock_groups or set_false_path.
+
+ Location Delay type Incr(ns) Path(ns) Netlist Resource(s)
+ ------------------------------------------------------------------- -------------------
+ (clock clk_out1_clk_wiz_0_1 rise edge)
+ 0.000 0.000 r
+ E3 0.000 0.000 r clk (IN)
+ net (fo=0) 0.000 0.000 pixelClk/inst/clk_in1
+ E3 IBUF (Prop_ibuf_I_O) 1.482 1.482 r pixelClk/inst/clkin1_ibufg/O
+ net (fo=1, routed) 1.233 2.715 pixelClk/inst/clk_in1_clk_wiz_0
+ MMCME2_ADV_X1Y2 MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKOUT0)
+ -7.070 -4.355 r pixelClk/inst/mmcm_adv_inst/CLKOUT0
+ net (fo=1, routed) 1.719 -2.636 pixelClk/inst/clk_out1_clk_wiz_0
+ BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.096 -2.540 r pixelClk/inst/clkout1_buf/O
+ net (fo=127, routed) 1.719 -0.821 vgaInterface/clk_out1
+ SLICE_X89Y70 FDCE r vgaInterface/counter_f_reg[2]/C
+ ------------------------------------------------------------------- -------------------
+ SLICE_X89Y70 FDCE (Prop_fdce_C_Q) 0.456 -0.365 f vgaInterface/counter_f_reg[2]/Q
+ net (fo=5, routed) 1.006 0.641 vgaInterface/counter_f_reg[2]
+ SLICE_X88Y67 LUT1 (Prop_lut1_I0_O) 0.124 0.765 r vgaInterface/FCounter_17bit_carry_i_3/O
+ net (fo=1, routed) 0.000 0.765 runnerObject/pos_object_y_target6_carry_0[1]
+ SLICE_X88Y67 CARRY4 (Prop_carry4_S[1]_CO[3])
+ 0.533 1.298 r runnerObject/FCounter_17bit_carry/CO[3]
+ net (fo=1, routed) 0.000 1.298 runnerObject/FCounter_17bit_carry_n_0
+ SLICE_X88Y68 CARRY4 (Prop_carry4_CI_O[2])
+ 0.239 1.537 r runnerObject/FCounter_17bit_carry__0/O[2]
+ net (fo=2, routed) 0.987 2.523 runnerObject/FCounter_17bit[7]
+ SLICE_X88Y71 LUT2 (Prop_lut2_I0_O) 0.301 2.824 r runnerObject/pos_object_y_target6_carry__0_i_1/O
+ net (fo=1, routed) 0.000 2.824 runnerObject/pos_object_y_target6_carry__0_i_1_n_0
+ SLICE_X88Y71 CARRY4 (Prop_carry4_S[3]_CO[3])
+ 0.376 3.200 r runnerObject/pos_object_y_target6_carry__0/CO[3]
+ net (fo=1, routed) 0.000 3.200 runnerObject/pos_object_y_target6_carry__0_n_0
+ SLICE_X88Y72 CARRY4 (Prop_carry4_CI_O[1])
+ 0.323 3.523 f runnerObject/pos_object_y_target6_carry__1/O[1]
+ net (fo=5, routed) 0.953 4.477 runnerObject/pos_object_y_target6[9]
+ SLICE_X82Y72 LUT1 (Prop_lut1_I0_O) 0.306 4.783 r runnerObject/i__carry__1_i_13/O
+ net (fo=1, routed) 0.000 4.783 runnerObject/p_0_in[9]
+ SLICE_X82Y72 CARRY4 (Prop_carry4_S[0]_O[2])
+ 0.547 5.330 f runnerObject/i__carry__1_i_9/O[2]
+ net (fo=2, routed) 0.821 6.151 runnerObject/pos_object_y_target9[11]
+ SLICE_X84Y71 LUT4 (Prop_lut4_I3_O) 0.302 6.453 r runnerObject/pos_object_y_target2_carry_i_13/O
+ net (fo=2, routed) 0.420 6.872 runnerObject/pos_object_y_target2_carry_i_13_n_0
+ SLICE_X87Y72 LUT6 (Prop_lut6_I0_O) 0.124 6.996 r runnerObject/pos_object_y_target2_carry_i_10/O
+ net (fo=34, routed) 1.081 8.077 runnerObject/pos_object_y_target2_carry_i_10_n_0
+ SLICE_X84Y70 LUT6 (Prop_lut6_I3_O) 0.124 8.201 r runnerObject/pos_object_y_target2_carry_i_9/O
+ net (fo=1, routed) 0.701 8.903 runnerObject/pos_object_y_target2_carry_i_9_n_0
+ SLICE_X85Y70 CARRY4 (Prop_carry4_S[0]_O[3])
+ 0.730 9.633 f runnerObject/pos_object_y_target2_carry/O[3]
+ net (fo=2, routed) 1.215 10.847 runnerObject/pos_object_y_target2[4]
+ SLICE_X84Y73 LUT2 (Prop_lut2_I1_O) 0.306 11.153 r runnerObject/pos_object_y_target1_carry_i_4/O
+ net (fo=1, routed) 0.000 11.153 runnerObject/pos_object_y_target1_carry_i_4_n_0
+ SLICE_X84Y73 CARRY4 (Prop_carry4_S[2]_CO[3])
+ 0.380 11.533 r runnerObject/pos_object_y_target1_carry/CO[3]
+ net (fo=1, routed) 0.000 11.533 runnerObject/pos_object_y_target1_carry_n_0
+ SLICE_X84Y74 CARRY4 (Prop_carry4_CI_CO[3])
+ 0.117 11.650 r runnerObject/pos_object_y_target1_carry__0/CO[3]
+ net (fo=1, routed) 0.009 11.659 runnerObject/pos_object_y_target1_carry__0_n_0
+ SLICE_X84Y75 CARRY4 (Prop_carry4_CI_CO[1])
+ 0.157 11.816 f runnerObject/pos_object_y_target1_carry__1/CO[1]
+ net (fo=11, routed) 0.629 12.445 runnerObject/pos_object_y_target1
+ SLICE_X86Y77 LUT3 (Prop_lut3_I0_O) 0.332 12.777 r runnerObject/pos_object_y_target[8]_i_1/O
+ net (fo=9, routed) 0.697 13.474 runnerObject/pos_object_y_target[8]_i_1_n_0
+ SLICE_X89Y79 FDSE r runnerObject/pos_object_y_target_reg[1]/S
+ ------------------------------------------------------------------- -------------------
+
+ (clock clk_out1_clk_wiz_0 rise edge)
+ 40.000 40.000 r
+ E3 0.000 40.000 r clk (IN)
+ net (fo=0) 0.000 40.000 pixelClk/inst/clk_in1
+ E3 IBUF (Prop_ibuf_I_O) 1.411 41.411 r pixelClk/inst/clkin1_ibufg/O
+ net (fo=1, routed) 1.162 42.573 pixelClk/inst/clk_in1_clk_wiz_0
+ MMCME2_ADV_X1Y2 MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKOUT0)
+ -7.324 35.249 r pixelClk/inst/mmcm_adv_inst/CLKOUT0
+ net (fo=1, routed) 1.639 36.888 pixelClk/inst/clk_out1_clk_wiz_0
+ BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.091 36.979 r pixelClk/inst/clkout1_buf/O
+ net (fo=127, routed) 1.601 38.581 runnerObject/clk_out1
+ SLICE_X89Y79 FDSE r runnerObject/pos_object_y_target_reg[1]/C
+ clock pessimism 0.559 39.140
+ clock uncertainty -0.098 39.043
+ SLICE_X89Y79 FDSE (Setup_fdse_C_S) -0.429 38.614 runnerObject/pos_object_y_target_reg[1]
+ -------------------------------------------------------------------
+ required time 38.614
+ arrival time -13.474
+ -------------------------------------------------------------------
+ slack 25.140
+
+Slack (MET) : 25.140ns (required time - arrival time)
+ Source: vgaInterface/counter_f_reg[2]/C
+ (rising edge-triggered cell FDCE clocked by clk_out1_clk_wiz_0_1 {rise@0.000ns fall@20.000ns period=40.000ns})
+ Destination: runnerObject/pos_object_y_target_reg[2]/S
+ (rising edge-triggered cell FDSE clocked by clk_out1_clk_wiz_0 {rise@0.000ns fall@20.000ns period=40.000ns})
+ Path Group: clk_out1_clk_wiz_0
+ Path Type: Setup (Max at Slow Process Corner)
+ Requirement: 40.000ns (clk_out1_clk_wiz_0 rise@40.000ns - clk_out1_clk_wiz_0_1 rise@0.000ns)
+ Data Path Delay: 14.294ns (logic 5.777ns (40.414%) route 8.517ns (59.586%))
+ Logic Levels: 17 (CARRY4=9 LUT1=2 LUT2=2 LUT3=1 LUT4=1 LUT6=2)
+ Clock Path Skew: -0.039ns (DCD - SCD + CPR)
+ Destination Clock Delay (DCD): -1.419ns = ( 38.581 - 40.000 )
+ Source Clock Delay (SCD): -0.821ns
+ Clock Pessimism Removal (CPR): 0.559ns
+ Clock Uncertainty: 0.098ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE
+ Total System Jitter (TSJ): 0.071ns
+ Discrete Jitter (DJ): 0.182ns
+ Phase Error (PE): 0.000ns
+ Clock Domain Crossing: Inter clock paths are considered valid unless explicitly excluded by timing constraints such as set_clock_groups or set_false_path.
+
+ Location Delay type Incr(ns) Path(ns) Netlist Resource(s)
+ ------------------------------------------------------------------- -------------------
+ (clock clk_out1_clk_wiz_0_1 rise edge)
+ 0.000 0.000 r
+ E3 0.000 0.000 r clk (IN)
+ net (fo=0) 0.000 0.000 pixelClk/inst/clk_in1
+ E3 IBUF (Prop_ibuf_I_O) 1.482 1.482 r pixelClk/inst/clkin1_ibufg/O
+ net (fo=1, routed) 1.233 2.715 pixelClk/inst/clk_in1_clk_wiz_0
+ MMCME2_ADV_X1Y2 MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKOUT0)
+ -7.070 -4.355 r pixelClk/inst/mmcm_adv_inst/CLKOUT0
+ net (fo=1, routed) 1.719 -2.636 pixelClk/inst/clk_out1_clk_wiz_0
+ BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.096 -2.540 r pixelClk/inst/clkout1_buf/O
+ net (fo=127, routed) 1.719 -0.821 vgaInterface/clk_out1
+ SLICE_X89Y70 FDCE r vgaInterface/counter_f_reg[2]/C
+ ------------------------------------------------------------------- -------------------
+ SLICE_X89Y70 FDCE (Prop_fdce_C_Q) 0.456 -0.365 f vgaInterface/counter_f_reg[2]/Q
+ net (fo=5, routed) 1.006 0.641 vgaInterface/counter_f_reg[2]
+ SLICE_X88Y67 LUT1 (Prop_lut1_I0_O) 0.124 0.765 r vgaInterface/FCounter_17bit_carry_i_3/O
+ net (fo=1, routed) 0.000 0.765 runnerObject/pos_object_y_target6_carry_0[1]
+ SLICE_X88Y67 CARRY4 (Prop_carry4_S[1]_CO[3])
+ 0.533 1.298 r runnerObject/FCounter_17bit_carry/CO[3]
+ net (fo=1, routed) 0.000 1.298 runnerObject/FCounter_17bit_carry_n_0
+ SLICE_X88Y68 CARRY4 (Prop_carry4_CI_O[2])
+ 0.239 1.537 r runnerObject/FCounter_17bit_carry__0/O[2]
+ net (fo=2, routed) 0.987 2.523 runnerObject/FCounter_17bit[7]
+ SLICE_X88Y71 LUT2 (Prop_lut2_I0_O) 0.301 2.824 r runnerObject/pos_object_y_target6_carry__0_i_1/O
+ net (fo=1, routed) 0.000 2.824 runnerObject/pos_object_y_target6_carry__0_i_1_n_0
+ SLICE_X88Y71 CARRY4 (Prop_carry4_S[3]_CO[3])
+ 0.376 3.200 r runnerObject/pos_object_y_target6_carry__0/CO[3]
+ net (fo=1, routed) 0.000 3.200 runnerObject/pos_object_y_target6_carry__0_n_0
+ SLICE_X88Y72 CARRY4 (Prop_carry4_CI_O[1])
+ 0.323 3.523 f runnerObject/pos_object_y_target6_carry__1/O[1]
+ net (fo=5, routed) 0.953 4.477 runnerObject/pos_object_y_target6[9]
+ SLICE_X82Y72 LUT1 (Prop_lut1_I0_O) 0.306 4.783 r runnerObject/i__carry__1_i_13/O
+ net (fo=1, routed) 0.000 4.783 runnerObject/p_0_in[9]
+ SLICE_X82Y72 CARRY4 (Prop_carry4_S[0]_O[2])
+ 0.547 5.330 f runnerObject/i__carry__1_i_9/O[2]
+ net (fo=2, routed) 0.821 6.151 runnerObject/pos_object_y_target9[11]
+ SLICE_X84Y71 LUT4 (Prop_lut4_I3_O) 0.302 6.453 r runnerObject/pos_object_y_target2_carry_i_13/O
+ net (fo=2, routed) 0.420 6.872 runnerObject/pos_object_y_target2_carry_i_13_n_0
+ SLICE_X87Y72 LUT6 (Prop_lut6_I0_O) 0.124 6.996 r runnerObject/pos_object_y_target2_carry_i_10/O
+ net (fo=34, routed) 1.081 8.077 runnerObject/pos_object_y_target2_carry_i_10_n_0
+ SLICE_X84Y70 LUT6 (Prop_lut6_I3_O) 0.124 8.201 r runnerObject/pos_object_y_target2_carry_i_9/O
+ net (fo=1, routed) 0.701 8.903 runnerObject/pos_object_y_target2_carry_i_9_n_0
+ SLICE_X85Y70 CARRY4 (Prop_carry4_S[0]_O[3])
+ 0.730 9.633 f runnerObject/pos_object_y_target2_carry/O[3]
+ net (fo=2, routed) 1.215 10.847 runnerObject/pos_object_y_target2[4]
+ SLICE_X84Y73 LUT2 (Prop_lut2_I1_O) 0.306 11.153 r runnerObject/pos_object_y_target1_carry_i_4/O
+ net (fo=1, routed) 0.000 11.153 runnerObject/pos_object_y_target1_carry_i_4_n_0
+ SLICE_X84Y73 CARRY4 (Prop_carry4_S[2]_CO[3])
+ 0.380 11.533 r runnerObject/pos_object_y_target1_carry/CO[3]
+ net (fo=1, routed) 0.000 11.533 runnerObject/pos_object_y_target1_carry_n_0
+ SLICE_X84Y74 CARRY4 (Prop_carry4_CI_CO[3])
+ 0.117 11.650 r runnerObject/pos_object_y_target1_carry__0/CO[3]
+ net (fo=1, routed) 0.009 11.659 runnerObject/pos_object_y_target1_carry__0_n_0
+ SLICE_X84Y75 CARRY4 (Prop_carry4_CI_CO[1])
+ 0.157 11.816 f runnerObject/pos_object_y_target1_carry__1/CO[1]
+ net (fo=11, routed) 0.629 12.445 runnerObject/pos_object_y_target1
+ SLICE_X86Y77 LUT3 (Prop_lut3_I0_O) 0.332 12.777 r runnerObject/pos_object_y_target[8]_i_1/O
+ net (fo=9, routed) 0.697 13.474 runnerObject/pos_object_y_target[8]_i_1_n_0
+ SLICE_X89Y79 FDSE r runnerObject/pos_object_y_target_reg[2]/S
+ ------------------------------------------------------------------- -------------------
+
+ (clock clk_out1_clk_wiz_0 rise edge)
+ 40.000 40.000 r
+ E3 0.000 40.000 r clk (IN)
+ net (fo=0) 0.000 40.000 pixelClk/inst/clk_in1
+ E3 IBUF (Prop_ibuf_I_O) 1.411 41.411 r pixelClk/inst/clkin1_ibufg/O
+ net (fo=1, routed) 1.162 42.573 pixelClk/inst/clk_in1_clk_wiz_0
+ MMCME2_ADV_X1Y2 MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKOUT0)
+ -7.324 35.249 r pixelClk/inst/mmcm_adv_inst/CLKOUT0
+ net (fo=1, routed) 1.639 36.888 pixelClk/inst/clk_out1_clk_wiz_0
+ BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.091 36.979 r pixelClk/inst/clkout1_buf/O
+ net (fo=127, routed) 1.601 38.581 runnerObject/clk_out1
+ SLICE_X89Y79 FDSE r runnerObject/pos_object_y_target_reg[2]/C
+ clock pessimism 0.559 39.140
+ clock uncertainty -0.098 39.043
+ SLICE_X89Y79 FDSE (Setup_fdse_C_S) -0.429 38.614 runnerObject/pos_object_y_target_reg[2]
+ -------------------------------------------------------------------
+ required time 38.614
+ arrival time -13.474
+ -------------------------------------------------------------------
+ slack 25.140
+
+Slack (MET) : 25.140ns (required time - arrival time)
+ Source: vgaInterface/counter_f_reg[2]/C
+ (rising edge-triggered cell FDCE clocked by clk_out1_clk_wiz_0_1 {rise@0.000ns fall@20.000ns period=40.000ns})
+ Destination: runnerObject/pos_object_y_target_reg[3]/S
+ (rising edge-triggered cell FDSE clocked by clk_out1_clk_wiz_0 {rise@0.000ns fall@20.000ns period=40.000ns})
+ Path Group: clk_out1_clk_wiz_0
+ Path Type: Setup (Max at Slow Process Corner)
+ Requirement: 40.000ns (clk_out1_clk_wiz_0 rise@40.000ns - clk_out1_clk_wiz_0_1 rise@0.000ns)
+ Data Path Delay: 14.294ns (logic 5.777ns (40.414%) route 8.517ns (59.586%))
+ Logic Levels: 17 (CARRY4=9 LUT1=2 LUT2=2 LUT3=1 LUT4=1 LUT6=2)
+ Clock Path Skew: -0.039ns (DCD - SCD + CPR)
+ Destination Clock Delay (DCD): -1.419ns = ( 38.581 - 40.000 )
+ Source Clock Delay (SCD): -0.821ns
+ Clock Pessimism Removal (CPR): 0.559ns
+ Clock Uncertainty: 0.098ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE
+ Total System Jitter (TSJ): 0.071ns
+ Discrete Jitter (DJ): 0.182ns
+ Phase Error (PE): 0.000ns
+ Clock Domain Crossing: Inter clock paths are considered valid unless explicitly excluded by timing constraints such as set_clock_groups or set_false_path.
+
+ Location Delay type Incr(ns) Path(ns) Netlist Resource(s)
+ ------------------------------------------------------------------- -------------------
+ (clock clk_out1_clk_wiz_0_1 rise edge)
+ 0.000 0.000 r
+ E3 0.000 0.000 r clk (IN)
+ net (fo=0) 0.000 0.000 pixelClk/inst/clk_in1
+ E3 IBUF (Prop_ibuf_I_O) 1.482 1.482 r pixelClk/inst/clkin1_ibufg/O
+ net (fo=1, routed) 1.233 2.715 pixelClk/inst/clk_in1_clk_wiz_0
+ MMCME2_ADV_X1Y2 MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKOUT0)
+ -7.070 -4.355 r pixelClk/inst/mmcm_adv_inst/CLKOUT0
+ net (fo=1, routed) 1.719 -2.636 pixelClk/inst/clk_out1_clk_wiz_0
+ BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.096 -2.540 r pixelClk/inst/clkout1_buf/O
+ net (fo=127, routed) 1.719 -0.821 vgaInterface/clk_out1
+ SLICE_X89Y70 FDCE r vgaInterface/counter_f_reg[2]/C
+ ------------------------------------------------------------------- -------------------
+ SLICE_X89Y70 FDCE (Prop_fdce_C_Q) 0.456 -0.365 f vgaInterface/counter_f_reg[2]/Q
+ net (fo=5, routed) 1.006 0.641 vgaInterface/counter_f_reg[2]
+ SLICE_X88Y67 LUT1 (Prop_lut1_I0_O) 0.124 0.765 r vgaInterface/FCounter_17bit_carry_i_3/O
+ net (fo=1, routed) 0.000 0.765 runnerObject/pos_object_y_target6_carry_0[1]
+ SLICE_X88Y67 CARRY4 (Prop_carry4_S[1]_CO[3])
+ 0.533 1.298 r runnerObject/FCounter_17bit_carry/CO[3]
+ net (fo=1, routed) 0.000 1.298 runnerObject/FCounter_17bit_carry_n_0
+ SLICE_X88Y68 CARRY4 (Prop_carry4_CI_O[2])
+ 0.239 1.537 r runnerObject/FCounter_17bit_carry__0/O[2]
+ net (fo=2, routed) 0.987 2.523 runnerObject/FCounter_17bit[7]
+ SLICE_X88Y71 LUT2 (Prop_lut2_I0_O) 0.301 2.824 r runnerObject/pos_object_y_target6_carry__0_i_1/O
+ net (fo=1, routed) 0.000 2.824 runnerObject/pos_object_y_target6_carry__0_i_1_n_0
+ SLICE_X88Y71 CARRY4 (Prop_carry4_S[3]_CO[3])
+ 0.376 3.200 r runnerObject/pos_object_y_target6_carry__0/CO[3]
+ net (fo=1, routed) 0.000 3.200 runnerObject/pos_object_y_target6_carry__0_n_0
+ SLICE_X88Y72 CARRY4 (Prop_carry4_CI_O[1])
+ 0.323 3.523 f runnerObject/pos_object_y_target6_carry__1/O[1]
+ net (fo=5, routed) 0.953 4.477 runnerObject/pos_object_y_target6[9]
+ SLICE_X82Y72 LUT1 (Prop_lut1_I0_O) 0.306 4.783 r runnerObject/i__carry__1_i_13/O
+ net (fo=1, routed) 0.000 4.783 runnerObject/p_0_in[9]
+ SLICE_X82Y72 CARRY4 (Prop_carry4_S[0]_O[2])
+ 0.547 5.330 f runnerObject/i__carry__1_i_9/O[2]
+ net (fo=2, routed) 0.821 6.151 runnerObject/pos_object_y_target9[11]
+ SLICE_X84Y71 LUT4 (Prop_lut4_I3_O) 0.302 6.453 r runnerObject/pos_object_y_target2_carry_i_13/O
+ net (fo=2, routed) 0.420 6.872 runnerObject/pos_object_y_target2_carry_i_13_n_0
+ SLICE_X87Y72 LUT6 (Prop_lut6_I0_O) 0.124 6.996 r runnerObject/pos_object_y_target2_carry_i_10/O
+ net (fo=34, routed) 1.081 8.077 runnerObject/pos_object_y_target2_carry_i_10_n_0
+ SLICE_X84Y70 LUT6 (Prop_lut6_I3_O) 0.124 8.201 r runnerObject/pos_object_y_target2_carry_i_9/O
+ net (fo=1, routed) 0.701 8.903 runnerObject/pos_object_y_target2_carry_i_9_n_0
+ SLICE_X85Y70 CARRY4 (Prop_carry4_S[0]_O[3])
+ 0.730 9.633 f runnerObject/pos_object_y_target2_carry/O[3]
+ net (fo=2, routed) 1.215 10.847 runnerObject/pos_object_y_target2[4]
+ SLICE_X84Y73 LUT2 (Prop_lut2_I1_O) 0.306 11.153 r runnerObject/pos_object_y_target1_carry_i_4/O
+ net (fo=1, routed) 0.000 11.153 runnerObject/pos_object_y_target1_carry_i_4_n_0
+ SLICE_X84Y73 CARRY4 (Prop_carry4_S[2]_CO[3])
+ 0.380 11.533 r runnerObject/pos_object_y_target1_carry/CO[3]
+ net (fo=1, routed) 0.000 11.533 runnerObject/pos_object_y_target1_carry_n_0
+ SLICE_X84Y74 CARRY4 (Prop_carry4_CI_CO[3])
+ 0.117 11.650 r runnerObject/pos_object_y_target1_carry__0/CO[3]
+ net (fo=1, routed) 0.009 11.659 runnerObject/pos_object_y_target1_carry__0_n_0
+ SLICE_X84Y75 CARRY4 (Prop_carry4_CI_CO[1])
+ 0.157 11.816 f runnerObject/pos_object_y_target1_carry__1/CO[1]
+ net (fo=11, routed) 0.629 12.445 runnerObject/pos_object_y_target1
+ SLICE_X86Y77 LUT3 (Prop_lut3_I0_O) 0.332 12.777 r runnerObject/pos_object_y_target[8]_i_1/O
+ net (fo=9, routed) 0.697 13.474 runnerObject/pos_object_y_target[8]_i_1_n_0
+ SLICE_X89Y79 FDSE r runnerObject/pos_object_y_target_reg[3]/S
+ ------------------------------------------------------------------- -------------------
+
+ (clock clk_out1_clk_wiz_0 rise edge)
+ 40.000 40.000 r
+ E3 0.000 40.000 r clk (IN)
+ net (fo=0) 0.000 40.000 pixelClk/inst/clk_in1
+ E3 IBUF (Prop_ibuf_I_O) 1.411 41.411 r pixelClk/inst/clkin1_ibufg/O
+ net (fo=1, routed) 1.162 42.573 pixelClk/inst/clk_in1_clk_wiz_0
+ MMCME2_ADV_X1Y2 MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKOUT0)
+ -7.324 35.249 r pixelClk/inst/mmcm_adv_inst/CLKOUT0
+ net (fo=1, routed) 1.639 36.888 pixelClk/inst/clk_out1_clk_wiz_0
+ BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.091 36.979 r pixelClk/inst/clkout1_buf/O
+ net (fo=127, routed) 1.601 38.581 runnerObject/clk_out1
+ SLICE_X89Y79 FDSE r runnerObject/pos_object_y_target_reg[3]/C
+ clock pessimism 0.559 39.140
+ clock uncertainty -0.098 39.043
+ SLICE_X89Y79 FDSE (Setup_fdse_C_S) -0.429 38.614 runnerObject/pos_object_y_target_reg[3]
+ -------------------------------------------------------------------
+ required time 38.614
+ arrival time -13.474
+ -------------------------------------------------------------------
+ slack 25.140
+
+Slack (MET) : 25.140ns (required time - arrival time)
+ Source: vgaInterface/counter_f_reg[2]/C
+ (rising edge-triggered cell FDCE clocked by clk_out1_clk_wiz_0_1 {rise@0.000ns fall@20.000ns period=40.000ns})
+ Destination: runnerObject/pos_object_y_target_reg[4]/S
+ (rising edge-triggered cell FDSE clocked by clk_out1_clk_wiz_0 {rise@0.000ns fall@20.000ns period=40.000ns})
+ Path Group: clk_out1_clk_wiz_0
+ Path Type: Setup (Max at Slow Process Corner)
+ Requirement: 40.000ns (clk_out1_clk_wiz_0 rise@40.000ns - clk_out1_clk_wiz_0_1 rise@0.000ns)
+ Data Path Delay: 14.294ns (logic 5.777ns (40.414%) route 8.517ns (59.586%))
+ Logic Levels: 17 (CARRY4=9 LUT1=2 LUT2=2 LUT3=1 LUT4=1 LUT6=2)
+ Clock Path Skew: -0.039ns (DCD - SCD + CPR)
+ Destination Clock Delay (DCD): -1.419ns = ( 38.581 - 40.000 )
+ Source Clock Delay (SCD): -0.821ns
+ Clock Pessimism Removal (CPR): 0.559ns
+ Clock Uncertainty: 0.098ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE
+ Total System Jitter (TSJ): 0.071ns
+ Discrete Jitter (DJ): 0.182ns
+ Phase Error (PE): 0.000ns
+ Clock Domain Crossing: Inter clock paths are considered valid unless explicitly excluded by timing constraints such as set_clock_groups or set_false_path.
+
+ Location Delay type Incr(ns) Path(ns) Netlist Resource(s)
+ ------------------------------------------------------------------- -------------------
+ (clock clk_out1_clk_wiz_0_1 rise edge)
+ 0.000 0.000 r
+ E3 0.000 0.000 r clk (IN)
+ net (fo=0) 0.000 0.000 pixelClk/inst/clk_in1
+ E3 IBUF (Prop_ibuf_I_O) 1.482 1.482 r pixelClk/inst/clkin1_ibufg/O
+ net (fo=1, routed) 1.233 2.715 pixelClk/inst/clk_in1_clk_wiz_0
+ MMCME2_ADV_X1Y2 MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKOUT0)
+ -7.070 -4.355 r pixelClk/inst/mmcm_adv_inst/CLKOUT0
+ net (fo=1, routed) 1.719 -2.636 pixelClk/inst/clk_out1_clk_wiz_0
+ BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.096 -2.540 r pixelClk/inst/clkout1_buf/O
+ net (fo=127, routed) 1.719 -0.821 vgaInterface/clk_out1
+ SLICE_X89Y70 FDCE r vgaInterface/counter_f_reg[2]/C
+ ------------------------------------------------------------------- -------------------
+ SLICE_X89Y70 FDCE (Prop_fdce_C_Q) 0.456 -0.365 f vgaInterface/counter_f_reg[2]/Q
+ net (fo=5, routed) 1.006 0.641 vgaInterface/counter_f_reg[2]
+ SLICE_X88Y67 LUT1 (Prop_lut1_I0_O) 0.124 0.765 r vgaInterface/FCounter_17bit_carry_i_3/O
+ net (fo=1, routed) 0.000 0.765 runnerObject/pos_object_y_target6_carry_0[1]
+ SLICE_X88Y67 CARRY4 (Prop_carry4_S[1]_CO[3])
+ 0.533 1.298 r runnerObject/FCounter_17bit_carry/CO[3]
+ net (fo=1, routed) 0.000 1.298 runnerObject/FCounter_17bit_carry_n_0
+ SLICE_X88Y68 CARRY4 (Prop_carry4_CI_O[2])
+ 0.239 1.537 r runnerObject/FCounter_17bit_carry__0/O[2]
+ net (fo=2, routed) 0.987 2.523 runnerObject/FCounter_17bit[7]
+ SLICE_X88Y71 LUT2 (Prop_lut2_I0_O) 0.301 2.824 r runnerObject/pos_object_y_target6_carry__0_i_1/O
+ net (fo=1, routed) 0.000 2.824 runnerObject/pos_object_y_target6_carry__0_i_1_n_0
+ SLICE_X88Y71 CARRY4 (Prop_carry4_S[3]_CO[3])
+ 0.376 3.200 r runnerObject/pos_object_y_target6_carry__0/CO[3]
+ net (fo=1, routed) 0.000 3.200 runnerObject/pos_object_y_target6_carry__0_n_0
+ SLICE_X88Y72 CARRY4 (Prop_carry4_CI_O[1])
+ 0.323 3.523 f runnerObject/pos_object_y_target6_carry__1/O[1]
+ net (fo=5, routed) 0.953 4.477 runnerObject/pos_object_y_target6[9]
+ SLICE_X82Y72 LUT1 (Prop_lut1_I0_O) 0.306 4.783 r runnerObject/i__carry__1_i_13/O
+ net (fo=1, routed) 0.000 4.783 runnerObject/p_0_in[9]
+ SLICE_X82Y72 CARRY4 (Prop_carry4_S[0]_O[2])
+ 0.547 5.330 f runnerObject/i__carry__1_i_9/O[2]
+ net (fo=2, routed) 0.821 6.151 runnerObject/pos_object_y_target9[11]
+ SLICE_X84Y71 LUT4 (Prop_lut4_I3_O) 0.302 6.453 r runnerObject/pos_object_y_target2_carry_i_13/O
+ net (fo=2, routed) 0.420 6.872 runnerObject/pos_object_y_target2_carry_i_13_n_0
+ SLICE_X87Y72 LUT6 (Prop_lut6_I0_O) 0.124 6.996 r runnerObject/pos_object_y_target2_carry_i_10/O
+ net (fo=34, routed) 1.081 8.077 runnerObject/pos_object_y_target2_carry_i_10_n_0
+ SLICE_X84Y70 LUT6 (Prop_lut6_I3_O) 0.124 8.201 r runnerObject/pos_object_y_target2_carry_i_9/O
+ net (fo=1, routed) 0.701 8.903 runnerObject/pos_object_y_target2_carry_i_9_n_0
+ SLICE_X85Y70 CARRY4 (Prop_carry4_S[0]_O[3])
+ 0.730 9.633 f runnerObject/pos_object_y_target2_carry/O[3]
+ net (fo=2, routed) 1.215 10.847 runnerObject/pos_object_y_target2[4]
+ SLICE_X84Y73 LUT2 (Prop_lut2_I1_O) 0.306 11.153 r runnerObject/pos_object_y_target1_carry_i_4/O
+ net (fo=1, routed) 0.000 11.153 runnerObject/pos_object_y_target1_carry_i_4_n_0
+ SLICE_X84Y73 CARRY4 (Prop_carry4_S[2]_CO[3])
+ 0.380 11.533 r runnerObject/pos_object_y_target1_carry/CO[3]
+ net (fo=1, routed) 0.000 11.533 runnerObject/pos_object_y_target1_carry_n_0
+ SLICE_X84Y74 CARRY4 (Prop_carry4_CI_CO[3])
+ 0.117 11.650 r runnerObject/pos_object_y_target1_carry__0/CO[3]
+ net (fo=1, routed) 0.009 11.659 runnerObject/pos_object_y_target1_carry__0_n_0
+ SLICE_X84Y75 CARRY4 (Prop_carry4_CI_CO[1])
+ 0.157 11.816 f runnerObject/pos_object_y_target1_carry__1/CO[1]
+ net (fo=11, routed) 0.629 12.445 runnerObject/pos_object_y_target1
+ SLICE_X86Y77 LUT3 (Prop_lut3_I0_O) 0.332 12.777 r runnerObject/pos_object_y_target[8]_i_1/O
+ net (fo=9, routed) 0.697 13.474 runnerObject/pos_object_y_target[8]_i_1_n_0
+ SLICE_X89Y79 FDSE r runnerObject/pos_object_y_target_reg[4]/S
+ ------------------------------------------------------------------- -------------------
+
+ (clock clk_out1_clk_wiz_0 rise edge)
+ 40.000 40.000 r
+ E3 0.000 40.000 r clk (IN)
+ net (fo=0) 0.000 40.000 pixelClk/inst/clk_in1
+ E3 IBUF (Prop_ibuf_I_O) 1.411 41.411 r pixelClk/inst/clkin1_ibufg/O
+ net (fo=1, routed) 1.162 42.573 pixelClk/inst/clk_in1_clk_wiz_0
+ MMCME2_ADV_X1Y2 MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKOUT0)
+ -7.324 35.249 r pixelClk/inst/mmcm_adv_inst/CLKOUT0
+ net (fo=1, routed) 1.639 36.888 pixelClk/inst/clk_out1_clk_wiz_0
+ BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.091 36.979 r pixelClk/inst/clkout1_buf/O
+ net (fo=127, routed) 1.601 38.581 runnerObject/clk_out1
+ SLICE_X89Y79 FDSE r runnerObject/pos_object_y_target_reg[4]/C
+ clock pessimism 0.559 39.140
+ clock uncertainty -0.098 39.043
+ SLICE_X89Y79 FDSE (Setup_fdse_C_S) -0.429 38.614 runnerObject/pos_object_y_target_reg[4]
+ -------------------------------------------------------------------
+ required time 38.614
+ arrival time -13.474
+ -------------------------------------------------------------------
+ slack 25.140
+
+
+
+
+
+Min Delay Paths
+--------------------------------------------------------------------------------------
+Slack (MET) : 0.063ns (arrival time - required time)
+ Source: vgaInterface/counter_f_reg[3]/C
+ (rising edge-triggered cell FDCE clocked by clk_out1_clk_wiz_0_1 {rise@0.000ns fall@20.000ns period=40.000ns})
+ Destination: runnerObject/fcount_edge_reg[3]/D
+ (rising edge-triggered cell FDCE clocked by clk_out1_clk_wiz_0 {rise@0.000ns fall@20.000ns period=40.000ns})
+ Path Group: clk_out1_clk_wiz_0
+ Path Type: Hold (Min at Fast Process Corner)
+ Requirement: 0.000ns (clk_out1_clk_wiz_0 rise@0.000ns - clk_out1_clk_wiz_0_1 rise@0.000ns)
+ Data Path Delay: 0.257ns (logic 0.141ns (54.962%) route 0.116ns (45.038%))
+ Logic Levels: 0
+ Clock Path Skew: 0.013ns (DCD - SCD - CPR)
+ Destination Clock Delay (DCD): -0.805ns
+ Source Clock Delay (SCD): -0.566ns
+ Clock Pessimism Removal (CPR): -0.252ns
+ Clock Uncertainty: 0.098ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE
+ Total System Jitter (TSJ): 0.071ns
+ Discrete Jitter (DJ): 0.182ns
+ Phase Error (PE): 0.000ns
+ Clock Domain Crossing: Inter clock paths are considered valid unless explicitly excluded by timing constraints such as set_clock_groups or set_false_path.
+
+ Location Delay type Incr(ns) Path(ns) Netlist Resource(s)
+ ------------------------------------------------------------------- -------------------
+ (clock clk_out1_clk_wiz_0_1 rise edge)
+ 0.000 0.000 r
+ E3 0.000 0.000 r clk (IN)
+ net (fo=0) 0.000 0.000 pixelClk/inst/clk_in1
+ E3 IBUF (Prop_ibuf_I_O) 0.250 0.250 r pixelClk/inst/clkin1_ibufg/O
+ net (fo=1, routed) 0.440 0.690 pixelClk/inst/clk_in1_clk_wiz_0
+ MMCME2_ADV_X1Y2 MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKOUT0)
+ -2.379 -1.689 r pixelClk/inst/mmcm_adv_inst/CLKOUT0
+ net (fo=1, routed) 0.499 -1.190 pixelClk/inst/clk_out1_clk_wiz_0
+ BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.026 -1.164 r pixelClk/inst/clkout1_buf/O
+ net (fo=127, routed) 0.598 -0.566 vgaInterface/clk_out1
+ SLICE_X89Y70 FDCE r vgaInterface/counter_f_reg[3]/C
+ ------------------------------------------------------------------- -------------------
+ SLICE_X89Y70 FDCE (Prop_fdce_C_Q) 0.141 -0.425 r vgaInterface/counter_f_reg[3]/Q
+ net (fo=5, routed) 0.116 -0.310 runnerObject/counter_f_reg[3]
+ SLICE_X88Y70 FDCE r runnerObject/fcount_edge_reg[3]/D
+ ------------------------------------------------------------------- -------------------
+
+ (clock clk_out1_clk_wiz_0 rise edge)
+ 0.000 0.000 r
+ E3 0.000 0.000 r clk (IN)
+ net (fo=0) 0.000 0.000 pixelClk/inst/clk_in1
+ E3 IBUF (Prop_ibuf_I_O) 0.438 0.438 r pixelClk/inst/clkin1_ibufg/O
+ net (fo=1, routed) 0.480 0.918 pixelClk/inst/clk_in1_clk_wiz_0
+ MMCME2_ADV_X1Y2 MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKOUT0)
+ -3.163 -2.245 r pixelClk/inst/mmcm_adv_inst/CLKOUT0
+ net (fo=1, routed) 0.544 -1.702 pixelClk/inst/clk_out1_clk_wiz_0
+ BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.029 -1.673 r pixelClk/inst/clkout1_buf/O
+ net (fo=127, routed) 0.868 -0.805 runnerObject/clk_out1
+ SLICE_X88Y70 FDCE r runnerObject/fcount_edge_reg[3]/C
+ clock pessimism 0.252 -0.553
+ clock uncertainty 0.098 -0.456
+ SLICE_X88Y70 FDCE (Hold_fdce_C_D) 0.083 -0.373 runnerObject/fcount_edge_reg[3]
+ -------------------------------------------------------------------
+ required time 0.373
+ arrival time -0.310
+ -------------------------------------------------------------------
+ slack 0.063
+
+Slack (MET) : 0.063ns (arrival time - required time)
+ Source: vgaInterface/counter_f_reg[7]/C
+ (rising edge-triggered cell FDCE clocked by clk_out1_clk_wiz_0_1 {rise@0.000ns fall@20.000ns period=40.000ns})
+ Destination: runnerObject/fcount_edge_reg[7]/D
+ (rising edge-triggered cell FDCE clocked by clk_out1_clk_wiz_0 {rise@0.000ns fall@20.000ns period=40.000ns})
+ Path Group: clk_out1_clk_wiz_0
+ Path Type: Hold (Min at Fast Process Corner)
+ Requirement: 0.000ns (clk_out1_clk_wiz_0 rise@0.000ns - clk_out1_clk_wiz_0_1 rise@0.000ns)
+ Data Path Delay: 0.257ns (logic 0.141ns (54.948%) route 0.116ns (45.052%))
+ Logic Levels: 0
+ Clock Path Skew: 0.013ns (DCD - SCD - CPR)
+ Destination Clock Delay (DCD): -0.806ns
+ Source Clock Delay (SCD): -0.567ns
+ Clock Pessimism Removal (CPR): -0.252ns
+ Clock Uncertainty: 0.098ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE
+ Total System Jitter (TSJ): 0.071ns
+ Discrete Jitter (DJ): 0.182ns
+ Phase Error (PE): 0.000ns
+ Clock Domain Crossing: Inter clock paths are considered valid unless explicitly excluded by timing constraints such as set_clock_groups or set_false_path.
+
+ Location Delay type Incr(ns) Path(ns) Netlist Resource(s)
+ ------------------------------------------------------------------- -------------------
+ (clock clk_out1_clk_wiz_0_1 rise edge)
+ 0.000 0.000 r
+ E3 0.000 0.000 r clk (IN)
+ net (fo=0) 0.000 0.000 pixelClk/inst/clk_in1
+ E3 IBUF (Prop_ibuf_I_O) 0.250 0.250 r pixelClk/inst/clkin1_ibufg/O
+ net (fo=1, routed) 0.440 0.690 pixelClk/inst/clk_in1_clk_wiz_0
+ MMCME2_ADV_X1Y2 MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKOUT0)
+ -2.379 -1.689 r pixelClk/inst/mmcm_adv_inst/CLKOUT0
+ net (fo=1, routed) 0.499 -1.190 pixelClk/inst/clk_out1_clk_wiz_0
+ BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.026 -1.164 r pixelClk/inst/clkout1_buf/O
+ net (fo=127, routed) 0.597 -0.567 vgaInterface/clk_out1
+ SLICE_X89Y71 FDCE r vgaInterface/counter_f_reg[7]/C
+ ------------------------------------------------------------------- -------------------
+ SLICE_X89Y71 FDCE (Prop_fdce_C_Q) 0.141 -0.426 r vgaInterface/counter_f_reg[7]/Q
+ net (fo=5, routed) 0.116 -0.311 runnerObject/counter_f_reg[7]
+ SLICE_X88Y71 FDCE r runnerObject/fcount_edge_reg[7]/D
+ ------------------------------------------------------------------- -------------------
+
+ (clock clk_out1_clk_wiz_0 rise edge)
+ 0.000 0.000 r
+ E3 0.000 0.000 r clk (IN)
+ net (fo=0) 0.000 0.000 pixelClk/inst/clk_in1
+ E3 IBUF (Prop_ibuf_I_O) 0.438 0.438 r pixelClk/inst/clkin1_ibufg/O
+ net (fo=1, routed) 0.480 0.918 pixelClk/inst/clk_in1_clk_wiz_0
+ MMCME2_ADV_X1Y2 MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKOUT0)
+ -3.163 -2.245 r pixelClk/inst/mmcm_adv_inst/CLKOUT0
+ net (fo=1, routed) 0.544 -1.702 pixelClk/inst/clk_out1_clk_wiz_0
+ BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.029 -1.673 r pixelClk/inst/clkout1_buf/O
+ net (fo=127, routed) 0.867 -0.806 runnerObject/clk_out1
+ SLICE_X88Y71 FDCE r runnerObject/fcount_edge_reg[7]/C
+ clock pessimism 0.252 -0.554
+ clock uncertainty 0.098 -0.457
+ SLICE_X88Y71 FDCE (Hold_fdce_C_D) 0.083 -0.374 runnerObject/fcount_edge_reg[7]
+ -------------------------------------------------------------------
+ required time 0.374
+ arrival time -0.311
+ -------------------------------------------------------------------
+ slack 0.063
+
+Slack (MET) : 0.068ns (arrival time - required time)
+ Source: vgaInterface/counter_f_reg[4]/C
+ (rising edge-triggered cell FDCE clocked by clk_out1_clk_wiz_0_1 {rise@0.000ns fall@20.000ns period=40.000ns})
+ Destination: runnerObject/fcount_edge_reg[4]/D
+ (rising edge-triggered cell FDCE clocked by clk_out1_clk_wiz_0 {rise@0.000ns fall@20.000ns period=40.000ns})
+ Path Group: clk_out1_clk_wiz_0
+ Path Type: Hold (Min at Fast Process Corner)
+ Requirement: 0.000ns (clk_out1_clk_wiz_0 rise@0.000ns - clk_out1_clk_wiz_0_1 rise@0.000ns)
+ Data Path Delay: 0.264ns (logic 0.141ns (53.502%) route 0.123ns (46.498%))
+ Logic Levels: 0
+ Clock Path Skew: 0.013ns (DCD - SCD - CPR)
+ Destination Clock Delay (DCD): -0.806ns
+ Source Clock Delay (SCD): -0.567ns
+ Clock Pessimism Removal (CPR): -0.252ns
+ Clock Uncertainty: 0.098ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE
+ Total System Jitter (TSJ): 0.071ns
+ Discrete Jitter (DJ): 0.182ns
+ Phase Error (PE): 0.000ns
+ Clock Domain Crossing: Inter clock paths are considered valid unless explicitly excluded by timing constraints such as set_clock_groups or set_false_path.
+
+ Location Delay type Incr(ns) Path(ns) Netlist Resource(s)
+ ------------------------------------------------------------------- -------------------
+ (clock clk_out1_clk_wiz_0_1 rise edge)
+ 0.000 0.000 r
+ E3 0.000 0.000 r clk (IN)
+ net (fo=0) 0.000 0.000 pixelClk/inst/clk_in1
+ E3 IBUF (Prop_ibuf_I_O) 0.250 0.250 r pixelClk/inst/clkin1_ibufg/O
+ net (fo=1, routed) 0.440 0.690 pixelClk/inst/clk_in1_clk_wiz_0
+ MMCME2_ADV_X1Y2 MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKOUT0)
+ -2.379 -1.689 r pixelClk/inst/mmcm_adv_inst/CLKOUT0
+ net (fo=1, routed) 0.499 -1.190 pixelClk/inst/clk_out1_clk_wiz_0
+ BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.026 -1.164 r pixelClk/inst/clkout1_buf/O
+ net (fo=127, routed) 0.597 -0.567 vgaInterface/clk_out1
+ SLICE_X89Y71 FDCE r vgaInterface/counter_f_reg[4]/C
+ ------------------------------------------------------------------- -------------------
+ SLICE_X89Y71 FDCE (Prop_fdce_C_Q) 0.141 -0.426 r vgaInterface/counter_f_reg[4]/Q
+ net (fo=5, routed) 0.123 -0.304 runnerObject/counter_f_reg[4]
+ SLICE_X88Y71 FDCE r runnerObject/fcount_edge_reg[4]/D
+ ------------------------------------------------------------------- -------------------
+
+ (clock clk_out1_clk_wiz_0 rise edge)
+ 0.000 0.000 r
+ E3 0.000 0.000 r clk (IN)
+ net (fo=0) 0.000 0.000 pixelClk/inst/clk_in1
+ E3 IBUF (Prop_ibuf_I_O) 0.438 0.438 r pixelClk/inst/clkin1_ibufg/O
+ net (fo=1, routed) 0.480 0.918 pixelClk/inst/clk_in1_clk_wiz_0
+ MMCME2_ADV_X1Y2 MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKOUT0)
+ -3.163 -2.245 r pixelClk/inst/mmcm_adv_inst/CLKOUT0
+ net (fo=1, routed) 0.544 -1.702 pixelClk/inst/clk_out1_clk_wiz_0
+ BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.029 -1.673 r pixelClk/inst/clkout1_buf/O
+ net (fo=127, routed) 0.867 -0.806 runnerObject/clk_out1
+ SLICE_X88Y71 FDCE r runnerObject/fcount_edge_reg[4]/C
+ clock pessimism 0.252 -0.554
+ clock uncertainty 0.098 -0.457
+ SLICE_X88Y71 FDCE (Hold_fdce_C_D) 0.085 -0.372 runnerObject/fcount_edge_reg[4]
+ -------------------------------------------------------------------
+ required time 0.372
+ arrival time -0.304
+ -------------------------------------------------------------------
+ slack 0.068
+
+Slack (MET) : 0.082ns (arrival time - required time)
+ Source: runnerObject/pos_object_y_target_reg[4]/C
+ (rising edge-triggered cell FDSE clocked by clk_out1_clk_wiz_0_1 {rise@0.000ns fall@20.000ns period=40.000ns})
+ Destination: runnerObject/pos_object_y_actual_reg[4]/D
+ (rising edge-triggered cell FDRE clocked by clk_out1_clk_wiz_0 {rise@0.000ns fall@20.000ns period=40.000ns})
+ Path Group: clk_out1_clk_wiz_0
+ Path Type: Hold (Min at Fast Process Corner)
+ Requirement: 0.000ns (clk_out1_clk_wiz_0 rise@0.000ns - clk_out1_clk_wiz_0_1 rise@0.000ns)
+ Data Path Delay: 0.263ns (logic 0.141ns (53.569%) route 0.122ns (46.431%))
+ Logic Levels: 0
+ Clock Path Skew: 0.014ns (DCD - SCD - CPR)
+ Destination Clock Delay (DCD): -0.805ns
+ Source Clock Delay (SCD): -0.566ns
+ Clock Pessimism Removal (CPR): -0.253ns
+ Clock Uncertainty: 0.098ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE
+ Total System Jitter (TSJ): 0.071ns
+ Discrete Jitter (DJ): 0.182ns
+ Phase Error (PE): 0.000ns
+ Clock Domain Crossing: Inter clock paths are considered valid unless explicitly excluded by timing constraints such as set_clock_groups or set_false_path.
+
+ Location Delay type Incr(ns) Path(ns) Netlist Resource(s)
+ ------------------------------------------------------------------- -------------------
+ (clock clk_out1_clk_wiz_0_1 rise edge)
+ 0.000 0.000 r
+ E3 0.000 0.000 r clk (IN)
+ net (fo=0) 0.000 0.000 pixelClk/inst/clk_in1
+ E3 IBUF (Prop_ibuf_I_O) 0.250 0.250 r pixelClk/inst/clkin1_ibufg/O
+ net (fo=1, routed) 0.440 0.690 pixelClk/inst/clk_in1_clk_wiz_0
+ MMCME2_ADV_X1Y2 MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKOUT0)
+ -2.379 -1.689 r pixelClk/inst/mmcm_adv_inst/CLKOUT0
+ net (fo=1, routed) 0.499 -1.190 pixelClk/inst/clk_out1_clk_wiz_0
+ BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.026 -1.164 r pixelClk/inst/clkout1_buf/O
+ net (fo=127, routed) 0.598 -0.566 runnerObject/clk_out1
+ SLICE_X89Y79 FDSE r runnerObject/pos_object_y_target_reg[4]/C
+ ------------------------------------------------------------------- -------------------
+ SLICE_X89Y79 FDSE (Prop_fdse_C_Q) 0.141 -0.425 r runnerObject/pos_object_y_target_reg[4]/Q
+ net (fo=4, routed) 0.122 -0.303 runnerObject/pos_object_y_target[4]
+ SLICE_X87Y79 FDRE r runnerObject/pos_object_y_actual_reg[4]/D
+ ------------------------------------------------------------------- -------------------
+
+ (clock clk_out1_clk_wiz_0 rise edge)
+ 0.000 0.000 r
+ E3 0.000 0.000 r clk (IN)
+ net (fo=0) 0.000 0.000 pixelClk/inst/clk_in1
+ E3 IBUF (Prop_ibuf_I_O) 0.438 0.438 r pixelClk/inst/clkin1_ibufg/O
+ net (fo=1, routed) 0.480 0.918 pixelClk/inst/clk_in1_clk_wiz_0
+ MMCME2_ADV_X1Y2 MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKOUT0)
+ -3.163 -2.245 r pixelClk/inst/mmcm_adv_inst/CLKOUT0
+ net (fo=1, routed) 0.544 -1.702 pixelClk/inst/clk_out1_clk_wiz_0
+ BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.029 -1.673 r pixelClk/inst/clkout1_buf/O
+ net (fo=127, routed) 0.868 -0.805 runnerObject/clk_out1
+ SLICE_X87Y79 FDRE r runnerObject/pos_object_y_actual_reg[4]/C
+ clock pessimism 0.253 -0.552
+ clock uncertainty 0.098 -0.455
+ SLICE_X87Y79 FDRE (Hold_fdre_C_D) 0.070 -0.385 runnerObject/pos_object_y_actual_reg[4]
+ -------------------------------------------------------------------
+ required time 0.385
+ arrival time -0.303
+ -------------------------------------------------------------------
+ slack 0.082
+
+Slack (MET) : 0.091ns (arrival time - required time)
+ Source: largeObstacle/pos_object_x_target_reg[0]/C
+ (rising edge-triggered cell FDCE clocked by clk_out1_clk_wiz_0_1 {rise@0.000ns fall@20.000ns period=40.000ns})
+ Destination: largeObstacle/pos_object_x_actual_reg[0]/D
+ (rising edge-triggered cell FDRE clocked by clk_out1_clk_wiz_0 {rise@0.000ns fall@20.000ns period=40.000ns})
+ Path Group: clk_out1_clk_wiz_0
+ Path Type: Hold (Min at Fast Process Corner)
+ Requirement: 0.000ns (clk_out1_clk_wiz_0 rise@0.000ns - clk_out1_clk_wiz_0_1 rise@0.000ns)
+ Data Path Delay: 0.272ns (logic 0.141ns (51.925%) route 0.131ns (48.075%))
+ Logic Levels: 0
+ Clock Path Skew: 0.013ns (DCD - SCD - CPR)
+ Destination Clock Delay (DCD): -0.805ns
+ Source Clock Delay (SCD): -0.565ns
+ Clock Pessimism Removal (CPR): -0.253ns
+ Clock Uncertainty: 0.098ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE
+ Total System Jitter (TSJ): 0.071ns
+ Discrete Jitter (DJ): 0.182ns
+ Phase Error (PE): 0.000ns
+ Clock Domain Crossing: Inter clock paths are considered valid unless explicitly excluded by timing constraints such as set_clock_groups or set_false_path.
+
+ Location Delay type Incr(ns) Path(ns) Netlist Resource(s)
+ ------------------------------------------------------------------- -------------------
+ (clock clk_out1_clk_wiz_0_1 rise edge)
+ 0.000 0.000 r
+ E3 0.000 0.000 r clk (IN)
+ net (fo=0) 0.000 0.000 pixelClk/inst/clk_in1
+ E3 IBUF (Prop_ibuf_I_O) 0.250 0.250 r pixelClk/inst/clkin1_ibufg/O
+ net (fo=1, routed) 0.440 0.690 pixelClk/inst/clk_in1_clk_wiz_0
+ MMCME2_ADV_X1Y2 MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKOUT0)
+ -2.379 -1.689 r pixelClk/inst/mmcm_adv_inst/CLKOUT0
+ net (fo=1, routed) 0.499 -1.190 pixelClk/inst/clk_out1_clk_wiz_0
+ BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.026 -1.164 r pixelClk/inst/clkout1_buf/O
+ net (fo=127, routed) 0.599 -0.565 largeObstacle/CLK
+ SLICE_X82Y81 FDCE r largeObstacle/pos_object_x_target_reg[0]/C
+ ------------------------------------------------------------------- -------------------
+ SLICE_X82Y81 FDCE (Prop_fdce_C_Q) 0.141 -0.424 r largeObstacle/pos_object_x_target_reg[0]/Q
+ net (fo=2, routed) 0.131 -0.294 largeObstacle/pos_object_x_target_reg[0]
+ SLICE_X82Y80 FDRE r largeObstacle/pos_object_x_actual_reg[0]/D
+ ------------------------------------------------------------------- -------------------
+
+ (clock clk_out1_clk_wiz_0 rise edge)
+ 0.000 0.000 r
+ E3 0.000 0.000 r clk (IN)
+ net (fo=0) 0.000 0.000 pixelClk/inst/clk_in1
+ E3 IBUF (Prop_ibuf_I_O) 0.438 0.438 r pixelClk/inst/clkin1_ibufg/O
+ net (fo=1, routed) 0.480 0.918 pixelClk/inst/clk_in1_clk_wiz_0
+ MMCME2_ADV_X1Y2 MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKOUT0)
+ -3.163 -2.245 r pixelClk/inst/mmcm_adv_inst/CLKOUT0
+ net (fo=1, routed) 0.544 -1.702 pixelClk/inst/clk_out1_clk_wiz_0
+ BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.029 -1.673 r pixelClk/inst/clkout1_buf/O
+ net (fo=127, routed) 0.868 -0.805 largeObstacle/CLK
+ SLICE_X82Y80 FDRE r largeObstacle/pos_object_x_actual_reg[0]/C
+ clock pessimism 0.253 -0.552
+ clock uncertainty 0.098 -0.455
+ SLICE_X82Y80 FDRE (Hold_fdre_C_D) 0.070 -0.385 largeObstacle/pos_object_x_actual_reg[0]
+ -------------------------------------------------------------------
+ required time 0.385
+ arrival time -0.294
+ -------------------------------------------------------------------
+ slack 0.091
+
+Slack (MET) : 0.101ns (arrival time - required time)
+ Source: runnerObject/pos_object_y_target_reg[2]/C
+ (rising edge-triggered cell FDSE clocked by clk_out1_clk_wiz_0_1 {rise@0.000ns fall@20.000ns period=40.000ns})
+ Destination: runnerObject/pos_object_y_actual_reg[2]/D
+ (rising edge-triggered cell FDRE clocked by clk_out1_clk_wiz_0 {rise@0.000ns fall@20.000ns period=40.000ns})
+ Path Group: clk_out1_clk_wiz_0
+ Path Type: Hold (Min at Fast Process Corner)
+ Requirement: 0.000ns (clk_out1_clk_wiz_0 rise@0.000ns - clk_out1_clk_wiz_0_1 rise@0.000ns)
+ Data Path Delay: 0.282ns (logic 0.141ns (49.964%) route 0.141ns (50.036%))
+ Logic Levels: 0
+ Clock Path Skew: 0.014ns (DCD - SCD - CPR)
+ Destination Clock Delay (DCD): -0.805ns
+ Source Clock Delay (SCD): -0.566ns
+ Clock Pessimism Removal (CPR): -0.253ns
+ Clock Uncertainty: 0.098ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE
+ Total System Jitter (TSJ): 0.071ns
+ Discrete Jitter (DJ): 0.182ns
+ Phase Error (PE): 0.000ns
+ Clock Domain Crossing: Inter clock paths are considered valid unless explicitly excluded by timing constraints such as set_clock_groups or set_false_path.
+
+ Location Delay type Incr(ns) Path(ns) Netlist Resource(s)
+ ------------------------------------------------------------------- -------------------
+ (clock clk_out1_clk_wiz_0_1 rise edge)
+ 0.000 0.000 r
+ E3 0.000 0.000 r clk (IN)
+ net (fo=0) 0.000 0.000 pixelClk/inst/clk_in1
+ E3 IBUF (Prop_ibuf_I_O) 0.250 0.250 r pixelClk/inst/clkin1_ibufg/O
+ net (fo=1, routed) 0.440 0.690 pixelClk/inst/clk_in1_clk_wiz_0
+ MMCME2_ADV_X1Y2 MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKOUT0)
+ -2.379 -1.689 r pixelClk/inst/mmcm_adv_inst/CLKOUT0
+ net (fo=1, routed) 0.499 -1.190 pixelClk/inst/clk_out1_clk_wiz_0
+ BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.026 -1.164 r pixelClk/inst/clkout1_buf/O
+ net (fo=127, routed) 0.598 -0.566 runnerObject/clk_out1
+ SLICE_X89Y79 FDSE r runnerObject/pos_object_y_target_reg[2]/C
+ ------------------------------------------------------------------- -------------------
+ SLICE_X89Y79 FDSE (Prop_fdse_C_Q) 0.141 -0.425 r runnerObject/pos_object_y_target_reg[2]/Q
+ net (fo=6, routed) 0.141 -0.284 runnerObject/pos_object_y_target[2]
+ SLICE_X86Y79 FDRE r runnerObject/pos_object_y_actual_reg[2]/D
+ ------------------------------------------------------------------- -------------------
+
+ (clock clk_out1_clk_wiz_0 rise edge)
+ 0.000 0.000 r
+ E3 0.000 0.000 r clk (IN)
+ net (fo=0) 0.000 0.000 pixelClk/inst/clk_in1
+ E3 IBUF (Prop_ibuf_I_O) 0.438 0.438 r pixelClk/inst/clkin1_ibufg/O
+ net (fo=1, routed) 0.480 0.918 pixelClk/inst/clk_in1_clk_wiz_0
+ MMCME2_ADV_X1Y2 MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKOUT0)
+ -3.163 -2.245 r pixelClk/inst/mmcm_adv_inst/CLKOUT0
+ net (fo=1, routed) 0.544 -1.702 pixelClk/inst/clk_out1_clk_wiz_0
+ BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.029 -1.673 r pixelClk/inst/clkout1_buf/O
+ net (fo=127, routed) 0.868 -0.805 runnerObject/clk_out1
+ SLICE_X86Y79 FDRE r runnerObject/pos_object_y_actual_reg[2]/C
+ clock pessimism 0.253 -0.552
+ clock uncertainty 0.098 -0.455
+ SLICE_X86Y79 FDRE (Hold_fdre_C_D) 0.070 -0.385 runnerObject/pos_object_y_actual_reg[2]
+ -------------------------------------------------------------------
+ required time 0.385
+ arrival time -0.284
+ -------------------------------------------------------------------
+ slack 0.101
+
+Slack (MET) : 0.104ns (arrival time - required time)
+ Source: runnerObject/pos_object_y_target_reg[0]/C
+ (rising edge-triggered cell FDRE clocked by clk_out1_clk_wiz_0_1 {rise@0.000ns fall@20.000ns period=40.000ns})
+ Destination: runnerObject/pos_object_y_actual_reg[0]/D
+ (rising edge-triggered cell FDRE clocked by clk_out1_clk_wiz_0 {rise@0.000ns fall@20.000ns period=40.000ns})
+ Path Group: clk_out1_clk_wiz_0
+ Path Type: Hold (Min at Fast Process Corner)
+ Requirement: 0.000ns (clk_out1_clk_wiz_0 rise@0.000ns - clk_out1_clk_wiz_0_1 rise@0.000ns)
+ Data Path Delay: 0.285ns (logic 0.141ns (49.436%) route 0.144ns (50.564%))
+ Logic Levels: 0
+ Clock Path Skew: 0.014ns (DCD - SCD - CPR)
+ Destination Clock Delay (DCD): -0.805ns
+ Source Clock Delay (SCD): -0.566ns
+ Clock Pessimism Removal (CPR): -0.253ns
+ Clock Uncertainty: 0.098ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE
+ Total System Jitter (TSJ): 0.071ns
+ Discrete Jitter (DJ): 0.182ns
+ Phase Error (PE): 0.000ns
+ Clock Domain Crossing: Inter clock paths are considered valid unless explicitly excluded by timing constraints such as set_clock_groups or set_false_path.
+
+ Location Delay type Incr(ns) Path(ns) Netlist Resource(s)
+ ------------------------------------------------------------------- -------------------
+ (clock clk_out1_clk_wiz_0_1 rise edge)
+ 0.000 0.000 r
+ E3 0.000 0.000 r clk (IN)
+ net (fo=0) 0.000 0.000 pixelClk/inst/clk_in1
+ E3 IBUF (Prop_ibuf_I_O) 0.250 0.250 r pixelClk/inst/clkin1_ibufg/O
+ net (fo=1, routed) 0.440 0.690 pixelClk/inst/clk_in1_clk_wiz_0
+ MMCME2_ADV_X1Y2 MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKOUT0)
+ -2.379 -1.689 r pixelClk/inst/mmcm_adv_inst/CLKOUT0
+ net (fo=1, routed) 0.499 -1.190 pixelClk/inst/clk_out1_clk_wiz_0
+ BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.026 -1.164 r pixelClk/inst/clkout1_buf/O
+ net (fo=127, routed) 0.598 -0.566 runnerObject/clk_out1
+ SLICE_X89Y79 FDRE r runnerObject/pos_object_y_target_reg[0]/C
+ ------------------------------------------------------------------- -------------------
+ SLICE_X89Y79 FDRE (Prop_fdre_C_Q) 0.141 -0.425 r runnerObject/pos_object_y_target_reg[0]/Q
+ net (fo=8, routed) 0.144 -0.281 runnerObject/pos_object_y_target[0]
+ SLICE_X87Y79 FDRE r runnerObject/pos_object_y_actual_reg[0]/D
+ ------------------------------------------------------------------- -------------------
+
+ (clock clk_out1_clk_wiz_0 rise edge)
+ 0.000 0.000 r
+ E3 0.000 0.000 r clk (IN)
+ net (fo=0) 0.000 0.000 pixelClk/inst/clk_in1
+ E3 IBUF (Prop_ibuf_I_O) 0.438 0.438 r pixelClk/inst/clkin1_ibufg/O
+ net (fo=1, routed) 0.480 0.918 pixelClk/inst/clk_in1_clk_wiz_0
+ MMCME2_ADV_X1Y2 MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKOUT0)
+ -3.163 -2.245 r pixelClk/inst/mmcm_adv_inst/CLKOUT0
+ net (fo=1, routed) 0.544 -1.702 pixelClk/inst/clk_out1_clk_wiz_0
+ BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.029 -1.673 r pixelClk/inst/clkout1_buf/O
+ net (fo=127, routed) 0.868 -0.805 runnerObject/clk_out1
+ SLICE_X87Y79 FDRE r runnerObject/pos_object_y_actual_reg[0]/C
+ clock pessimism 0.253 -0.552
+ clock uncertainty 0.098 -0.455
+ SLICE_X87Y79 FDRE (Hold_fdre_C_D) 0.070 -0.385 runnerObject/pos_object_y_actual_reg[0]
+ -------------------------------------------------------------------
+ required time 0.385
+ arrival time -0.281
+ -------------------------------------------------------------------
+ slack 0.104
+
+Slack (MET) : 0.107ns (arrival time - required time)
+ Source: vgaInterface/counter_f_reg[1]/C
+ (rising edge-triggered cell FDCE clocked by clk_out1_clk_wiz_0_1 {rise@0.000ns fall@20.000ns period=40.000ns})
+ Destination: runnerObject/fcount_edge_reg[1]/D
+ (rising edge-triggered cell FDCE clocked by clk_out1_clk_wiz_0 {rise@0.000ns fall@20.000ns period=40.000ns})
+ Path Group: clk_out1_clk_wiz_0
+ Path Type: Hold (Min at Fast Process Corner)
+ Requirement: 0.000ns (clk_out1_clk_wiz_0 rise@0.000ns - clk_out1_clk_wiz_0_1 rise@0.000ns)
+ Data Path Delay: 0.303ns (logic 0.141ns (46.482%) route 0.162ns (53.518%))
+ Logic Levels: 0
+ Clock Path Skew: 0.013ns (DCD - SCD - CPR)
+ Destination Clock Delay (DCD): -0.805ns
+ Source Clock Delay (SCD): -0.566ns
+ Clock Pessimism Removal (CPR): -0.252ns
+ Clock Uncertainty: 0.098ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE
+ Total System Jitter (TSJ): 0.071ns
+ Discrete Jitter (DJ): 0.182ns
+ Phase Error (PE): 0.000ns
+ Clock Domain Crossing: Inter clock paths are considered valid unless explicitly excluded by timing constraints such as set_clock_groups or set_false_path.
+
+ Location Delay type Incr(ns) Path(ns) Netlist Resource(s)
+ ------------------------------------------------------------------- -------------------
+ (clock clk_out1_clk_wiz_0_1 rise edge)
+ 0.000 0.000 r
+ E3 0.000 0.000 r clk (IN)
+ net (fo=0) 0.000 0.000 pixelClk/inst/clk_in1
+ E3 IBUF (Prop_ibuf_I_O) 0.250 0.250 r pixelClk/inst/clkin1_ibufg/O
+ net (fo=1, routed) 0.440 0.690 pixelClk/inst/clk_in1_clk_wiz_0
+ MMCME2_ADV_X1Y2 MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKOUT0)
+ -2.379 -1.689 r pixelClk/inst/mmcm_adv_inst/CLKOUT0
+ net (fo=1, routed) 0.499 -1.190 pixelClk/inst/clk_out1_clk_wiz_0
+ BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.026 -1.164 r pixelClk/inst/clkout1_buf/O
+ net (fo=127, routed) 0.598 -0.566 vgaInterface/clk_out1
+ SLICE_X89Y70 FDCE r vgaInterface/counter_f_reg[1]/C
+ ------------------------------------------------------------------- -------------------
+ SLICE_X89Y70 FDCE (Prop_fdce_C_Q) 0.141 -0.425 r vgaInterface/counter_f_reg[1]/Q
+ net (fo=5, routed) 0.162 -0.263 runnerObject/counter_f_reg[1]
+ SLICE_X88Y70 FDCE r runnerObject/fcount_edge_reg[1]/D
+ ------------------------------------------------------------------- -------------------
+
+ (clock clk_out1_clk_wiz_0 rise edge)
+ 0.000 0.000 r
+ E3 0.000 0.000 r clk (IN)
+ net (fo=0) 0.000 0.000 pixelClk/inst/clk_in1
+ E3 IBUF (Prop_ibuf_I_O) 0.438 0.438 r pixelClk/inst/clkin1_ibufg/O
+ net (fo=1, routed) 0.480 0.918 pixelClk/inst/clk_in1_clk_wiz_0
+ MMCME2_ADV_X1Y2 MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKOUT0)
+ -3.163 -2.245 r pixelClk/inst/mmcm_adv_inst/CLKOUT0
+ net (fo=1, routed) 0.544 -1.702 pixelClk/inst/clk_out1_clk_wiz_0
+ BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.029 -1.673 r pixelClk/inst/clkout1_buf/O
+ net (fo=127, routed) 0.868 -0.805 runnerObject/clk_out1
+ SLICE_X88Y70 FDCE r runnerObject/fcount_edge_reg[1]/C
+ clock pessimism 0.252 -0.553
+ clock uncertainty 0.098 -0.456
+ SLICE_X88Y70 FDCE (Hold_fdce_C_D) 0.086 -0.370 runnerObject/fcount_edge_reg[1]
+ -------------------------------------------------------------------
+ required time 0.370
+ arrival time -0.263
+ -------------------------------------------------------------------
+ slack 0.107
+
+Slack (MET) : 0.107ns (arrival time - required time)
+ Source: vgaInterface/counter_f_reg[5]/C
+ (rising edge-triggered cell FDCE clocked by clk_out1_clk_wiz_0_1 {rise@0.000ns fall@20.000ns period=40.000ns})
+ Destination: runnerObject/fcount_edge_reg[5]/D
+ (rising edge-triggered cell FDCE clocked by clk_out1_clk_wiz_0 {rise@0.000ns fall@20.000ns period=40.000ns})
+ Path Group: clk_out1_clk_wiz_0
+ Path Type: Hold (Min at Fast Process Corner)
+ Requirement: 0.000ns (clk_out1_clk_wiz_0 rise@0.000ns - clk_out1_clk_wiz_0_1 rise@0.000ns)
+ Data Path Delay: 0.303ns (logic 0.141ns (46.472%) route 0.162ns (53.528%))
+ Logic Levels: 0
+ Clock Path Skew: 0.013ns (DCD - SCD - CPR)
+ Destination Clock Delay (DCD): -0.806ns
+ Source Clock Delay (SCD): -0.567ns
+ Clock Pessimism Removal (CPR): -0.252ns
+ Clock Uncertainty: 0.098ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE
+ Total System Jitter (TSJ): 0.071ns
+ Discrete Jitter (DJ): 0.182ns
+ Phase Error (PE): 0.000ns
+ Clock Domain Crossing: Inter clock paths are considered valid unless explicitly excluded by timing constraints such as set_clock_groups or set_false_path.
+
+ Location Delay type Incr(ns) Path(ns) Netlist Resource(s)
+ ------------------------------------------------------------------- -------------------
+ (clock clk_out1_clk_wiz_0_1 rise edge)
+ 0.000 0.000 r
+ E3 0.000 0.000 r clk (IN)
+ net (fo=0) 0.000 0.000 pixelClk/inst/clk_in1
+ E3 IBUF (Prop_ibuf_I_O) 0.250 0.250 r pixelClk/inst/clkin1_ibufg/O
+ net (fo=1, routed) 0.440 0.690 pixelClk/inst/clk_in1_clk_wiz_0
+ MMCME2_ADV_X1Y2 MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKOUT0)
+ -2.379 -1.689 r pixelClk/inst/mmcm_adv_inst/CLKOUT0
+ net (fo=1, routed) 0.499 -1.190 pixelClk/inst/clk_out1_clk_wiz_0
+ BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.026 -1.164 r pixelClk/inst/clkout1_buf/O
+ net (fo=127, routed) 0.597 -0.567 vgaInterface/clk_out1
+ SLICE_X89Y71 FDCE r vgaInterface/counter_f_reg[5]/C
+ ------------------------------------------------------------------- -------------------
+ SLICE_X89Y71 FDCE (Prop_fdce_C_Q) 0.141 -0.426 r vgaInterface/counter_f_reg[5]/Q
+ net (fo=5, routed) 0.162 -0.264 runnerObject/counter_f_reg[5]
+ SLICE_X88Y71 FDCE r runnerObject/fcount_edge_reg[5]/D
+ ------------------------------------------------------------------- -------------------
+
+ (clock clk_out1_clk_wiz_0 rise edge)
+ 0.000 0.000 r
+ E3 0.000 0.000 r clk (IN)
+ net (fo=0) 0.000 0.000 pixelClk/inst/clk_in1
+ E3 IBUF (Prop_ibuf_I_O) 0.438 0.438 r pixelClk/inst/clkin1_ibufg/O
+ net (fo=1, routed) 0.480 0.918 pixelClk/inst/clk_in1_clk_wiz_0
+ MMCME2_ADV_X1Y2 MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKOUT0)
+ -3.163 -2.245 r pixelClk/inst/mmcm_adv_inst/CLKOUT0
+ net (fo=1, routed) 0.544 -1.702 pixelClk/inst/clk_out1_clk_wiz_0
+ BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.029 -1.673 r pixelClk/inst/clkout1_buf/O
+ net (fo=127, routed) 0.867 -0.806 runnerObject/clk_out1
+ SLICE_X88Y71 FDCE r runnerObject/fcount_edge_reg[5]/C
+ clock pessimism 0.252 -0.554
+ clock uncertainty 0.098 -0.457
+ SLICE_X88Y71 FDCE (Hold_fdce_C_D) 0.086 -0.371 runnerObject/fcount_edge_reg[5]
+ -------------------------------------------------------------------
+ required time 0.371
+ arrival time -0.264
+ -------------------------------------------------------------------
+ slack 0.107
+
+Slack (MET) : 0.117ns (arrival time - required time)
+ Source: largeObstacle/pos_object_x_target_reg[4]/C
+ (rising edge-triggered cell FDCE clocked by clk_out1_clk_wiz_0_1 {rise@0.000ns fall@20.000ns period=40.000ns})
+ Destination: largeObstacle/pos_object_x_actual_reg[4]/D
+ (rising edge-triggered cell FDRE clocked by clk_out1_clk_wiz_0 {rise@0.000ns fall@20.000ns period=40.000ns})
+ Path Group: clk_out1_clk_wiz_0
+ Path Type: Hold (Min at Fast Process Corner)
+ Requirement: 0.000ns (clk_out1_clk_wiz_0 rise@0.000ns - clk_out1_clk_wiz_0_1 rise@0.000ns)
+ Data Path Delay: 0.288ns (logic 0.164ns (56.904%) route 0.124ns (43.096%))
+ Logic Levels: 0
+ Clock Path Skew: 0.015ns (DCD - SCD - CPR)
+ Destination Clock Delay (DCD): -0.810ns
+ Source Clock Delay (SCD): -0.572ns
+ Clock Pessimism Removal (CPR): -0.253ns
+ Clock Uncertainty: 0.098ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE
+ Total System Jitter (TSJ): 0.071ns
+ Discrete Jitter (DJ): 0.182ns
+ Phase Error (PE): 0.000ns
+ Clock Domain Crossing: Inter clock paths are considered valid unless explicitly excluded by timing constraints such as set_clock_groups or set_false_path.
+
+ Location Delay type Incr(ns) Path(ns) Netlist Resource(s)
+ ------------------------------------------------------------------- -------------------
+ (clock clk_out1_clk_wiz_0_1 rise edge)
+ 0.000 0.000 r
+ E3 0.000 0.000 r clk (IN)
+ net (fo=0) 0.000 0.000 pixelClk/inst/clk_in1
+ E3 IBUF (Prop_ibuf_I_O) 0.250 0.250 r pixelClk/inst/clkin1_ibufg/O
+ net (fo=1, routed) 0.440 0.690 pixelClk/inst/clk_in1_clk_wiz_0
+ MMCME2_ADV_X1Y2 MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKOUT0)
+ -2.379 -1.689 r pixelClk/inst/mmcm_adv_inst/CLKOUT0
+ net (fo=1, routed) 0.499 -1.190 pixelClk/inst/clk_out1_clk_wiz_0
+ BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.026 -1.164 r pixelClk/inst/clkout1_buf/O
+ net (fo=127, routed) 0.592 -0.572 largeObstacle/CLK
+ SLICE_X80Y78 FDCE r largeObstacle/pos_object_x_target_reg[4]/C
+ ------------------------------------------------------------------- -------------------
+ SLICE_X80Y78 FDCE (Prop_fdce_C_Q) 0.164 -0.408 r largeObstacle/pos_object_x_target_reg[4]/Q
+ net (fo=5, routed) 0.124 -0.284 largeObstacle/pos_object_x_target_reg[4]
+ SLICE_X80Y79 FDRE r largeObstacle/pos_object_x_actual_reg[4]/D
+ ------------------------------------------------------------------- -------------------
+
+ (clock clk_out1_clk_wiz_0 rise edge)
+ 0.000 0.000 r
+ E3 0.000 0.000 r clk (IN)
+ net (fo=0) 0.000 0.000 pixelClk/inst/clk_in1
+ E3 IBUF (Prop_ibuf_I_O) 0.438 0.438 r pixelClk/inst/clkin1_ibufg/O
+ net (fo=1, routed) 0.480 0.918 pixelClk/inst/clk_in1_clk_wiz_0
+ MMCME2_ADV_X1Y2 MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKOUT0)
+ -3.163 -2.245 r pixelClk/inst/mmcm_adv_inst/CLKOUT0
+ net (fo=1, routed) 0.544 -1.702 pixelClk/inst/clk_out1_clk_wiz_0
+ BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.029 -1.673 r pixelClk/inst/clkout1_buf/O
+ net (fo=127, routed) 0.863 -0.810 largeObstacle/CLK
+ SLICE_X80Y79 FDRE r largeObstacle/pos_object_x_actual_reg[4]/C
+ clock pessimism 0.253 -0.557
+ clock uncertainty 0.098 -0.460
+ SLICE_X80Y79 FDRE (Hold_fdre_C_D) 0.059 -0.401 largeObstacle/pos_object_x_actual_reg[4]
+ -------------------------------------------------------------------
+ required time 0.401
+ arrival time -0.284
+ -------------------------------------------------------------------
+ slack 0.117
+
+
+
+
+
+---------------------------------------------------------------------------------------------------
+From Clock: clk_out1_clk_wiz_0
+ To Clock: clk_out1_clk_wiz_0_1
+
+Setup : 0 Failing Endpoints, Worst Slack 24.909ns, Total Violation 0.000ns
+Hold : 0 Failing Endpoints, Worst Slack 0.063ns, Total Violation 0.000ns
+---------------------------------------------------------------------------------------------------
+
+
+Max Delay Paths
+--------------------------------------------------------------------------------------
+Slack (MET) : 24.909ns (required time - arrival time)
+ Source: vgaInterface/counter_f_reg[2]/C
+ (rising edge-triggered cell FDCE clocked by clk_out1_clk_wiz_0 {rise@0.000ns fall@20.000ns period=40.000ns})
+ Destination: runnerObject/pos_object_y_target_reg[8]/D
+ (rising edge-triggered cell FDSE clocked by clk_out1_clk_wiz_0_1 {rise@0.000ns fall@20.000ns period=40.000ns})
+ Path Group: clk_out1_clk_wiz_0_1
+ Path Type: Setup (Max at Slow Process Corner)
+ Requirement: 40.000ns (clk_out1_clk_wiz_0_1 rise@40.000ns - clk_out1_clk_wiz_0 rise@0.000ns)
+ Data Path Delay: 15.033ns (logic 5.901ns (39.253%) route 9.132ns (60.747%))
+ Logic Levels: 18 (CARRY4=9 LUT1=2 LUT2=2 LUT4=2 LUT5=1 LUT6=2)
+ Clock Path Skew: -0.039ns (DCD - SCD + CPR)
+ Destination Clock Delay (DCD): -1.419ns = ( 38.581 - 40.000 )
+ Source Clock Delay (SCD): -0.821ns
+ Clock Pessimism Removal (CPR): 0.559ns
+ Clock Uncertainty: 0.098ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE
+ Total System Jitter (TSJ): 0.071ns
+ Discrete Jitter (DJ): 0.182ns
+ Phase Error (PE): 0.000ns
+ Clock Domain Crossing: Inter clock paths are considered valid unless explicitly excluded by timing constraints such as set_clock_groups or set_false_path.
+
+ Location Delay type Incr(ns) Path(ns) Netlist Resource(s)
+ ------------------------------------------------------------------- -------------------
+ (clock clk_out1_clk_wiz_0 rise edge)
+ 0.000 0.000 r
+ E3 0.000 0.000 r clk (IN)
+ net (fo=0) 0.000 0.000 pixelClk/inst/clk_in1
+ E3 IBUF (Prop_ibuf_I_O) 1.482 1.482 r pixelClk/inst/clkin1_ibufg/O
+ net (fo=1, routed) 1.233 2.715 pixelClk/inst/clk_in1_clk_wiz_0
+ MMCME2_ADV_X1Y2 MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKOUT0)
+ -7.070 -4.355 r pixelClk/inst/mmcm_adv_inst/CLKOUT0
+ net (fo=1, routed) 1.719 -2.636 pixelClk/inst/clk_out1_clk_wiz_0
+ BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.096 -2.540 r pixelClk/inst/clkout1_buf/O
+ net (fo=127, routed) 1.719 -0.821 vgaInterface/clk_out1
+ SLICE_X89Y70 FDCE r vgaInterface/counter_f_reg[2]/C
+ ------------------------------------------------------------------- -------------------
+ SLICE_X89Y70 FDCE (Prop_fdce_C_Q) 0.456 -0.365 f vgaInterface/counter_f_reg[2]/Q
+ net (fo=5, routed) 1.006 0.641 vgaInterface/counter_f_reg[2]
+ SLICE_X88Y67 LUT1 (Prop_lut1_I0_O) 0.124 0.765 r vgaInterface/FCounter_17bit_carry_i_3/O
+ net (fo=1, routed) 0.000 0.765 runnerObject/pos_object_y_target6_carry_0[1]
+ SLICE_X88Y67 CARRY4 (Prop_carry4_S[1]_CO[3])
+ 0.533 1.298 r runnerObject/FCounter_17bit_carry/CO[3]
+ net (fo=1, routed) 0.000 1.298 runnerObject/FCounter_17bit_carry_n_0
+ SLICE_X88Y68 CARRY4 (Prop_carry4_CI_O[2])
+ 0.239 1.537 r runnerObject/FCounter_17bit_carry__0/O[2]
+ net (fo=2, routed) 0.987 2.523 runnerObject/FCounter_17bit[7]
+ SLICE_X88Y71 LUT2 (Prop_lut2_I0_O) 0.301 2.824 r runnerObject/pos_object_y_target6_carry__0_i_1/O
+ net (fo=1, routed) 0.000 2.824 runnerObject/pos_object_y_target6_carry__0_i_1_n_0
+ SLICE_X88Y71 CARRY4 (Prop_carry4_S[3]_CO[3])
+ 0.376 3.200 r runnerObject/pos_object_y_target6_carry__0/CO[3]
+ net (fo=1, routed) 0.000 3.200 runnerObject/pos_object_y_target6_carry__0_n_0
+ SLICE_X88Y72 CARRY4 (Prop_carry4_CI_O[1])
+ 0.323 3.523 f runnerObject/pos_object_y_target6_carry__1/O[1]
+ net (fo=5, routed) 0.953 4.477 runnerObject/pos_object_y_target6[9]
+ SLICE_X82Y72 LUT1 (Prop_lut1_I0_O) 0.306 4.783 r runnerObject/i__carry__1_i_13/O
+ net (fo=1, routed) 0.000 4.783 runnerObject/p_0_in[9]
+ SLICE_X82Y72 CARRY4 (Prop_carry4_S[0]_O[2])
+ 0.547 5.330 f runnerObject/i__carry__1_i_9/O[2]
+ net (fo=2, routed) 0.821 6.151 runnerObject/pos_object_y_target9[11]
+ SLICE_X84Y71 LUT4 (Prop_lut4_I3_O) 0.302 6.453 r runnerObject/pos_object_y_target2_carry_i_13/O
+ net (fo=2, routed) 0.420 6.872 runnerObject/pos_object_y_target2_carry_i_13_n_0
+ SLICE_X87Y72 LUT6 (Prop_lut6_I0_O) 0.124 6.996 r runnerObject/pos_object_y_target2_carry_i_10/O
+ net (fo=34, routed) 1.081 8.077 runnerObject/pos_object_y_target2_carry_i_10_n_0
+ SLICE_X84Y70 LUT6 (Prop_lut6_I3_O) 0.124 8.201 r runnerObject/pos_object_y_target2_carry_i_9/O
+ net (fo=1, routed) 0.701 8.903 runnerObject/pos_object_y_target2_carry_i_9_n_0
+ SLICE_X85Y70 CARRY4 (Prop_carry4_S[0]_O[3])
+ 0.730 9.633 f runnerObject/pos_object_y_target2_carry/O[3]
+ net (fo=2, routed) 1.215 10.847 runnerObject/pos_object_y_target2[4]
+ SLICE_X84Y73 LUT2 (Prop_lut2_I1_O) 0.306 11.153 r runnerObject/pos_object_y_target1_carry_i_4/O
+ net (fo=1, routed) 0.000 11.153 runnerObject/pos_object_y_target1_carry_i_4_n_0
+ SLICE_X84Y73 CARRY4 (Prop_carry4_S[2]_CO[3])
+ 0.380 11.533 r runnerObject/pos_object_y_target1_carry/CO[3]
+ net (fo=1, routed) 0.000 11.533 runnerObject/pos_object_y_target1_carry_n_0
+ SLICE_X84Y74 CARRY4 (Prop_carry4_CI_CO[3])
+ 0.117 11.650 r runnerObject/pos_object_y_target1_carry__0/CO[3]
+ net (fo=1, routed) 0.009 11.659 runnerObject/pos_object_y_target1_carry__0_n_0
+ SLICE_X84Y75 CARRY4 (Prop_carry4_CI_CO[1])
+ 0.157 11.816 r runnerObject/pos_object_y_target1_carry__1/CO[1]
+ net (fo=11, routed) 1.258 13.075 runnerObject/pos_object_y_target1
+ SLICE_X88Y80 LUT5 (Prop_lut5_I1_O) 0.332 13.407 r runnerObject/pos_object_y_target[8]_i_4/O
+ net (fo=2, routed) 0.682 14.088 runnerObject/pos_object_y_target[8]_i_4_n_0
+ SLICE_X88Y80 LUT4 (Prop_lut4_I3_O) 0.124 14.212 r runnerObject/pos_object_y_target[8]_i_3/O
+ net (fo=1, routed) 0.000 14.212 runnerObject/pos_object_y_target[8]_i_3_n_0
+ SLICE_X88Y80 FDSE r runnerObject/pos_object_y_target_reg[8]/D
+ ------------------------------------------------------------------- -------------------
+
+ (clock clk_out1_clk_wiz_0_1 rise edge)
+ 40.000 40.000 r
+ E3 0.000 40.000 r clk (IN)
+ net (fo=0) 0.000 40.000 pixelClk/inst/clk_in1
+ E3 IBUF (Prop_ibuf_I_O) 1.411 41.411 r pixelClk/inst/clkin1_ibufg/O
+ net (fo=1, routed) 1.162 42.573 pixelClk/inst/clk_in1_clk_wiz_0
+ MMCME2_ADV_X1Y2 MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKOUT0)
+ -7.324 35.249 r pixelClk/inst/mmcm_adv_inst/CLKOUT0
+ net (fo=1, routed) 1.639 36.888 pixelClk/inst/clk_out1_clk_wiz_0
+ BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.091 36.979 r pixelClk/inst/clkout1_buf/O
+ net (fo=127, routed) 1.601 38.581 runnerObject/clk_out1
+ SLICE_X88Y80 FDSE r runnerObject/pos_object_y_target_reg[8]/C
+ clock pessimism 0.559 39.140
+ clock uncertainty -0.098 39.043
+ SLICE_X88Y80 FDSE (Setup_fdse_C_D) 0.079 39.122 runnerObject/pos_object_y_target_reg[8]
+ -------------------------------------------------------------------
+ required time 39.122
+ arrival time -14.212
+ -------------------------------------------------------------------
+ slack 24.909
+
+Slack (MET) : 25.045ns (required time - arrival time)
+ Source: vgaInterface/counter_f_reg[2]/C
+ (rising edge-triggered cell FDCE clocked by clk_out1_clk_wiz_0 {rise@0.000ns fall@20.000ns period=40.000ns})
+ Destination: runnerObject/pos_object_y_target_reg[5]/R
+ (rising edge-triggered cell FDRE clocked by clk_out1_clk_wiz_0_1 {rise@0.000ns fall@20.000ns period=40.000ns})
+ Path Group: clk_out1_clk_wiz_0_1
+ Path Type: Setup (Max at Slow Process Corner)
+ Requirement: 40.000ns (clk_out1_clk_wiz_0_1 rise@40.000ns - clk_out1_clk_wiz_0 rise@0.000ns)
+ Data Path Delay: 14.294ns (logic 5.777ns (40.414%) route 8.517ns (59.586%))
+ Logic Levels: 17 (CARRY4=9 LUT1=2 LUT2=2 LUT3=1 LUT4=1 LUT6=2)
+ Clock Path Skew: -0.039ns (DCD - SCD + CPR)
+ Destination Clock Delay (DCD): -1.419ns = ( 38.581 - 40.000 )
+ Source Clock Delay (SCD): -0.821ns
+ Clock Pessimism Removal (CPR): 0.559ns
+ Clock Uncertainty: 0.098ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE
+ Total System Jitter (TSJ): 0.071ns
+ Discrete Jitter (DJ): 0.182ns
+ Phase Error (PE): 0.000ns
+ Clock Domain Crossing: Inter clock paths are considered valid unless explicitly excluded by timing constraints such as set_clock_groups or set_false_path.
+
+ Location Delay type Incr(ns) Path(ns) Netlist Resource(s)
+ ------------------------------------------------------------------- -------------------
+ (clock clk_out1_clk_wiz_0 rise edge)
+ 0.000 0.000 r
+ E3 0.000 0.000 r clk (IN)
+ net (fo=0) 0.000 0.000 pixelClk/inst/clk_in1
+ E3 IBUF (Prop_ibuf_I_O) 1.482 1.482 r pixelClk/inst/clkin1_ibufg/O
+ net (fo=1, routed) 1.233 2.715 pixelClk/inst/clk_in1_clk_wiz_0
+ MMCME2_ADV_X1Y2 MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKOUT0)
+ -7.070 -4.355 r pixelClk/inst/mmcm_adv_inst/CLKOUT0
+ net (fo=1, routed) 1.719 -2.636 pixelClk/inst/clk_out1_clk_wiz_0
+ BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.096 -2.540 r pixelClk/inst/clkout1_buf/O
+ net (fo=127, routed) 1.719 -0.821 vgaInterface/clk_out1
+ SLICE_X89Y70 FDCE r vgaInterface/counter_f_reg[2]/C
+ ------------------------------------------------------------------- -------------------
+ SLICE_X89Y70 FDCE (Prop_fdce_C_Q) 0.456 -0.365 f vgaInterface/counter_f_reg[2]/Q
+ net (fo=5, routed) 1.006 0.641 vgaInterface/counter_f_reg[2]
+ SLICE_X88Y67 LUT1 (Prop_lut1_I0_O) 0.124 0.765 r vgaInterface/FCounter_17bit_carry_i_3/O
+ net (fo=1, routed) 0.000 0.765 runnerObject/pos_object_y_target6_carry_0[1]
+ SLICE_X88Y67 CARRY4 (Prop_carry4_S[1]_CO[3])
+ 0.533 1.298 r runnerObject/FCounter_17bit_carry/CO[3]
+ net (fo=1, routed) 0.000 1.298 runnerObject/FCounter_17bit_carry_n_0
+ SLICE_X88Y68 CARRY4 (Prop_carry4_CI_O[2])
+ 0.239 1.537 r runnerObject/FCounter_17bit_carry__0/O[2]
+ net (fo=2, routed) 0.987 2.523 runnerObject/FCounter_17bit[7]
+ SLICE_X88Y71 LUT2 (Prop_lut2_I0_O) 0.301 2.824 r runnerObject/pos_object_y_target6_carry__0_i_1/O
+ net (fo=1, routed) 0.000 2.824 runnerObject/pos_object_y_target6_carry__0_i_1_n_0
+ SLICE_X88Y71 CARRY4 (Prop_carry4_S[3]_CO[3])
+ 0.376 3.200 r runnerObject/pos_object_y_target6_carry__0/CO[3]
+ net (fo=1, routed) 0.000 3.200 runnerObject/pos_object_y_target6_carry__0_n_0
+ SLICE_X88Y72 CARRY4 (Prop_carry4_CI_O[1])
+ 0.323 3.523 f runnerObject/pos_object_y_target6_carry__1/O[1]
+ net (fo=5, routed) 0.953 4.477 runnerObject/pos_object_y_target6[9]
+ SLICE_X82Y72 LUT1 (Prop_lut1_I0_O) 0.306 4.783 r runnerObject/i__carry__1_i_13/O
+ net (fo=1, routed) 0.000 4.783 runnerObject/p_0_in[9]
+ SLICE_X82Y72 CARRY4 (Prop_carry4_S[0]_O[2])
+ 0.547 5.330 f runnerObject/i__carry__1_i_9/O[2]
+ net (fo=2, routed) 0.821 6.151 runnerObject/pos_object_y_target9[11]
+ SLICE_X84Y71 LUT4 (Prop_lut4_I3_O) 0.302 6.453 r runnerObject/pos_object_y_target2_carry_i_13/O
+ net (fo=2, routed) 0.420 6.872 runnerObject/pos_object_y_target2_carry_i_13_n_0
+ SLICE_X87Y72 LUT6 (Prop_lut6_I0_O) 0.124 6.996 r runnerObject/pos_object_y_target2_carry_i_10/O
+ net (fo=34, routed) 1.081 8.077 runnerObject/pos_object_y_target2_carry_i_10_n_0
+ SLICE_X84Y70 LUT6 (Prop_lut6_I3_O) 0.124 8.201 r runnerObject/pos_object_y_target2_carry_i_9/O
+ net (fo=1, routed) 0.701 8.903 runnerObject/pos_object_y_target2_carry_i_9_n_0
+ SLICE_X85Y70 CARRY4 (Prop_carry4_S[0]_O[3])
+ 0.730 9.633 f runnerObject/pos_object_y_target2_carry/O[3]
+ net (fo=2, routed) 1.215 10.847 runnerObject/pos_object_y_target2[4]
+ SLICE_X84Y73 LUT2 (Prop_lut2_I1_O) 0.306 11.153 r runnerObject/pos_object_y_target1_carry_i_4/O
+ net (fo=1, routed) 0.000 11.153 runnerObject/pos_object_y_target1_carry_i_4_n_0
+ SLICE_X84Y73 CARRY4 (Prop_carry4_S[2]_CO[3])
+ 0.380 11.533 r runnerObject/pos_object_y_target1_carry/CO[3]
+ net (fo=1, routed) 0.000 11.533 runnerObject/pos_object_y_target1_carry_n_0
+ SLICE_X84Y74 CARRY4 (Prop_carry4_CI_CO[3])
+ 0.117 11.650 r runnerObject/pos_object_y_target1_carry__0/CO[3]
+ net (fo=1, routed) 0.009 11.659 runnerObject/pos_object_y_target1_carry__0_n_0
+ SLICE_X84Y75 CARRY4 (Prop_carry4_CI_CO[1])
+ 0.157 11.816 f runnerObject/pos_object_y_target1_carry__1/CO[1]
+ net (fo=11, routed) 0.629 12.445 runnerObject/pos_object_y_target1
+ SLICE_X86Y77 LUT3 (Prop_lut3_I0_O) 0.332 12.777 r runnerObject/pos_object_y_target[8]_i_1/O
+ net (fo=9, routed) 0.697 13.474 runnerObject/pos_object_y_target[8]_i_1_n_0
+ SLICE_X88Y79 FDRE r runnerObject/pos_object_y_target_reg[5]/R
+ ------------------------------------------------------------------- -------------------
+
+ (clock clk_out1_clk_wiz_0_1 rise edge)
+ 40.000 40.000 r
+ E3 0.000 40.000 r clk (IN)
+ net (fo=0) 0.000 40.000 pixelClk/inst/clk_in1
+ E3 IBUF (Prop_ibuf_I_O) 1.411 41.411 r pixelClk/inst/clkin1_ibufg/O
+ net (fo=1, routed) 1.162 42.573 pixelClk/inst/clk_in1_clk_wiz_0
+ MMCME2_ADV_X1Y2 MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKOUT0)
+ -7.324 35.249 r pixelClk/inst/mmcm_adv_inst/CLKOUT0
+ net (fo=1, routed) 1.639 36.888 pixelClk/inst/clk_out1_clk_wiz_0
+ BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.091 36.979 r pixelClk/inst/clkout1_buf/O
+ net (fo=127, routed) 1.601 38.581 runnerObject/clk_out1
+ SLICE_X88Y79 FDRE r runnerObject/pos_object_y_target_reg[5]/C
+ clock pessimism 0.559 39.140
+ clock uncertainty -0.098 39.043
+ SLICE_X88Y79 FDRE (Setup_fdre_C_R) -0.524 38.519 runnerObject/pos_object_y_target_reg[5]
+ -------------------------------------------------------------------
+ required time 38.519
+ arrival time -13.474
+ -------------------------------------------------------------------
+ slack 25.045
+
+Slack (MET) : 25.102ns (required time - arrival time)
+ Source: vgaInterface/counter_f_reg[2]/C
+ (rising edge-triggered cell FDCE clocked by clk_out1_clk_wiz_0 {rise@0.000ns fall@20.000ns period=40.000ns})
+ Destination: runnerObject/pos_object_y_target_reg[6]/S
+ (rising edge-triggered cell FDSE clocked by clk_out1_clk_wiz_0_1 {rise@0.000ns fall@20.000ns period=40.000ns})
+ Path Group: clk_out1_clk_wiz_0_1
+ Path Type: Setup (Max at Slow Process Corner)
+ Requirement: 40.000ns (clk_out1_clk_wiz_0_1 rise@40.000ns - clk_out1_clk_wiz_0 rise@0.000ns)
+ Data Path Delay: 14.237ns (logic 5.777ns (40.577%) route 8.460ns (59.423%))
+ Logic Levels: 17 (CARRY4=9 LUT1=2 LUT2=2 LUT3=1 LUT4=1 LUT6=2)
+ Clock Path Skew: -0.039ns (DCD - SCD + CPR)
+ Destination Clock Delay (DCD): -1.419ns = ( 38.581 - 40.000 )
+ Source Clock Delay (SCD): -0.821ns
+ Clock Pessimism Removal (CPR): 0.559ns
+ Clock Uncertainty: 0.098ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE
+ Total System Jitter (TSJ): 0.071ns
+ Discrete Jitter (DJ): 0.182ns
+ Phase Error (PE): 0.000ns
+ Clock Domain Crossing: Inter clock paths are considered valid unless explicitly excluded by timing constraints such as set_clock_groups or set_false_path.
+
+ Location Delay type Incr(ns) Path(ns) Netlist Resource(s)
+ ------------------------------------------------------------------- -------------------
+ (clock clk_out1_clk_wiz_0 rise edge)
+ 0.000 0.000 r
+ E3 0.000 0.000 r clk (IN)
+ net (fo=0) 0.000 0.000 pixelClk/inst/clk_in1
+ E3 IBUF (Prop_ibuf_I_O) 1.482 1.482 r pixelClk/inst/clkin1_ibufg/O
+ net (fo=1, routed) 1.233 2.715 pixelClk/inst/clk_in1_clk_wiz_0
+ MMCME2_ADV_X1Y2 MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKOUT0)
+ -7.070 -4.355 r pixelClk/inst/mmcm_adv_inst/CLKOUT0
+ net (fo=1, routed) 1.719 -2.636 pixelClk/inst/clk_out1_clk_wiz_0
+ BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.096 -2.540 r pixelClk/inst/clkout1_buf/O
+ net (fo=127, routed) 1.719 -0.821 vgaInterface/clk_out1
+ SLICE_X89Y70 FDCE r vgaInterface/counter_f_reg[2]/C
+ ------------------------------------------------------------------- -------------------
+ SLICE_X89Y70 FDCE (Prop_fdce_C_Q) 0.456 -0.365 f vgaInterface/counter_f_reg[2]/Q
+ net (fo=5, routed) 1.006 0.641 vgaInterface/counter_f_reg[2]
+ SLICE_X88Y67 LUT1 (Prop_lut1_I0_O) 0.124 0.765 r vgaInterface/FCounter_17bit_carry_i_3/O
+ net (fo=1, routed) 0.000 0.765 runnerObject/pos_object_y_target6_carry_0[1]
+ SLICE_X88Y67 CARRY4 (Prop_carry4_S[1]_CO[3])
+ 0.533 1.298 r runnerObject/FCounter_17bit_carry/CO[3]
+ net (fo=1, routed) 0.000 1.298 runnerObject/FCounter_17bit_carry_n_0
+ SLICE_X88Y68 CARRY4 (Prop_carry4_CI_O[2])
+ 0.239 1.537 r runnerObject/FCounter_17bit_carry__0/O[2]
+ net (fo=2, routed) 0.987 2.523 runnerObject/FCounter_17bit[7]
+ SLICE_X88Y71 LUT2 (Prop_lut2_I0_O) 0.301 2.824 r runnerObject/pos_object_y_target6_carry__0_i_1/O
+ net (fo=1, routed) 0.000 2.824 runnerObject/pos_object_y_target6_carry__0_i_1_n_0
+ SLICE_X88Y71 CARRY4 (Prop_carry4_S[3]_CO[3])
+ 0.376 3.200 r runnerObject/pos_object_y_target6_carry__0/CO[3]
+ net (fo=1, routed) 0.000 3.200 runnerObject/pos_object_y_target6_carry__0_n_0
+ SLICE_X88Y72 CARRY4 (Prop_carry4_CI_O[1])
+ 0.323 3.523 f runnerObject/pos_object_y_target6_carry__1/O[1]
+ net (fo=5, routed) 0.953 4.477 runnerObject/pos_object_y_target6[9]
+ SLICE_X82Y72 LUT1 (Prop_lut1_I0_O) 0.306 4.783 r runnerObject/i__carry__1_i_13/O
+ net (fo=1, routed) 0.000 4.783 runnerObject/p_0_in[9]
+ SLICE_X82Y72 CARRY4 (Prop_carry4_S[0]_O[2])
+ 0.547 5.330 f runnerObject/i__carry__1_i_9/O[2]
+ net (fo=2, routed) 0.821 6.151 runnerObject/pos_object_y_target9[11]
+ SLICE_X84Y71 LUT4 (Prop_lut4_I3_O) 0.302 6.453 r runnerObject/pos_object_y_target2_carry_i_13/O
+ net (fo=2, routed) 0.420 6.872 runnerObject/pos_object_y_target2_carry_i_13_n_0
+ SLICE_X87Y72 LUT6 (Prop_lut6_I0_O) 0.124 6.996 r runnerObject/pos_object_y_target2_carry_i_10/O
+ net (fo=34, routed) 1.081 8.077 runnerObject/pos_object_y_target2_carry_i_10_n_0
+ SLICE_X84Y70 LUT6 (Prop_lut6_I3_O) 0.124 8.201 r runnerObject/pos_object_y_target2_carry_i_9/O
+ net (fo=1, routed) 0.701 8.903 runnerObject/pos_object_y_target2_carry_i_9_n_0
+ SLICE_X85Y70 CARRY4 (Prop_carry4_S[0]_O[3])
+ 0.730 9.633 f runnerObject/pos_object_y_target2_carry/O[3]
+ net (fo=2, routed) 1.215 10.847 runnerObject/pos_object_y_target2[4]
+ SLICE_X84Y73 LUT2 (Prop_lut2_I1_O) 0.306 11.153 r runnerObject/pos_object_y_target1_carry_i_4/O
+ net (fo=1, routed) 0.000 11.153 runnerObject/pos_object_y_target1_carry_i_4_n_0
+ SLICE_X84Y73 CARRY4 (Prop_carry4_S[2]_CO[3])
+ 0.380 11.533 r runnerObject/pos_object_y_target1_carry/CO[3]
+ net (fo=1, routed) 0.000 11.533 runnerObject/pos_object_y_target1_carry_n_0
+ SLICE_X84Y74 CARRY4 (Prop_carry4_CI_CO[3])
+ 0.117 11.650 r runnerObject/pos_object_y_target1_carry__0/CO[3]
+ net (fo=1, routed) 0.009 11.659 runnerObject/pos_object_y_target1_carry__0_n_0
+ SLICE_X84Y75 CARRY4 (Prop_carry4_CI_CO[1])
+ 0.157 11.816 f runnerObject/pos_object_y_target1_carry__1/CO[1]
+ net (fo=11, routed) 0.629 12.445 runnerObject/pos_object_y_target1
+ SLICE_X86Y77 LUT3 (Prop_lut3_I0_O) 0.332 12.777 r runnerObject/pos_object_y_target[8]_i_1/O
+ net (fo=9, routed) 0.639 13.416 runnerObject/pos_object_y_target[8]_i_1_n_0
+ SLICE_X88Y80 FDSE r runnerObject/pos_object_y_target_reg[6]/S
+ ------------------------------------------------------------------- -------------------
+
+ (clock clk_out1_clk_wiz_0_1 rise edge)
+ 40.000 40.000 r
+ E3 0.000 40.000 r clk (IN)
+ net (fo=0) 0.000 40.000 pixelClk/inst/clk_in1
+ E3 IBUF (Prop_ibuf_I_O) 1.411 41.411 r pixelClk/inst/clkin1_ibufg/O
+ net (fo=1, routed) 1.162 42.573 pixelClk/inst/clk_in1_clk_wiz_0
+ MMCME2_ADV_X1Y2 MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKOUT0)
+ -7.324 35.249 r pixelClk/inst/mmcm_adv_inst/CLKOUT0
+ net (fo=1, routed) 1.639 36.888 pixelClk/inst/clk_out1_clk_wiz_0
+ BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.091 36.979 r pixelClk/inst/clkout1_buf/O
+ net (fo=127, routed) 1.601 38.581 runnerObject/clk_out1
+ SLICE_X88Y80 FDSE r runnerObject/pos_object_y_target_reg[6]/C
+ clock pessimism 0.559 39.140
+ clock uncertainty -0.098 39.043
+ SLICE_X88Y80 FDSE (Setup_fdse_C_S) -0.524 38.519 runnerObject/pos_object_y_target_reg[6]
+ -------------------------------------------------------------------
+ required time 38.519
+ arrival time -13.416
+ -------------------------------------------------------------------
+ slack 25.102
+
+Slack (MET) : 25.102ns (required time - arrival time)
+ Source: vgaInterface/counter_f_reg[2]/C
+ (rising edge-triggered cell FDCE clocked by clk_out1_clk_wiz_0 {rise@0.000ns fall@20.000ns period=40.000ns})
+ Destination: runnerObject/pos_object_y_target_reg[7]/R
+ (rising edge-triggered cell FDRE clocked by clk_out1_clk_wiz_0_1 {rise@0.000ns fall@20.000ns period=40.000ns})
+ Path Group: clk_out1_clk_wiz_0_1
+ Path Type: Setup (Max at Slow Process Corner)
+ Requirement: 40.000ns (clk_out1_clk_wiz_0_1 rise@40.000ns - clk_out1_clk_wiz_0 rise@0.000ns)
+ Data Path Delay: 14.237ns (logic 5.777ns (40.577%) route 8.460ns (59.423%))
+ Logic Levels: 17 (CARRY4=9 LUT1=2 LUT2=2 LUT3=1 LUT4=1 LUT6=2)
+ Clock Path Skew: -0.039ns (DCD - SCD + CPR)
+ Destination Clock Delay (DCD): -1.419ns = ( 38.581 - 40.000 )
+ Source Clock Delay (SCD): -0.821ns
+ Clock Pessimism Removal (CPR): 0.559ns
+ Clock Uncertainty: 0.098ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE
+ Total System Jitter (TSJ): 0.071ns
+ Discrete Jitter (DJ): 0.182ns
+ Phase Error (PE): 0.000ns
+ Clock Domain Crossing: Inter clock paths are considered valid unless explicitly excluded by timing constraints such as set_clock_groups or set_false_path.
+
+ Location Delay type Incr(ns) Path(ns) Netlist Resource(s)
+ ------------------------------------------------------------------- -------------------
+ (clock clk_out1_clk_wiz_0 rise edge)
+ 0.000 0.000 r
+ E3 0.000 0.000 r clk (IN)
+ net (fo=0) 0.000 0.000 pixelClk/inst/clk_in1
+ E3 IBUF (Prop_ibuf_I_O) 1.482 1.482 r pixelClk/inst/clkin1_ibufg/O
+ net (fo=1, routed) 1.233 2.715 pixelClk/inst/clk_in1_clk_wiz_0
+ MMCME2_ADV_X1Y2 MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKOUT0)
+ -7.070 -4.355 r pixelClk/inst/mmcm_adv_inst/CLKOUT0
+ net (fo=1, routed) 1.719 -2.636 pixelClk/inst/clk_out1_clk_wiz_0
+ BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.096 -2.540 r pixelClk/inst/clkout1_buf/O
+ net (fo=127, routed) 1.719 -0.821 vgaInterface/clk_out1
+ SLICE_X89Y70 FDCE r vgaInterface/counter_f_reg[2]/C
+ ------------------------------------------------------------------- -------------------
+ SLICE_X89Y70 FDCE (Prop_fdce_C_Q) 0.456 -0.365 f vgaInterface/counter_f_reg[2]/Q
+ net (fo=5, routed) 1.006 0.641 vgaInterface/counter_f_reg[2]
+ SLICE_X88Y67 LUT1 (Prop_lut1_I0_O) 0.124 0.765 r vgaInterface/FCounter_17bit_carry_i_3/O
+ net (fo=1, routed) 0.000 0.765 runnerObject/pos_object_y_target6_carry_0[1]
+ SLICE_X88Y67 CARRY4 (Prop_carry4_S[1]_CO[3])
+ 0.533 1.298 r runnerObject/FCounter_17bit_carry/CO[3]
+ net (fo=1, routed) 0.000 1.298 runnerObject/FCounter_17bit_carry_n_0
+ SLICE_X88Y68 CARRY4 (Prop_carry4_CI_O[2])
+ 0.239 1.537 r runnerObject/FCounter_17bit_carry__0/O[2]
+ net (fo=2, routed) 0.987 2.523 runnerObject/FCounter_17bit[7]
+ SLICE_X88Y71 LUT2 (Prop_lut2_I0_O) 0.301 2.824 r runnerObject/pos_object_y_target6_carry__0_i_1/O
+ net (fo=1, routed) 0.000 2.824 runnerObject/pos_object_y_target6_carry__0_i_1_n_0
+ SLICE_X88Y71 CARRY4 (Prop_carry4_S[3]_CO[3])
+ 0.376 3.200 r runnerObject/pos_object_y_target6_carry__0/CO[3]
+ net (fo=1, routed) 0.000 3.200 runnerObject/pos_object_y_target6_carry__0_n_0
+ SLICE_X88Y72 CARRY4 (Prop_carry4_CI_O[1])
+ 0.323 3.523 f runnerObject/pos_object_y_target6_carry__1/O[1]
+ net (fo=5, routed) 0.953 4.477 runnerObject/pos_object_y_target6[9]
+ SLICE_X82Y72 LUT1 (Prop_lut1_I0_O) 0.306 4.783 r runnerObject/i__carry__1_i_13/O
+ net (fo=1, routed) 0.000 4.783 runnerObject/p_0_in[9]
+ SLICE_X82Y72 CARRY4 (Prop_carry4_S[0]_O[2])
+ 0.547 5.330 f runnerObject/i__carry__1_i_9/O[2]
+ net (fo=2, routed) 0.821 6.151 runnerObject/pos_object_y_target9[11]
+ SLICE_X84Y71 LUT4 (Prop_lut4_I3_O) 0.302 6.453 r runnerObject/pos_object_y_target2_carry_i_13/O
+ net (fo=2, routed) 0.420 6.872 runnerObject/pos_object_y_target2_carry_i_13_n_0
+ SLICE_X87Y72 LUT6 (Prop_lut6_I0_O) 0.124 6.996 r runnerObject/pos_object_y_target2_carry_i_10/O
+ net (fo=34, routed) 1.081 8.077 runnerObject/pos_object_y_target2_carry_i_10_n_0
+ SLICE_X84Y70 LUT6 (Prop_lut6_I3_O) 0.124 8.201 r runnerObject/pos_object_y_target2_carry_i_9/O
+ net (fo=1, routed) 0.701 8.903 runnerObject/pos_object_y_target2_carry_i_9_n_0
+ SLICE_X85Y70 CARRY4 (Prop_carry4_S[0]_O[3])
+ 0.730 9.633 f runnerObject/pos_object_y_target2_carry/O[3]
+ net (fo=2, routed) 1.215 10.847 runnerObject/pos_object_y_target2[4]
+ SLICE_X84Y73 LUT2 (Prop_lut2_I1_O) 0.306 11.153 r runnerObject/pos_object_y_target1_carry_i_4/O
+ net (fo=1, routed) 0.000 11.153 runnerObject/pos_object_y_target1_carry_i_4_n_0
+ SLICE_X84Y73 CARRY4 (Prop_carry4_S[2]_CO[3])
+ 0.380 11.533 r runnerObject/pos_object_y_target1_carry/CO[3]
+ net (fo=1, routed) 0.000 11.533 runnerObject/pos_object_y_target1_carry_n_0
+ SLICE_X84Y74 CARRY4 (Prop_carry4_CI_CO[3])
+ 0.117 11.650 r runnerObject/pos_object_y_target1_carry__0/CO[3]
+ net (fo=1, routed) 0.009 11.659 runnerObject/pos_object_y_target1_carry__0_n_0
+ SLICE_X84Y75 CARRY4 (Prop_carry4_CI_CO[1])
+ 0.157 11.816 f runnerObject/pos_object_y_target1_carry__1/CO[1]
+ net (fo=11, routed) 0.629 12.445 runnerObject/pos_object_y_target1
+ SLICE_X86Y77 LUT3 (Prop_lut3_I0_O) 0.332 12.777 r runnerObject/pos_object_y_target[8]_i_1/O
+ net (fo=9, routed) 0.639 13.416 runnerObject/pos_object_y_target[8]_i_1_n_0
+ SLICE_X88Y80 FDRE r runnerObject/pos_object_y_target_reg[7]/R
+ ------------------------------------------------------------------- -------------------
+
+ (clock clk_out1_clk_wiz_0_1 rise edge)
+ 40.000 40.000 r
+ E3 0.000 40.000 r clk (IN)
+ net (fo=0) 0.000 40.000 pixelClk/inst/clk_in1
+ E3 IBUF (Prop_ibuf_I_O) 1.411 41.411 r pixelClk/inst/clkin1_ibufg/O
+ net (fo=1, routed) 1.162 42.573 pixelClk/inst/clk_in1_clk_wiz_0
+ MMCME2_ADV_X1Y2 MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKOUT0)
+ -7.324 35.249 r pixelClk/inst/mmcm_adv_inst/CLKOUT0
+ net (fo=1, routed) 1.639 36.888 pixelClk/inst/clk_out1_clk_wiz_0
+ BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.091 36.979 r pixelClk/inst/clkout1_buf/O
+ net (fo=127, routed) 1.601 38.581 runnerObject/clk_out1
+ SLICE_X88Y80 FDRE r runnerObject/pos_object_y_target_reg[7]/C
+ clock pessimism 0.559 39.140
+ clock uncertainty -0.098 39.043
+ SLICE_X88Y80 FDRE (Setup_fdre_C_R) -0.524 38.519 runnerObject/pos_object_y_target_reg[7]
+ -------------------------------------------------------------------
+ required time 38.519
+ arrival time -13.416
+ -------------------------------------------------------------------
+ slack 25.102
+
+Slack (MET) : 25.102ns (required time - arrival time)
+ Source: vgaInterface/counter_f_reg[2]/C
+ (rising edge-triggered cell FDCE clocked by clk_out1_clk_wiz_0 {rise@0.000ns fall@20.000ns period=40.000ns})
+ Destination: runnerObject/pos_object_y_target_reg[8]/S
+ (rising edge-triggered cell FDSE clocked by clk_out1_clk_wiz_0_1 {rise@0.000ns fall@20.000ns period=40.000ns})
+ Path Group: clk_out1_clk_wiz_0_1
+ Path Type: Setup (Max at Slow Process Corner)
+ Requirement: 40.000ns (clk_out1_clk_wiz_0_1 rise@40.000ns - clk_out1_clk_wiz_0 rise@0.000ns)
+ Data Path Delay: 14.237ns (logic 5.777ns (40.577%) route 8.460ns (59.423%))
+ Logic Levels: 17 (CARRY4=9 LUT1=2 LUT2=2 LUT3=1 LUT4=1 LUT6=2)
+ Clock Path Skew: -0.039ns (DCD - SCD + CPR)
+ Destination Clock Delay (DCD): -1.419ns = ( 38.581 - 40.000 )
+ Source Clock Delay (SCD): -0.821ns
+ Clock Pessimism Removal (CPR): 0.559ns
+ Clock Uncertainty: 0.098ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE
+ Total System Jitter (TSJ): 0.071ns
+ Discrete Jitter (DJ): 0.182ns
+ Phase Error (PE): 0.000ns
+ Clock Domain Crossing: Inter clock paths are considered valid unless explicitly excluded by timing constraints such as set_clock_groups or set_false_path.
+
+ Location Delay type Incr(ns) Path(ns) Netlist Resource(s)
+ ------------------------------------------------------------------- -------------------
+ (clock clk_out1_clk_wiz_0 rise edge)
+ 0.000 0.000 r
+ E3 0.000 0.000 r clk (IN)
+ net (fo=0) 0.000 0.000 pixelClk/inst/clk_in1
+ E3 IBUF (Prop_ibuf_I_O) 1.482 1.482 r pixelClk/inst/clkin1_ibufg/O
+ net (fo=1, routed) 1.233 2.715 pixelClk/inst/clk_in1_clk_wiz_0
+ MMCME2_ADV_X1Y2 MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKOUT0)
+ -7.070 -4.355 r pixelClk/inst/mmcm_adv_inst/CLKOUT0
+ net (fo=1, routed) 1.719 -2.636 pixelClk/inst/clk_out1_clk_wiz_0
+ BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.096 -2.540 r pixelClk/inst/clkout1_buf/O
+ net (fo=127, routed) 1.719 -0.821 vgaInterface/clk_out1
+ SLICE_X89Y70 FDCE r vgaInterface/counter_f_reg[2]/C
+ ------------------------------------------------------------------- -------------------
+ SLICE_X89Y70 FDCE (Prop_fdce_C_Q) 0.456 -0.365 f vgaInterface/counter_f_reg[2]/Q
+ net (fo=5, routed) 1.006 0.641 vgaInterface/counter_f_reg[2]
+ SLICE_X88Y67 LUT1 (Prop_lut1_I0_O) 0.124 0.765 r vgaInterface/FCounter_17bit_carry_i_3/O
+ net (fo=1, routed) 0.000 0.765 runnerObject/pos_object_y_target6_carry_0[1]
+ SLICE_X88Y67 CARRY4 (Prop_carry4_S[1]_CO[3])
+ 0.533 1.298 r runnerObject/FCounter_17bit_carry/CO[3]
+ net (fo=1, routed) 0.000 1.298 runnerObject/FCounter_17bit_carry_n_0
+ SLICE_X88Y68 CARRY4 (Prop_carry4_CI_O[2])
+ 0.239 1.537 r runnerObject/FCounter_17bit_carry__0/O[2]
+ net (fo=2, routed) 0.987 2.523 runnerObject/FCounter_17bit[7]
+ SLICE_X88Y71 LUT2 (Prop_lut2_I0_O) 0.301 2.824 r runnerObject/pos_object_y_target6_carry__0_i_1/O
+ net (fo=1, routed) 0.000 2.824 runnerObject/pos_object_y_target6_carry__0_i_1_n_0
+ SLICE_X88Y71 CARRY4 (Prop_carry4_S[3]_CO[3])
+ 0.376 3.200 r runnerObject/pos_object_y_target6_carry__0/CO[3]
+ net (fo=1, routed) 0.000 3.200 runnerObject/pos_object_y_target6_carry__0_n_0
+ SLICE_X88Y72 CARRY4 (Prop_carry4_CI_O[1])
+ 0.323 3.523 f runnerObject/pos_object_y_target6_carry__1/O[1]
+ net (fo=5, routed) 0.953 4.477 runnerObject/pos_object_y_target6[9]
+ SLICE_X82Y72 LUT1 (Prop_lut1_I0_O) 0.306 4.783 r runnerObject/i__carry__1_i_13/O
+ net (fo=1, routed) 0.000 4.783 runnerObject/p_0_in[9]
+ SLICE_X82Y72 CARRY4 (Prop_carry4_S[0]_O[2])
+ 0.547 5.330 f runnerObject/i__carry__1_i_9/O[2]
+ net (fo=2, routed) 0.821 6.151 runnerObject/pos_object_y_target9[11]
+ SLICE_X84Y71 LUT4 (Prop_lut4_I3_O) 0.302 6.453 r runnerObject/pos_object_y_target2_carry_i_13/O
+ net (fo=2, routed) 0.420 6.872 runnerObject/pos_object_y_target2_carry_i_13_n_0
+ SLICE_X87Y72 LUT6 (Prop_lut6_I0_O) 0.124 6.996 r runnerObject/pos_object_y_target2_carry_i_10/O
+ net (fo=34, routed) 1.081 8.077 runnerObject/pos_object_y_target2_carry_i_10_n_0
+ SLICE_X84Y70 LUT6 (Prop_lut6_I3_O) 0.124 8.201 r runnerObject/pos_object_y_target2_carry_i_9/O
+ net (fo=1, routed) 0.701 8.903 runnerObject/pos_object_y_target2_carry_i_9_n_0
+ SLICE_X85Y70 CARRY4 (Prop_carry4_S[0]_O[3])
+ 0.730 9.633 f runnerObject/pos_object_y_target2_carry/O[3]
+ net (fo=2, routed) 1.215 10.847 runnerObject/pos_object_y_target2[4]
+ SLICE_X84Y73 LUT2 (Prop_lut2_I1_O) 0.306 11.153 r runnerObject/pos_object_y_target1_carry_i_4/O
+ net (fo=1, routed) 0.000 11.153 runnerObject/pos_object_y_target1_carry_i_4_n_0
+ SLICE_X84Y73 CARRY4 (Prop_carry4_S[2]_CO[3])
+ 0.380 11.533 r runnerObject/pos_object_y_target1_carry/CO[3]
+ net (fo=1, routed) 0.000 11.533 runnerObject/pos_object_y_target1_carry_n_0
+ SLICE_X84Y74 CARRY4 (Prop_carry4_CI_CO[3])
+ 0.117 11.650 r runnerObject/pos_object_y_target1_carry__0/CO[3]
+ net (fo=1, routed) 0.009 11.659 runnerObject/pos_object_y_target1_carry__0_n_0
+ SLICE_X84Y75 CARRY4 (Prop_carry4_CI_CO[1])
+ 0.157 11.816 f runnerObject/pos_object_y_target1_carry__1/CO[1]
+ net (fo=11, routed) 0.629 12.445 runnerObject/pos_object_y_target1
+ SLICE_X86Y77 LUT3 (Prop_lut3_I0_O) 0.332 12.777 r runnerObject/pos_object_y_target[8]_i_1/O
+ net (fo=9, routed) 0.639 13.416 runnerObject/pos_object_y_target[8]_i_1_n_0
+ SLICE_X88Y80 FDSE r runnerObject/pos_object_y_target_reg[8]/S
+ ------------------------------------------------------------------- -------------------
+
+ (clock clk_out1_clk_wiz_0_1 rise edge)
+ 40.000 40.000 r
+ E3 0.000 40.000 r clk (IN)
+ net (fo=0) 0.000 40.000 pixelClk/inst/clk_in1
+ E3 IBUF (Prop_ibuf_I_O) 1.411 41.411 r pixelClk/inst/clkin1_ibufg/O
+ net (fo=1, routed) 1.162 42.573 pixelClk/inst/clk_in1_clk_wiz_0
+ MMCME2_ADV_X1Y2 MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKOUT0)
+ -7.324 35.249 r pixelClk/inst/mmcm_adv_inst/CLKOUT0
+ net (fo=1, routed) 1.639 36.888 pixelClk/inst/clk_out1_clk_wiz_0
+ BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.091 36.979 r pixelClk/inst/clkout1_buf/O
+ net (fo=127, routed) 1.601 38.581 runnerObject/clk_out1
+ SLICE_X88Y80 FDSE r runnerObject/pos_object_y_target_reg[8]/C
+ clock pessimism 0.559 39.140
+ clock uncertainty -0.098 39.043
+ SLICE_X88Y80 FDSE (Setup_fdse_C_S) -0.524 38.519 runnerObject/pos_object_y_target_reg[8]
+ -------------------------------------------------------------------
+ required time 38.519
+ arrival time -13.416
+ -------------------------------------------------------------------
+ slack 25.102
+
+Slack (MET) : 25.140ns (required time - arrival time)
+ Source: vgaInterface/counter_f_reg[2]/C
+ (rising edge-triggered cell FDCE clocked by clk_out1_clk_wiz_0 {rise@0.000ns fall@20.000ns period=40.000ns})
+ Destination: runnerObject/pos_object_y_target_reg[0]/R
+ (rising edge-triggered cell FDRE clocked by clk_out1_clk_wiz_0_1 {rise@0.000ns fall@20.000ns period=40.000ns})
+ Path Group: clk_out1_clk_wiz_0_1
+ Path Type: Setup (Max at Slow Process Corner)
+ Requirement: 40.000ns (clk_out1_clk_wiz_0_1 rise@40.000ns - clk_out1_clk_wiz_0 rise@0.000ns)
+ Data Path Delay: 14.294ns (logic 5.777ns (40.414%) route 8.517ns (59.586%))
+ Logic Levels: 17 (CARRY4=9 LUT1=2 LUT2=2 LUT3=1 LUT4=1 LUT6=2)
+ Clock Path Skew: -0.039ns (DCD - SCD + CPR)
+ Destination Clock Delay (DCD): -1.419ns = ( 38.581 - 40.000 )
+ Source Clock Delay (SCD): -0.821ns
+ Clock Pessimism Removal (CPR): 0.559ns
+ Clock Uncertainty: 0.098ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE
+ Total System Jitter (TSJ): 0.071ns
+ Discrete Jitter (DJ): 0.182ns
+ Phase Error (PE): 0.000ns
+ Clock Domain Crossing: Inter clock paths are considered valid unless explicitly excluded by timing constraints such as set_clock_groups or set_false_path.
+
+ Location Delay type Incr(ns) Path(ns) Netlist Resource(s)
+ ------------------------------------------------------------------- -------------------
+ (clock clk_out1_clk_wiz_0 rise edge)
+ 0.000 0.000 r
+ E3 0.000 0.000 r clk (IN)
+ net (fo=0) 0.000 0.000 pixelClk/inst/clk_in1
+ E3 IBUF (Prop_ibuf_I_O) 1.482 1.482 r pixelClk/inst/clkin1_ibufg/O
+ net (fo=1, routed) 1.233 2.715 pixelClk/inst/clk_in1_clk_wiz_0
+ MMCME2_ADV_X1Y2 MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKOUT0)
+ -7.070 -4.355 r pixelClk/inst/mmcm_adv_inst/CLKOUT0
+ net (fo=1, routed) 1.719 -2.636 pixelClk/inst/clk_out1_clk_wiz_0
+ BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.096 -2.540 r pixelClk/inst/clkout1_buf/O
+ net (fo=127, routed) 1.719 -0.821 vgaInterface/clk_out1
+ SLICE_X89Y70 FDCE r vgaInterface/counter_f_reg[2]/C
+ ------------------------------------------------------------------- -------------------
+ SLICE_X89Y70 FDCE (Prop_fdce_C_Q) 0.456 -0.365 f vgaInterface/counter_f_reg[2]/Q
+ net (fo=5, routed) 1.006 0.641 vgaInterface/counter_f_reg[2]
+ SLICE_X88Y67 LUT1 (Prop_lut1_I0_O) 0.124 0.765 r vgaInterface/FCounter_17bit_carry_i_3/O
+ net (fo=1, routed) 0.000 0.765 runnerObject/pos_object_y_target6_carry_0[1]
+ SLICE_X88Y67 CARRY4 (Prop_carry4_S[1]_CO[3])
+ 0.533 1.298 r runnerObject/FCounter_17bit_carry/CO[3]
+ net (fo=1, routed) 0.000 1.298 runnerObject/FCounter_17bit_carry_n_0
+ SLICE_X88Y68 CARRY4 (Prop_carry4_CI_O[2])
+ 0.239 1.537 r runnerObject/FCounter_17bit_carry__0/O[2]
+ net (fo=2, routed) 0.987 2.523 runnerObject/FCounter_17bit[7]
+ SLICE_X88Y71 LUT2 (Prop_lut2_I0_O) 0.301 2.824 r runnerObject/pos_object_y_target6_carry__0_i_1/O
+ net (fo=1, routed) 0.000 2.824 runnerObject/pos_object_y_target6_carry__0_i_1_n_0
+ SLICE_X88Y71 CARRY4 (Prop_carry4_S[3]_CO[3])
+ 0.376 3.200 r runnerObject/pos_object_y_target6_carry__0/CO[3]
+ net (fo=1, routed) 0.000 3.200 runnerObject/pos_object_y_target6_carry__0_n_0
+ SLICE_X88Y72 CARRY4 (Prop_carry4_CI_O[1])
+ 0.323 3.523 f runnerObject/pos_object_y_target6_carry__1/O[1]
+ net (fo=5, routed) 0.953 4.477 runnerObject/pos_object_y_target6[9]
+ SLICE_X82Y72 LUT1 (Prop_lut1_I0_O) 0.306 4.783 r runnerObject/i__carry__1_i_13/O
+ net (fo=1, routed) 0.000 4.783 runnerObject/p_0_in[9]
+ SLICE_X82Y72 CARRY4 (Prop_carry4_S[0]_O[2])
+ 0.547 5.330 f runnerObject/i__carry__1_i_9/O[2]
+ net (fo=2, routed) 0.821 6.151 runnerObject/pos_object_y_target9[11]
+ SLICE_X84Y71 LUT4 (Prop_lut4_I3_O) 0.302 6.453 r runnerObject/pos_object_y_target2_carry_i_13/O
+ net (fo=2, routed) 0.420 6.872 runnerObject/pos_object_y_target2_carry_i_13_n_0
+ SLICE_X87Y72 LUT6 (Prop_lut6_I0_O) 0.124 6.996 r runnerObject/pos_object_y_target2_carry_i_10/O
+ net (fo=34, routed) 1.081 8.077 runnerObject/pos_object_y_target2_carry_i_10_n_0
+ SLICE_X84Y70 LUT6 (Prop_lut6_I3_O) 0.124 8.201 r runnerObject/pos_object_y_target2_carry_i_9/O
+ net (fo=1, routed) 0.701 8.903 runnerObject/pos_object_y_target2_carry_i_9_n_0
+ SLICE_X85Y70 CARRY4 (Prop_carry4_S[0]_O[3])
+ 0.730 9.633 f runnerObject/pos_object_y_target2_carry/O[3]
+ net (fo=2, routed) 1.215 10.847 runnerObject/pos_object_y_target2[4]
+ SLICE_X84Y73 LUT2 (Prop_lut2_I1_O) 0.306 11.153 r runnerObject/pos_object_y_target1_carry_i_4/O
+ net (fo=1, routed) 0.000 11.153 runnerObject/pos_object_y_target1_carry_i_4_n_0
+ SLICE_X84Y73 CARRY4 (Prop_carry4_S[2]_CO[3])
+ 0.380 11.533 r runnerObject/pos_object_y_target1_carry/CO[3]
+ net (fo=1, routed) 0.000 11.533 runnerObject/pos_object_y_target1_carry_n_0
+ SLICE_X84Y74 CARRY4 (Prop_carry4_CI_CO[3])
+ 0.117 11.650 r runnerObject/pos_object_y_target1_carry__0/CO[3]
+ net (fo=1, routed) 0.009 11.659 runnerObject/pos_object_y_target1_carry__0_n_0
+ SLICE_X84Y75 CARRY4 (Prop_carry4_CI_CO[1])
+ 0.157 11.816 f runnerObject/pos_object_y_target1_carry__1/CO[1]
+ net (fo=11, routed) 0.629 12.445 runnerObject/pos_object_y_target1
+ SLICE_X86Y77 LUT3 (Prop_lut3_I0_O) 0.332 12.777 r runnerObject/pos_object_y_target[8]_i_1/O
+ net (fo=9, routed) 0.697 13.474 runnerObject/pos_object_y_target[8]_i_1_n_0
+ SLICE_X89Y79 FDRE r runnerObject/pos_object_y_target_reg[0]/R
+ ------------------------------------------------------------------- -------------------
+
+ (clock clk_out1_clk_wiz_0_1 rise edge)
+ 40.000 40.000 r
+ E3 0.000 40.000 r clk (IN)
+ net (fo=0) 0.000 40.000 pixelClk/inst/clk_in1
+ E3 IBUF (Prop_ibuf_I_O) 1.411 41.411 r pixelClk/inst/clkin1_ibufg/O
+ net (fo=1, routed) 1.162 42.573 pixelClk/inst/clk_in1_clk_wiz_0
+ MMCME2_ADV_X1Y2 MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKOUT0)
+ -7.324 35.249 r pixelClk/inst/mmcm_adv_inst/CLKOUT0
+ net (fo=1, routed) 1.639 36.888 pixelClk/inst/clk_out1_clk_wiz_0
+ BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.091 36.979 r pixelClk/inst/clkout1_buf/O
+ net (fo=127, routed) 1.601 38.581 runnerObject/clk_out1
+ SLICE_X89Y79 FDRE r runnerObject/pos_object_y_target_reg[0]/C
+ clock pessimism 0.559 39.140
+ clock uncertainty -0.098 39.043
+ SLICE_X89Y79 FDRE (Setup_fdre_C_R) -0.429 38.614 runnerObject/pos_object_y_target_reg[0]
+ -------------------------------------------------------------------
+ required time 38.614
+ arrival time -13.474
+ -------------------------------------------------------------------
+ slack 25.140
+
+Slack (MET) : 25.140ns (required time - arrival time)
+ Source: vgaInterface/counter_f_reg[2]/C
+ (rising edge-triggered cell FDCE clocked by clk_out1_clk_wiz_0 {rise@0.000ns fall@20.000ns period=40.000ns})
+ Destination: runnerObject/pos_object_y_target_reg[1]/S
+ (rising edge-triggered cell FDSE clocked by clk_out1_clk_wiz_0_1 {rise@0.000ns fall@20.000ns period=40.000ns})
+ Path Group: clk_out1_clk_wiz_0_1
+ Path Type: Setup (Max at Slow Process Corner)
+ Requirement: 40.000ns (clk_out1_clk_wiz_0_1 rise@40.000ns - clk_out1_clk_wiz_0 rise@0.000ns)
+ Data Path Delay: 14.294ns (logic 5.777ns (40.414%) route 8.517ns (59.586%))
+ Logic Levels: 17 (CARRY4=9 LUT1=2 LUT2=2 LUT3=1 LUT4=1 LUT6=2)
+ Clock Path Skew: -0.039ns (DCD - SCD + CPR)
+ Destination Clock Delay (DCD): -1.419ns = ( 38.581 - 40.000 )
+ Source Clock Delay (SCD): -0.821ns
+ Clock Pessimism Removal (CPR): 0.559ns
+ Clock Uncertainty: 0.098ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE
+ Total System Jitter (TSJ): 0.071ns
+ Discrete Jitter (DJ): 0.182ns
+ Phase Error (PE): 0.000ns
+ Clock Domain Crossing: Inter clock paths are considered valid unless explicitly excluded by timing constraints such as set_clock_groups or set_false_path.
+
+ Location Delay type Incr(ns) Path(ns) Netlist Resource(s)
+ ------------------------------------------------------------------- -------------------
+ (clock clk_out1_clk_wiz_0 rise edge)
+ 0.000 0.000 r
+ E3 0.000 0.000 r clk (IN)
+ net (fo=0) 0.000 0.000 pixelClk/inst/clk_in1
+ E3 IBUF (Prop_ibuf_I_O) 1.482 1.482 r pixelClk/inst/clkin1_ibufg/O
+ net (fo=1, routed) 1.233 2.715 pixelClk/inst/clk_in1_clk_wiz_0
+ MMCME2_ADV_X1Y2 MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKOUT0)
+ -7.070 -4.355 r pixelClk/inst/mmcm_adv_inst/CLKOUT0
+ net (fo=1, routed) 1.719 -2.636 pixelClk/inst/clk_out1_clk_wiz_0
+ BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.096 -2.540 r pixelClk/inst/clkout1_buf/O
+ net (fo=127, routed) 1.719 -0.821 vgaInterface/clk_out1
+ SLICE_X89Y70 FDCE r vgaInterface/counter_f_reg[2]/C
+ ------------------------------------------------------------------- -------------------
+ SLICE_X89Y70 FDCE (Prop_fdce_C_Q) 0.456 -0.365 f vgaInterface/counter_f_reg[2]/Q
+ net (fo=5, routed) 1.006 0.641 vgaInterface/counter_f_reg[2]
+ SLICE_X88Y67 LUT1 (Prop_lut1_I0_O) 0.124 0.765 r vgaInterface/FCounter_17bit_carry_i_3/O
+ net (fo=1, routed) 0.000 0.765 runnerObject/pos_object_y_target6_carry_0[1]
+ SLICE_X88Y67 CARRY4 (Prop_carry4_S[1]_CO[3])
+ 0.533 1.298 r runnerObject/FCounter_17bit_carry/CO[3]
+ net (fo=1, routed) 0.000 1.298 runnerObject/FCounter_17bit_carry_n_0
+ SLICE_X88Y68 CARRY4 (Prop_carry4_CI_O[2])
+ 0.239 1.537 r runnerObject/FCounter_17bit_carry__0/O[2]
+ net (fo=2, routed) 0.987 2.523 runnerObject/FCounter_17bit[7]
+ SLICE_X88Y71 LUT2 (Prop_lut2_I0_O) 0.301 2.824 r runnerObject/pos_object_y_target6_carry__0_i_1/O
+ net (fo=1, routed) 0.000 2.824 runnerObject/pos_object_y_target6_carry__0_i_1_n_0
+ SLICE_X88Y71 CARRY4 (Prop_carry4_S[3]_CO[3])
+ 0.376 3.200 r runnerObject/pos_object_y_target6_carry__0/CO[3]
+ net (fo=1, routed) 0.000 3.200 runnerObject/pos_object_y_target6_carry__0_n_0
+ SLICE_X88Y72 CARRY4 (Prop_carry4_CI_O[1])
+ 0.323 3.523 f runnerObject/pos_object_y_target6_carry__1/O[1]
+ net (fo=5, routed) 0.953 4.477 runnerObject/pos_object_y_target6[9]
+ SLICE_X82Y72 LUT1 (Prop_lut1_I0_O) 0.306 4.783 r runnerObject/i__carry__1_i_13/O
+ net (fo=1, routed) 0.000 4.783 runnerObject/p_0_in[9]
+ SLICE_X82Y72 CARRY4 (Prop_carry4_S[0]_O[2])
+ 0.547 5.330 f runnerObject/i__carry__1_i_9/O[2]
+ net (fo=2, routed) 0.821 6.151 runnerObject/pos_object_y_target9[11]
+ SLICE_X84Y71 LUT4 (Prop_lut4_I3_O) 0.302 6.453 r runnerObject/pos_object_y_target2_carry_i_13/O
+ net (fo=2, routed) 0.420 6.872 runnerObject/pos_object_y_target2_carry_i_13_n_0
+ SLICE_X87Y72 LUT6 (Prop_lut6_I0_O) 0.124 6.996 r runnerObject/pos_object_y_target2_carry_i_10/O
+ net (fo=34, routed) 1.081 8.077 runnerObject/pos_object_y_target2_carry_i_10_n_0
+ SLICE_X84Y70 LUT6 (Prop_lut6_I3_O) 0.124 8.201 r runnerObject/pos_object_y_target2_carry_i_9/O
+ net (fo=1, routed) 0.701 8.903 runnerObject/pos_object_y_target2_carry_i_9_n_0
+ SLICE_X85Y70 CARRY4 (Prop_carry4_S[0]_O[3])
+ 0.730 9.633 f runnerObject/pos_object_y_target2_carry/O[3]
+ net (fo=2, routed) 1.215 10.847 runnerObject/pos_object_y_target2[4]
+ SLICE_X84Y73 LUT2 (Prop_lut2_I1_O) 0.306 11.153 r runnerObject/pos_object_y_target1_carry_i_4/O
+ net (fo=1, routed) 0.000 11.153 runnerObject/pos_object_y_target1_carry_i_4_n_0
+ SLICE_X84Y73 CARRY4 (Prop_carry4_S[2]_CO[3])
+ 0.380 11.533 r runnerObject/pos_object_y_target1_carry/CO[3]
+ net (fo=1, routed) 0.000 11.533 runnerObject/pos_object_y_target1_carry_n_0
+ SLICE_X84Y74 CARRY4 (Prop_carry4_CI_CO[3])
+ 0.117 11.650 r runnerObject/pos_object_y_target1_carry__0/CO[3]
+ net (fo=1, routed) 0.009 11.659 runnerObject/pos_object_y_target1_carry__0_n_0
+ SLICE_X84Y75 CARRY4 (Prop_carry4_CI_CO[1])
+ 0.157 11.816 f runnerObject/pos_object_y_target1_carry__1/CO[1]
+ net (fo=11, routed) 0.629 12.445 runnerObject/pos_object_y_target1
+ SLICE_X86Y77 LUT3 (Prop_lut3_I0_O) 0.332 12.777 r runnerObject/pos_object_y_target[8]_i_1/O
+ net (fo=9, routed) 0.697 13.474 runnerObject/pos_object_y_target[8]_i_1_n_0
+ SLICE_X89Y79 FDSE r runnerObject/pos_object_y_target_reg[1]/S
+ ------------------------------------------------------------------- -------------------
+
+ (clock clk_out1_clk_wiz_0_1 rise edge)
+ 40.000 40.000 r
+ E3 0.000 40.000 r clk (IN)
+ net (fo=0) 0.000 40.000 pixelClk/inst/clk_in1
+ E3 IBUF (Prop_ibuf_I_O) 1.411 41.411 r pixelClk/inst/clkin1_ibufg/O
+ net (fo=1, routed) 1.162 42.573 pixelClk/inst/clk_in1_clk_wiz_0
+ MMCME2_ADV_X1Y2 MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKOUT0)
+ -7.324 35.249 r pixelClk/inst/mmcm_adv_inst/CLKOUT0
+ net (fo=1, routed) 1.639 36.888 pixelClk/inst/clk_out1_clk_wiz_0
+ BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.091 36.979 r pixelClk/inst/clkout1_buf/O
+ net (fo=127, routed) 1.601 38.581 runnerObject/clk_out1
+ SLICE_X89Y79 FDSE r runnerObject/pos_object_y_target_reg[1]/C
+ clock pessimism 0.559 39.140
+ clock uncertainty -0.098 39.043
+ SLICE_X89Y79 FDSE (Setup_fdse_C_S) -0.429 38.614 runnerObject/pos_object_y_target_reg[1]
+ -------------------------------------------------------------------
+ required time 38.614
+ arrival time -13.474
+ -------------------------------------------------------------------
+ slack 25.140
+
+Slack (MET) : 25.140ns (required time - arrival time)
+ Source: vgaInterface/counter_f_reg[2]/C
+ (rising edge-triggered cell FDCE clocked by clk_out1_clk_wiz_0 {rise@0.000ns fall@20.000ns period=40.000ns})
+ Destination: runnerObject/pos_object_y_target_reg[2]/S
+ (rising edge-triggered cell FDSE clocked by clk_out1_clk_wiz_0_1 {rise@0.000ns fall@20.000ns period=40.000ns})
+ Path Group: clk_out1_clk_wiz_0_1
+ Path Type: Setup (Max at Slow Process Corner)
+ Requirement: 40.000ns (clk_out1_clk_wiz_0_1 rise@40.000ns - clk_out1_clk_wiz_0 rise@0.000ns)
+ Data Path Delay: 14.294ns (logic 5.777ns (40.414%) route 8.517ns (59.586%))
+ Logic Levels: 17 (CARRY4=9 LUT1=2 LUT2=2 LUT3=1 LUT4=1 LUT6=2)
+ Clock Path Skew: -0.039ns (DCD - SCD + CPR)
+ Destination Clock Delay (DCD): -1.419ns = ( 38.581 - 40.000 )
+ Source Clock Delay (SCD): -0.821ns
+ Clock Pessimism Removal (CPR): 0.559ns
+ Clock Uncertainty: 0.098ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE
+ Total System Jitter (TSJ): 0.071ns
+ Discrete Jitter (DJ): 0.182ns
+ Phase Error (PE): 0.000ns
+ Clock Domain Crossing: Inter clock paths are considered valid unless explicitly excluded by timing constraints such as set_clock_groups or set_false_path.
+
+ Location Delay type Incr(ns) Path(ns) Netlist Resource(s)
+ ------------------------------------------------------------------- -------------------
+ (clock clk_out1_clk_wiz_0 rise edge)
+ 0.000 0.000 r
+ E3 0.000 0.000 r clk (IN)
+ net (fo=0) 0.000 0.000 pixelClk/inst/clk_in1
+ E3 IBUF (Prop_ibuf_I_O) 1.482 1.482 r pixelClk/inst/clkin1_ibufg/O
+ net (fo=1, routed) 1.233 2.715 pixelClk/inst/clk_in1_clk_wiz_0
+ MMCME2_ADV_X1Y2 MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKOUT0)
+ -7.070 -4.355 r pixelClk/inst/mmcm_adv_inst/CLKOUT0
+ net (fo=1, routed) 1.719 -2.636 pixelClk/inst/clk_out1_clk_wiz_0
+ BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.096 -2.540 r pixelClk/inst/clkout1_buf/O
+ net (fo=127, routed) 1.719 -0.821 vgaInterface/clk_out1
+ SLICE_X89Y70 FDCE r vgaInterface/counter_f_reg[2]/C
+ ------------------------------------------------------------------- -------------------
+ SLICE_X89Y70 FDCE (Prop_fdce_C_Q) 0.456 -0.365 f vgaInterface/counter_f_reg[2]/Q
+ net (fo=5, routed) 1.006 0.641 vgaInterface/counter_f_reg[2]
+ SLICE_X88Y67 LUT1 (Prop_lut1_I0_O) 0.124 0.765 r vgaInterface/FCounter_17bit_carry_i_3/O
+ net (fo=1, routed) 0.000 0.765 runnerObject/pos_object_y_target6_carry_0[1]
+ SLICE_X88Y67 CARRY4 (Prop_carry4_S[1]_CO[3])
+ 0.533 1.298 r runnerObject/FCounter_17bit_carry/CO[3]
+ net (fo=1, routed) 0.000 1.298 runnerObject/FCounter_17bit_carry_n_0
+ SLICE_X88Y68 CARRY4 (Prop_carry4_CI_O[2])
+ 0.239 1.537 r runnerObject/FCounter_17bit_carry__0/O[2]
+ net (fo=2, routed) 0.987 2.523 runnerObject/FCounter_17bit[7]
+ SLICE_X88Y71 LUT2 (Prop_lut2_I0_O) 0.301 2.824 r runnerObject/pos_object_y_target6_carry__0_i_1/O
+ net (fo=1, routed) 0.000 2.824 runnerObject/pos_object_y_target6_carry__0_i_1_n_0
+ SLICE_X88Y71 CARRY4 (Prop_carry4_S[3]_CO[3])
+ 0.376 3.200 r runnerObject/pos_object_y_target6_carry__0/CO[3]
+ net (fo=1, routed) 0.000 3.200 runnerObject/pos_object_y_target6_carry__0_n_0
+ SLICE_X88Y72 CARRY4 (Prop_carry4_CI_O[1])
+ 0.323 3.523 f runnerObject/pos_object_y_target6_carry__1/O[1]
+ net (fo=5, routed) 0.953 4.477 runnerObject/pos_object_y_target6[9]
+ SLICE_X82Y72 LUT1 (Prop_lut1_I0_O) 0.306 4.783 r runnerObject/i__carry__1_i_13/O
+ net (fo=1, routed) 0.000 4.783 runnerObject/p_0_in[9]
+ SLICE_X82Y72 CARRY4 (Prop_carry4_S[0]_O[2])
+ 0.547 5.330 f runnerObject/i__carry__1_i_9/O[2]
+ net (fo=2, routed) 0.821 6.151 runnerObject/pos_object_y_target9[11]
+ SLICE_X84Y71 LUT4 (Prop_lut4_I3_O) 0.302 6.453 r runnerObject/pos_object_y_target2_carry_i_13/O
+ net (fo=2, routed) 0.420 6.872 runnerObject/pos_object_y_target2_carry_i_13_n_0
+ SLICE_X87Y72 LUT6 (Prop_lut6_I0_O) 0.124 6.996 r runnerObject/pos_object_y_target2_carry_i_10/O
+ net (fo=34, routed) 1.081 8.077 runnerObject/pos_object_y_target2_carry_i_10_n_0
+ SLICE_X84Y70 LUT6 (Prop_lut6_I3_O) 0.124 8.201 r runnerObject/pos_object_y_target2_carry_i_9/O
+ net (fo=1, routed) 0.701 8.903 runnerObject/pos_object_y_target2_carry_i_9_n_0
+ SLICE_X85Y70 CARRY4 (Prop_carry4_S[0]_O[3])
+ 0.730 9.633 f runnerObject/pos_object_y_target2_carry/O[3]
+ net (fo=2, routed) 1.215 10.847 runnerObject/pos_object_y_target2[4]
+ SLICE_X84Y73 LUT2 (Prop_lut2_I1_O) 0.306 11.153 r runnerObject/pos_object_y_target1_carry_i_4/O
+ net (fo=1, routed) 0.000 11.153 runnerObject/pos_object_y_target1_carry_i_4_n_0
+ SLICE_X84Y73 CARRY4 (Prop_carry4_S[2]_CO[3])
+ 0.380 11.533 r runnerObject/pos_object_y_target1_carry/CO[3]
+ net (fo=1, routed) 0.000 11.533 runnerObject/pos_object_y_target1_carry_n_0
+ SLICE_X84Y74 CARRY4 (Prop_carry4_CI_CO[3])
+ 0.117 11.650 r runnerObject/pos_object_y_target1_carry__0/CO[3]
+ net (fo=1, routed) 0.009 11.659 runnerObject/pos_object_y_target1_carry__0_n_0
+ SLICE_X84Y75 CARRY4 (Prop_carry4_CI_CO[1])
+ 0.157 11.816 f runnerObject/pos_object_y_target1_carry__1/CO[1]
+ net (fo=11, routed) 0.629 12.445 runnerObject/pos_object_y_target1
+ SLICE_X86Y77 LUT3 (Prop_lut3_I0_O) 0.332 12.777 r runnerObject/pos_object_y_target[8]_i_1/O
+ net (fo=9, routed) 0.697 13.474 runnerObject/pos_object_y_target[8]_i_1_n_0
+ SLICE_X89Y79 FDSE r runnerObject/pos_object_y_target_reg[2]/S
+ ------------------------------------------------------------------- -------------------
+
+ (clock clk_out1_clk_wiz_0_1 rise edge)
+ 40.000 40.000 r
+ E3 0.000 40.000 r clk (IN)
+ net (fo=0) 0.000 40.000 pixelClk/inst/clk_in1
+ E3 IBUF (Prop_ibuf_I_O) 1.411 41.411 r pixelClk/inst/clkin1_ibufg/O
+ net (fo=1, routed) 1.162 42.573 pixelClk/inst/clk_in1_clk_wiz_0
+ MMCME2_ADV_X1Y2 MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKOUT0)
+ -7.324 35.249 r pixelClk/inst/mmcm_adv_inst/CLKOUT0
+ net (fo=1, routed) 1.639 36.888 pixelClk/inst/clk_out1_clk_wiz_0
+ BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.091 36.979 r pixelClk/inst/clkout1_buf/O
+ net (fo=127, routed) 1.601 38.581 runnerObject/clk_out1
+ SLICE_X89Y79 FDSE r runnerObject/pos_object_y_target_reg[2]/C
+ clock pessimism 0.559 39.140
+ clock uncertainty -0.098 39.043
+ SLICE_X89Y79 FDSE (Setup_fdse_C_S) -0.429 38.614 runnerObject/pos_object_y_target_reg[2]
+ -------------------------------------------------------------------
+ required time 38.614
+ arrival time -13.474
+ -------------------------------------------------------------------
+ slack 25.140
+
+Slack (MET) : 25.140ns (required time - arrival time)
+ Source: vgaInterface/counter_f_reg[2]/C
+ (rising edge-triggered cell FDCE clocked by clk_out1_clk_wiz_0 {rise@0.000ns fall@20.000ns period=40.000ns})
+ Destination: runnerObject/pos_object_y_target_reg[3]/S
+ (rising edge-triggered cell FDSE clocked by clk_out1_clk_wiz_0_1 {rise@0.000ns fall@20.000ns period=40.000ns})
+ Path Group: clk_out1_clk_wiz_0_1
+ Path Type: Setup (Max at Slow Process Corner)
+ Requirement: 40.000ns (clk_out1_clk_wiz_0_1 rise@40.000ns - clk_out1_clk_wiz_0 rise@0.000ns)
+ Data Path Delay: 14.294ns (logic 5.777ns (40.414%) route 8.517ns (59.586%))
+ Logic Levels: 17 (CARRY4=9 LUT1=2 LUT2=2 LUT3=1 LUT4=1 LUT6=2)
+ Clock Path Skew: -0.039ns (DCD - SCD + CPR)
+ Destination Clock Delay (DCD): -1.419ns = ( 38.581 - 40.000 )
+ Source Clock Delay (SCD): -0.821ns
+ Clock Pessimism Removal (CPR): 0.559ns
+ Clock Uncertainty: 0.098ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE
+ Total System Jitter (TSJ): 0.071ns
+ Discrete Jitter (DJ): 0.182ns
+ Phase Error (PE): 0.000ns
+ Clock Domain Crossing: Inter clock paths are considered valid unless explicitly excluded by timing constraints such as set_clock_groups or set_false_path.
+
+ Location Delay type Incr(ns) Path(ns) Netlist Resource(s)
+ ------------------------------------------------------------------- -------------------
+ (clock clk_out1_clk_wiz_0 rise edge)
+ 0.000 0.000 r
+ E3 0.000 0.000 r clk (IN)
+ net (fo=0) 0.000 0.000 pixelClk/inst/clk_in1
+ E3 IBUF (Prop_ibuf_I_O) 1.482 1.482 r pixelClk/inst/clkin1_ibufg/O
+ net (fo=1, routed) 1.233 2.715 pixelClk/inst/clk_in1_clk_wiz_0
+ MMCME2_ADV_X1Y2 MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKOUT0)
+ -7.070 -4.355 r pixelClk/inst/mmcm_adv_inst/CLKOUT0
+ net (fo=1, routed) 1.719 -2.636 pixelClk/inst/clk_out1_clk_wiz_0
+ BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.096 -2.540 r pixelClk/inst/clkout1_buf/O
+ net (fo=127, routed) 1.719 -0.821 vgaInterface/clk_out1
+ SLICE_X89Y70 FDCE r vgaInterface/counter_f_reg[2]/C
+ ------------------------------------------------------------------- -------------------
+ SLICE_X89Y70 FDCE (Prop_fdce_C_Q) 0.456 -0.365 f vgaInterface/counter_f_reg[2]/Q
+ net (fo=5, routed) 1.006 0.641 vgaInterface/counter_f_reg[2]
+ SLICE_X88Y67 LUT1 (Prop_lut1_I0_O) 0.124 0.765 r vgaInterface/FCounter_17bit_carry_i_3/O
+ net (fo=1, routed) 0.000 0.765 runnerObject/pos_object_y_target6_carry_0[1]
+ SLICE_X88Y67 CARRY4 (Prop_carry4_S[1]_CO[3])
+ 0.533 1.298 r runnerObject/FCounter_17bit_carry/CO[3]
+ net (fo=1, routed) 0.000 1.298 runnerObject/FCounter_17bit_carry_n_0
+ SLICE_X88Y68 CARRY4 (Prop_carry4_CI_O[2])
+ 0.239 1.537 r runnerObject/FCounter_17bit_carry__0/O[2]
+ net (fo=2, routed) 0.987 2.523 runnerObject/FCounter_17bit[7]
+ SLICE_X88Y71 LUT2 (Prop_lut2_I0_O) 0.301 2.824 r runnerObject/pos_object_y_target6_carry__0_i_1/O
+ net (fo=1, routed) 0.000 2.824 runnerObject/pos_object_y_target6_carry__0_i_1_n_0
+ SLICE_X88Y71 CARRY4 (Prop_carry4_S[3]_CO[3])
+ 0.376 3.200 r runnerObject/pos_object_y_target6_carry__0/CO[3]
+ net (fo=1, routed) 0.000 3.200 runnerObject/pos_object_y_target6_carry__0_n_0
+ SLICE_X88Y72 CARRY4 (Prop_carry4_CI_O[1])
+ 0.323 3.523 f runnerObject/pos_object_y_target6_carry__1/O[1]
+ net (fo=5, routed) 0.953 4.477 runnerObject/pos_object_y_target6[9]
+ SLICE_X82Y72 LUT1 (Prop_lut1_I0_O) 0.306 4.783 r runnerObject/i__carry__1_i_13/O
+ net (fo=1, routed) 0.000 4.783 runnerObject/p_0_in[9]
+ SLICE_X82Y72 CARRY4 (Prop_carry4_S[0]_O[2])
+ 0.547 5.330 f runnerObject/i__carry__1_i_9/O[2]
+ net (fo=2, routed) 0.821 6.151 runnerObject/pos_object_y_target9[11]
+ SLICE_X84Y71 LUT4 (Prop_lut4_I3_O) 0.302 6.453 r runnerObject/pos_object_y_target2_carry_i_13/O
+ net (fo=2, routed) 0.420 6.872 runnerObject/pos_object_y_target2_carry_i_13_n_0
+ SLICE_X87Y72 LUT6 (Prop_lut6_I0_O) 0.124 6.996 r runnerObject/pos_object_y_target2_carry_i_10/O
+ net (fo=34, routed) 1.081 8.077 runnerObject/pos_object_y_target2_carry_i_10_n_0
+ SLICE_X84Y70 LUT6 (Prop_lut6_I3_O) 0.124 8.201 r runnerObject/pos_object_y_target2_carry_i_9/O
+ net (fo=1, routed) 0.701 8.903 runnerObject/pos_object_y_target2_carry_i_9_n_0
+ SLICE_X85Y70 CARRY4 (Prop_carry4_S[0]_O[3])
+ 0.730 9.633 f runnerObject/pos_object_y_target2_carry/O[3]
+ net (fo=2, routed) 1.215 10.847 runnerObject/pos_object_y_target2[4]
+ SLICE_X84Y73 LUT2 (Prop_lut2_I1_O) 0.306 11.153 r runnerObject/pos_object_y_target1_carry_i_4/O
+ net (fo=1, routed) 0.000 11.153 runnerObject/pos_object_y_target1_carry_i_4_n_0
+ SLICE_X84Y73 CARRY4 (Prop_carry4_S[2]_CO[3])
+ 0.380 11.533 r runnerObject/pos_object_y_target1_carry/CO[3]
+ net (fo=1, routed) 0.000 11.533 runnerObject/pos_object_y_target1_carry_n_0
+ SLICE_X84Y74 CARRY4 (Prop_carry4_CI_CO[3])
+ 0.117 11.650 r runnerObject/pos_object_y_target1_carry__0/CO[3]
+ net (fo=1, routed) 0.009 11.659 runnerObject/pos_object_y_target1_carry__0_n_0
+ SLICE_X84Y75 CARRY4 (Prop_carry4_CI_CO[1])
+ 0.157 11.816 f runnerObject/pos_object_y_target1_carry__1/CO[1]
+ net (fo=11, routed) 0.629 12.445 runnerObject/pos_object_y_target1
+ SLICE_X86Y77 LUT3 (Prop_lut3_I0_O) 0.332 12.777 r runnerObject/pos_object_y_target[8]_i_1/O
+ net (fo=9, routed) 0.697 13.474 runnerObject/pos_object_y_target[8]_i_1_n_0
+ SLICE_X89Y79 FDSE r runnerObject/pos_object_y_target_reg[3]/S
+ ------------------------------------------------------------------- -------------------
+
+ (clock clk_out1_clk_wiz_0_1 rise edge)
+ 40.000 40.000 r
+ E3 0.000 40.000 r clk (IN)
+ net (fo=0) 0.000 40.000 pixelClk/inst/clk_in1
+ E3 IBUF (Prop_ibuf_I_O) 1.411 41.411 r pixelClk/inst/clkin1_ibufg/O
+ net (fo=1, routed) 1.162 42.573 pixelClk/inst/clk_in1_clk_wiz_0
+ MMCME2_ADV_X1Y2 MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKOUT0)
+ -7.324 35.249 r pixelClk/inst/mmcm_adv_inst/CLKOUT0
+ net (fo=1, routed) 1.639 36.888 pixelClk/inst/clk_out1_clk_wiz_0
+ BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.091 36.979 r pixelClk/inst/clkout1_buf/O
+ net (fo=127, routed) 1.601 38.581 runnerObject/clk_out1
+ SLICE_X89Y79 FDSE r runnerObject/pos_object_y_target_reg[3]/C
+ clock pessimism 0.559 39.140
+ clock uncertainty -0.098 39.043
+ SLICE_X89Y79 FDSE (Setup_fdse_C_S) -0.429 38.614 runnerObject/pos_object_y_target_reg[3]
+ -------------------------------------------------------------------
+ required time 38.614
+ arrival time -13.474
+ -------------------------------------------------------------------
+ slack 25.140
+
+Slack (MET) : 25.140ns (required time - arrival time)
+ Source: vgaInterface/counter_f_reg[2]/C
+ (rising edge-triggered cell FDCE clocked by clk_out1_clk_wiz_0 {rise@0.000ns fall@20.000ns period=40.000ns})
+ Destination: runnerObject/pos_object_y_target_reg[4]/S
+ (rising edge-triggered cell FDSE clocked by clk_out1_clk_wiz_0_1 {rise@0.000ns fall@20.000ns period=40.000ns})
+ Path Group: clk_out1_clk_wiz_0_1
+ Path Type: Setup (Max at Slow Process Corner)
+ Requirement: 40.000ns (clk_out1_clk_wiz_0_1 rise@40.000ns - clk_out1_clk_wiz_0 rise@0.000ns)
+ Data Path Delay: 14.294ns (logic 5.777ns (40.414%) route 8.517ns (59.586%))
+ Logic Levels: 17 (CARRY4=9 LUT1=2 LUT2=2 LUT3=1 LUT4=1 LUT6=2)
+ Clock Path Skew: -0.039ns (DCD - SCD + CPR)
+ Destination Clock Delay (DCD): -1.419ns = ( 38.581 - 40.000 )
+ Source Clock Delay (SCD): -0.821ns
+ Clock Pessimism Removal (CPR): 0.559ns
+ Clock Uncertainty: 0.098ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE
+ Total System Jitter (TSJ): 0.071ns
+ Discrete Jitter (DJ): 0.182ns
+ Phase Error (PE): 0.000ns
+ Clock Domain Crossing: Inter clock paths are considered valid unless explicitly excluded by timing constraints such as set_clock_groups or set_false_path.
+
+ Location Delay type Incr(ns) Path(ns) Netlist Resource(s)
+ ------------------------------------------------------------------- -------------------
+ (clock clk_out1_clk_wiz_0 rise edge)
+ 0.000 0.000 r
+ E3 0.000 0.000 r clk (IN)
+ net (fo=0) 0.000 0.000 pixelClk/inst/clk_in1
+ E3 IBUF (Prop_ibuf_I_O) 1.482 1.482 r pixelClk/inst/clkin1_ibufg/O
+ net (fo=1, routed) 1.233 2.715 pixelClk/inst/clk_in1_clk_wiz_0
+ MMCME2_ADV_X1Y2 MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKOUT0)
+ -7.070 -4.355 r pixelClk/inst/mmcm_adv_inst/CLKOUT0
+ net (fo=1, routed) 1.719 -2.636 pixelClk/inst/clk_out1_clk_wiz_0
+ BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.096 -2.540 r pixelClk/inst/clkout1_buf/O
+ net (fo=127, routed) 1.719 -0.821 vgaInterface/clk_out1
+ SLICE_X89Y70 FDCE r vgaInterface/counter_f_reg[2]/C
+ ------------------------------------------------------------------- -------------------
+ SLICE_X89Y70 FDCE (Prop_fdce_C_Q) 0.456 -0.365 f vgaInterface/counter_f_reg[2]/Q
+ net (fo=5, routed) 1.006 0.641 vgaInterface/counter_f_reg[2]
+ SLICE_X88Y67 LUT1 (Prop_lut1_I0_O) 0.124 0.765 r vgaInterface/FCounter_17bit_carry_i_3/O
+ net (fo=1, routed) 0.000 0.765 runnerObject/pos_object_y_target6_carry_0[1]
+ SLICE_X88Y67 CARRY4 (Prop_carry4_S[1]_CO[3])
+ 0.533 1.298 r runnerObject/FCounter_17bit_carry/CO[3]
+ net (fo=1, routed) 0.000 1.298 runnerObject/FCounter_17bit_carry_n_0
+ SLICE_X88Y68 CARRY4 (Prop_carry4_CI_O[2])
+ 0.239 1.537 r runnerObject/FCounter_17bit_carry__0/O[2]
+ net (fo=2, routed) 0.987 2.523 runnerObject/FCounter_17bit[7]
+ SLICE_X88Y71 LUT2 (Prop_lut2_I0_O) 0.301 2.824 r runnerObject/pos_object_y_target6_carry__0_i_1/O
+ net (fo=1, routed) 0.000 2.824 runnerObject/pos_object_y_target6_carry__0_i_1_n_0
+ SLICE_X88Y71 CARRY4 (Prop_carry4_S[3]_CO[3])
+ 0.376 3.200 r runnerObject/pos_object_y_target6_carry__0/CO[3]
+ net (fo=1, routed) 0.000 3.200 runnerObject/pos_object_y_target6_carry__0_n_0
+ SLICE_X88Y72 CARRY4 (Prop_carry4_CI_O[1])
+ 0.323 3.523 f runnerObject/pos_object_y_target6_carry__1/O[1]
+ net (fo=5, routed) 0.953 4.477 runnerObject/pos_object_y_target6[9]
+ SLICE_X82Y72 LUT1 (Prop_lut1_I0_O) 0.306 4.783 r runnerObject/i__carry__1_i_13/O
+ net (fo=1, routed) 0.000 4.783 runnerObject/p_0_in[9]
+ SLICE_X82Y72 CARRY4 (Prop_carry4_S[0]_O[2])
+ 0.547 5.330 f runnerObject/i__carry__1_i_9/O[2]
+ net (fo=2, routed) 0.821 6.151 runnerObject/pos_object_y_target9[11]
+ SLICE_X84Y71 LUT4 (Prop_lut4_I3_O) 0.302 6.453 r runnerObject/pos_object_y_target2_carry_i_13/O
+ net (fo=2, routed) 0.420 6.872 runnerObject/pos_object_y_target2_carry_i_13_n_0
+ SLICE_X87Y72 LUT6 (Prop_lut6_I0_O) 0.124 6.996 r runnerObject/pos_object_y_target2_carry_i_10/O
+ net (fo=34, routed) 1.081 8.077 runnerObject/pos_object_y_target2_carry_i_10_n_0
+ SLICE_X84Y70 LUT6 (Prop_lut6_I3_O) 0.124 8.201 r runnerObject/pos_object_y_target2_carry_i_9/O
+ net (fo=1, routed) 0.701 8.903 runnerObject/pos_object_y_target2_carry_i_9_n_0
+ SLICE_X85Y70 CARRY4 (Prop_carry4_S[0]_O[3])
+ 0.730 9.633 f runnerObject/pos_object_y_target2_carry/O[3]
+ net (fo=2, routed) 1.215 10.847 runnerObject/pos_object_y_target2[4]
+ SLICE_X84Y73 LUT2 (Prop_lut2_I1_O) 0.306 11.153 r runnerObject/pos_object_y_target1_carry_i_4/O
+ net (fo=1, routed) 0.000 11.153 runnerObject/pos_object_y_target1_carry_i_4_n_0
+ SLICE_X84Y73 CARRY4 (Prop_carry4_S[2]_CO[3])
+ 0.380 11.533 r runnerObject/pos_object_y_target1_carry/CO[3]
+ net (fo=1, routed) 0.000 11.533 runnerObject/pos_object_y_target1_carry_n_0
+ SLICE_X84Y74 CARRY4 (Prop_carry4_CI_CO[3])
+ 0.117 11.650 r runnerObject/pos_object_y_target1_carry__0/CO[3]
+ net (fo=1, routed) 0.009 11.659 runnerObject/pos_object_y_target1_carry__0_n_0
+ SLICE_X84Y75 CARRY4 (Prop_carry4_CI_CO[1])
+ 0.157 11.816 f runnerObject/pos_object_y_target1_carry__1/CO[1]
+ net (fo=11, routed) 0.629 12.445 runnerObject/pos_object_y_target1
+ SLICE_X86Y77 LUT3 (Prop_lut3_I0_O) 0.332 12.777 r runnerObject/pos_object_y_target[8]_i_1/O
+ net (fo=9, routed) 0.697 13.474 runnerObject/pos_object_y_target[8]_i_1_n_0
+ SLICE_X89Y79 FDSE r runnerObject/pos_object_y_target_reg[4]/S
+ ------------------------------------------------------------------- -------------------
+
+ (clock clk_out1_clk_wiz_0_1 rise edge)
+ 40.000 40.000 r
+ E3 0.000 40.000 r clk (IN)
+ net (fo=0) 0.000 40.000 pixelClk/inst/clk_in1
+ E3 IBUF (Prop_ibuf_I_O) 1.411 41.411 r pixelClk/inst/clkin1_ibufg/O
+ net (fo=1, routed) 1.162 42.573 pixelClk/inst/clk_in1_clk_wiz_0
+ MMCME2_ADV_X1Y2 MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKOUT0)
+ -7.324 35.249 r pixelClk/inst/mmcm_adv_inst/CLKOUT0
+ net (fo=1, routed) 1.639 36.888 pixelClk/inst/clk_out1_clk_wiz_0
+ BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.091 36.979 r pixelClk/inst/clkout1_buf/O
+ net (fo=127, routed) 1.601 38.581 runnerObject/clk_out1
+ SLICE_X89Y79 FDSE r runnerObject/pos_object_y_target_reg[4]/C
+ clock pessimism 0.559 39.140
+ clock uncertainty -0.098 39.043
+ SLICE_X89Y79 FDSE (Setup_fdse_C_S) -0.429 38.614 runnerObject/pos_object_y_target_reg[4]
+ -------------------------------------------------------------------
+ required time 38.614
+ arrival time -13.474
+ -------------------------------------------------------------------
+ slack 25.140
+
+
+
+
+
+Min Delay Paths
+--------------------------------------------------------------------------------------
+Slack (MET) : 0.063ns (arrival time - required time)
+ Source: vgaInterface/counter_f_reg[3]/C
+ (rising edge-triggered cell FDCE clocked by clk_out1_clk_wiz_0 {rise@0.000ns fall@20.000ns period=40.000ns})
+ Destination: runnerObject/fcount_edge_reg[3]/D
+ (rising edge-triggered cell FDCE clocked by clk_out1_clk_wiz_0_1 {rise@0.000ns fall@20.000ns period=40.000ns})
+ Path Group: clk_out1_clk_wiz_0_1
+ Path Type: Hold (Min at Fast Process Corner)
+ Requirement: 0.000ns (clk_out1_clk_wiz_0_1 rise@0.000ns - clk_out1_clk_wiz_0 rise@0.000ns)
+ Data Path Delay: 0.257ns (logic 0.141ns (54.962%) route 0.116ns (45.038%))
+ Logic Levels: 0
+ Clock Path Skew: 0.013ns (DCD - SCD - CPR)
+ Destination Clock Delay (DCD): -0.805ns
+ Source Clock Delay (SCD): -0.566ns
+ Clock Pessimism Removal (CPR): -0.252ns
+ Clock Uncertainty: 0.098ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE
+ Total System Jitter (TSJ): 0.071ns
+ Discrete Jitter (DJ): 0.182ns
+ Phase Error (PE): 0.000ns
+ Clock Domain Crossing: Inter clock paths are considered valid unless explicitly excluded by timing constraints such as set_clock_groups or set_false_path.
+
+ Location Delay type Incr(ns) Path(ns) Netlist Resource(s)
+ ------------------------------------------------------------------- -------------------
+ (clock clk_out1_clk_wiz_0 rise edge)
+ 0.000 0.000 r
+ E3 0.000 0.000 r clk (IN)
+ net (fo=0) 0.000 0.000 pixelClk/inst/clk_in1
+ E3 IBUF (Prop_ibuf_I_O) 0.250 0.250 r pixelClk/inst/clkin1_ibufg/O
+ net (fo=1, routed) 0.440 0.690 pixelClk/inst/clk_in1_clk_wiz_0
+ MMCME2_ADV_X1Y2 MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKOUT0)
+ -2.379 -1.689 r pixelClk/inst/mmcm_adv_inst/CLKOUT0
+ net (fo=1, routed) 0.499 -1.190 pixelClk/inst/clk_out1_clk_wiz_0
+ BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.026 -1.164 r pixelClk/inst/clkout1_buf/O
+ net (fo=127, routed) 0.598 -0.566 vgaInterface/clk_out1
+ SLICE_X89Y70 FDCE r vgaInterface/counter_f_reg[3]/C
+ ------------------------------------------------------------------- -------------------
+ SLICE_X89Y70 FDCE (Prop_fdce_C_Q) 0.141 -0.425 r vgaInterface/counter_f_reg[3]/Q
+ net (fo=5, routed) 0.116 -0.310 runnerObject/counter_f_reg[3]
+ SLICE_X88Y70 FDCE r runnerObject/fcount_edge_reg[3]/D
+ ------------------------------------------------------------------- -------------------
+
+ (clock clk_out1_clk_wiz_0_1 rise edge)
+ 0.000 0.000 r
+ E3 0.000 0.000 r clk (IN)
+ net (fo=0) 0.000 0.000 pixelClk/inst/clk_in1
+ E3 IBUF (Prop_ibuf_I_O) 0.438 0.438 r pixelClk/inst/clkin1_ibufg/O
+ net (fo=1, routed) 0.480 0.918 pixelClk/inst/clk_in1_clk_wiz_0
+ MMCME2_ADV_X1Y2 MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKOUT0)
+ -3.163 -2.245 r pixelClk/inst/mmcm_adv_inst/CLKOUT0
+ net (fo=1, routed) 0.544 -1.702 pixelClk/inst/clk_out1_clk_wiz_0
+ BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.029 -1.673 r pixelClk/inst/clkout1_buf/O
+ net (fo=127, routed) 0.868 -0.805 runnerObject/clk_out1
+ SLICE_X88Y70 FDCE r runnerObject/fcount_edge_reg[3]/C
+ clock pessimism 0.252 -0.553
+ clock uncertainty 0.098 -0.456
+ SLICE_X88Y70 FDCE (Hold_fdce_C_D) 0.083 -0.373 runnerObject/fcount_edge_reg[3]
+ -------------------------------------------------------------------
+ required time 0.373
+ arrival time -0.310
+ -------------------------------------------------------------------
+ slack 0.063
+
+Slack (MET) : 0.063ns (arrival time - required time)
+ Source: vgaInterface/counter_f_reg[7]/C
+ (rising edge-triggered cell FDCE clocked by clk_out1_clk_wiz_0 {rise@0.000ns fall@20.000ns period=40.000ns})
+ Destination: runnerObject/fcount_edge_reg[7]/D
+ (rising edge-triggered cell FDCE clocked by clk_out1_clk_wiz_0_1 {rise@0.000ns fall@20.000ns period=40.000ns})
+ Path Group: clk_out1_clk_wiz_0_1
+ Path Type: Hold (Min at Fast Process Corner)
+ Requirement: 0.000ns (clk_out1_clk_wiz_0_1 rise@0.000ns - clk_out1_clk_wiz_0 rise@0.000ns)
+ Data Path Delay: 0.257ns (logic 0.141ns (54.948%) route 0.116ns (45.052%))
+ Logic Levels: 0
+ Clock Path Skew: 0.013ns (DCD - SCD - CPR)
+ Destination Clock Delay (DCD): -0.806ns
+ Source Clock Delay (SCD): -0.567ns
+ Clock Pessimism Removal (CPR): -0.252ns
+ Clock Uncertainty: 0.098ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE
+ Total System Jitter (TSJ): 0.071ns
+ Discrete Jitter (DJ): 0.182ns
+ Phase Error (PE): 0.000ns
+ Clock Domain Crossing: Inter clock paths are considered valid unless explicitly excluded by timing constraints such as set_clock_groups or set_false_path.
+
+ Location Delay type Incr(ns) Path(ns) Netlist Resource(s)
+ ------------------------------------------------------------------- -------------------
+ (clock clk_out1_clk_wiz_0 rise edge)
+ 0.000 0.000 r
+ E3 0.000 0.000 r clk (IN)
+ net (fo=0) 0.000 0.000 pixelClk/inst/clk_in1
+ E3 IBUF (Prop_ibuf_I_O) 0.250 0.250 r pixelClk/inst/clkin1_ibufg/O
+ net (fo=1, routed) 0.440 0.690 pixelClk/inst/clk_in1_clk_wiz_0
+ MMCME2_ADV_X1Y2 MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKOUT0)
+ -2.379 -1.689 r pixelClk/inst/mmcm_adv_inst/CLKOUT0
+ net (fo=1, routed) 0.499 -1.190 pixelClk/inst/clk_out1_clk_wiz_0
+ BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.026 -1.164 r pixelClk/inst/clkout1_buf/O
+ net (fo=127, routed) 0.597 -0.567 vgaInterface/clk_out1
+ SLICE_X89Y71 FDCE r vgaInterface/counter_f_reg[7]/C
+ ------------------------------------------------------------------- -------------------
+ SLICE_X89Y71 FDCE (Prop_fdce_C_Q) 0.141 -0.426 r vgaInterface/counter_f_reg[7]/Q
+ net (fo=5, routed) 0.116 -0.311 runnerObject/counter_f_reg[7]
+ SLICE_X88Y71 FDCE r runnerObject/fcount_edge_reg[7]/D
+ ------------------------------------------------------------------- -------------------
+
+ (clock clk_out1_clk_wiz_0_1 rise edge)
+ 0.000 0.000 r
+ E3 0.000 0.000 r clk (IN)
+ net (fo=0) 0.000 0.000 pixelClk/inst/clk_in1
+ E3 IBUF (Prop_ibuf_I_O) 0.438 0.438 r pixelClk/inst/clkin1_ibufg/O
+ net (fo=1, routed) 0.480 0.918 pixelClk/inst/clk_in1_clk_wiz_0
+ MMCME2_ADV_X1Y2 MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKOUT0)
+ -3.163 -2.245 r pixelClk/inst/mmcm_adv_inst/CLKOUT0
+ net (fo=1, routed) 0.544 -1.702 pixelClk/inst/clk_out1_clk_wiz_0
+ BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.029 -1.673 r pixelClk/inst/clkout1_buf/O
+ net (fo=127, routed) 0.867 -0.806 runnerObject/clk_out1
+ SLICE_X88Y71 FDCE r runnerObject/fcount_edge_reg[7]/C
+ clock pessimism 0.252 -0.554
+ clock uncertainty 0.098 -0.457
+ SLICE_X88Y71 FDCE (Hold_fdce_C_D) 0.083 -0.374 runnerObject/fcount_edge_reg[7]
+ -------------------------------------------------------------------
+ required time 0.374
+ arrival time -0.311
+ -------------------------------------------------------------------
+ slack 0.063
+
+Slack (MET) : 0.068ns (arrival time - required time)
+ Source: vgaInterface/counter_f_reg[4]/C
+ (rising edge-triggered cell FDCE clocked by clk_out1_clk_wiz_0 {rise@0.000ns fall@20.000ns period=40.000ns})
+ Destination: runnerObject/fcount_edge_reg[4]/D
+ (rising edge-triggered cell FDCE clocked by clk_out1_clk_wiz_0_1 {rise@0.000ns fall@20.000ns period=40.000ns})
+ Path Group: clk_out1_clk_wiz_0_1
+ Path Type: Hold (Min at Fast Process Corner)
+ Requirement: 0.000ns (clk_out1_clk_wiz_0_1 rise@0.000ns - clk_out1_clk_wiz_0 rise@0.000ns)
+ Data Path Delay: 0.264ns (logic 0.141ns (53.502%) route 0.123ns (46.498%))
+ Logic Levels: 0
+ Clock Path Skew: 0.013ns (DCD - SCD - CPR)
+ Destination Clock Delay (DCD): -0.806ns
+ Source Clock Delay (SCD): -0.567ns
+ Clock Pessimism Removal (CPR): -0.252ns
+ Clock Uncertainty: 0.098ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE
+ Total System Jitter (TSJ): 0.071ns
+ Discrete Jitter (DJ): 0.182ns
+ Phase Error (PE): 0.000ns
+ Clock Domain Crossing: Inter clock paths are considered valid unless explicitly excluded by timing constraints such as set_clock_groups or set_false_path.
+
+ Location Delay type Incr(ns) Path(ns) Netlist Resource(s)
+ ------------------------------------------------------------------- -------------------
+ (clock clk_out1_clk_wiz_0 rise edge)
+ 0.000 0.000 r
+ E3 0.000 0.000 r clk (IN)
+ net (fo=0) 0.000 0.000 pixelClk/inst/clk_in1
+ E3 IBUF (Prop_ibuf_I_O) 0.250 0.250 r pixelClk/inst/clkin1_ibufg/O
+ net (fo=1, routed) 0.440 0.690 pixelClk/inst/clk_in1_clk_wiz_0
+ MMCME2_ADV_X1Y2 MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKOUT0)
+ -2.379 -1.689 r pixelClk/inst/mmcm_adv_inst/CLKOUT0
+ net (fo=1, routed) 0.499 -1.190 pixelClk/inst/clk_out1_clk_wiz_0
+ BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.026 -1.164 r pixelClk/inst/clkout1_buf/O
+ net (fo=127, routed) 0.597 -0.567 vgaInterface/clk_out1
+ SLICE_X89Y71 FDCE r vgaInterface/counter_f_reg[4]/C
+ ------------------------------------------------------------------- -------------------
+ SLICE_X89Y71 FDCE (Prop_fdce_C_Q) 0.141 -0.426 r vgaInterface/counter_f_reg[4]/Q
+ net (fo=5, routed) 0.123 -0.304 runnerObject/counter_f_reg[4]
+ SLICE_X88Y71 FDCE r runnerObject/fcount_edge_reg[4]/D
+ ------------------------------------------------------------------- -------------------
+
+ (clock clk_out1_clk_wiz_0_1 rise edge)
+ 0.000 0.000 r
+ E3 0.000 0.000 r clk (IN)
+ net (fo=0) 0.000 0.000 pixelClk/inst/clk_in1
+ E3 IBUF (Prop_ibuf_I_O) 0.438 0.438 r pixelClk/inst/clkin1_ibufg/O
+ net (fo=1, routed) 0.480 0.918 pixelClk/inst/clk_in1_clk_wiz_0
+ MMCME2_ADV_X1Y2 MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKOUT0)
+ -3.163 -2.245 r pixelClk/inst/mmcm_adv_inst/CLKOUT0
+ net (fo=1, routed) 0.544 -1.702 pixelClk/inst/clk_out1_clk_wiz_0
+ BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.029 -1.673 r pixelClk/inst/clkout1_buf/O
+ net (fo=127, routed) 0.867 -0.806 runnerObject/clk_out1
+ SLICE_X88Y71 FDCE r runnerObject/fcount_edge_reg[4]/C
+ clock pessimism 0.252 -0.554
+ clock uncertainty 0.098 -0.457
+ SLICE_X88Y71 FDCE (Hold_fdce_C_D) 0.085 -0.372 runnerObject/fcount_edge_reg[4]
+ -------------------------------------------------------------------
+ required time 0.372
+ arrival time -0.304
+ -------------------------------------------------------------------
+ slack 0.068
+
+Slack (MET) : 0.082ns (arrival time - required time)
+ Source: runnerObject/pos_object_y_target_reg[4]/C
+ (rising edge-triggered cell FDSE clocked by clk_out1_clk_wiz_0 {rise@0.000ns fall@20.000ns period=40.000ns})
+ Destination: runnerObject/pos_object_y_actual_reg[4]/D
+ (rising edge-triggered cell FDRE clocked by clk_out1_clk_wiz_0_1 {rise@0.000ns fall@20.000ns period=40.000ns})
+ Path Group: clk_out1_clk_wiz_0_1
+ Path Type: Hold (Min at Fast Process Corner)
+ Requirement: 0.000ns (clk_out1_clk_wiz_0_1 rise@0.000ns - clk_out1_clk_wiz_0 rise@0.000ns)
+ Data Path Delay: 0.263ns (logic 0.141ns (53.569%) route 0.122ns (46.431%))
+ Logic Levels: 0
+ Clock Path Skew: 0.014ns (DCD - SCD - CPR)
+ Destination Clock Delay (DCD): -0.805ns
+ Source Clock Delay (SCD): -0.566ns
+ Clock Pessimism Removal (CPR): -0.253ns
+ Clock Uncertainty: 0.098ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE
+ Total System Jitter (TSJ): 0.071ns
+ Discrete Jitter (DJ): 0.182ns
+ Phase Error (PE): 0.000ns
+ Clock Domain Crossing: Inter clock paths are considered valid unless explicitly excluded by timing constraints such as set_clock_groups or set_false_path.
+
+ Location Delay type Incr(ns) Path(ns) Netlist Resource(s)
+ ------------------------------------------------------------------- -------------------
+ (clock clk_out1_clk_wiz_0 rise edge)
+ 0.000 0.000 r
+ E3 0.000 0.000 r clk (IN)
+ net (fo=0) 0.000 0.000 pixelClk/inst/clk_in1
+ E3 IBUF (Prop_ibuf_I_O) 0.250 0.250 r pixelClk/inst/clkin1_ibufg/O
+ net (fo=1, routed) 0.440 0.690 pixelClk/inst/clk_in1_clk_wiz_0
+ MMCME2_ADV_X1Y2 MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKOUT0)
+ -2.379 -1.689 r pixelClk/inst/mmcm_adv_inst/CLKOUT0
+ net (fo=1, routed) 0.499 -1.190 pixelClk/inst/clk_out1_clk_wiz_0
+ BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.026 -1.164 r pixelClk/inst/clkout1_buf/O
+ net (fo=127, routed) 0.598 -0.566 runnerObject/clk_out1
+ SLICE_X89Y79 FDSE r runnerObject/pos_object_y_target_reg[4]/C
+ ------------------------------------------------------------------- -------------------
+ SLICE_X89Y79 FDSE (Prop_fdse_C_Q) 0.141 -0.425 r runnerObject/pos_object_y_target_reg[4]/Q
+ net (fo=4, routed) 0.122 -0.303 runnerObject/pos_object_y_target[4]
+ SLICE_X87Y79 FDRE r runnerObject/pos_object_y_actual_reg[4]/D
+ ------------------------------------------------------------------- -------------------
+
+ (clock clk_out1_clk_wiz_0_1 rise edge)
+ 0.000 0.000 r
+ E3 0.000 0.000 r clk (IN)
+ net (fo=0) 0.000 0.000 pixelClk/inst/clk_in1
+ E3 IBUF (Prop_ibuf_I_O) 0.438 0.438 r pixelClk/inst/clkin1_ibufg/O
+ net (fo=1, routed) 0.480 0.918 pixelClk/inst/clk_in1_clk_wiz_0
+ MMCME2_ADV_X1Y2 MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKOUT0)
+ -3.163 -2.245 r pixelClk/inst/mmcm_adv_inst/CLKOUT0
+ net (fo=1, routed) 0.544 -1.702 pixelClk/inst/clk_out1_clk_wiz_0
+ BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.029 -1.673 r pixelClk/inst/clkout1_buf/O
+ net (fo=127, routed) 0.868 -0.805 runnerObject/clk_out1
+ SLICE_X87Y79 FDRE r runnerObject/pos_object_y_actual_reg[4]/C
+ clock pessimism 0.253 -0.552
+ clock uncertainty 0.098 -0.455
+ SLICE_X87Y79 FDRE (Hold_fdre_C_D) 0.070 -0.385 runnerObject/pos_object_y_actual_reg[4]
+ -------------------------------------------------------------------
+ required time 0.385
+ arrival time -0.303
+ -------------------------------------------------------------------
+ slack 0.082
+
+Slack (MET) : 0.091ns (arrival time - required time)
+ Source: largeObstacle/pos_object_x_target_reg[0]/C
+ (rising edge-triggered cell FDCE clocked by clk_out1_clk_wiz_0 {rise@0.000ns fall@20.000ns period=40.000ns})
+ Destination: largeObstacle/pos_object_x_actual_reg[0]/D
+ (rising edge-triggered cell FDRE clocked by clk_out1_clk_wiz_0_1 {rise@0.000ns fall@20.000ns period=40.000ns})
+ Path Group: clk_out1_clk_wiz_0_1
+ Path Type: Hold (Min at Fast Process Corner)
+ Requirement: 0.000ns (clk_out1_clk_wiz_0_1 rise@0.000ns - clk_out1_clk_wiz_0 rise@0.000ns)
+ Data Path Delay: 0.272ns (logic 0.141ns (51.925%) route 0.131ns (48.075%))
+ Logic Levels: 0
+ Clock Path Skew: 0.013ns (DCD - SCD - CPR)
+ Destination Clock Delay (DCD): -0.805ns
+ Source Clock Delay (SCD): -0.565ns
+ Clock Pessimism Removal (CPR): -0.253ns
+ Clock Uncertainty: 0.098ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE
+ Total System Jitter (TSJ): 0.071ns
+ Discrete Jitter (DJ): 0.182ns
+ Phase Error (PE): 0.000ns
+ Clock Domain Crossing: Inter clock paths are considered valid unless explicitly excluded by timing constraints such as set_clock_groups or set_false_path.
+
+ Location Delay type Incr(ns) Path(ns) Netlist Resource(s)
+ ------------------------------------------------------------------- -------------------
+ (clock clk_out1_clk_wiz_0 rise edge)
+ 0.000 0.000 r
+ E3 0.000 0.000 r clk (IN)
+ net (fo=0) 0.000 0.000 pixelClk/inst/clk_in1
+ E3 IBUF (Prop_ibuf_I_O) 0.250 0.250 r pixelClk/inst/clkin1_ibufg/O
+ net (fo=1, routed) 0.440 0.690 pixelClk/inst/clk_in1_clk_wiz_0
+ MMCME2_ADV_X1Y2 MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKOUT0)
+ -2.379 -1.689 r pixelClk/inst/mmcm_adv_inst/CLKOUT0
+ net (fo=1, routed) 0.499 -1.190 pixelClk/inst/clk_out1_clk_wiz_0
+ BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.026 -1.164 r pixelClk/inst/clkout1_buf/O
+ net (fo=127, routed) 0.599 -0.565 largeObstacle/CLK
+ SLICE_X82Y81 FDCE r largeObstacle/pos_object_x_target_reg[0]/C
+ ------------------------------------------------------------------- -------------------
+ SLICE_X82Y81 FDCE (Prop_fdce_C_Q) 0.141 -0.424 r largeObstacle/pos_object_x_target_reg[0]/Q
+ net (fo=2, routed) 0.131 -0.294 largeObstacle/pos_object_x_target_reg[0]
+ SLICE_X82Y80 FDRE r largeObstacle/pos_object_x_actual_reg[0]/D
+ ------------------------------------------------------------------- -------------------
+
+ (clock clk_out1_clk_wiz_0_1 rise edge)
+ 0.000 0.000 r
+ E3 0.000 0.000 r clk (IN)
+ net (fo=0) 0.000 0.000 pixelClk/inst/clk_in1
+ E3 IBUF (Prop_ibuf_I_O) 0.438 0.438 r pixelClk/inst/clkin1_ibufg/O
+ net (fo=1, routed) 0.480 0.918 pixelClk/inst/clk_in1_clk_wiz_0
+ MMCME2_ADV_X1Y2 MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKOUT0)
+ -3.163 -2.245 r pixelClk/inst/mmcm_adv_inst/CLKOUT0
+ net (fo=1, routed) 0.544 -1.702 pixelClk/inst/clk_out1_clk_wiz_0
+ BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.029 -1.673 r pixelClk/inst/clkout1_buf/O
+ net (fo=127, routed) 0.868 -0.805 largeObstacle/CLK
+ SLICE_X82Y80 FDRE r largeObstacle/pos_object_x_actual_reg[0]/C
+ clock pessimism 0.253 -0.552
+ clock uncertainty 0.098 -0.455
+ SLICE_X82Y80 FDRE (Hold_fdre_C_D) 0.070 -0.385 largeObstacle/pos_object_x_actual_reg[0]
+ -------------------------------------------------------------------
+ required time 0.385
+ arrival time -0.294
+ -------------------------------------------------------------------
+ slack 0.091
+
+Slack (MET) : 0.101ns (arrival time - required time)
+ Source: runnerObject/pos_object_y_target_reg[2]/C
+ (rising edge-triggered cell FDSE clocked by clk_out1_clk_wiz_0 {rise@0.000ns fall@20.000ns period=40.000ns})
+ Destination: runnerObject/pos_object_y_actual_reg[2]/D
+ (rising edge-triggered cell FDRE clocked by clk_out1_clk_wiz_0_1 {rise@0.000ns fall@20.000ns period=40.000ns})
+ Path Group: clk_out1_clk_wiz_0_1
+ Path Type: Hold (Min at Fast Process Corner)
+ Requirement: 0.000ns (clk_out1_clk_wiz_0_1 rise@0.000ns - clk_out1_clk_wiz_0 rise@0.000ns)
+ Data Path Delay: 0.282ns (logic 0.141ns (49.964%) route 0.141ns (50.036%))
+ Logic Levels: 0
+ Clock Path Skew: 0.014ns (DCD - SCD - CPR)
+ Destination Clock Delay (DCD): -0.805ns
+ Source Clock Delay (SCD): -0.566ns
+ Clock Pessimism Removal (CPR): -0.253ns
+ Clock Uncertainty: 0.098ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE
+ Total System Jitter (TSJ): 0.071ns
+ Discrete Jitter (DJ): 0.182ns
+ Phase Error (PE): 0.000ns
+ Clock Domain Crossing: Inter clock paths are considered valid unless explicitly excluded by timing constraints such as set_clock_groups or set_false_path.
+
+ Location Delay type Incr(ns) Path(ns) Netlist Resource(s)
+ ------------------------------------------------------------------- -------------------
+ (clock clk_out1_clk_wiz_0 rise edge)
+ 0.000 0.000 r
+ E3 0.000 0.000 r clk (IN)
+ net (fo=0) 0.000 0.000 pixelClk/inst/clk_in1
+ E3 IBUF (Prop_ibuf_I_O) 0.250 0.250 r pixelClk/inst/clkin1_ibufg/O
+ net (fo=1, routed) 0.440 0.690 pixelClk/inst/clk_in1_clk_wiz_0
+ MMCME2_ADV_X1Y2 MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKOUT0)
+ -2.379 -1.689 r pixelClk/inst/mmcm_adv_inst/CLKOUT0
+ net (fo=1, routed) 0.499 -1.190 pixelClk/inst/clk_out1_clk_wiz_0
+ BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.026 -1.164 r pixelClk/inst/clkout1_buf/O
+ net (fo=127, routed) 0.598 -0.566 runnerObject/clk_out1
+ SLICE_X89Y79 FDSE r runnerObject/pos_object_y_target_reg[2]/C
+ ------------------------------------------------------------------- -------------------
+ SLICE_X89Y79 FDSE (Prop_fdse_C_Q) 0.141 -0.425 r runnerObject/pos_object_y_target_reg[2]/Q
+ net (fo=6, routed) 0.141 -0.284 runnerObject/pos_object_y_target[2]
+ SLICE_X86Y79 FDRE r runnerObject/pos_object_y_actual_reg[2]/D
+ ------------------------------------------------------------------- -------------------
+
+ (clock clk_out1_clk_wiz_0_1 rise edge)
+ 0.000 0.000 r
+ E3 0.000 0.000 r clk (IN)
+ net (fo=0) 0.000 0.000 pixelClk/inst/clk_in1
+ E3 IBUF (Prop_ibuf_I_O) 0.438 0.438 r pixelClk/inst/clkin1_ibufg/O
+ net (fo=1, routed) 0.480 0.918 pixelClk/inst/clk_in1_clk_wiz_0
+ MMCME2_ADV_X1Y2 MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKOUT0)
+ -3.163 -2.245 r pixelClk/inst/mmcm_adv_inst/CLKOUT0
+ net (fo=1, routed) 0.544 -1.702 pixelClk/inst/clk_out1_clk_wiz_0
+ BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.029 -1.673 r pixelClk/inst/clkout1_buf/O
+ net (fo=127, routed) 0.868 -0.805 runnerObject/clk_out1
+ SLICE_X86Y79 FDRE r runnerObject/pos_object_y_actual_reg[2]/C
+ clock pessimism 0.253 -0.552
+ clock uncertainty 0.098 -0.455
+ SLICE_X86Y79 FDRE (Hold_fdre_C_D) 0.070 -0.385 runnerObject/pos_object_y_actual_reg[2]
+ -------------------------------------------------------------------
+ required time 0.385
+ arrival time -0.284
+ -------------------------------------------------------------------
+ slack 0.101
+
+Slack (MET) : 0.104ns (arrival time - required time)
+ Source: runnerObject/pos_object_y_target_reg[0]/C
+ (rising edge-triggered cell FDRE clocked by clk_out1_clk_wiz_0 {rise@0.000ns fall@20.000ns period=40.000ns})
+ Destination: runnerObject/pos_object_y_actual_reg[0]/D
+ (rising edge-triggered cell FDRE clocked by clk_out1_clk_wiz_0_1 {rise@0.000ns fall@20.000ns period=40.000ns})
+ Path Group: clk_out1_clk_wiz_0_1
+ Path Type: Hold (Min at Fast Process Corner)
+ Requirement: 0.000ns (clk_out1_clk_wiz_0_1 rise@0.000ns - clk_out1_clk_wiz_0 rise@0.000ns)
+ Data Path Delay: 0.285ns (logic 0.141ns (49.436%) route 0.144ns (50.564%))
+ Logic Levels: 0
+ Clock Path Skew: 0.014ns (DCD - SCD - CPR)
+ Destination Clock Delay (DCD): -0.805ns
+ Source Clock Delay (SCD): -0.566ns
+ Clock Pessimism Removal (CPR): -0.253ns
+ Clock Uncertainty: 0.098ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE
+ Total System Jitter (TSJ): 0.071ns
+ Discrete Jitter (DJ): 0.182ns
+ Phase Error (PE): 0.000ns
+ Clock Domain Crossing: Inter clock paths are considered valid unless explicitly excluded by timing constraints such as set_clock_groups or set_false_path.
+
+ Location Delay type Incr(ns) Path(ns) Netlist Resource(s)
+ ------------------------------------------------------------------- -------------------
+ (clock clk_out1_clk_wiz_0 rise edge)
+ 0.000 0.000 r
+ E3 0.000 0.000 r clk (IN)
+ net (fo=0) 0.000 0.000 pixelClk/inst/clk_in1
+ E3 IBUF (Prop_ibuf_I_O) 0.250 0.250 r pixelClk/inst/clkin1_ibufg/O
+ net (fo=1, routed) 0.440 0.690 pixelClk/inst/clk_in1_clk_wiz_0
+ MMCME2_ADV_X1Y2 MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKOUT0)
+ -2.379 -1.689 r pixelClk/inst/mmcm_adv_inst/CLKOUT0
+ net (fo=1, routed) 0.499 -1.190 pixelClk/inst/clk_out1_clk_wiz_0
+ BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.026 -1.164 r pixelClk/inst/clkout1_buf/O
+ net (fo=127, routed) 0.598 -0.566 runnerObject/clk_out1
+ SLICE_X89Y79 FDRE r runnerObject/pos_object_y_target_reg[0]/C
+ ------------------------------------------------------------------- -------------------
+ SLICE_X89Y79 FDRE (Prop_fdre_C_Q) 0.141 -0.425 r runnerObject/pos_object_y_target_reg[0]/Q
+ net (fo=8, routed) 0.144 -0.281 runnerObject/pos_object_y_target[0]
+ SLICE_X87Y79 FDRE r runnerObject/pos_object_y_actual_reg[0]/D
+ ------------------------------------------------------------------- -------------------
+
+ (clock clk_out1_clk_wiz_0_1 rise edge)
+ 0.000 0.000 r
+ E3 0.000 0.000 r clk (IN)
+ net (fo=0) 0.000 0.000 pixelClk/inst/clk_in1
+ E3 IBUF (Prop_ibuf_I_O) 0.438 0.438 r pixelClk/inst/clkin1_ibufg/O
+ net (fo=1, routed) 0.480 0.918 pixelClk/inst/clk_in1_clk_wiz_0
+ MMCME2_ADV_X1Y2 MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKOUT0)
+ -3.163 -2.245 r pixelClk/inst/mmcm_adv_inst/CLKOUT0
+ net (fo=1, routed) 0.544 -1.702 pixelClk/inst/clk_out1_clk_wiz_0
+ BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.029 -1.673 r pixelClk/inst/clkout1_buf/O
+ net (fo=127, routed) 0.868 -0.805 runnerObject/clk_out1
+ SLICE_X87Y79 FDRE r runnerObject/pos_object_y_actual_reg[0]/C
+ clock pessimism 0.253 -0.552
+ clock uncertainty 0.098 -0.455
+ SLICE_X87Y79 FDRE (Hold_fdre_C_D) 0.070 -0.385 runnerObject/pos_object_y_actual_reg[0]
+ -------------------------------------------------------------------
+ required time 0.385
+ arrival time -0.281
+ -------------------------------------------------------------------
+ slack 0.104
+
+Slack (MET) : 0.107ns (arrival time - required time)
+ Source: vgaInterface/counter_f_reg[1]/C
+ (rising edge-triggered cell FDCE clocked by clk_out1_clk_wiz_0 {rise@0.000ns fall@20.000ns period=40.000ns})
+ Destination: runnerObject/fcount_edge_reg[1]/D
+ (rising edge-triggered cell FDCE clocked by clk_out1_clk_wiz_0_1 {rise@0.000ns fall@20.000ns period=40.000ns})
+ Path Group: clk_out1_clk_wiz_0_1
+ Path Type: Hold (Min at Fast Process Corner)
+ Requirement: 0.000ns (clk_out1_clk_wiz_0_1 rise@0.000ns - clk_out1_clk_wiz_0 rise@0.000ns)
+ Data Path Delay: 0.303ns (logic 0.141ns (46.482%) route 0.162ns (53.518%))
+ Logic Levels: 0
+ Clock Path Skew: 0.013ns (DCD - SCD - CPR)
+ Destination Clock Delay (DCD): -0.805ns
+ Source Clock Delay (SCD): -0.566ns
+ Clock Pessimism Removal (CPR): -0.252ns
+ Clock Uncertainty: 0.098ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE
+ Total System Jitter (TSJ): 0.071ns
+ Discrete Jitter (DJ): 0.182ns
+ Phase Error (PE): 0.000ns
+ Clock Domain Crossing: Inter clock paths are considered valid unless explicitly excluded by timing constraints such as set_clock_groups or set_false_path.
+
+ Location Delay type Incr(ns) Path(ns) Netlist Resource(s)
+ ------------------------------------------------------------------- -------------------
+ (clock clk_out1_clk_wiz_0 rise edge)
+ 0.000 0.000 r
+ E3 0.000 0.000 r clk (IN)
+ net (fo=0) 0.000 0.000 pixelClk/inst/clk_in1
+ E3 IBUF (Prop_ibuf_I_O) 0.250 0.250 r pixelClk/inst/clkin1_ibufg/O
+ net (fo=1, routed) 0.440 0.690 pixelClk/inst/clk_in1_clk_wiz_0
+ MMCME2_ADV_X1Y2 MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKOUT0)
+ -2.379 -1.689 r pixelClk/inst/mmcm_adv_inst/CLKOUT0
+ net (fo=1, routed) 0.499 -1.190 pixelClk/inst/clk_out1_clk_wiz_0
+ BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.026 -1.164 r pixelClk/inst/clkout1_buf/O
+ net (fo=127, routed) 0.598 -0.566 vgaInterface/clk_out1
+ SLICE_X89Y70 FDCE r vgaInterface/counter_f_reg[1]/C
+ ------------------------------------------------------------------- -------------------
+ SLICE_X89Y70 FDCE (Prop_fdce_C_Q) 0.141 -0.425 r vgaInterface/counter_f_reg[1]/Q
+ net (fo=5, routed) 0.162 -0.263 runnerObject/counter_f_reg[1]
+ SLICE_X88Y70 FDCE r runnerObject/fcount_edge_reg[1]/D
+ ------------------------------------------------------------------- -------------------
+
+ (clock clk_out1_clk_wiz_0_1 rise edge)
+ 0.000 0.000 r
+ E3 0.000 0.000 r clk (IN)
+ net (fo=0) 0.000 0.000 pixelClk/inst/clk_in1
+ E3 IBUF (Prop_ibuf_I_O) 0.438 0.438 r pixelClk/inst/clkin1_ibufg/O
+ net (fo=1, routed) 0.480 0.918 pixelClk/inst/clk_in1_clk_wiz_0
+ MMCME2_ADV_X1Y2 MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKOUT0)
+ -3.163 -2.245 r pixelClk/inst/mmcm_adv_inst/CLKOUT0
+ net (fo=1, routed) 0.544 -1.702 pixelClk/inst/clk_out1_clk_wiz_0
+ BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.029 -1.673 r pixelClk/inst/clkout1_buf/O
+ net (fo=127, routed) 0.868 -0.805 runnerObject/clk_out1
+ SLICE_X88Y70 FDCE r runnerObject/fcount_edge_reg[1]/C
+ clock pessimism 0.252 -0.553
+ clock uncertainty 0.098 -0.456
+ SLICE_X88Y70 FDCE (Hold_fdce_C_D) 0.086 -0.370 runnerObject/fcount_edge_reg[1]
+ -------------------------------------------------------------------
+ required time 0.370
+ arrival time -0.263
+ -------------------------------------------------------------------
+ slack 0.107
+
+Slack (MET) : 0.107ns (arrival time - required time)
+ Source: vgaInterface/counter_f_reg[5]/C
+ (rising edge-triggered cell FDCE clocked by clk_out1_clk_wiz_0 {rise@0.000ns fall@20.000ns period=40.000ns})
+ Destination: runnerObject/fcount_edge_reg[5]/D
+ (rising edge-triggered cell FDCE clocked by clk_out1_clk_wiz_0_1 {rise@0.000ns fall@20.000ns period=40.000ns})
+ Path Group: clk_out1_clk_wiz_0_1
+ Path Type: Hold (Min at Fast Process Corner)
+ Requirement: 0.000ns (clk_out1_clk_wiz_0_1 rise@0.000ns - clk_out1_clk_wiz_0 rise@0.000ns)
+ Data Path Delay: 0.303ns (logic 0.141ns (46.472%) route 0.162ns (53.528%))
+ Logic Levels: 0
+ Clock Path Skew: 0.013ns (DCD - SCD - CPR)
+ Destination Clock Delay (DCD): -0.806ns
+ Source Clock Delay (SCD): -0.567ns
+ Clock Pessimism Removal (CPR): -0.252ns
+ Clock Uncertainty: 0.098ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE
+ Total System Jitter (TSJ): 0.071ns
+ Discrete Jitter (DJ): 0.182ns
+ Phase Error (PE): 0.000ns
+ Clock Domain Crossing: Inter clock paths are considered valid unless explicitly excluded by timing constraints such as set_clock_groups or set_false_path.
+
+ Location Delay type Incr(ns) Path(ns) Netlist Resource(s)
+ ------------------------------------------------------------------- -------------------
+ (clock clk_out1_clk_wiz_0 rise edge)
+ 0.000 0.000 r
+ E3 0.000 0.000 r clk (IN)
+ net (fo=0) 0.000 0.000 pixelClk/inst/clk_in1
+ E3 IBUF (Prop_ibuf_I_O) 0.250 0.250 r pixelClk/inst/clkin1_ibufg/O
+ net (fo=1, routed) 0.440 0.690 pixelClk/inst/clk_in1_clk_wiz_0
+ MMCME2_ADV_X1Y2 MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKOUT0)
+ -2.379 -1.689 r pixelClk/inst/mmcm_adv_inst/CLKOUT0
+ net (fo=1, routed) 0.499 -1.190 pixelClk/inst/clk_out1_clk_wiz_0
+ BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.026 -1.164 r pixelClk/inst/clkout1_buf/O
+ net (fo=127, routed) 0.597 -0.567 vgaInterface/clk_out1
+ SLICE_X89Y71 FDCE r vgaInterface/counter_f_reg[5]/C
+ ------------------------------------------------------------------- -------------------
+ SLICE_X89Y71 FDCE (Prop_fdce_C_Q) 0.141 -0.426 r vgaInterface/counter_f_reg[5]/Q
+ net (fo=5, routed) 0.162 -0.264 runnerObject/counter_f_reg[5]
+ SLICE_X88Y71 FDCE r runnerObject/fcount_edge_reg[5]/D
+ ------------------------------------------------------------------- -------------------
+
+ (clock clk_out1_clk_wiz_0_1 rise edge)
+ 0.000 0.000 r
+ E3 0.000 0.000 r clk (IN)
+ net (fo=0) 0.000 0.000 pixelClk/inst/clk_in1
+ E3 IBUF (Prop_ibuf_I_O) 0.438 0.438 r pixelClk/inst/clkin1_ibufg/O
+ net (fo=1, routed) 0.480 0.918 pixelClk/inst/clk_in1_clk_wiz_0
+ MMCME2_ADV_X1Y2 MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKOUT0)
+ -3.163 -2.245 r pixelClk/inst/mmcm_adv_inst/CLKOUT0
+ net (fo=1, routed) 0.544 -1.702 pixelClk/inst/clk_out1_clk_wiz_0
+ BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.029 -1.673 r pixelClk/inst/clkout1_buf/O
+ net (fo=127, routed) 0.867 -0.806 runnerObject/clk_out1
+ SLICE_X88Y71 FDCE r runnerObject/fcount_edge_reg[5]/C
+ clock pessimism 0.252 -0.554
+ clock uncertainty 0.098 -0.457
+ SLICE_X88Y71 FDCE (Hold_fdce_C_D) 0.086 -0.371 runnerObject/fcount_edge_reg[5]
+ -------------------------------------------------------------------
+ required time 0.371
+ arrival time -0.264
+ -------------------------------------------------------------------
+ slack 0.107
+
+Slack (MET) : 0.117ns (arrival time - required time)
+ Source: largeObstacle/pos_object_x_target_reg[4]/C
+ (rising edge-triggered cell FDCE clocked by clk_out1_clk_wiz_0 {rise@0.000ns fall@20.000ns period=40.000ns})
+ Destination: largeObstacle/pos_object_x_actual_reg[4]/D
+ (rising edge-triggered cell FDRE clocked by clk_out1_clk_wiz_0_1 {rise@0.000ns fall@20.000ns period=40.000ns})
+ Path Group: clk_out1_clk_wiz_0_1
+ Path Type: Hold (Min at Fast Process Corner)
+ Requirement: 0.000ns (clk_out1_clk_wiz_0_1 rise@0.000ns - clk_out1_clk_wiz_0 rise@0.000ns)
+ Data Path Delay: 0.288ns (logic 0.164ns (56.904%) route 0.124ns (43.096%))
+ Logic Levels: 0
+ Clock Path Skew: 0.015ns (DCD - SCD - CPR)
+ Destination Clock Delay (DCD): -0.810ns
+ Source Clock Delay (SCD): -0.572ns
+ Clock Pessimism Removal (CPR): -0.253ns
+ Clock Uncertainty: 0.098ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE
+ Total System Jitter (TSJ): 0.071ns
+ Discrete Jitter (DJ): 0.182ns
+ Phase Error (PE): 0.000ns
+ Clock Domain Crossing: Inter clock paths are considered valid unless explicitly excluded by timing constraints such as set_clock_groups or set_false_path.
+
+ Location Delay type Incr(ns) Path(ns) Netlist Resource(s)
+ ------------------------------------------------------------------- -------------------
+ (clock clk_out1_clk_wiz_0 rise edge)
+ 0.000 0.000 r
+ E3 0.000 0.000 r clk (IN)
+ net (fo=0) 0.000 0.000 pixelClk/inst/clk_in1
+ E3 IBUF (Prop_ibuf_I_O) 0.250 0.250 r pixelClk/inst/clkin1_ibufg/O
+ net (fo=1, routed) 0.440 0.690 pixelClk/inst/clk_in1_clk_wiz_0
+ MMCME2_ADV_X1Y2 MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKOUT0)
+ -2.379 -1.689 r pixelClk/inst/mmcm_adv_inst/CLKOUT0
+ net (fo=1, routed) 0.499 -1.190 pixelClk/inst/clk_out1_clk_wiz_0
+ BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.026 -1.164 r pixelClk/inst/clkout1_buf/O
+ net (fo=127, routed) 0.592 -0.572 largeObstacle/CLK
+ SLICE_X80Y78 FDCE r largeObstacle/pos_object_x_target_reg[4]/C
+ ------------------------------------------------------------------- -------------------
+ SLICE_X80Y78 FDCE (Prop_fdce_C_Q) 0.164 -0.408 r largeObstacle/pos_object_x_target_reg[4]/Q
+ net (fo=5, routed) 0.124 -0.284 largeObstacle/pos_object_x_target_reg[4]
+ SLICE_X80Y79 FDRE r largeObstacle/pos_object_x_actual_reg[4]/D
+ ------------------------------------------------------------------- -------------------
+
+ (clock clk_out1_clk_wiz_0_1 rise edge)
+ 0.000 0.000 r
+ E3 0.000 0.000 r clk (IN)
+ net (fo=0) 0.000 0.000 pixelClk/inst/clk_in1
+ E3 IBUF (Prop_ibuf_I_O) 0.438 0.438 r pixelClk/inst/clkin1_ibufg/O
+ net (fo=1, routed) 0.480 0.918 pixelClk/inst/clk_in1_clk_wiz_0
+ MMCME2_ADV_X1Y2 MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKOUT0)
+ -3.163 -2.245 r pixelClk/inst/mmcm_adv_inst/CLKOUT0
+ net (fo=1, routed) 0.544 -1.702 pixelClk/inst/clk_out1_clk_wiz_0
+ BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.029 -1.673 r pixelClk/inst/clkout1_buf/O
+ net (fo=127, routed) 0.863 -0.810 largeObstacle/CLK
+ SLICE_X80Y79 FDRE r largeObstacle/pos_object_x_actual_reg[4]/C
+ clock pessimism 0.253 -0.557
+ clock uncertainty 0.098 -0.460
+ SLICE_X80Y79 FDRE (Hold_fdre_C_D) 0.059 -0.401 largeObstacle/pos_object_x_actual_reg[4]
+ -------------------------------------------------------------------
+ required time 0.401
+ arrival time -0.284
+ -------------------------------------------------------------------
+ slack 0.117
+
+
+
+
+
+--------------------------------------------------------------------------------------
+Path Group: (none)
+From Clock: clk_out1_clk_wiz_0
+ To Clock:
+
+Max Delay 30 Endpoints
+Min Delay 30 Endpoints
+--------------------------------------------------------------------------------------
+
+
+Max Delay Paths
+--------------------------------------------------------------------------------------
+Slack: inf
+ Source: runnerObject/pos_object_y_actual_reg[1]/C
+ (rising edge-triggered cell FDRE clocked by clk_out1_clk_wiz_0 {rise@0.000ns fall@20.000ns period=40.000ns})
+ Destination: vgaBlue[3]
+ (output port)
+ Path Group: (none)
+ Path Type: Max at Slow Process Corner
+ Data Path Delay: 13.564ns (logic 5.677ns (41.849%) route 7.888ns (58.151%))
+ Logic Levels: 7 (CARRY4=2 LUT4=2 LUT5=1 LUT6=1 OBUF=1)
+ Clock Uncertainty: 0.199ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE
+ Total System Jitter (TSJ): 0.050ns
+ Discrete Jitter (DJ): 0.182ns
+ Phase Error (PE): 0.104ns
+
+ Location Delay type Incr(ns) Path(ns) Netlist Resource(s)
+ ------------------------------------------------------------------- -------------------
+ (clock clk_out1_clk_wiz_0 rise edge)
+ 0.000 0.000 r
+ E3 0.000 0.000 r clk (IN)
+ net (fo=0) 0.000 0.000 pixelClk/inst/clk_in1
+ E3 IBUF (Prop_ibuf_I_O) 1.482 1.482 r pixelClk/inst/clkin1_ibufg/O
+ net (fo=1, routed) 1.233 2.715 pixelClk/inst/clk_in1_clk_wiz_0
+ MMCME2_ADV_X1Y2 MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKOUT0)
+ -7.070 -4.355 r pixelClk/inst/mmcm_adv_inst/CLKOUT0
+ net (fo=1, routed) 1.719 -2.636 pixelClk/inst/clk_out1_clk_wiz_0
+ BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.096 -2.540 r pixelClk/inst/clkout1_buf/O
+ net (fo=127, routed) 1.719 -0.821 runnerObject/clk_out1
+ SLICE_X87Y79 FDRE r runnerObject/pos_object_y_actual_reg[1]/C
+ ------------------------------------------------------------------- -------------------
+ SLICE_X87Y79 FDRE (Prop_fdre_C_Q) 0.456 -0.365 r runnerObject/pos_object_y_actual_reg[1]/Q
+ net (fo=11, routed) 1.064 0.699 runnerObject/pos_object_y_actual_reg[8]_0[1]
+ SLICE_X86Y78 LUT4 (Prop_lut4_I1_O) 0.124 0.823 r runnerObject/color_runner3_carry_i_9/O
+ net (fo=4, routed) 0.844 1.667 runnerObject/color_runner3_carry_i_9_n_0
+ SLICE_X88Y79 LUT6 (Prop_lut6_I4_O) 0.124 1.791 r runnerObject/color_runner3_carry_i_1/O
+ net (fo=1, routed) 0.663 2.454 runnerObject/color_runner3_carry_i_1_n_0
+ SLICE_X86Y79 CARRY4 (Prop_carry4_DI[3]_CO[3])
+ 0.385 2.839 r runnerObject/color_runner3_carry/CO[3]
+ net (fo=1, routed) 0.000 2.839 runnerObject/color_runner3_carry_n_0
+ SLICE_X86Y80 CARRY4 (Prop_carry4_CI_CO[1])
+ 0.157 2.996 r runnerObject/color_runner3_carry__0/CO[1]
+ net (fo=7, routed) 0.997 3.992 runnerObject/color_runner3
+ SLICE_X87Y84 LUT4 (Prop_lut4_I3_O) 0.357 4.349 r runnerObject/vgaBlue_OBUF[3]_inst_i_4/O
+ net (fo=5, routed) 0.616 4.965 vgaInterface/vgaGreen[1]_0
+ SLICE_X87Y83 LUT5 (Prop_lut5_I4_O) 0.320 5.285 r vgaInterface/vgaBlue_OBUF[3]_inst_i_1/O
+ net (fo=1, routed) 3.705 8.990 vgaBlue_OBUF[3]
+ D8 OBUF (Prop_obuf_I_O) 3.754 12.744 r vgaBlue_OBUF[3]_inst/O
+ net (fo=0) 0.000 12.744 vgaBlue[3]
+ D8 r vgaBlue[3] (OUT)
+ ------------------------------------------------------------------- -------------------
+
+Slack: inf
+ Source: runnerObject/pos_object_y_actual_reg[1]/C
+ (rising edge-triggered cell FDRE clocked by clk_out1_clk_wiz_0 {rise@0.000ns fall@20.000ns period=40.000ns})
+ Destination: vgaGreen[1]
+ (output port)
+ Path Group: (none)
+ Path Type: Max at Slow Process Corner
+ Data Path Delay: 13.545ns (logic 5.474ns (40.411%) route 8.071ns (59.589%))
+ Logic Levels: 7 (CARRY4=2 LUT4=3 LUT6=1 OBUF=1)
+ Clock Uncertainty: 0.199ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE
+ Total System Jitter (TSJ): 0.050ns
+ Discrete Jitter (DJ): 0.182ns
+ Phase Error (PE): 0.104ns
+
+ Location Delay type Incr(ns) Path(ns) Netlist Resource(s)
+ ------------------------------------------------------------------- -------------------
+ (clock clk_out1_clk_wiz_0 rise edge)
+ 0.000 0.000 r
+ E3 0.000 0.000 r clk (IN)
+ net (fo=0) 0.000 0.000 pixelClk/inst/clk_in1
+ E3 IBUF (Prop_ibuf_I_O) 1.482 1.482 r pixelClk/inst/clkin1_ibufg/O
+ net (fo=1, routed) 1.233 2.715 pixelClk/inst/clk_in1_clk_wiz_0
+ MMCME2_ADV_X1Y2 MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKOUT0)
+ -7.070 -4.355 r pixelClk/inst/mmcm_adv_inst/CLKOUT0
+ net (fo=1, routed) 1.719 -2.636 pixelClk/inst/clk_out1_clk_wiz_0
+ BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.096 -2.540 r pixelClk/inst/clkout1_buf/O
+ net (fo=127, routed) 1.719 -0.821 runnerObject/clk_out1
+ SLICE_X87Y79 FDRE r runnerObject/pos_object_y_actual_reg[1]/C
+ ------------------------------------------------------------------- -------------------
+ SLICE_X87Y79 FDRE (Prop_fdre_C_Q) 0.456 -0.365 r runnerObject/pos_object_y_actual_reg[1]/Q
+ net (fo=11, routed) 1.064 0.699 runnerObject/pos_object_y_actual_reg[8]_0[1]
+ SLICE_X86Y78 LUT4 (Prop_lut4_I1_O) 0.124 0.823 r runnerObject/color_runner3_carry_i_9/O
+ net (fo=4, routed) 0.844 1.667 runnerObject/color_runner3_carry_i_9_n_0
+ SLICE_X88Y79 LUT6 (Prop_lut6_I4_O) 0.124 1.791 r runnerObject/color_runner3_carry_i_1/O
+ net (fo=1, routed) 0.663 2.454 runnerObject/color_runner3_carry_i_1_n_0
+ SLICE_X86Y79 CARRY4 (Prop_carry4_DI[3]_CO[3])
+ 0.385 2.839 r runnerObject/color_runner3_carry/CO[3]
+ net (fo=1, routed) 0.000 2.839 runnerObject/color_runner3_carry_n_0
+ SLICE_X86Y80 CARRY4 (Prop_carry4_CI_CO[1])
+ 0.157 2.996 r runnerObject/color_runner3_carry__0/CO[1]
+ net (fo=7, routed) 0.997 3.992 runnerObject/color_runner3
+ SLICE_X87Y84 LUT4 (Prop_lut4_I3_O) 0.357 4.349 r runnerObject/vgaBlue_OBUF[3]_inst_i_4/O
+ net (fo=5, routed) 0.810 5.159 vgaInterface/vgaGreen[1]_0
+ SLICE_X87Y83 LUT4 (Prop_lut4_I1_O) 0.326 5.485 r vgaInterface/vgaGreen_OBUF[1]_inst_i_1/O
+ net (fo=1, routed) 3.695 9.180 vgaGreen_OBUF[1]
+ A5 OBUF (Prop_obuf_I_O) 3.545 12.724 r vgaGreen_OBUF[1]_inst/O
+ net (fo=0) 0.000 12.724 vgaGreen[1]
+ A5 r vgaGreen[1] (OUT)
+ ------------------------------------------------------------------- -------------------
+
+Slack: inf
+ Source: runnerObject/pos_object_y_actual_reg[1]/C
+ (rising edge-triggered cell FDRE clocked by clk_out1_clk_wiz_0 {rise@0.000ns fall@20.000ns period=40.000ns})
+ Destination: vgaGreen[2]
+ (output port)
+ Path Group: (none)
+ Path Type: Max at Slow Process Corner
+ Data Path Delay: 13.522ns (logic 5.678ns (41.995%) route 7.843ns (58.005%))
+ Logic Levels: 7 (CARRY4=2 LUT4=2 LUT5=1 LUT6=1 OBUF=1)
+ Clock Uncertainty: 0.199ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE
+ Total System Jitter (TSJ): 0.050ns
+ Discrete Jitter (DJ): 0.182ns
+ Phase Error (PE): 0.104ns
+
+ Location Delay type Incr(ns) Path(ns) Netlist Resource(s)
+ ------------------------------------------------------------------- -------------------
+ (clock clk_out1_clk_wiz_0 rise edge)
+ 0.000 0.000 r
+ E3 0.000 0.000 r clk (IN)
+ net (fo=0) 0.000 0.000 pixelClk/inst/clk_in1
+ E3 IBUF (Prop_ibuf_I_O) 1.482 1.482 r pixelClk/inst/clkin1_ibufg/O
+ net (fo=1, routed) 1.233 2.715 pixelClk/inst/clk_in1_clk_wiz_0
+ MMCME2_ADV_X1Y2 MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKOUT0)
+ -7.070 -4.355 r pixelClk/inst/mmcm_adv_inst/CLKOUT0
+ net (fo=1, routed) 1.719 -2.636 pixelClk/inst/clk_out1_clk_wiz_0
+ BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.096 -2.540 r pixelClk/inst/clkout1_buf/O
+ net (fo=127, routed) 1.719 -0.821 runnerObject/clk_out1
+ SLICE_X87Y79 FDRE r runnerObject/pos_object_y_actual_reg[1]/C
+ ------------------------------------------------------------------- -------------------
+ SLICE_X87Y79 FDRE (Prop_fdre_C_Q) 0.456 -0.365 r runnerObject/pos_object_y_actual_reg[1]/Q
+ net (fo=11, routed) 1.064 0.699 runnerObject/pos_object_y_actual_reg[8]_0[1]
+ SLICE_X86Y78 LUT4 (Prop_lut4_I1_O) 0.124 0.823 r runnerObject/color_runner3_carry_i_9/O
+ net (fo=4, routed) 0.844 1.667 runnerObject/color_runner3_carry_i_9_n_0
+ SLICE_X88Y79 LUT6 (Prop_lut6_I4_O) 0.124 1.791 r runnerObject/color_runner3_carry_i_1/O
+ net (fo=1, routed) 0.663 2.454 runnerObject/color_runner3_carry_i_1_n_0
+ SLICE_X86Y79 CARRY4 (Prop_carry4_DI[3]_CO[3])
+ 0.385 2.839 r runnerObject/color_runner3_carry/CO[3]
+ net (fo=1, routed) 0.000 2.839 runnerObject/color_runner3_carry_n_0
+ SLICE_X86Y80 CARRY4 (Prop_carry4_CI_CO[1])
+ 0.157 2.996 f runnerObject/color_runner3_carry__0/CO[1]
+ net (fo=7, routed) 0.997 3.992 runnerObject/color_runner3
+ SLICE_X87Y84 LUT4 (Prop_lut4_I3_O) 0.357 4.349 f runnerObject/vgaBlue_OBUF[3]_inst_i_4/O
+ net (fo=5, routed) 0.620 4.969 vgaInterface/vgaGreen[1]_0
+ SLICE_X87Y83 LUT5 (Prop_lut5_I2_O) 0.321 5.290 r vgaInterface/vgaGreen_OBUF[2]_inst_i_1/O
+ net (fo=1, routed) 3.657 8.947 vgaGreen_OBUF[2]
+ B6 OBUF (Prop_obuf_I_O) 3.754 12.701 r vgaGreen_OBUF[2]_inst/O
+ net (fo=0) 0.000 12.701 vgaGreen[2]
+ B6 r vgaGreen[2] (OUT)
+ ------------------------------------------------------------------- -------------------
+
+Slack: inf
+ Source: runnerObject/pos_object_y_actual_reg[1]/C
+ (rising edge-triggered cell FDRE clocked by clk_out1_clk_wiz_0 {rise@0.000ns fall@20.000ns period=40.000ns})
+ Destination: vgaBlue[1]
+ (output port)
+ Path Group: (none)
+ Path Type: Max at Slow Process Corner
+ Data Path Delay: 13.363ns (logic 5.480ns (41.011%) route 7.883ns (58.989%))
+ Logic Levels: 7 (CARRY4=2 LUT4=2 LUT5=1 LUT6=1 OBUF=1)
+ Clock Uncertainty: 0.199ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE
+ Total System Jitter (TSJ): 0.050ns
+ Discrete Jitter (DJ): 0.182ns
+ Phase Error (PE): 0.104ns
+
+ Location Delay type Incr(ns) Path(ns) Netlist Resource(s)
+ ------------------------------------------------------------------- -------------------
+ (clock clk_out1_clk_wiz_0 rise edge)
+ 0.000 0.000 r
+ E3 0.000 0.000 r clk (IN)
+ net (fo=0) 0.000 0.000 pixelClk/inst/clk_in1
+ E3 IBUF (Prop_ibuf_I_O) 1.482 1.482 r pixelClk/inst/clkin1_ibufg/O
+ net (fo=1, routed) 1.233 2.715 pixelClk/inst/clk_in1_clk_wiz_0
+ MMCME2_ADV_X1Y2 MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKOUT0)
+ -7.070 -4.355 r pixelClk/inst/mmcm_adv_inst/CLKOUT0
+ net (fo=1, routed) 1.719 -2.636 pixelClk/inst/clk_out1_clk_wiz_0
+ BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.096 -2.540 r pixelClk/inst/clkout1_buf/O
+ net (fo=127, routed) 1.719 -0.821 runnerObject/clk_out1
+ SLICE_X87Y79 FDRE r runnerObject/pos_object_y_actual_reg[1]/C
+ ------------------------------------------------------------------- -------------------
+ SLICE_X87Y79 FDRE (Prop_fdre_C_Q) 0.456 -0.365 r runnerObject/pos_object_y_actual_reg[1]/Q
+ net (fo=11, routed) 1.064 0.699 runnerObject/pos_object_y_actual_reg[8]_0[1]
+ SLICE_X86Y78 LUT4 (Prop_lut4_I1_O) 0.124 0.823 r runnerObject/color_runner3_carry_i_9/O
+ net (fo=4, routed) 0.844 1.667 runnerObject/color_runner3_carry_i_9_n_0
+ SLICE_X88Y79 LUT6 (Prop_lut6_I4_O) 0.124 1.791 r runnerObject/color_runner3_carry_i_1/O
+ net (fo=1, routed) 0.663 2.454 runnerObject/color_runner3_carry_i_1_n_0
+ SLICE_X86Y79 CARRY4 (Prop_carry4_DI[3]_CO[3])
+ 0.385 2.839 r runnerObject/color_runner3_carry/CO[3]
+ net (fo=1, routed) 0.000 2.839 runnerObject/color_runner3_carry_n_0
+ SLICE_X86Y80 CARRY4 (Prop_carry4_CI_CO[1])
+ 0.157 2.996 r runnerObject/color_runner3_carry__0/CO[1]
+ net (fo=7, routed) 0.997 3.992 runnerObject/color_runner3
+ SLICE_X87Y84 LUT4 (Prop_lut4_I3_O) 0.357 4.349 r runnerObject/vgaBlue_OBUF[3]_inst_i_4/O
+ net (fo=5, routed) 0.616 4.965 vgaInterface/vgaGreen[1]_0
+ SLICE_X87Y83 LUT5 (Prop_lut5_I2_O) 0.326 5.291 r vgaInterface/vgaBlue_OBUF[1]_inst_i_1/O
+ net (fo=1, routed) 3.700 8.991 vgaBlue_OBUF[1]
+ C7 OBUF (Prop_obuf_I_O) 3.551 12.542 r vgaBlue_OBUF[1]_inst/O
+ net (fo=0) 0.000 12.542 vgaBlue[1]
+ C7 r vgaBlue[1] (OUT)
+ ------------------------------------------------------------------- -------------------
+
+Slack: inf
+ Source: runnerObject/pos_object_y_actual_reg[1]/C
+ (rising edge-triggered cell FDRE clocked by clk_out1_clk_wiz_0 {rise@0.000ns fall@20.000ns period=40.000ns})
+ Destination: vgaBlue[2]
+ (output port)
+ Path Group: (none)
+ Path Type: Max at Slow Process Corner
+ Data Path Delay: 13.104ns (logic 5.452ns (41.609%) route 7.651ns (58.391%))
+ Logic Levels: 7 (CARRY4=2 LUT4=3 LUT6=1 OBUF=1)
+ Clock Uncertainty: 0.199ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE
+ Total System Jitter (TSJ): 0.050ns
+ Discrete Jitter (DJ): 0.182ns
+ Phase Error (PE): 0.104ns
+
+ Location Delay type Incr(ns) Path(ns) Netlist Resource(s)
+ ------------------------------------------------------------------- -------------------
+ (clock clk_out1_clk_wiz_0 rise edge)
+ 0.000 0.000 r
+ E3 0.000 0.000 r clk (IN)
+ net (fo=0) 0.000 0.000 pixelClk/inst/clk_in1
+ E3 IBUF (Prop_ibuf_I_O) 1.482 1.482 r pixelClk/inst/clkin1_ibufg/O
+ net (fo=1, routed) 1.233 2.715 pixelClk/inst/clk_in1_clk_wiz_0
+ MMCME2_ADV_X1Y2 MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKOUT0)
+ -7.070 -4.355 r pixelClk/inst/mmcm_adv_inst/CLKOUT0
+ net (fo=1, routed) 1.719 -2.636 pixelClk/inst/clk_out1_clk_wiz_0
+ BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.096 -2.540 r pixelClk/inst/clkout1_buf/O
+ net (fo=127, routed) 1.719 -0.821 runnerObject/clk_out1
+ SLICE_X87Y79 FDRE r runnerObject/pos_object_y_actual_reg[1]/C
+ ------------------------------------------------------------------- -------------------
+ SLICE_X87Y79 FDRE (Prop_fdre_C_Q) 0.456 -0.365 r runnerObject/pos_object_y_actual_reg[1]/Q
+ net (fo=11, routed) 1.064 0.699 runnerObject/pos_object_y_actual_reg[8]_0[1]
+ SLICE_X86Y78 LUT4 (Prop_lut4_I1_O) 0.124 0.823 r runnerObject/color_runner3_carry_i_9/O
+ net (fo=4, routed) 0.844 1.667 runnerObject/color_runner3_carry_i_9_n_0
+ SLICE_X88Y79 LUT6 (Prop_lut6_I4_O) 0.124 1.791 r runnerObject/color_runner3_carry_i_1/O
+ net (fo=1, routed) 0.663 2.454 runnerObject/color_runner3_carry_i_1_n_0
+ SLICE_X86Y79 CARRY4 (Prop_carry4_DI[3]_CO[3])
+ 0.385 2.839 r runnerObject/color_runner3_carry/CO[3]
+ net (fo=1, routed) 0.000 2.839 runnerObject/color_runner3_carry_n_0
+ SLICE_X86Y80 CARRY4 (Prop_carry4_CI_CO[1])
+ 0.157 2.996 r runnerObject/color_runner3_carry__0/CO[1]
+ net (fo=7, routed) 0.997 3.992 runnerObject/color_runner3
+ SLICE_X87Y84 LUT4 (Prop_lut4_I3_O) 0.357 4.349 r runnerObject/vgaBlue_OBUF[3]_inst_i_4/O
+ net (fo=5, routed) 0.620 4.969 vgaInterface/vgaGreen[1]_0
+ SLICE_X87Y83 LUT4 (Prop_lut4_I3_O) 0.326 5.295 r vgaInterface/vgaBlue_OBUF[2]_inst_i_1/O
+ net (fo=1, routed) 3.465 8.760 vgaBlue_OBUF[2]
+ D7 OBUF (Prop_obuf_I_O) 3.523 12.283 r vgaBlue_OBUF[2]_inst/O
+ net (fo=0) 0.000 12.283 vgaBlue[2]
+ D7 r vgaBlue[2] (OUT)
+ ------------------------------------------------------------------- -------------------
+
+Slack: inf
+ Source: largeObstacle/pos_object_x_actual_reg[1]/C
+ (rising edge-triggered cell FDRE clocked by clk_out1_clk_wiz_0 {rise@0.000ns fall@20.000ns period=40.000ns})
+ Destination: vgaGreen[3]
+ (output port)
+ Path Group: (none)
+ Path Type: Max at Slow Process Corner
+ Data Path Delay: 12.861ns (logic 5.316ns (41.338%) route 7.544ns (58.662%))
+ Logic Levels: 7 (CARRY4=2 LUT4=1 LUT5=1 LUT6=2 OBUF=1)
+ Clock Uncertainty: 0.199ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE
+ Total System Jitter (TSJ): 0.050ns
+ Discrete Jitter (DJ): 0.182ns
+ Phase Error (PE): 0.104ns
+
+ Location Delay type Incr(ns) Path(ns) Netlist Resource(s)
+ ------------------------------------------------------------------- -------------------
+ (clock clk_out1_clk_wiz_0 rise edge)
+ 0.000 0.000 r
+ E3 0.000 0.000 r clk (IN)
+ net (fo=0) 0.000 0.000 pixelClk/inst/clk_in1
+ E3 IBUF (Prop_ibuf_I_O) 1.482 1.482 r pixelClk/inst/clkin1_ibufg/O
+ net (fo=1, routed) 1.233 2.715 pixelClk/inst/clk_in1_clk_wiz_0
+ MMCME2_ADV_X1Y2 MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKOUT0)
+ -7.070 -4.355 r pixelClk/inst/mmcm_adv_inst/CLKOUT0
+ net (fo=1, routed) 1.719 -2.636 pixelClk/inst/clk_out1_clk_wiz_0
+ BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.096 -2.540 r pixelClk/inst/clkout1_buf/O
+ net (fo=127, routed) 1.710 -0.830 largeObstacle/CLK
+ SLICE_X81Y78 FDRE r largeObstacle/pos_object_x_actual_reg[1]/C
+ ------------------------------------------------------------------- -------------------
+ SLICE_X81Y78 FDRE (Prop_fdre_C_Q) 0.456 -0.374 f largeObstacle/pos_object_x_actual_reg[1]/Q
+ net (fo=8, routed) 1.456 1.082 largeObstacle/pos_object_x_actual_reg[9]_0[1]
+ SLICE_X80Y79 LUT6 (Prop_lut6_I3_O) 0.124 1.206 r largeObstacle/_carry__0_i_5__0/O
+ net (fo=5, routed) 0.897 2.103 largeObstacle/_carry__0_i_5__0_n_0
+ SLICE_X81Y79 LUT4 (Prop_lut4_I1_O) 0.124 2.227 r largeObstacle/_carry__0_i_1__0/O
+ net (fo=1, routed) 0.000 2.227 largeObstacle/_carry__0_i_1__0_n_0
+ SLICE_X81Y79 CARRY4 (Prop_carry4_S[3]_CO[3])
+ 0.401 2.628 r largeObstacle/_carry__0/CO[3]
+ net (fo=1, routed) 0.000 2.628 largeObstacle/_carry__0_n_0
+ SLICE_X81Y80 CARRY4 (Prop_carry4_CI_CO[2])
+ 0.228 2.856 r largeObstacle/_carry__1/CO[2]
+ net (fo=1, routed) 0.501 3.357 largeObstacle/_carry__1_n_1
+ SLICE_X83Y80 LUT5 (Prop_lut5_I1_O) 0.313 3.670 f largeObstacle/vgaRed_OBUF[3]_inst_i_2/O
+ net (fo=9, routed) 0.996 4.666 runnerObject/collision_cnt_reg[15]_4
+ SLICE_X87Y84 LUT6 (Prop_lut6_I4_O) 0.124 4.790 r runnerObject/vgaGreen_OBUF[3]_inst_i_1/O
+ net (fo=1, routed) 3.695 8.485 vgaGreen_OBUF[3]
+ A6 OBUF (Prop_obuf_I_O) 3.546 12.031 r vgaGreen_OBUF[3]_inst/O
+ net (fo=0) 0.000 12.031 vgaGreen[3]
+ A6 r vgaGreen[3] (OUT)
+ ------------------------------------------------------------------- -------------------
+
+Slack: inf
+ Source: largeObstacle/pos_object_x_actual_reg[1]/C
+ (rising edge-triggered cell FDRE clocked by clk_out1_clk_wiz_0 {rise@0.000ns fall@20.000ns period=40.000ns})
+ Destination: vgaRed[3]
+ (output port)
+ Path Group: (none)
+ Path Type: Max at Slow Process Corner
+ Data Path Delay: 12.647ns (logic 5.322ns (42.078%) route 7.325ns (57.922%))
+ Logic Levels: 7 (CARRY4=2 LUT4=1 LUT5=1 LUT6=2 OBUF=1)
+ Clock Uncertainty: 0.199ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE
+ Total System Jitter (TSJ): 0.050ns
+ Discrete Jitter (DJ): 0.182ns
+ Phase Error (PE): 0.104ns
+
+ Location Delay type Incr(ns) Path(ns) Netlist Resource(s)
+ ------------------------------------------------------------------- -------------------
+ (clock clk_out1_clk_wiz_0 rise edge)
+ 0.000 0.000 r
+ E3 0.000 0.000 r clk (IN)
+ net (fo=0) 0.000 0.000 pixelClk/inst/clk_in1
+ E3 IBUF (Prop_ibuf_I_O) 1.482 1.482 r pixelClk/inst/clkin1_ibufg/O
+ net (fo=1, routed) 1.233 2.715 pixelClk/inst/clk_in1_clk_wiz_0
+ MMCME2_ADV_X1Y2 MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKOUT0)
+ -7.070 -4.355 r pixelClk/inst/mmcm_adv_inst/CLKOUT0
+ net (fo=1, routed) 1.719 -2.636 pixelClk/inst/clk_out1_clk_wiz_0
+ BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.096 -2.540 r pixelClk/inst/clkout1_buf/O
+ net (fo=127, routed) 1.710 -0.830 largeObstacle/CLK
+ SLICE_X81Y78 FDRE r largeObstacle/pos_object_x_actual_reg[1]/C
+ ------------------------------------------------------------------- -------------------
+ SLICE_X81Y78 FDRE (Prop_fdre_C_Q) 0.456 -0.374 f largeObstacle/pos_object_x_actual_reg[1]/Q
+ net (fo=8, routed) 1.456 1.082 largeObstacle/pos_object_x_actual_reg[9]_0[1]
+ SLICE_X80Y79 LUT6 (Prop_lut6_I3_O) 0.124 1.206 r largeObstacle/_carry__0_i_5__0/O
+ net (fo=5, routed) 0.897 2.103 largeObstacle/_carry__0_i_5__0_n_0
+ SLICE_X81Y79 LUT4 (Prop_lut4_I1_O) 0.124 2.227 r largeObstacle/_carry__0_i_1__0/O
+ net (fo=1, routed) 0.000 2.227 largeObstacle/_carry__0_i_1__0_n_0
+ SLICE_X81Y79 CARRY4 (Prop_carry4_S[3]_CO[3])
+ 0.401 2.628 r largeObstacle/_carry__0/CO[3]
+ net (fo=1, routed) 0.000 2.628 largeObstacle/_carry__0_n_0
+ SLICE_X81Y80 CARRY4 (Prop_carry4_CI_CO[2])
+ 0.228 2.856 f largeObstacle/_carry__1/CO[2]
+ net (fo=1, routed) 0.501 3.357 largeObstacle/_carry__1_n_1
+ SLICE_X83Y80 LUT5 (Prop_lut5_I1_O) 0.313 3.670 r largeObstacle/vgaRed_OBUF[3]_inst_i_2/O
+ net (fo=9, routed) 1.010 4.680 runnerObject/collision_cnt_reg[15]_4
+ SLICE_X86Y84 LUT6 (Prop_lut6_I4_O) 0.124 4.804 r runnerObject/vgaRed_OBUF[3]_inst_i_1/O
+ net (fo=1, routed) 3.462 8.266 vgaRed_OBUF[3]
+ A4 OBUF (Prop_obuf_I_O) 3.552 11.817 r vgaRed_OBUF[3]_inst/O
+ net (fo=0) 0.000 11.817 vgaRed[3]
+ A4 r vgaRed[3] (OUT)
+ ------------------------------------------------------------------- -------------------
+
+Slack: inf
+ Source: vgaInterface/counter_v_reg[7]/C
+ (rising edge-triggered cell FDCE clocked by clk_out1_clk_wiz_0 {rise@0.000ns fall@20.000ns period=40.000ns})
+ Destination: vgaRed[0]
+ (output port)
+ Path Group: (none)
+ Path Type: Max at Slow Process Corner
+ Data Path Delay: 12.551ns (logic 5.059ns (40.306%) route 7.492ns (59.694%))
+ Logic Levels: 6 (LUT4=1 LUT6=4 OBUF=1)
+ Clock Uncertainty: 0.199ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE
+ Total System Jitter (TSJ): 0.050ns
+ Discrete Jitter (DJ): 0.182ns
+ Phase Error (PE): 0.104ns
+
+ Location Delay type Incr(ns) Path(ns) Netlist Resource(s)
+ ------------------------------------------------------------------- -------------------
+ (clock clk_out1_clk_wiz_0 rise edge)
+ 0.000 0.000 r
+ E3 0.000 0.000 r clk (IN)
+ net (fo=0) 0.000 0.000 pixelClk/inst/clk_in1
+ E3 IBUF (Prop_ibuf_I_O) 1.482 1.482 r pixelClk/inst/clkin1_ibufg/O
+ net (fo=1, routed) 1.233 2.715 pixelClk/inst/clk_in1_clk_wiz_0
+ MMCME2_ADV_X1Y2 MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKOUT0)
+ -7.070 -4.355 r pixelClk/inst/mmcm_adv_inst/CLKOUT0
+ net (fo=1, routed) 1.719 -2.636 pixelClk/inst/clk_out1_clk_wiz_0
+ BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.096 -2.540 r pixelClk/inst/clkout1_buf/O
+ net (fo=127, routed) 1.715 -0.825 vgaInterface/clk_out1
+ SLICE_X88Y77 FDCE r vgaInterface/counter_v_reg[7]/C
+ ------------------------------------------------------------------- -------------------
+ SLICE_X88Y77 FDCE (Prop_fdce_C_Q) 0.478 -0.347 f vgaInterface/counter_v_reg[7]/Q
+ net (fo=17, routed) 1.176 0.829 vgaInterface/counter_v_reg[9]_0[7]
+ SLICE_X83Y79 LUT4 (Prop_lut4_I1_O) 0.329 1.158 r vgaInterface/vgaBlue_OBUF[0]_inst_i_5/O
+ net (fo=1, routed) 0.433 1.592 vgaInterface/vgaBlue_OBUF[0]_inst_i_5_n_0
+ SLICE_X83Y79 LUT6 (Prop_lut6_I3_O) 0.326 1.918 r vgaInterface/vgaBlue_OBUF[0]_inst_i_2/O
+ net (fo=1, routed) 0.573 2.491 vgaInterface/vgaBlue_OBUF[0]_inst_i_2_n_0
+ SLICE_X83Y80 LUT6 (Prop_lut6_I0_O) 0.124 2.615 r vgaInterface/vgaBlue_OBUF[0]_inst_i_1/O
+ net (fo=6, routed) 0.721 3.335 vgaInterface/vgaBlue_OBUF[0]
+ SLICE_X83Y81 LUT6 (Prop_lut6_I0_O) 0.124 3.459 r vgaInterface/vgaRed_OBUF[3]_inst_i_3/O
+ net (fo=7, routed) 1.156 4.615 runnerObject/vgaGreen[0]
+ SLICE_X87Y84 LUT6 (Prop_lut6_I5_O) 0.124 4.739 r runnerObject/vgaRed_OBUF[0]_inst_i_1/O
+ net (fo=1, routed) 3.433 8.172 vgaRed_OBUF[0]
+ A3 OBUF (Prop_obuf_I_O) 3.554 11.726 r vgaRed_OBUF[0]_inst/O
+ net (fo=0) 0.000 11.726 vgaRed[0]
+ A3 r vgaRed[0] (OUT)
+ ------------------------------------------------------------------- -------------------
+
+Slack: inf
+ Source: vgaInterface/counter_v_reg[7]/C
+ (rising edge-triggered cell FDCE clocked by clk_out1_clk_wiz_0 {rise@0.000ns fall@20.000ns period=40.000ns})
+ Destination: vgaRed[1]
+ (output port)
+ Path Group: (none)
+ Path Type: Max at Slow Process Corner
+ Data Path Delay: 12.423ns (logic 5.256ns (42.310%) route 7.167ns (57.690%))
+ Logic Levels: 6 (LUT4=1 LUT5=1 LUT6=3 OBUF=1)
+ Clock Uncertainty: 0.199ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE
+ Total System Jitter (TSJ): 0.050ns
+ Discrete Jitter (DJ): 0.182ns
+ Phase Error (PE): 0.104ns
+
+ Location Delay type Incr(ns) Path(ns) Netlist Resource(s)
+ ------------------------------------------------------------------- -------------------
+ (clock clk_out1_clk_wiz_0 rise edge)
+ 0.000 0.000 r
+ E3 0.000 0.000 r clk (IN)
+ net (fo=0) 0.000 0.000 pixelClk/inst/clk_in1
+ E3 IBUF (Prop_ibuf_I_O) 1.482 1.482 r pixelClk/inst/clkin1_ibufg/O
+ net (fo=1, routed) 1.233 2.715 pixelClk/inst/clk_in1_clk_wiz_0
+ MMCME2_ADV_X1Y2 MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKOUT0)
+ -7.070 -4.355 r pixelClk/inst/mmcm_adv_inst/CLKOUT0
+ net (fo=1, routed) 1.719 -2.636 pixelClk/inst/clk_out1_clk_wiz_0
+ BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.096 -2.540 r pixelClk/inst/clkout1_buf/O
+ net (fo=127, routed) 1.715 -0.825 vgaInterface/clk_out1
+ SLICE_X88Y77 FDCE r vgaInterface/counter_v_reg[7]/C
+ ------------------------------------------------------------------- -------------------
+ SLICE_X88Y77 FDCE (Prop_fdce_C_Q) 0.478 -0.347 f vgaInterface/counter_v_reg[7]/Q
+ net (fo=17, routed) 1.176 0.829 vgaInterface/counter_v_reg[9]_0[7]
+ SLICE_X83Y79 LUT4 (Prop_lut4_I1_O) 0.329 1.158 r vgaInterface/vgaBlue_OBUF[0]_inst_i_5/O
+ net (fo=1, routed) 0.433 1.592 vgaInterface/vgaBlue_OBUF[0]_inst_i_5_n_0
+ SLICE_X83Y79 LUT6 (Prop_lut6_I3_O) 0.326 1.918 r vgaInterface/vgaBlue_OBUF[0]_inst_i_2/O
+ net (fo=1, routed) 0.573 2.491 vgaInterface/vgaBlue_OBUF[0]_inst_i_2_n_0
+ SLICE_X83Y80 LUT6 (Prop_lut6_I0_O) 0.124 2.615 r vgaInterface/vgaBlue_OBUF[0]_inst_i_1/O
+ net (fo=6, routed) 0.721 3.335 vgaInterface/vgaBlue_OBUF[0]
+ SLICE_X83Y81 LUT6 (Prop_lut6_I0_O) 0.124 3.459 r vgaInterface/vgaRed_OBUF[3]_inst_i_3/O
+ net (fo=7, routed) 0.750 4.209 runnerObject/vgaGreen[0]
+ SLICE_X87Y84 LUT5 (Prop_lut5_I4_O) 0.119 4.328 r runnerObject/vgaRed_OBUF[1]_inst_i_1/O
+ net (fo=1, routed) 3.514 7.842 vgaRed_OBUF[1]
+ B4 OBUF (Prop_obuf_I_O) 3.756 11.599 r vgaRed_OBUF[1]_inst/O
+ net (fo=0) 0.000 11.599 vgaRed[1]
+ B4 r vgaRed[1] (OUT)
+ ------------------------------------------------------------------- -------------------
+
+Slack: inf
+ Source: vgaInterface/counter_v_reg[7]/C
+ (rising edge-triggered cell FDCE clocked by clk_out1_clk_wiz_0 {rise@0.000ns fall@20.000ns period=40.000ns})
+ Destination: vgaGreen[0]
+ (output port)
+ Path Group: (none)
+ Path Type: Max at Slow Process Corner
+ Data Path Delay: 12.404ns (logic 5.043ns (40.659%) route 7.360ns (59.341%))
+ Logic Levels: 6 (LUT4=1 LUT5=1 LUT6=3 OBUF=1)
+ Clock Uncertainty: 0.199ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE
+ Total System Jitter (TSJ): 0.050ns
+ Discrete Jitter (DJ): 0.182ns
+ Phase Error (PE): 0.104ns
+
+ Location Delay type Incr(ns) Path(ns) Netlist Resource(s)
+ ------------------------------------------------------------------- -------------------
+ (clock clk_out1_clk_wiz_0 rise edge)
+ 0.000 0.000 r
+ E3 0.000 0.000 r clk (IN)
+ net (fo=0) 0.000 0.000 pixelClk/inst/clk_in1
+ E3 IBUF (Prop_ibuf_I_O) 1.482 1.482 r pixelClk/inst/clkin1_ibufg/O
+ net (fo=1, routed) 1.233 2.715 pixelClk/inst/clk_in1_clk_wiz_0
+ MMCME2_ADV_X1Y2 MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKOUT0)
+ -7.070 -4.355 r pixelClk/inst/mmcm_adv_inst/CLKOUT0
+ net (fo=1, routed) 1.719 -2.636 pixelClk/inst/clk_out1_clk_wiz_0
+ BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.096 -2.540 r pixelClk/inst/clkout1_buf/O
+ net (fo=127, routed) 1.715 -0.825 vgaInterface/clk_out1
+ SLICE_X88Y77 FDCE r vgaInterface/counter_v_reg[7]/C
+ ------------------------------------------------------------------- -------------------
+ SLICE_X88Y77 FDCE (Prop_fdce_C_Q) 0.478 -0.347 f vgaInterface/counter_v_reg[7]/Q
+ net (fo=17, routed) 1.176 0.829 vgaInterface/counter_v_reg[9]_0[7]
+ SLICE_X83Y79 LUT4 (Prop_lut4_I1_O) 0.329 1.158 r vgaInterface/vgaBlue_OBUF[0]_inst_i_5/O
+ net (fo=1, routed) 0.433 1.592 vgaInterface/vgaBlue_OBUF[0]_inst_i_5_n_0
+ SLICE_X83Y79 LUT6 (Prop_lut6_I3_O) 0.326 1.918 r vgaInterface/vgaBlue_OBUF[0]_inst_i_2/O
+ net (fo=1, routed) 0.573 2.491 vgaInterface/vgaBlue_OBUF[0]_inst_i_2_n_0
+ SLICE_X83Y80 LUT6 (Prop_lut6_I0_O) 0.124 2.615 r vgaInterface/vgaBlue_OBUF[0]_inst_i_1/O
+ net (fo=6, routed) 0.721 3.335 vgaInterface/vgaBlue_OBUF[0]
+ SLICE_X83Y81 LUT6 (Prop_lut6_I0_O) 0.124 3.459 r vgaInterface/vgaRed_OBUF[3]_inst_i_3/O
+ net (fo=7, routed) 0.750 4.209 runnerObject/vgaGreen[0]
+ SLICE_X87Y84 LUT5 (Prop_lut5_I0_O) 0.124 4.333 r runnerObject/vgaGreen_OBUF[0]_inst_i_1/O
+ net (fo=1, routed) 3.708 8.041 vgaGreen_OBUF[0]
+ C6 OBUF (Prop_obuf_I_O) 3.538 11.579 r vgaGreen_OBUF[0]_inst/O
+ net (fo=0) 0.000 11.579 vgaGreen[0]
+ C6 r vgaGreen[0] (OUT)
+ ------------------------------------------------------------------- -------------------
+
+
+
+
+
+Min Delay Paths
+--------------------------------------------------------------------------------------
+Slack: inf
+ Source: collisionDetection/collision_cnt_reg[12]/C
+ (rising edge-triggered cell FDCE clocked by clk_out1_clk_wiz_0 {rise@0.000ns fall@20.000ns period=40.000ns})
+ Destination: led[12]
+ (output port)
+ Path Group: (none)
+ Path Type: Min at Fast Process Corner
+ Data Path Delay: 1.741ns (logic 1.374ns (78.953%) route 0.366ns (21.047%))
+ Logic Levels: 1 (OBUF=1)
+ Clock Uncertainty: 0.199ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE
+ Total System Jitter (TSJ): 0.050ns
+ Discrete Jitter (DJ): 0.182ns
+ Phase Error (PE): 0.104ns
+
+ Location Delay type Incr(ns) Path(ns) Netlist Resource(s)
+ ------------------------------------------------------------------- -------------------
+ (clock clk_out1_clk_wiz_0 rise edge)
+ 0.000 0.000 r
+ E3 0.000 0.000 r clk (IN)
+ net (fo=0) 0.000 0.000 pixelClk/inst/clk_in1
+ E3 IBUF (Prop_ibuf_I_O) 0.250 0.250 r pixelClk/inst/clkin1_ibufg/O
+ net (fo=1, routed) 0.440 0.690 pixelClk/inst/clk_in1_clk_wiz_0
+ MMCME2_ADV_X1Y2 MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKOUT0)
+ -2.379 -1.689 r pixelClk/inst/mmcm_adv_inst/CLKOUT0
+ net (fo=1, routed) 0.499 -1.190 pixelClk/inst/clk_out1_clk_wiz_0
+ BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.026 -1.164 r pixelClk/inst/clkout1_buf/O
+ net (fo=127, routed) 0.599 -0.565 collisionDetection/CLK
+ SLICE_X89Y69 FDCE r collisionDetection/collision_cnt_reg[12]/C
+ ------------------------------------------------------------------- -------------------
+ SLICE_X89Y69 FDCE (Prop_fdce_C_Q) 0.141 -0.424 r collisionDetection/collision_cnt_reg[12]/Q
+ net (fo=3, routed) 0.366 -0.058 led_OBUF[12]
+ P5 OBUF (Prop_obuf_I_O) 1.233 1.175 r led_OBUF[12]_inst/O
+ net (fo=0) 0.000 1.175 led[12]
+ P5 r led[12] (OUT)
+ ------------------------------------------------------------------- -------------------
+
+Slack: inf
+ Source: collisionDetection/collision_cnt_reg[11]/C
+ (rising edge-triggered cell FDCE clocked by clk_out1_clk_wiz_0 {rise@0.000ns fall@20.000ns period=40.000ns})
+ Destination: led[11]
+ (output port)
+ Path Group: (none)
+ Path Type: Min at Fast Process Corner
+ Data Path Delay: 1.753ns (logic 1.395ns (79.584%) route 0.358ns (20.416%))
+ Logic Levels: 1 (OBUF=1)
+ Clock Uncertainty: 0.199ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE
+ Total System Jitter (TSJ): 0.050ns
+ Discrete Jitter (DJ): 0.182ns
+ Phase Error (PE): 0.104ns
+
+ Location Delay type Incr(ns) Path(ns) Netlist Resource(s)
+ ------------------------------------------------------------------- -------------------
+ (clock clk_out1_clk_wiz_0 rise edge)
+ 0.000 0.000 r
+ E3 0.000 0.000 r clk (IN)
+ net (fo=0) 0.000 0.000 pixelClk/inst/clk_in1
+ E3 IBUF (Prop_ibuf_I_O) 0.250 0.250 r pixelClk/inst/clkin1_ibufg/O
+ net (fo=1, routed) 0.440 0.690 pixelClk/inst/clk_in1_clk_wiz_0
+ MMCME2_ADV_X1Y2 MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKOUT0)
+ -2.379 -1.689 r pixelClk/inst/mmcm_adv_inst/CLKOUT0
+ net (fo=1, routed) 0.499 -1.190 pixelClk/inst/clk_out1_clk_wiz_0
+ BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.026 -1.164 r pixelClk/inst/clkout1_buf/O
+ net (fo=127, routed) 0.601 -0.563 collisionDetection/CLK
+ SLICE_X88Y67 FDCE r collisionDetection/collision_cnt_reg[11]/C
+ ------------------------------------------------------------------- -------------------
+ SLICE_X88Y67 FDCE (Prop_fdce_C_Q) 0.164 -0.399 r collisionDetection/collision_cnt_reg[11]/Q
+ net (fo=3, routed) 0.358 -0.041 led_OBUF[11]
+ R1 OBUF (Prop_obuf_I_O) 1.231 1.190 r led_OBUF[11]_inst/O
+ net (fo=0) 0.000 1.190 led[11]
+ R1 r led[11] (OUT)
+ ------------------------------------------------------------------- -------------------
+
+Slack: inf
+ Source: collisionDetection/collision_cnt_reg[15]/C
+ (rising edge-triggered cell FDCE clocked by clk_out1_clk_wiz_0 {rise@0.000ns fall@20.000ns period=40.000ns})
+ Destination: led[15]
+ (output port)
+ Path Group: (none)
+ Path Type: Min at Fast Process Corner
+ Data Path Delay: 1.757ns (logic 1.398ns (79.568%) route 0.359ns (20.432%))
+ Logic Levels: 1 (OBUF=1)
+ Clock Uncertainty: 0.199ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE
+ Total System Jitter (TSJ): 0.050ns
+ Discrete Jitter (DJ): 0.182ns
+ Phase Error (PE): 0.104ns
+
+ Location Delay type Incr(ns) Path(ns) Netlist Resource(s)
+ ------------------------------------------------------------------- -------------------
+ (clock clk_out1_clk_wiz_0 rise edge)
+ 0.000 0.000 r
+ E3 0.000 0.000 r clk (IN)
+ net (fo=0) 0.000 0.000 pixelClk/inst/clk_in1
+ E3 IBUF (Prop_ibuf_I_O) 0.250 0.250 r pixelClk/inst/clkin1_ibufg/O
+ net (fo=1, routed) 0.440 0.690 pixelClk/inst/clk_in1_clk_wiz_0
+ MMCME2_ADV_X1Y2 MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKOUT0)
+ -2.379 -1.689 r pixelClk/inst/mmcm_adv_inst/CLKOUT0
+ net (fo=1, routed) 0.499 -1.190 pixelClk/inst/clk_out1_clk_wiz_0
+ BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.026 -1.164 r pixelClk/inst/clkout1_buf/O
+ net (fo=127, routed) 0.599 -0.565 collisionDetection/CLK
+ SLICE_X88Y69 FDCE r collisionDetection/collision_cnt_reg[15]/C
+ ------------------------------------------------------------------- -------------------
+ SLICE_X88Y69 FDCE (Prop_fdce_C_Q) 0.164 -0.401 r collisionDetection/collision_cnt_reg[15]/Q
+ net (fo=3, routed) 0.359 -0.042 led_OBUF[15]
+ P2 OBUF (Prop_obuf_I_O) 1.234 1.192 r led_OBUF[15]_inst/O
+ net (fo=0) 0.000 1.192 led[15]
+ P2 r led[15] (OUT)
+ ------------------------------------------------------------------- -------------------
+
+Slack: inf
+ Source: collisionDetection/collision_cnt_reg[14]/C
+ (rising edge-triggered cell FDCE clocked by clk_out1_clk_wiz_0 {rise@0.000ns fall@20.000ns period=40.000ns})
+ Destination: led[14]
+ (output port)
+ Path Group: (none)
+ Path Type: Min at Fast Process Corner
+ Data Path Delay: 1.770ns (logic 1.412ns (79.757%) route 0.358ns (20.243%))
+ Logic Levels: 1 (OBUF=1)
+ Clock Uncertainty: 0.199ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE
+ Total System Jitter (TSJ): 0.050ns
+ Discrete Jitter (DJ): 0.182ns
+ Phase Error (PE): 0.104ns
+
+ Location Delay type Incr(ns) Path(ns) Netlist Resource(s)
+ ------------------------------------------------------------------- -------------------
+ (clock clk_out1_clk_wiz_0 rise edge)
+ 0.000 0.000 r
+ E3 0.000 0.000 r clk (IN)
+ net (fo=0) 0.000 0.000 pixelClk/inst/clk_in1
+ E3 IBUF (Prop_ibuf_I_O) 0.250 0.250 r pixelClk/inst/clkin1_ibufg/O
+ net (fo=1, routed) 0.440 0.690 pixelClk/inst/clk_in1_clk_wiz_0
+ MMCME2_ADV_X1Y2 MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKOUT0)
+ -2.379 -1.689 r pixelClk/inst/mmcm_adv_inst/CLKOUT0
+ net (fo=1, routed) 0.499 -1.190 pixelClk/inst/clk_out1_clk_wiz_0
+ BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.026 -1.164 r pixelClk/inst/clkout1_buf/O
+ net (fo=127, routed) 0.599 -0.565 collisionDetection/CLK
+ SLICE_X89Y69 FDCE r collisionDetection/collision_cnt_reg[14]/C
+ ------------------------------------------------------------------- -------------------
+ SLICE_X89Y69 FDCE (Prop_fdce_C_Q) 0.128 -0.437 r collisionDetection/collision_cnt_reg[14]/Q
+ net (fo=4, routed) 0.358 -0.079 led_OBUF[14]
+ R2 OBUF (Prop_obuf_I_O) 1.284 1.205 r led_OBUF[14]_inst/O
+ net (fo=0) 0.000 1.205 led[14]
+ R2 r led[14] (OUT)
+ ------------------------------------------------------------------- -------------------
+
+Slack: inf
+ Source: collisionDetection/collision_cnt_reg[1]/C
+ (rising edge-triggered cell FDCE clocked by clk_out1_clk_wiz_0 {rise@0.000ns fall@20.000ns period=40.000ns})
+ Destination: led[1]
+ (output port)
+ Path Group: (none)
+ Path Type: Min at Fast Process Corner
+ Data Path Delay: 1.861ns (logic 1.409ns (75.700%) route 0.452ns (24.300%))
+ Logic Levels: 1 (OBUF=1)
+ Clock Uncertainty: 0.199ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE
+ Total System Jitter (TSJ): 0.050ns
+ Discrete Jitter (DJ): 0.182ns
+ Phase Error (PE): 0.104ns
+
+ Location Delay type Incr(ns) Path(ns) Netlist Resource(s)
+ ------------------------------------------------------------------- -------------------
+ (clock clk_out1_clk_wiz_0 rise edge)
+ 0.000 0.000 r
+ E3 0.000 0.000 r clk (IN)
+ net (fo=0) 0.000 0.000 pixelClk/inst/clk_in1
+ E3 IBUF (Prop_ibuf_I_O) 0.250 0.250 r pixelClk/inst/clkin1_ibufg/O
+ net (fo=1, routed) 0.440 0.690 pixelClk/inst/clk_in1_clk_wiz_0
+ MMCME2_ADV_X1Y2 MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKOUT0)
+ -2.379 -1.689 r pixelClk/inst/mmcm_adv_inst/CLKOUT0
+ net (fo=1, routed) 0.499 -1.190 pixelClk/inst/clk_out1_clk_wiz_0
+ BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.026 -1.164 r pixelClk/inst/clkout1_buf/O
+ net (fo=127, routed) 0.601 -0.563 collisionDetection/CLK
+ SLICE_X89Y67 FDCE r collisionDetection/collision_cnt_reg[1]/C
+ ------------------------------------------------------------------- -------------------
+ SLICE_X89Y67 FDCE (Prop_fdce_C_Q) 0.141 -0.422 r collisionDetection/collision_cnt_reg[1]/Q
+ net (fo=3, routed) 0.452 0.030 led_OBUF[1]
+ V9 OBUF (Prop_obuf_I_O) 1.268 1.298 r led_OBUF[1]_inst/O
+ net (fo=0) 0.000 1.298 led[1]
+ V9 r led[1] (OUT)
+ ------------------------------------------------------------------- -------------------
+
+Slack: inf
+ Source: collisionDetection/collision_cnt_reg[5]/C
+ (rising edge-triggered cell FDCE clocked by clk_out1_clk_wiz_0 {rise@0.000ns fall@20.000ns period=40.000ns})
+ Destination: led[5]
+ (output port)
+ Path Group: (none)
+ Path Type: Min at Fast Process Corner
+ Data Path Delay: 1.867ns (logic 1.393ns (74.599%) route 0.474ns (25.401%))
+ Logic Levels: 1 (OBUF=1)
+ Clock Uncertainty: 0.199ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE
+ Total System Jitter (TSJ): 0.050ns
+ Discrete Jitter (DJ): 0.182ns
+ Phase Error (PE): 0.104ns
+
+ Location Delay type Incr(ns) Path(ns) Netlist Resource(s)
+ ------------------------------------------------------------------- -------------------
+ (clock clk_out1_clk_wiz_0 rise edge)
+ 0.000 0.000 r
+ E3 0.000 0.000 r clk (IN)
+ net (fo=0) 0.000 0.000 pixelClk/inst/clk_in1
+ E3 IBUF (Prop_ibuf_I_O) 0.250 0.250 r pixelClk/inst/clkin1_ibufg/O
+ net (fo=1, routed) 0.440 0.690 pixelClk/inst/clk_in1_clk_wiz_0
+ MMCME2_ADV_X1Y2 MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKOUT0)
+ -2.379 -1.689 r pixelClk/inst/mmcm_adv_inst/CLKOUT0
+ net (fo=1, routed) 0.499 -1.190 pixelClk/inst/clk_out1_clk_wiz_0
+ BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.026 -1.164 r pixelClk/inst/clkout1_buf/O
+ net (fo=127, routed) 0.600 -0.564 collisionDetection/CLK
+ SLICE_X89Y68 FDCE r collisionDetection/collision_cnt_reg[5]/C
+ ------------------------------------------------------------------- -------------------
+ SLICE_X89Y68 FDCE (Prop_fdce_C_Q) 0.141 -0.423 r collisionDetection/collision_cnt_reg[5]/Q
+ net (fo=3, routed) 0.474 0.051 led_OBUF[5]
+ T4 OBUF (Prop_obuf_I_O) 1.252 1.303 r led_OBUF[5]_inst/O
+ net (fo=0) 0.000 1.303 led[5]
+ T4 r led[5] (OUT)
+ ------------------------------------------------------------------- -------------------
+
+Slack: inf
+ Source: collisionDetection/collision_cnt_reg[9]_lopt_replica/C
+ (rising edge-triggered cell FDCE clocked by clk_out1_clk_wiz_0 {rise@0.000ns fall@20.000ns period=40.000ns})
+ Destination: led[9]
+ (output port)
+ Path Group: (none)
+ Path Type: Min at Fast Process Corner
+ Data Path Delay: 1.891ns (logic 1.412ns (74.707%) route 0.478ns (25.293%))
+ Logic Levels: 1 (OBUF=1)
+ Clock Uncertainty: 0.199ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE
+ Total System Jitter (TSJ): 0.050ns
+ Discrete Jitter (DJ): 0.182ns
+ Phase Error (PE): 0.104ns
+
+ Location Delay type Incr(ns) Path(ns) Netlist Resource(s)
+ ------------------------------------------------------------------- -------------------
+ (clock clk_out1_clk_wiz_0 rise edge)
+ 0.000 0.000 r
+ E3 0.000 0.000 r clk (IN)
+ net (fo=0) 0.000 0.000 pixelClk/inst/clk_in1
+ E3 IBUF (Prop_ibuf_I_O) 0.250 0.250 r pixelClk/inst/clkin1_ibufg/O
+ net (fo=1, routed) 0.440 0.690 pixelClk/inst/clk_in1_clk_wiz_0
+ MMCME2_ADV_X1Y2 MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKOUT0)
+ -2.379 -1.689 r pixelClk/inst/mmcm_adv_inst/CLKOUT0
+ net (fo=1, routed) 0.499 -1.190 pixelClk/inst/clk_out1_clk_wiz_0
+ BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.026 -1.164 r pixelClk/inst/clkout1_buf/O
+ net (fo=127, routed) 0.594 -0.570 collisionDetection/CLK
+ SLICE_X89Y74 FDCE r collisionDetection/collision_cnt_reg[9]_lopt_replica/C
+ ------------------------------------------------------------------- -------------------
+ SLICE_X89Y74 FDCE (Prop_fdce_C_Q) 0.141 -0.429 r collisionDetection/collision_cnt_reg[9]_lopt_replica/Q
+ net (fo=1, routed) 0.478 0.049 lopt_2
+ U3 OBUF (Prop_obuf_I_O) 1.271 1.320 r led_OBUF[9]_inst/O
+ net (fo=0) 0.000 1.320 led[9]
+ U3 r led[9] (OUT)
+ ------------------------------------------------------------------- -------------------
+
+Slack: inf
+ Source: collisionDetection/collision_cnt_reg[7]/C
+ (rising edge-triggered cell FDCE clocked by clk_out1_clk_wiz_0 {rise@0.000ns fall@20.000ns period=40.000ns})
+ Destination: led[7]
+ (output port)
+ Path Group: (none)
+ Path Type: Min at Fast Process Corner
+ Data Path Delay: 1.920ns (logic 1.404ns (73.103%) route 0.516ns (26.897%))
+ Logic Levels: 1 (OBUF=1)
+ Clock Uncertainty: 0.199ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE
+ Total System Jitter (TSJ): 0.050ns
+ Discrete Jitter (DJ): 0.182ns
+ Phase Error (PE): 0.104ns
+
+ Location Delay type Incr(ns) Path(ns) Netlist Resource(s)
+ ------------------------------------------------------------------- -------------------
+ (clock clk_out1_clk_wiz_0 rise edge)
+ 0.000 0.000 r
+ E3 0.000 0.000 r clk (IN)
+ net (fo=0) 0.000 0.000 pixelClk/inst/clk_in1
+ E3 IBUF (Prop_ibuf_I_O) 0.250 0.250 r pixelClk/inst/clkin1_ibufg/O
+ net (fo=1, routed) 0.440 0.690 pixelClk/inst/clk_in1_clk_wiz_0
+ MMCME2_ADV_X1Y2 MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKOUT0)
+ -2.379 -1.689 r pixelClk/inst/mmcm_adv_inst/CLKOUT0
+ net (fo=1, routed) 0.499 -1.190 pixelClk/inst/clk_out1_clk_wiz_0
+ BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.026 -1.164 r pixelClk/inst/clkout1_buf/O
+ net (fo=127, routed) 0.600 -0.564 collisionDetection/CLK
+ SLICE_X89Y68 FDCE r collisionDetection/collision_cnt_reg[7]/C
+ ------------------------------------------------------------------- -------------------
+ SLICE_X89Y68 FDCE (Prop_fdce_C_Q) 0.141 -0.423 r collisionDetection/collision_cnt_reg[7]/Q
+ net (fo=3, routed) 0.516 0.093 led_OBUF[7]
+ U6 OBUF (Prop_obuf_I_O) 1.263 1.356 r led_OBUF[7]_inst/O
+ net (fo=0) 0.000 1.356 led[7]
+ U6 r led[7] (OUT)
+ ------------------------------------------------------------------- -------------------
+
+Slack: inf
+ Source: collisionDetection/collision_cnt_reg[0]/C
+ (rising edge-triggered cell FDCE clocked by clk_out1_clk_wiz_0 {rise@0.000ns fall@20.000ns period=40.000ns})
+ Destination: led[0]
+ (output port)
+ Path Group: (none)
+ Path Type: Min at Fast Process Corner
+ Data Path Delay: 1.934ns (logic 1.394ns (72.063%) route 0.540ns (27.937%))
+ Logic Levels: 1 (OBUF=1)
+ Clock Uncertainty: 0.199ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE
+ Total System Jitter (TSJ): 0.050ns
+ Discrete Jitter (DJ): 0.182ns
+ Phase Error (PE): 0.104ns
+
+ Location Delay type Incr(ns) Path(ns) Netlist Resource(s)
+ ------------------------------------------------------------------- -------------------
+ (clock clk_out1_clk_wiz_0 rise edge)
+ 0.000 0.000 r
+ E3 0.000 0.000 r clk (IN)
+ net (fo=0) 0.000 0.000 pixelClk/inst/clk_in1
+ E3 IBUF (Prop_ibuf_I_O) 0.250 0.250 r pixelClk/inst/clkin1_ibufg/O
+ net (fo=1, routed) 0.440 0.690 pixelClk/inst/clk_in1_clk_wiz_0
+ MMCME2_ADV_X1Y2 MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKOUT0)
+ -2.379 -1.689 r pixelClk/inst/mmcm_adv_inst/CLKOUT0
+ net (fo=1, routed) 0.499 -1.190 pixelClk/inst/clk_out1_clk_wiz_0
+ BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.026 -1.164 r pixelClk/inst/clkout1_buf/O
+ net (fo=127, routed) 0.601 -0.563 collisionDetection/CLK
+ SLICE_X89Y67 FDCE r collisionDetection/collision_cnt_reg[0]/C
+ ------------------------------------------------------------------- -------------------
+ SLICE_X89Y67 FDCE (Prop_fdce_C_Q) 0.141 -0.422 r collisionDetection/collision_cnt_reg[0]/Q
+ net (fo=2, routed) 0.540 0.118 led_OBUF[0]
+ T8 OBUF (Prop_obuf_I_O) 1.253 1.371 r led_OBUF[0]_inst/O
+ net (fo=0) 0.000 1.371 led[0]
+ T8 r led[0] (OUT)
+ ------------------------------------------------------------------- -------------------
+
+Slack: inf
+ Source: collisionDetection/collision_cnt_reg[4]/C
+ (rising edge-triggered cell FDCE clocked by clk_out1_clk_wiz_0 {rise@0.000ns fall@20.000ns period=40.000ns})
+ Destination: led[4]
+ (output port)
+ Path Group: (none)
+ Path Type: Min at Fast Process Corner
+ Data Path Delay: 1.940ns (logic 1.439ns (74.195%) route 0.501ns (25.805%))
+ Logic Levels: 1 (OBUF=1)
+ Clock Uncertainty: 0.199ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE
+ Total System Jitter (TSJ): 0.050ns
+ Discrete Jitter (DJ): 0.182ns
+ Phase Error (PE): 0.104ns
+
+ Location Delay type Incr(ns) Path(ns) Netlist Resource(s)
+ ------------------------------------------------------------------- -------------------
+ (clock clk_out1_clk_wiz_0 rise edge)
+ 0.000 0.000 r
+ E3 0.000 0.000 r clk (IN)
+ net (fo=0) 0.000 0.000 pixelClk/inst/clk_in1
+ E3 IBUF (Prop_ibuf_I_O) 0.250 0.250 r pixelClk/inst/clkin1_ibufg/O
+ net (fo=1, routed) 0.440 0.690 pixelClk/inst/clk_in1_clk_wiz_0
+ MMCME2_ADV_X1Y2 MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKOUT0)
+ -2.379 -1.689 r pixelClk/inst/mmcm_adv_inst/CLKOUT0
+ net (fo=1, routed) 0.499 -1.190 pixelClk/inst/clk_out1_clk_wiz_0
+ BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.026 -1.164 r pixelClk/inst/clkout1_buf/O
+ net (fo=127, routed) 0.600 -0.564 collisionDetection/CLK
+ SLICE_X89Y68 FDCE r collisionDetection/collision_cnt_reg[4]/C
+ ------------------------------------------------------------------- -------------------
+ SLICE_X89Y68 FDCE (Prop_fdce_C_Q) 0.128 -0.436 r collisionDetection/collision_cnt_reg[4]/Q
+ net (fo=4, routed) 0.501 0.064 led_OBUF[4]
+ T5 OBUF (Prop_obuf_I_O) 1.311 1.375 r led_OBUF[4]_inst/O
+ net (fo=0) 0.000 1.375 led[4]
+ T5 r led[4] (OUT)
+ ------------------------------------------------------------------- -------------------
+
+
+
+
+
+--------------------------------------------------------------------------------------
+Path Group: (none)
+From Clock: clk_out1_clk_wiz_0_1
+ To Clock:
+
+Max Delay 30 Endpoints
+Min Delay 30 Endpoints
+--------------------------------------------------------------------------------------
+
+
+Max Delay Paths
+--------------------------------------------------------------------------------------
+Slack: inf
+ Source: runnerObject/pos_object_y_actual_reg[1]/C
+ (rising edge-triggered cell FDRE clocked by clk_out1_clk_wiz_0_1 {rise@0.000ns fall@20.000ns period=40.000ns})
+ Destination: vgaBlue[3]
+ (output port)
+ Path Group: (none)
+ Path Type: Max at Slow Process Corner
+ Data Path Delay: 13.564ns (logic 5.677ns (41.849%) route 7.888ns (58.151%))
+ Logic Levels: 7 (CARRY4=2 LUT4=2 LUT5=1 LUT6=1 OBUF=1)
+ Clock Uncertainty: 0.195ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE
+ Total System Jitter (TSJ): 0.050ns
+ Discrete Jitter (DJ): 0.175ns
+ Phase Error (PE): 0.104ns
+
+ Location Delay type Incr(ns) Path(ns) Netlist Resource(s)
+ ------------------------------------------------------------------- -------------------
+ (clock clk_out1_clk_wiz_0_1 rise edge)
+ 0.000 0.000 r
+ E3 0.000 0.000 r clk (IN)
+ net (fo=0) 0.000 0.000 pixelClk/inst/clk_in1
+ E3 IBUF (Prop_ibuf_I_O) 1.482 1.482 r pixelClk/inst/clkin1_ibufg/O
+ net (fo=1, routed) 1.233 2.715 pixelClk/inst/clk_in1_clk_wiz_0
+ MMCME2_ADV_X1Y2 MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKOUT0)
+ -7.070 -4.355 r pixelClk/inst/mmcm_adv_inst/CLKOUT0
+ net (fo=1, routed) 1.719 -2.636 pixelClk/inst/clk_out1_clk_wiz_0
+ BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.096 -2.540 r pixelClk/inst/clkout1_buf/O
+ net (fo=127, routed) 1.719 -0.821 runnerObject/clk_out1
+ SLICE_X87Y79 FDRE r runnerObject/pos_object_y_actual_reg[1]/C
+ ------------------------------------------------------------------- -------------------
+ SLICE_X87Y79 FDRE (Prop_fdre_C_Q) 0.456 -0.365 r runnerObject/pos_object_y_actual_reg[1]/Q
+ net (fo=11, routed) 1.064 0.699 runnerObject/pos_object_y_actual_reg[8]_0[1]
+ SLICE_X86Y78 LUT4 (Prop_lut4_I1_O) 0.124 0.823 r runnerObject/color_runner3_carry_i_9/O
+ net (fo=4, routed) 0.844 1.667 runnerObject/color_runner3_carry_i_9_n_0
+ SLICE_X88Y79 LUT6 (Prop_lut6_I4_O) 0.124 1.791 r runnerObject/color_runner3_carry_i_1/O
+ net (fo=1, routed) 0.663 2.454 runnerObject/color_runner3_carry_i_1_n_0
+ SLICE_X86Y79 CARRY4 (Prop_carry4_DI[3]_CO[3])
+ 0.385 2.839 r runnerObject/color_runner3_carry/CO[3]
+ net (fo=1, routed) 0.000 2.839 runnerObject/color_runner3_carry_n_0
+ SLICE_X86Y80 CARRY4 (Prop_carry4_CI_CO[1])
+ 0.157 2.996 r runnerObject/color_runner3_carry__0/CO[1]
+ net (fo=7, routed) 0.997 3.992 runnerObject/color_runner3
+ SLICE_X87Y84 LUT4 (Prop_lut4_I3_O) 0.357 4.349 r runnerObject/vgaBlue_OBUF[3]_inst_i_4/O
+ net (fo=5, routed) 0.616 4.965 vgaInterface/vgaGreen[1]_0
+ SLICE_X87Y83 LUT5 (Prop_lut5_I4_O) 0.320 5.285 r vgaInterface/vgaBlue_OBUF[3]_inst_i_1/O
+ net (fo=1, routed) 3.705 8.990 vgaBlue_OBUF[3]
+ D8 OBUF (Prop_obuf_I_O) 3.754 12.744 r vgaBlue_OBUF[3]_inst/O
+ net (fo=0) 0.000 12.744 vgaBlue[3]
+ D8 r vgaBlue[3] (OUT)
+ ------------------------------------------------------------------- -------------------
+
+Slack: inf
+ Source: runnerObject/pos_object_y_actual_reg[1]/C
+ (rising edge-triggered cell FDRE clocked by clk_out1_clk_wiz_0_1 {rise@0.000ns fall@20.000ns period=40.000ns})
+ Destination: vgaGreen[1]
+ (output port)
+ Path Group: (none)
+ Path Type: Max at Slow Process Corner
+ Data Path Delay: 13.545ns (logic 5.474ns (40.411%) route 8.071ns (59.589%))
+ Logic Levels: 7 (CARRY4=2 LUT4=3 LUT6=1 OBUF=1)
+ Clock Uncertainty: 0.195ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE
+ Total System Jitter (TSJ): 0.050ns
+ Discrete Jitter (DJ): 0.175ns
+ Phase Error (PE): 0.104ns
+
+ Location Delay type Incr(ns) Path(ns) Netlist Resource(s)
+ ------------------------------------------------------------------- -------------------
+ (clock clk_out1_clk_wiz_0_1 rise edge)
+ 0.000 0.000 r
+ E3 0.000 0.000 r clk (IN)
+ net (fo=0) 0.000 0.000 pixelClk/inst/clk_in1
+ E3 IBUF (Prop_ibuf_I_O) 1.482 1.482 r pixelClk/inst/clkin1_ibufg/O
+ net (fo=1, routed) 1.233 2.715 pixelClk/inst/clk_in1_clk_wiz_0
+ MMCME2_ADV_X1Y2 MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKOUT0)
+ -7.070 -4.355 r pixelClk/inst/mmcm_adv_inst/CLKOUT0
+ net (fo=1, routed) 1.719 -2.636 pixelClk/inst/clk_out1_clk_wiz_0
+ BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.096 -2.540 r pixelClk/inst/clkout1_buf/O
+ net (fo=127, routed) 1.719 -0.821 runnerObject/clk_out1
+ SLICE_X87Y79 FDRE r runnerObject/pos_object_y_actual_reg[1]/C
+ ------------------------------------------------------------------- -------------------
+ SLICE_X87Y79 FDRE (Prop_fdre_C_Q) 0.456 -0.365 r runnerObject/pos_object_y_actual_reg[1]/Q
+ net (fo=11, routed) 1.064 0.699 runnerObject/pos_object_y_actual_reg[8]_0[1]
+ SLICE_X86Y78 LUT4 (Prop_lut4_I1_O) 0.124 0.823 r runnerObject/color_runner3_carry_i_9/O
+ net (fo=4, routed) 0.844 1.667 runnerObject/color_runner3_carry_i_9_n_0
+ SLICE_X88Y79 LUT6 (Prop_lut6_I4_O) 0.124 1.791 r runnerObject/color_runner3_carry_i_1/O
+ net (fo=1, routed) 0.663 2.454 runnerObject/color_runner3_carry_i_1_n_0
+ SLICE_X86Y79 CARRY4 (Prop_carry4_DI[3]_CO[3])
+ 0.385 2.839 r runnerObject/color_runner3_carry/CO[3]
+ net (fo=1, routed) 0.000 2.839 runnerObject/color_runner3_carry_n_0
+ SLICE_X86Y80 CARRY4 (Prop_carry4_CI_CO[1])
+ 0.157 2.996 r runnerObject/color_runner3_carry__0/CO[1]
+ net (fo=7, routed) 0.997 3.992 runnerObject/color_runner3
+ SLICE_X87Y84 LUT4 (Prop_lut4_I3_O) 0.357 4.349 r runnerObject/vgaBlue_OBUF[3]_inst_i_4/O
+ net (fo=5, routed) 0.810 5.159 vgaInterface/vgaGreen[1]_0
+ SLICE_X87Y83 LUT4 (Prop_lut4_I1_O) 0.326 5.485 r vgaInterface/vgaGreen_OBUF[1]_inst_i_1/O
+ net (fo=1, routed) 3.695 9.180 vgaGreen_OBUF[1]
+ A5 OBUF (Prop_obuf_I_O) 3.545 12.724 r vgaGreen_OBUF[1]_inst/O
+ net (fo=0) 0.000 12.724 vgaGreen[1]
+ A5 r vgaGreen[1] (OUT)
+ ------------------------------------------------------------------- -------------------
+
+Slack: inf
+ Source: runnerObject/pos_object_y_actual_reg[1]/C
+ (rising edge-triggered cell FDRE clocked by clk_out1_clk_wiz_0_1 {rise@0.000ns fall@20.000ns period=40.000ns})
+ Destination: vgaGreen[2]
+ (output port)
+ Path Group: (none)
+ Path Type: Max at Slow Process Corner
+ Data Path Delay: 13.522ns (logic 5.678ns (41.995%) route 7.843ns (58.005%))
+ Logic Levels: 7 (CARRY4=2 LUT4=2 LUT5=1 LUT6=1 OBUF=1)
+ Clock Uncertainty: 0.195ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE
+ Total System Jitter (TSJ): 0.050ns
+ Discrete Jitter (DJ): 0.175ns
+ Phase Error (PE): 0.104ns
+
+ Location Delay type Incr(ns) Path(ns) Netlist Resource(s)
+ ------------------------------------------------------------------- -------------------
+ (clock clk_out1_clk_wiz_0_1 rise edge)
+ 0.000 0.000 r
+ E3 0.000 0.000 r clk (IN)
+ net (fo=0) 0.000 0.000 pixelClk/inst/clk_in1
+ E3 IBUF (Prop_ibuf_I_O) 1.482 1.482 r pixelClk/inst/clkin1_ibufg/O
+ net (fo=1, routed) 1.233 2.715 pixelClk/inst/clk_in1_clk_wiz_0
+ MMCME2_ADV_X1Y2 MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKOUT0)
+ -7.070 -4.355 r pixelClk/inst/mmcm_adv_inst/CLKOUT0
+ net (fo=1, routed) 1.719 -2.636 pixelClk/inst/clk_out1_clk_wiz_0
+ BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.096 -2.540 r pixelClk/inst/clkout1_buf/O
+ net (fo=127, routed) 1.719 -0.821 runnerObject/clk_out1
+ SLICE_X87Y79 FDRE r runnerObject/pos_object_y_actual_reg[1]/C
+ ------------------------------------------------------------------- -------------------
+ SLICE_X87Y79 FDRE (Prop_fdre_C_Q) 0.456 -0.365 r runnerObject/pos_object_y_actual_reg[1]/Q
+ net (fo=11, routed) 1.064 0.699 runnerObject/pos_object_y_actual_reg[8]_0[1]
+ SLICE_X86Y78 LUT4 (Prop_lut4_I1_O) 0.124 0.823 r runnerObject/color_runner3_carry_i_9/O
+ net (fo=4, routed) 0.844 1.667 runnerObject/color_runner3_carry_i_9_n_0
+ SLICE_X88Y79 LUT6 (Prop_lut6_I4_O) 0.124 1.791 r runnerObject/color_runner3_carry_i_1/O
+ net (fo=1, routed) 0.663 2.454 runnerObject/color_runner3_carry_i_1_n_0
+ SLICE_X86Y79 CARRY4 (Prop_carry4_DI[3]_CO[3])
+ 0.385 2.839 r runnerObject/color_runner3_carry/CO[3]
+ net (fo=1, routed) 0.000 2.839 runnerObject/color_runner3_carry_n_0
+ SLICE_X86Y80 CARRY4 (Prop_carry4_CI_CO[1])
+ 0.157 2.996 f runnerObject/color_runner3_carry__0/CO[1]
+ net (fo=7, routed) 0.997 3.992 runnerObject/color_runner3
+ SLICE_X87Y84 LUT4 (Prop_lut4_I3_O) 0.357 4.349 f runnerObject/vgaBlue_OBUF[3]_inst_i_4/O
+ net (fo=5, routed) 0.620 4.969 vgaInterface/vgaGreen[1]_0
+ SLICE_X87Y83 LUT5 (Prop_lut5_I2_O) 0.321 5.290 r vgaInterface/vgaGreen_OBUF[2]_inst_i_1/O
+ net (fo=1, routed) 3.657 8.947 vgaGreen_OBUF[2]
+ B6 OBUF (Prop_obuf_I_O) 3.754 12.701 r vgaGreen_OBUF[2]_inst/O
+ net (fo=0) 0.000 12.701 vgaGreen[2]
+ B6 r vgaGreen[2] (OUT)
+ ------------------------------------------------------------------- -------------------
+
+Slack: inf
+ Source: runnerObject/pos_object_y_actual_reg[1]/C
+ (rising edge-triggered cell FDRE clocked by clk_out1_clk_wiz_0_1 {rise@0.000ns fall@20.000ns period=40.000ns})
+ Destination: vgaBlue[1]
+ (output port)
+ Path Group: (none)
+ Path Type: Max at Slow Process Corner
+ Data Path Delay: 13.363ns (logic 5.480ns (41.011%) route 7.883ns (58.989%))
+ Logic Levels: 7 (CARRY4=2 LUT4=2 LUT5=1 LUT6=1 OBUF=1)
+ Clock Uncertainty: 0.195ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE
+ Total System Jitter (TSJ): 0.050ns
+ Discrete Jitter (DJ): 0.175ns
+ Phase Error (PE): 0.104ns
+
+ Location Delay type Incr(ns) Path(ns) Netlist Resource(s)
+ ------------------------------------------------------------------- -------------------
+ (clock clk_out1_clk_wiz_0_1 rise edge)
+ 0.000 0.000 r
+ E3 0.000 0.000 r clk (IN)
+ net (fo=0) 0.000 0.000 pixelClk/inst/clk_in1
+ E3 IBUF (Prop_ibuf_I_O) 1.482 1.482 r pixelClk/inst/clkin1_ibufg/O
+ net (fo=1, routed) 1.233 2.715 pixelClk/inst/clk_in1_clk_wiz_0
+ MMCME2_ADV_X1Y2 MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKOUT0)
+ -7.070 -4.355 r pixelClk/inst/mmcm_adv_inst/CLKOUT0
+ net (fo=1, routed) 1.719 -2.636 pixelClk/inst/clk_out1_clk_wiz_0
+ BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.096 -2.540 r pixelClk/inst/clkout1_buf/O
+ net (fo=127, routed) 1.719 -0.821 runnerObject/clk_out1
+ SLICE_X87Y79 FDRE r runnerObject/pos_object_y_actual_reg[1]/C
+ ------------------------------------------------------------------- -------------------
+ SLICE_X87Y79 FDRE (Prop_fdre_C_Q) 0.456 -0.365 r runnerObject/pos_object_y_actual_reg[1]/Q
+ net (fo=11, routed) 1.064 0.699 runnerObject/pos_object_y_actual_reg[8]_0[1]
+ SLICE_X86Y78 LUT4 (Prop_lut4_I1_O) 0.124 0.823 r runnerObject/color_runner3_carry_i_9/O
+ net (fo=4, routed) 0.844 1.667 runnerObject/color_runner3_carry_i_9_n_0
+ SLICE_X88Y79 LUT6 (Prop_lut6_I4_O) 0.124 1.791 r runnerObject/color_runner3_carry_i_1/O
+ net (fo=1, routed) 0.663 2.454 runnerObject/color_runner3_carry_i_1_n_0
+ SLICE_X86Y79 CARRY4 (Prop_carry4_DI[3]_CO[3])
+ 0.385 2.839 r runnerObject/color_runner3_carry/CO[3]
+ net (fo=1, routed) 0.000 2.839 runnerObject/color_runner3_carry_n_0
+ SLICE_X86Y80 CARRY4 (Prop_carry4_CI_CO[1])
+ 0.157 2.996 r runnerObject/color_runner3_carry__0/CO[1]
+ net (fo=7, routed) 0.997 3.992 runnerObject/color_runner3
+ SLICE_X87Y84 LUT4 (Prop_lut4_I3_O) 0.357 4.349 r runnerObject/vgaBlue_OBUF[3]_inst_i_4/O
+ net (fo=5, routed) 0.616 4.965 vgaInterface/vgaGreen[1]_0
+ SLICE_X87Y83 LUT5 (Prop_lut5_I2_O) 0.326 5.291 r vgaInterface/vgaBlue_OBUF[1]_inst_i_1/O
+ net (fo=1, routed) 3.700 8.991 vgaBlue_OBUF[1]
+ C7 OBUF (Prop_obuf_I_O) 3.551 12.542 r vgaBlue_OBUF[1]_inst/O
+ net (fo=0) 0.000 12.542 vgaBlue[1]
+ C7 r vgaBlue[1] (OUT)
+ ------------------------------------------------------------------- -------------------
+
+Slack: inf
+ Source: runnerObject/pos_object_y_actual_reg[1]/C
+ (rising edge-triggered cell FDRE clocked by clk_out1_clk_wiz_0_1 {rise@0.000ns fall@20.000ns period=40.000ns})
+ Destination: vgaBlue[2]
+ (output port)
+ Path Group: (none)
+ Path Type: Max at Slow Process Corner
+ Data Path Delay: 13.104ns (logic 5.452ns (41.609%) route 7.651ns (58.391%))
+ Logic Levels: 7 (CARRY4=2 LUT4=3 LUT6=1 OBUF=1)
+ Clock Uncertainty: 0.195ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE
+ Total System Jitter (TSJ): 0.050ns
+ Discrete Jitter (DJ): 0.175ns
+ Phase Error (PE): 0.104ns
+
+ Location Delay type Incr(ns) Path(ns) Netlist Resource(s)
+ ------------------------------------------------------------------- -------------------
+ (clock clk_out1_clk_wiz_0_1 rise edge)
+ 0.000 0.000 r
+ E3 0.000 0.000 r clk (IN)
+ net (fo=0) 0.000 0.000 pixelClk/inst/clk_in1
+ E3 IBUF (Prop_ibuf_I_O) 1.482 1.482 r pixelClk/inst/clkin1_ibufg/O
+ net (fo=1, routed) 1.233 2.715 pixelClk/inst/clk_in1_clk_wiz_0
+ MMCME2_ADV_X1Y2 MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKOUT0)
+ -7.070 -4.355 r pixelClk/inst/mmcm_adv_inst/CLKOUT0
+ net (fo=1, routed) 1.719 -2.636 pixelClk/inst/clk_out1_clk_wiz_0
+ BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.096 -2.540 r pixelClk/inst/clkout1_buf/O
+ net (fo=127, routed) 1.719 -0.821 runnerObject/clk_out1
+ SLICE_X87Y79 FDRE r runnerObject/pos_object_y_actual_reg[1]/C
+ ------------------------------------------------------------------- -------------------
+ SLICE_X87Y79 FDRE (Prop_fdre_C_Q) 0.456 -0.365 r runnerObject/pos_object_y_actual_reg[1]/Q
+ net (fo=11, routed) 1.064 0.699 runnerObject/pos_object_y_actual_reg[8]_0[1]
+ SLICE_X86Y78 LUT4 (Prop_lut4_I1_O) 0.124 0.823 r runnerObject/color_runner3_carry_i_9/O
+ net (fo=4, routed) 0.844 1.667 runnerObject/color_runner3_carry_i_9_n_0
+ SLICE_X88Y79 LUT6 (Prop_lut6_I4_O) 0.124 1.791 r runnerObject/color_runner3_carry_i_1/O
+ net (fo=1, routed) 0.663 2.454 runnerObject/color_runner3_carry_i_1_n_0
+ SLICE_X86Y79 CARRY4 (Prop_carry4_DI[3]_CO[3])
+ 0.385 2.839 r runnerObject/color_runner3_carry/CO[3]
+ net (fo=1, routed) 0.000 2.839 runnerObject/color_runner3_carry_n_0
+ SLICE_X86Y80 CARRY4 (Prop_carry4_CI_CO[1])
+ 0.157 2.996 r runnerObject/color_runner3_carry__0/CO[1]
+ net (fo=7, routed) 0.997 3.992 runnerObject/color_runner3
+ SLICE_X87Y84 LUT4 (Prop_lut4_I3_O) 0.357 4.349 r runnerObject/vgaBlue_OBUF[3]_inst_i_4/O
+ net (fo=5, routed) 0.620 4.969 vgaInterface/vgaGreen[1]_0
+ SLICE_X87Y83 LUT4 (Prop_lut4_I3_O) 0.326 5.295 r vgaInterface/vgaBlue_OBUF[2]_inst_i_1/O
+ net (fo=1, routed) 3.465 8.760 vgaBlue_OBUF[2]
+ D7 OBUF (Prop_obuf_I_O) 3.523 12.283 r vgaBlue_OBUF[2]_inst/O
+ net (fo=0) 0.000 12.283 vgaBlue[2]
+ D7 r vgaBlue[2] (OUT)
+ ------------------------------------------------------------------- -------------------
+
+Slack: inf
+ Source: largeObstacle/pos_object_x_actual_reg[1]/C
+ (rising edge-triggered cell FDRE clocked by clk_out1_clk_wiz_0_1 {rise@0.000ns fall@20.000ns period=40.000ns})
+ Destination: vgaGreen[3]
+ (output port)
+ Path Group: (none)
+ Path Type: Max at Slow Process Corner
+ Data Path Delay: 12.861ns (logic 5.316ns (41.338%) route 7.544ns (58.662%))
+ Logic Levels: 7 (CARRY4=2 LUT4=1 LUT5=1 LUT6=2 OBUF=1)
+ Clock Uncertainty: 0.195ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE
+ Total System Jitter (TSJ): 0.050ns
+ Discrete Jitter (DJ): 0.175ns
+ Phase Error (PE): 0.104ns
+
+ Location Delay type Incr(ns) Path(ns) Netlist Resource(s)
+ ------------------------------------------------------------------- -------------------
+ (clock clk_out1_clk_wiz_0_1 rise edge)
+ 0.000 0.000 r
+ E3 0.000 0.000 r clk (IN)
+ net (fo=0) 0.000 0.000 pixelClk/inst/clk_in1
+ E3 IBUF (Prop_ibuf_I_O) 1.482 1.482 r pixelClk/inst/clkin1_ibufg/O
+ net (fo=1, routed) 1.233 2.715 pixelClk/inst/clk_in1_clk_wiz_0
+ MMCME2_ADV_X1Y2 MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKOUT0)
+ -7.070 -4.355 r pixelClk/inst/mmcm_adv_inst/CLKOUT0
+ net (fo=1, routed) 1.719 -2.636 pixelClk/inst/clk_out1_clk_wiz_0
+ BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.096 -2.540 r pixelClk/inst/clkout1_buf/O
+ net (fo=127, routed) 1.710 -0.830 largeObstacle/CLK
+ SLICE_X81Y78 FDRE r largeObstacle/pos_object_x_actual_reg[1]/C
+ ------------------------------------------------------------------- -------------------
+ SLICE_X81Y78 FDRE (Prop_fdre_C_Q) 0.456 -0.374 f largeObstacle/pos_object_x_actual_reg[1]/Q
+ net (fo=8, routed) 1.456 1.082 largeObstacle/pos_object_x_actual_reg[9]_0[1]
+ SLICE_X80Y79 LUT6 (Prop_lut6_I3_O) 0.124 1.206 r largeObstacle/_carry__0_i_5__0/O
+ net (fo=5, routed) 0.897 2.103 largeObstacle/_carry__0_i_5__0_n_0
+ SLICE_X81Y79 LUT4 (Prop_lut4_I1_O) 0.124 2.227 r largeObstacle/_carry__0_i_1__0/O
+ net (fo=1, routed) 0.000 2.227 largeObstacle/_carry__0_i_1__0_n_0
+ SLICE_X81Y79 CARRY4 (Prop_carry4_S[3]_CO[3])
+ 0.401 2.628 r largeObstacle/_carry__0/CO[3]
+ net (fo=1, routed) 0.000 2.628 largeObstacle/_carry__0_n_0
+ SLICE_X81Y80 CARRY4 (Prop_carry4_CI_CO[2])
+ 0.228 2.856 r largeObstacle/_carry__1/CO[2]
+ net (fo=1, routed) 0.501 3.357 largeObstacle/_carry__1_n_1
+ SLICE_X83Y80 LUT5 (Prop_lut5_I1_O) 0.313 3.670 f largeObstacle/vgaRed_OBUF[3]_inst_i_2/O
+ net (fo=9, routed) 0.996 4.666 runnerObject/collision_cnt_reg[15]_4
+ SLICE_X87Y84 LUT6 (Prop_lut6_I4_O) 0.124 4.790 r runnerObject/vgaGreen_OBUF[3]_inst_i_1/O
+ net (fo=1, routed) 3.695 8.485 vgaGreen_OBUF[3]
+ A6 OBUF (Prop_obuf_I_O) 3.546 12.031 r vgaGreen_OBUF[3]_inst/O
+ net (fo=0) 0.000 12.031 vgaGreen[3]
+ A6 r vgaGreen[3] (OUT)
+ ------------------------------------------------------------------- -------------------
+
+Slack: inf
+ Source: largeObstacle/pos_object_x_actual_reg[1]/C
+ (rising edge-triggered cell FDRE clocked by clk_out1_clk_wiz_0_1 {rise@0.000ns fall@20.000ns period=40.000ns})
+ Destination: vgaRed[3]
+ (output port)
+ Path Group: (none)
+ Path Type: Max at Slow Process Corner
+ Data Path Delay: 12.647ns (logic 5.322ns (42.078%) route 7.325ns (57.922%))
+ Logic Levels: 7 (CARRY4=2 LUT4=1 LUT5=1 LUT6=2 OBUF=1)
+ Clock Uncertainty: 0.195ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE
+ Total System Jitter (TSJ): 0.050ns
+ Discrete Jitter (DJ): 0.175ns
+ Phase Error (PE): 0.104ns
+
+ Location Delay type Incr(ns) Path(ns) Netlist Resource(s)
+ ------------------------------------------------------------------- -------------------
+ (clock clk_out1_clk_wiz_0_1 rise edge)
+ 0.000 0.000 r
+ E3 0.000 0.000 r clk (IN)
+ net (fo=0) 0.000 0.000 pixelClk/inst/clk_in1
+ E3 IBUF (Prop_ibuf_I_O) 1.482 1.482 r pixelClk/inst/clkin1_ibufg/O
+ net (fo=1, routed) 1.233 2.715 pixelClk/inst/clk_in1_clk_wiz_0
+ MMCME2_ADV_X1Y2 MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKOUT0)
+ -7.070 -4.355 r pixelClk/inst/mmcm_adv_inst/CLKOUT0
+ net (fo=1, routed) 1.719 -2.636 pixelClk/inst/clk_out1_clk_wiz_0
+ BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.096 -2.540 r pixelClk/inst/clkout1_buf/O
+ net (fo=127, routed) 1.710 -0.830 largeObstacle/CLK
+ SLICE_X81Y78 FDRE r largeObstacle/pos_object_x_actual_reg[1]/C
+ ------------------------------------------------------------------- -------------------
+ SLICE_X81Y78 FDRE (Prop_fdre_C_Q) 0.456 -0.374 f largeObstacle/pos_object_x_actual_reg[1]/Q
+ net (fo=8, routed) 1.456 1.082 largeObstacle/pos_object_x_actual_reg[9]_0[1]
+ SLICE_X80Y79 LUT6 (Prop_lut6_I3_O) 0.124 1.206 r largeObstacle/_carry__0_i_5__0/O
+ net (fo=5, routed) 0.897 2.103 largeObstacle/_carry__0_i_5__0_n_0
+ SLICE_X81Y79 LUT4 (Prop_lut4_I1_O) 0.124 2.227 r largeObstacle/_carry__0_i_1__0/O
+ net (fo=1, routed) 0.000 2.227 largeObstacle/_carry__0_i_1__0_n_0
+ SLICE_X81Y79 CARRY4 (Prop_carry4_S[3]_CO[3])
+ 0.401 2.628 r largeObstacle/_carry__0/CO[3]
+ net (fo=1, routed) 0.000 2.628 largeObstacle/_carry__0_n_0
+ SLICE_X81Y80 CARRY4 (Prop_carry4_CI_CO[2])
+ 0.228 2.856 f largeObstacle/_carry__1/CO[2]
+ net (fo=1, routed) 0.501 3.357 largeObstacle/_carry__1_n_1
+ SLICE_X83Y80 LUT5 (Prop_lut5_I1_O) 0.313 3.670 r largeObstacle/vgaRed_OBUF[3]_inst_i_2/O
+ net (fo=9, routed) 1.010 4.680 runnerObject/collision_cnt_reg[15]_4
+ SLICE_X86Y84 LUT6 (Prop_lut6_I4_O) 0.124 4.804 r runnerObject/vgaRed_OBUF[3]_inst_i_1/O
+ net (fo=1, routed) 3.462 8.266 vgaRed_OBUF[3]
+ A4 OBUF (Prop_obuf_I_O) 3.552 11.817 r vgaRed_OBUF[3]_inst/O
+ net (fo=0) 0.000 11.817 vgaRed[3]
+ A4 r vgaRed[3] (OUT)
+ ------------------------------------------------------------------- -------------------
+
+Slack: inf
+ Source: vgaInterface/counter_v_reg[7]/C
+ (rising edge-triggered cell FDCE clocked by clk_out1_clk_wiz_0_1 {rise@0.000ns fall@20.000ns period=40.000ns})
+ Destination: vgaRed[0]
+ (output port)
+ Path Group: (none)
+ Path Type: Max at Slow Process Corner
+ Data Path Delay: 12.551ns (logic 5.059ns (40.306%) route 7.492ns (59.694%))
+ Logic Levels: 6 (LUT4=1 LUT6=4 OBUF=1)
+ Clock Uncertainty: 0.195ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE
+ Total System Jitter (TSJ): 0.050ns
+ Discrete Jitter (DJ): 0.175ns
+ Phase Error (PE): 0.104ns
+
+ Location Delay type Incr(ns) Path(ns) Netlist Resource(s)
+ ------------------------------------------------------------------- -------------------
+ (clock clk_out1_clk_wiz_0_1 rise edge)
+ 0.000 0.000 r
+ E3 0.000 0.000 r clk (IN)
+ net (fo=0) 0.000 0.000 pixelClk/inst/clk_in1
+ E3 IBUF (Prop_ibuf_I_O) 1.482 1.482 r pixelClk/inst/clkin1_ibufg/O
+ net (fo=1, routed) 1.233 2.715 pixelClk/inst/clk_in1_clk_wiz_0
+ MMCME2_ADV_X1Y2 MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKOUT0)
+ -7.070 -4.355 r pixelClk/inst/mmcm_adv_inst/CLKOUT0
+ net (fo=1, routed) 1.719 -2.636 pixelClk/inst/clk_out1_clk_wiz_0
+ BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.096 -2.540 r pixelClk/inst/clkout1_buf/O
+ net (fo=127, routed) 1.715 -0.825 vgaInterface/clk_out1
+ SLICE_X88Y77 FDCE r vgaInterface/counter_v_reg[7]/C
+ ------------------------------------------------------------------- -------------------
+ SLICE_X88Y77 FDCE (Prop_fdce_C_Q) 0.478 -0.347 f vgaInterface/counter_v_reg[7]/Q
+ net (fo=17, routed) 1.176 0.829 vgaInterface/counter_v_reg[9]_0[7]
+ SLICE_X83Y79 LUT4 (Prop_lut4_I1_O) 0.329 1.158 r vgaInterface/vgaBlue_OBUF[0]_inst_i_5/O
+ net (fo=1, routed) 0.433 1.592 vgaInterface/vgaBlue_OBUF[0]_inst_i_5_n_0
+ SLICE_X83Y79 LUT6 (Prop_lut6_I3_O) 0.326 1.918 r vgaInterface/vgaBlue_OBUF[0]_inst_i_2/O
+ net (fo=1, routed) 0.573 2.491 vgaInterface/vgaBlue_OBUF[0]_inst_i_2_n_0
+ SLICE_X83Y80 LUT6 (Prop_lut6_I0_O) 0.124 2.615 r vgaInterface/vgaBlue_OBUF[0]_inst_i_1/O
+ net (fo=6, routed) 0.721 3.335 vgaInterface/vgaBlue_OBUF[0]
+ SLICE_X83Y81 LUT6 (Prop_lut6_I0_O) 0.124 3.459 r vgaInterface/vgaRed_OBUF[3]_inst_i_3/O
+ net (fo=7, routed) 1.156 4.615 runnerObject/vgaGreen[0]
+ SLICE_X87Y84 LUT6 (Prop_lut6_I5_O) 0.124 4.739 r runnerObject/vgaRed_OBUF[0]_inst_i_1/O
+ net (fo=1, routed) 3.433 8.172 vgaRed_OBUF[0]
+ A3 OBUF (Prop_obuf_I_O) 3.554 11.726 r vgaRed_OBUF[0]_inst/O
+ net (fo=0) 0.000 11.726 vgaRed[0]
+ A3 r vgaRed[0] (OUT)
+ ------------------------------------------------------------------- -------------------
+
+Slack: inf
+ Source: vgaInterface/counter_v_reg[7]/C
+ (rising edge-triggered cell FDCE clocked by clk_out1_clk_wiz_0_1 {rise@0.000ns fall@20.000ns period=40.000ns})
+ Destination: vgaRed[1]
+ (output port)
+ Path Group: (none)
+ Path Type: Max at Slow Process Corner
+ Data Path Delay: 12.423ns (logic 5.256ns (42.310%) route 7.167ns (57.690%))
+ Logic Levels: 6 (LUT4=1 LUT5=1 LUT6=3 OBUF=1)
+ Clock Uncertainty: 0.195ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE
+ Total System Jitter (TSJ): 0.050ns
+ Discrete Jitter (DJ): 0.175ns
+ Phase Error (PE): 0.104ns
+
+ Location Delay type Incr(ns) Path(ns) Netlist Resource(s)
+ ------------------------------------------------------------------- -------------------
+ (clock clk_out1_clk_wiz_0_1 rise edge)
+ 0.000 0.000 r
+ E3 0.000 0.000 r clk (IN)
+ net (fo=0) 0.000 0.000 pixelClk/inst/clk_in1
+ E3 IBUF (Prop_ibuf_I_O) 1.482 1.482 r pixelClk/inst/clkin1_ibufg/O
+ net (fo=1, routed) 1.233 2.715 pixelClk/inst/clk_in1_clk_wiz_0
+ MMCME2_ADV_X1Y2 MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKOUT0)
+ -7.070 -4.355 r pixelClk/inst/mmcm_adv_inst/CLKOUT0
+ net (fo=1, routed) 1.719 -2.636 pixelClk/inst/clk_out1_clk_wiz_0
+ BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.096 -2.540 r pixelClk/inst/clkout1_buf/O
+ net (fo=127, routed) 1.715 -0.825 vgaInterface/clk_out1
+ SLICE_X88Y77 FDCE r vgaInterface/counter_v_reg[7]/C
+ ------------------------------------------------------------------- -------------------
+ SLICE_X88Y77 FDCE (Prop_fdce_C_Q) 0.478 -0.347 f vgaInterface/counter_v_reg[7]/Q
+ net (fo=17, routed) 1.176 0.829 vgaInterface/counter_v_reg[9]_0[7]
+ SLICE_X83Y79 LUT4 (Prop_lut4_I1_O) 0.329 1.158 r vgaInterface/vgaBlue_OBUF[0]_inst_i_5/O
+ net (fo=1, routed) 0.433 1.592 vgaInterface/vgaBlue_OBUF[0]_inst_i_5_n_0
+ SLICE_X83Y79 LUT6 (Prop_lut6_I3_O) 0.326 1.918 r vgaInterface/vgaBlue_OBUF[0]_inst_i_2/O
+ net (fo=1, routed) 0.573 2.491 vgaInterface/vgaBlue_OBUF[0]_inst_i_2_n_0
+ SLICE_X83Y80 LUT6 (Prop_lut6_I0_O) 0.124 2.615 r vgaInterface/vgaBlue_OBUF[0]_inst_i_1/O
+ net (fo=6, routed) 0.721 3.335 vgaInterface/vgaBlue_OBUF[0]
+ SLICE_X83Y81 LUT6 (Prop_lut6_I0_O) 0.124 3.459 r vgaInterface/vgaRed_OBUF[3]_inst_i_3/O
+ net (fo=7, routed) 0.750 4.209 runnerObject/vgaGreen[0]
+ SLICE_X87Y84 LUT5 (Prop_lut5_I4_O) 0.119 4.328 r runnerObject/vgaRed_OBUF[1]_inst_i_1/O
+ net (fo=1, routed) 3.514 7.842 vgaRed_OBUF[1]
+ B4 OBUF (Prop_obuf_I_O) 3.756 11.599 r vgaRed_OBUF[1]_inst/O
+ net (fo=0) 0.000 11.599 vgaRed[1]
+ B4 r vgaRed[1] (OUT)
+ ------------------------------------------------------------------- -------------------
+
+Slack: inf
+ Source: vgaInterface/counter_v_reg[7]/C
+ (rising edge-triggered cell FDCE clocked by clk_out1_clk_wiz_0_1 {rise@0.000ns fall@20.000ns period=40.000ns})
+ Destination: vgaGreen[0]
+ (output port)
+ Path Group: (none)
+ Path Type: Max at Slow Process Corner
+ Data Path Delay: 12.404ns (logic 5.043ns (40.659%) route 7.360ns (59.341%))
+ Logic Levels: 6 (LUT4=1 LUT5=1 LUT6=3 OBUF=1)
+ Clock Uncertainty: 0.195ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE
+ Total System Jitter (TSJ): 0.050ns
+ Discrete Jitter (DJ): 0.175ns
+ Phase Error (PE): 0.104ns
+
+ Location Delay type Incr(ns) Path(ns) Netlist Resource(s)
+ ------------------------------------------------------------------- -------------------
+ (clock clk_out1_clk_wiz_0_1 rise edge)
+ 0.000 0.000 r
+ E3 0.000 0.000 r clk (IN)
+ net (fo=0) 0.000 0.000 pixelClk/inst/clk_in1
+ E3 IBUF (Prop_ibuf_I_O) 1.482 1.482 r pixelClk/inst/clkin1_ibufg/O
+ net (fo=1, routed) 1.233 2.715 pixelClk/inst/clk_in1_clk_wiz_0
+ MMCME2_ADV_X1Y2 MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKOUT0)
+ -7.070 -4.355 r pixelClk/inst/mmcm_adv_inst/CLKOUT0
+ net (fo=1, routed) 1.719 -2.636 pixelClk/inst/clk_out1_clk_wiz_0
+ BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.096 -2.540 r pixelClk/inst/clkout1_buf/O
+ net (fo=127, routed) 1.715 -0.825 vgaInterface/clk_out1
+ SLICE_X88Y77 FDCE r vgaInterface/counter_v_reg[7]/C
+ ------------------------------------------------------------------- -------------------
+ SLICE_X88Y77 FDCE (Prop_fdce_C_Q) 0.478 -0.347 f vgaInterface/counter_v_reg[7]/Q
+ net (fo=17, routed) 1.176 0.829 vgaInterface/counter_v_reg[9]_0[7]
+ SLICE_X83Y79 LUT4 (Prop_lut4_I1_O) 0.329 1.158 r vgaInterface/vgaBlue_OBUF[0]_inst_i_5/O
+ net (fo=1, routed) 0.433 1.592 vgaInterface/vgaBlue_OBUF[0]_inst_i_5_n_0
+ SLICE_X83Y79 LUT6 (Prop_lut6_I3_O) 0.326 1.918 r vgaInterface/vgaBlue_OBUF[0]_inst_i_2/O
+ net (fo=1, routed) 0.573 2.491 vgaInterface/vgaBlue_OBUF[0]_inst_i_2_n_0
+ SLICE_X83Y80 LUT6 (Prop_lut6_I0_O) 0.124 2.615 r vgaInterface/vgaBlue_OBUF[0]_inst_i_1/O
+ net (fo=6, routed) 0.721 3.335 vgaInterface/vgaBlue_OBUF[0]
+ SLICE_X83Y81 LUT6 (Prop_lut6_I0_O) 0.124 3.459 r vgaInterface/vgaRed_OBUF[3]_inst_i_3/O
+ net (fo=7, routed) 0.750 4.209 runnerObject/vgaGreen[0]
+ SLICE_X87Y84 LUT5 (Prop_lut5_I0_O) 0.124 4.333 r runnerObject/vgaGreen_OBUF[0]_inst_i_1/O
+ net (fo=1, routed) 3.708 8.041 vgaGreen_OBUF[0]
+ C6 OBUF (Prop_obuf_I_O) 3.538 11.579 r vgaGreen_OBUF[0]_inst/O
+ net (fo=0) 0.000 11.579 vgaGreen[0]
+ C6 r vgaGreen[0] (OUT)
+ ------------------------------------------------------------------- -------------------
+
+
+
+
+
+Min Delay Paths
+--------------------------------------------------------------------------------------
+Slack: inf
+ Source: collisionDetection/collision_cnt_reg[12]/C
+ (rising edge-triggered cell FDCE clocked by clk_out1_clk_wiz_0_1 {rise@0.000ns fall@20.000ns period=40.000ns})
+ Destination: led[12]
+ (output port)
+ Path Group: (none)
+ Path Type: Min at Fast Process Corner
+ Data Path Delay: 1.741ns (logic 1.374ns (78.953%) route 0.366ns (21.047%))
+ Logic Levels: 1 (OBUF=1)
+ Clock Uncertainty: 0.195ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE
+ Total System Jitter (TSJ): 0.050ns
+ Discrete Jitter (DJ): 0.175ns
+ Phase Error (PE): 0.104ns
+
+ Location Delay type Incr(ns) Path(ns) Netlist Resource(s)
+ ------------------------------------------------------------------- -------------------
+ (clock clk_out1_clk_wiz_0_1 rise edge)
+ 0.000 0.000 r
+ E3 0.000 0.000 r clk (IN)
+ net (fo=0) 0.000 0.000 pixelClk/inst/clk_in1
+ E3 IBUF (Prop_ibuf_I_O) 0.250 0.250 r pixelClk/inst/clkin1_ibufg/O
+ net (fo=1, routed) 0.440 0.690 pixelClk/inst/clk_in1_clk_wiz_0
+ MMCME2_ADV_X1Y2 MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKOUT0)
+ -2.379 -1.689 r pixelClk/inst/mmcm_adv_inst/CLKOUT0
+ net (fo=1, routed) 0.499 -1.190 pixelClk/inst/clk_out1_clk_wiz_0
+ BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.026 -1.164 r pixelClk/inst/clkout1_buf/O
+ net (fo=127, routed) 0.599 -0.565 collisionDetection/CLK
+ SLICE_X89Y69 FDCE r collisionDetection/collision_cnt_reg[12]/C
+ ------------------------------------------------------------------- -------------------
+ SLICE_X89Y69 FDCE (Prop_fdce_C_Q) 0.141 -0.424 r collisionDetection/collision_cnt_reg[12]/Q
+ net (fo=3, routed) 0.366 -0.058 led_OBUF[12]
+ P5 OBUF (Prop_obuf_I_O) 1.233 1.175 r led_OBUF[12]_inst/O
+ net (fo=0) 0.000 1.175 led[12]
+ P5 r led[12] (OUT)
+ ------------------------------------------------------------------- -------------------
+
+Slack: inf
+ Source: collisionDetection/collision_cnt_reg[11]/C
+ (rising edge-triggered cell FDCE clocked by clk_out1_clk_wiz_0_1 {rise@0.000ns fall@20.000ns period=40.000ns})
+ Destination: led[11]
+ (output port)
+ Path Group: (none)
+ Path Type: Min at Fast Process Corner
+ Data Path Delay: 1.753ns (logic 1.395ns (79.584%) route 0.358ns (20.416%))
+ Logic Levels: 1 (OBUF=1)
+ Clock Uncertainty: 0.195ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE
+ Total System Jitter (TSJ): 0.050ns
+ Discrete Jitter (DJ): 0.175ns
+ Phase Error (PE): 0.104ns
+
+ Location Delay type Incr(ns) Path(ns) Netlist Resource(s)
+ ------------------------------------------------------------------- -------------------
+ (clock clk_out1_clk_wiz_0_1 rise edge)
+ 0.000 0.000 r
+ E3 0.000 0.000 r clk (IN)
+ net (fo=0) 0.000 0.000 pixelClk/inst/clk_in1
+ E3 IBUF (Prop_ibuf_I_O) 0.250 0.250 r pixelClk/inst/clkin1_ibufg/O
+ net (fo=1, routed) 0.440 0.690 pixelClk/inst/clk_in1_clk_wiz_0
+ MMCME2_ADV_X1Y2 MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKOUT0)
+ -2.379 -1.689 r pixelClk/inst/mmcm_adv_inst/CLKOUT0
+ net (fo=1, routed) 0.499 -1.190 pixelClk/inst/clk_out1_clk_wiz_0
+ BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.026 -1.164 r pixelClk/inst/clkout1_buf/O
+ net (fo=127, routed) 0.601 -0.563 collisionDetection/CLK
+ SLICE_X88Y67 FDCE r collisionDetection/collision_cnt_reg[11]/C
+ ------------------------------------------------------------------- -------------------
+ SLICE_X88Y67 FDCE (Prop_fdce_C_Q) 0.164 -0.399 r collisionDetection/collision_cnt_reg[11]/Q
+ net (fo=3, routed) 0.358 -0.041 led_OBUF[11]
+ R1 OBUF (Prop_obuf_I_O) 1.231 1.190 r led_OBUF[11]_inst/O
+ net (fo=0) 0.000 1.190 led[11]
+ R1 r led[11] (OUT)
+ ------------------------------------------------------------------- -------------------
+
+Slack: inf
+ Source: collisionDetection/collision_cnt_reg[15]/C
+ (rising edge-triggered cell FDCE clocked by clk_out1_clk_wiz_0_1 {rise@0.000ns fall@20.000ns period=40.000ns})
+ Destination: led[15]
+ (output port)
+ Path Group: (none)
+ Path Type: Min at Fast Process Corner
+ Data Path Delay: 1.757ns (logic 1.398ns (79.568%) route 0.359ns (20.432%))
+ Logic Levels: 1 (OBUF=1)
+ Clock Uncertainty: 0.195ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE
+ Total System Jitter (TSJ): 0.050ns
+ Discrete Jitter (DJ): 0.175ns
+ Phase Error (PE): 0.104ns
+
+ Location Delay type Incr(ns) Path(ns) Netlist Resource(s)
+ ------------------------------------------------------------------- -------------------
+ (clock clk_out1_clk_wiz_0_1 rise edge)
+ 0.000 0.000 r
+ E3 0.000 0.000 r clk (IN)
+ net (fo=0) 0.000 0.000 pixelClk/inst/clk_in1
+ E3 IBUF (Prop_ibuf_I_O) 0.250 0.250 r pixelClk/inst/clkin1_ibufg/O
+ net (fo=1, routed) 0.440 0.690 pixelClk/inst/clk_in1_clk_wiz_0
+ MMCME2_ADV_X1Y2 MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKOUT0)
+ -2.379 -1.689 r pixelClk/inst/mmcm_adv_inst/CLKOUT0
+ net (fo=1, routed) 0.499 -1.190 pixelClk/inst/clk_out1_clk_wiz_0
+ BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.026 -1.164 r pixelClk/inst/clkout1_buf/O
+ net (fo=127, routed) 0.599 -0.565 collisionDetection/CLK
+ SLICE_X88Y69 FDCE r collisionDetection/collision_cnt_reg[15]/C
+ ------------------------------------------------------------------- -------------------
+ SLICE_X88Y69 FDCE (Prop_fdce_C_Q) 0.164 -0.401 r collisionDetection/collision_cnt_reg[15]/Q
+ net (fo=3, routed) 0.359 -0.042 led_OBUF[15]
+ P2 OBUF (Prop_obuf_I_O) 1.234 1.192 r led_OBUF[15]_inst/O
+ net (fo=0) 0.000 1.192 led[15]
+ P2 r led[15] (OUT)
+ ------------------------------------------------------------------- -------------------
+
+Slack: inf
+ Source: collisionDetection/collision_cnt_reg[14]/C
+ (rising edge-triggered cell FDCE clocked by clk_out1_clk_wiz_0_1 {rise@0.000ns fall@20.000ns period=40.000ns})
+ Destination: led[14]
+ (output port)
+ Path Group: (none)
+ Path Type: Min at Fast Process Corner
+ Data Path Delay: 1.770ns (logic 1.412ns (79.757%) route 0.358ns (20.243%))
+ Logic Levels: 1 (OBUF=1)
+ Clock Uncertainty: 0.195ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE
+ Total System Jitter (TSJ): 0.050ns
+ Discrete Jitter (DJ): 0.175ns
+ Phase Error (PE): 0.104ns
+
+ Location Delay type Incr(ns) Path(ns) Netlist Resource(s)
+ ------------------------------------------------------------------- -------------------
+ (clock clk_out1_clk_wiz_0_1 rise edge)
+ 0.000 0.000 r
+ E3 0.000 0.000 r clk (IN)
+ net (fo=0) 0.000 0.000 pixelClk/inst/clk_in1
+ E3 IBUF (Prop_ibuf_I_O) 0.250 0.250 r pixelClk/inst/clkin1_ibufg/O
+ net (fo=1, routed) 0.440 0.690 pixelClk/inst/clk_in1_clk_wiz_0
+ MMCME2_ADV_X1Y2 MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKOUT0)
+ -2.379 -1.689 r pixelClk/inst/mmcm_adv_inst/CLKOUT0
+ net (fo=1, routed) 0.499 -1.190 pixelClk/inst/clk_out1_clk_wiz_0
+ BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.026 -1.164 r pixelClk/inst/clkout1_buf/O
+ net (fo=127, routed) 0.599 -0.565 collisionDetection/CLK
+ SLICE_X89Y69 FDCE r collisionDetection/collision_cnt_reg[14]/C
+ ------------------------------------------------------------------- -------------------
+ SLICE_X89Y69 FDCE (Prop_fdce_C_Q) 0.128 -0.437 r collisionDetection/collision_cnt_reg[14]/Q
+ net (fo=4, routed) 0.358 -0.079 led_OBUF[14]
+ R2 OBUF (Prop_obuf_I_O) 1.284 1.205 r led_OBUF[14]_inst/O
+ net (fo=0) 0.000 1.205 led[14]
+ R2 r led[14] (OUT)
+ ------------------------------------------------------------------- -------------------
+
+Slack: inf
+ Source: collisionDetection/collision_cnt_reg[1]/C
+ (rising edge-triggered cell FDCE clocked by clk_out1_clk_wiz_0_1 {rise@0.000ns fall@20.000ns period=40.000ns})
+ Destination: led[1]
+ (output port)
+ Path Group: (none)
+ Path Type: Min at Fast Process Corner
+ Data Path Delay: 1.861ns (logic 1.409ns (75.700%) route 0.452ns (24.300%))
+ Logic Levels: 1 (OBUF=1)
+ Clock Uncertainty: 0.195ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE
+ Total System Jitter (TSJ): 0.050ns
+ Discrete Jitter (DJ): 0.175ns
+ Phase Error (PE): 0.104ns
+
+ Location Delay type Incr(ns) Path(ns) Netlist Resource(s)
+ ------------------------------------------------------------------- -------------------
+ (clock clk_out1_clk_wiz_0_1 rise edge)
+ 0.000 0.000 r
+ E3 0.000 0.000 r clk (IN)
+ net (fo=0) 0.000 0.000 pixelClk/inst/clk_in1
+ E3 IBUF (Prop_ibuf_I_O) 0.250 0.250 r pixelClk/inst/clkin1_ibufg/O
+ net (fo=1, routed) 0.440 0.690 pixelClk/inst/clk_in1_clk_wiz_0
+ MMCME2_ADV_X1Y2 MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKOUT0)
+ -2.379 -1.689 r pixelClk/inst/mmcm_adv_inst/CLKOUT0
+ net (fo=1, routed) 0.499 -1.190 pixelClk/inst/clk_out1_clk_wiz_0
+ BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.026 -1.164 r pixelClk/inst/clkout1_buf/O
+ net (fo=127, routed) 0.601 -0.563 collisionDetection/CLK
+ SLICE_X89Y67 FDCE r collisionDetection/collision_cnt_reg[1]/C
+ ------------------------------------------------------------------- -------------------
+ SLICE_X89Y67 FDCE (Prop_fdce_C_Q) 0.141 -0.422 r collisionDetection/collision_cnt_reg[1]/Q
+ net (fo=3, routed) 0.452 0.030 led_OBUF[1]
+ V9 OBUF (Prop_obuf_I_O) 1.268 1.298 r led_OBUF[1]_inst/O
+ net (fo=0) 0.000 1.298 led[1]
+ V9 r led[1] (OUT)
+ ------------------------------------------------------------------- -------------------
+
+Slack: inf
+ Source: collisionDetection/collision_cnt_reg[5]/C
+ (rising edge-triggered cell FDCE clocked by clk_out1_clk_wiz_0_1 {rise@0.000ns fall@20.000ns period=40.000ns})
+ Destination: led[5]
+ (output port)
+ Path Group: (none)
+ Path Type: Min at Fast Process Corner
+ Data Path Delay: 1.867ns (logic 1.393ns (74.599%) route 0.474ns (25.401%))
+ Logic Levels: 1 (OBUF=1)
+ Clock Uncertainty: 0.195ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE
+ Total System Jitter (TSJ): 0.050ns
+ Discrete Jitter (DJ): 0.175ns
+ Phase Error (PE): 0.104ns
+
+ Location Delay type Incr(ns) Path(ns) Netlist Resource(s)
+ ------------------------------------------------------------------- -------------------
+ (clock clk_out1_clk_wiz_0_1 rise edge)
+ 0.000 0.000 r
+ E3 0.000 0.000 r clk (IN)
+ net (fo=0) 0.000 0.000 pixelClk/inst/clk_in1
+ E3 IBUF (Prop_ibuf_I_O) 0.250 0.250 r pixelClk/inst/clkin1_ibufg/O
+ net (fo=1, routed) 0.440 0.690 pixelClk/inst/clk_in1_clk_wiz_0
+ MMCME2_ADV_X1Y2 MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKOUT0)
+ -2.379 -1.689 r pixelClk/inst/mmcm_adv_inst/CLKOUT0
+ net (fo=1, routed) 0.499 -1.190 pixelClk/inst/clk_out1_clk_wiz_0
+ BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.026 -1.164 r pixelClk/inst/clkout1_buf/O
+ net (fo=127, routed) 0.600 -0.564 collisionDetection/CLK
+ SLICE_X89Y68 FDCE r collisionDetection/collision_cnt_reg[5]/C
+ ------------------------------------------------------------------- -------------------
+ SLICE_X89Y68 FDCE (Prop_fdce_C_Q) 0.141 -0.423 r collisionDetection/collision_cnt_reg[5]/Q
+ net (fo=3, routed) 0.474 0.051 led_OBUF[5]
+ T4 OBUF (Prop_obuf_I_O) 1.252 1.303 r led_OBUF[5]_inst/O
+ net (fo=0) 0.000 1.303 led[5]
+ T4 r led[5] (OUT)
+ ------------------------------------------------------------------- -------------------
+
+Slack: inf
+ Source: collisionDetection/collision_cnt_reg[9]_lopt_replica/C
+ (rising edge-triggered cell FDCE clocked by clk_out1_clk_wiz_0_1 {rise@0.000ns fall@20.000ns period=40.000ns})
+ Destination: led[9]
+ (output port)
+ Path Group: (none)
+ Path Type: Min at Fast Process Corner
+ Data Path Delay: 1.891ns (logic 1.412ns (74.707%) route 0.478ns (25.293%))
+ Logic Levels: 1 (OBUF=1)
+ Clock Uncertainty: 0.195ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE
+ Total System Jitter (TSJ): 0.050ns
+ Discrete Jitter (DJ): 0.175ns
+ Phase Error (PE): 0.104ns
+
+ Location Delay type Incr(ns) Path(ns) Netlist Resource(s)
+ ------------------------------------------------------------------- -------------------
+ (clock clk_out1_clk_wiz_0_1 rise edge)
+ 0.000 0.000 r
+ E3 0.000 0.000 r clk (IN)
+ net (fo=0) 0.000 0.000 pixelClk/inst/clk_in1
+ E3 IBUF (Prop_ibuf_I_O) 0.250 0.250 r pixelClk/inst/clkin1_ibufg/O
+ net (fo=1, routed) 0.440 0.690 pixelClk/inst/clk_in1_clk_wiz_0
+ MMCME2_ADV_X1Y2 MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKOUT0)
+ -2.379 -1.689 r pixelClk/inst/mmcm_adv_inst/CLKOUT0
+ net (fo=1, routed) 0.499 -1.190 pixelClk/inst/clk_out1_clk_wiz_0
+ BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.026 -1.164 r pixelClk/inst/clkout1_buf/O
+ net (fo=127, routed) 0.594 -0.570 collisionDetection/CLK
+ SLICE_X89Y74 FDCE r collisionDetection/collision_cnt_reg[9]_lopt_replica/C
+ ------------------------------------------------------------------- -------------------
+ SLICE_X89Y74 FDCE (Prop_fdce_C_Q) 0.141 -0.429 r collisionDetection/collision_cnt_reg[9]_lopt_replica/Q
+ net (fo=1, routed) 0.478 0.049 lopt_2
+ U3 OBUF (Prop_obuf_I_O) 1.271 1.320 r led_OBUF[9]_inst/O
+ net (fo=0) 0.000 1.320 led[9]
+ U3 r led[9] (OUT)
+ ------------------------------------------------------------------- -------------------
+
+Slack: inf
+ Source: collisionDetection/collision_cnt_reg[7]/C
+ (rising edge-triggered cell FDCE clocked by clk_out1_clk_wiz_0_1 {rise@0.000ns fall@20.000ns period=40.000ns})
+ Destination: led[7]
+ (output port)
+ Path Group: (none)
+ Path Type: Min at Fast Process Corner
+ Data Path Delay: 1.920ns (logic 1.404ns (73.103%) route 0.516ns (26.897%))
+ Logic Levels: 1 (OBUF=1)
+ Clock Uncertainty: 0.195ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE
+ Total System Jitter (TSJ): 0.050ns
+ Discrete Jitter (DJ): 0.175ns
+ Phase Error (PE): 0.104ns
+
+ Location Delay type Incr(ns) Path(ns) Netlist Resource(s)
+ ------------------------------------------------------------------- -------------------
+ (clock clk_out1_clk_wiz_0_1 rise edge)
+ 0.000 0.000 r
+ E3 0.000 0.000 r clk (IN)
+ net (fo=0) 0.000 0.000 pixelClk/inst/clk_in1
+ E3 IBUF (Prop_ibuf_I_O) 0.250 0.250 r pixelClk/inst/clkin1_ibufg/O
+ net (fo=1, routed) 0.440 0.690 pixelClk/inst/clk_in1_clk_wiz_0
+ MMCME2_ADV_X1Y2 MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKOUT0)
+ -2.379 -1.689 r pixelClk/inst/mmcm_adv_inst/CLKOUT0
+ net (fo=1, routed) 0.499 -1.190 pixelClk/inst/clk_out1_clk_wiz_0
+ BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.026 -1.164 r pixelClk/inst/clkout1_buf/O
+ net (fo=127, routed) 0.600 -0.564 collisionDetection/CLK
+ SLICE_X89Y68 FDCE r collisionDetection/collision_cnt_reg[7]/C
+ ------------------------------------------------------------------- -------------------
+ SLICE_X89Y68 FDCE (Prop_fdce_C_Q) 0.141 -0.423 r collisionDetection/collision_cnt_reg[7]/Q
+ net (fo=3, routed) 0.516 0.093 led_OBUF[7]
+ U6 OBUF (Prop_obuf_I_O) 1.263 1.356 r led_OBUF[7]_inst/O
+ net (fo=0) 0.000 1.356 led[7]
+ U6 r led[7] (OUT)
+ ------------------------------------------------------------------- -------------------
+
+Slack: inf
+ Source: collisionDetection/collision_cnt_reg[0]/C
+ (rising edge-triggered cell FDCE clocked by clk_out1_clk_wiz_0_1 {rise@0.000ns fall@20.000ns period=40.000ns})
+ Destination: led[0]
+ (output port)
+ Path Group: (none)
+ Path Type: Min at Fast Process Corner
+ Data Path Delay: 1.934ns (logic 1.394ns (72.063%) route 0.540ns (27.937%))
+ Logic Levels: 1 (OBUF=1)
+ Clock Uncertainty: 0.195ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE
+ Total System Jitter (TSJ): 0.050ns
+ Discrete Jitter (DJ): 0.175ns
+ Phase Error (PE): 0.104ns
+
+ Location Delay type Incr(ns) Path(ns) Netlist Resource(s)
+ ------------------------------------------------------------------- -------------------
+ (clock clk_out1_clk_wiz_0_1 rise edge)
+ 0.000 0.000 r
+ E3 0.000 0.000 r clk (IN)
+ net (fo=0) 0.000 0.000 pixelClk/inst/clk_in1
+ E3 IBUF (Prop_ibuf_I_O) 0.250 0.250 r pixelClk/inst/clkin1_ibufg/O
+ net (fo=1, routed) 0.440 0.690 pixelClk/inst/clk_in1_clk_wiz_0
+ MMCME2_ADV_X1Y2 MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKOUT0)
+ -2.379 -1.689 r pixelClk/inst/mmcm_adv_inst/CLKOUT0
+ net (fo=1, routed) 0.499 -1.190 pixelClk/inst/clk_out1_clk_wiz_0
+ BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.026 -1.164 r pixelClk/inst/clkout1_buf/O
+ net (fo=127, routed) 0.601 -0.563 collisionDetection/CLK
+ SLICE_X89Y67 FDCE r collisionDetection/collision_cnt_reg[0]/C
+ ------------------------------------------------------------------- -------------------
+ SLICE_X89Y67 FDCE (Prop_fdce_C_Q) 0.141 -0.422 r collisionDetection/collision_cnt_reg[0]/Q
+ net (fo=2, routed) 0.540 0.118 led_OBUF[0]
+ T8 OBUF (Prop_obuf_I_O) 1.253 1.371 r led_OBUF[0]_inst/O
+ net (fo=0) 0.000 1.371 led[0]
+ T8 r led[0] (OUT)
+ ------------------------------------------------------------------- -------------------
+
+Slack: inf
+ Source: collisionDetection/collision_cnt_reg[4]/C
+ (rising edge-triggered cell FDCE clocked by clk_out1_clk_wiz_0_1 {rise@0.000ns fall@20.000ns period=40.000ns})
+ Destination: led[4]
+ (output port)
+ Path Group: (none)
+ Path Type: Min at Fast Process Corner
+ Data Path Delay: 1.940ns (logic 1.439ns (74.195%) route 0.501ns (25.805%))
+ Logic Levels: 1 (OBUF=1)
+ Clock Uncertainty: 0.195ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE
+ Total System Jitter (TSJ): 0.050ns
+ Discrete Jitter (DJ): 0.175ns
+ Phase Error (PE): 0.104ns
+
+ Location Delay type Incr(ns) Path(ns) Netlist Resource(s)
+ ------------------------------------------------------------------- -------------------
+ (clock clk_out1_clk_wiz_0_1 rise edge)
+ 0.000 0.000 r
+ E3 0.000 0.000 r clk (IN)
+ net (fo=0) 0.000 0.000 pixelClk/inst/clk_in1
+ E3 IBUF (Prop_ibuf_I_O) 0.250 0.250 r pixelClk/inst/clkin1_ibufg/O
+ net (fo=1, routed) 0.440 0.690 pixelClk/inst/clk_in1_clk_wiz_0
+ MMCME2_ADV_X1Y2 MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKOUT0)
+ -2.379 -1.689 r pixelClk/inst/mmcm_adv_inst/CLKOUT0
+ net (fo=1, routed) 0.499 -1.190 pixelClk/inst/clk_out1_clk_wiz_0
+ BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.026 -1.164 r pixelClk/inst/clkout1_buf/O
+ net (fo=127, routed) 0.600 -0.564 collisionDetection/CLK
+ SLICE_X89Y68 FDCE r collisionDetection/collision_cnt_reg[4]/C
+ ------------------------------------------------------------------- -------------------
+ SLICE_X89Y68 FDCE (Prop_fdce_C_Q) 0.128 -0.436 r collisionDetection/collision_cnt_reg[4]/Q
+ net (fo=4, routed) 0.501 0.064 led_OBUF[4]
+ T5 OBUF (Prop_obuf_I_O) 1.311 1.375 r led_OBUF[4]_inst/O
+ net (fo=0) 0.000 1.375 led[4]
+ T5 r led[4] (OUT)
+ ------------------------------------------------------------------- -------------------
+
+
+
+
+
+--------------------------------------------------------------------------------------
+Path Group: (none)
+From Clock: clkfbout_clk_wiz_0
+ To Clock:
+
+Max Delay 1 Endpoint
+Min Delay 1 Endpoint
+--------------------------------------------------------------------------------------
+
+
+Max Delay Paths
+--------------------------------------------------------------------------------------
+Slack: inf
+ Source: pixelClk/inst/mmcm_adv_inst/CLKFBOUT
+ (clock source 'clkfbout_clk_wiz_0' {rise@0.000ns fall@5.000ns period=10.000ns})
+ Destination: pixelClk/inst/mmcm_adv_inst/CLKFBIN
+ Path Group: (none)
+ Path Type: Max at Fast Process Corner
+ Data Path Delay: 1.396ns (logic 0.029ns (2.077%) route 1.367ns (97.923%))
+ Logic Levels: 1 (BUFG=1)
+ Clock Uncertainty: 0.156ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE
+ Total System Jitter (TSJ): 0.050ns
+ Discrete Jitter (DJ): 0.090ns
+ Phase Error (PE): 0.104ns
+
+ Location Delay type Incr(ns) Path(ns) Netlist Resource(s)
+ ------------------------------------------------------------------- -------------------
+ (clock clkfbout_clk_wiz_0 fall edge)
+ 5.000 5.000 f
+ E3 0.000 5.000 f clk (IN)
+ net (fo=0) 0.000 5.000 pixelClk/inst/clk_in1
+ E3 IBUF (Prop_ibuf_I_O) 0.438 5.438 f pixelClk/inst/clkin1_ibufg/O
+ net (fo=1, routed) 0.480 5.918 pixelClk/inst/clk_in1_clk_wiz_0
+ ------------------------------------------------------------------- -------------------
+ MMCME2_ADV_X1Y2 MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKFBOUT)
+ -3.163 2.755 f pixelClk/inst/mmcm_adv_inst/CLKFBOUT
+ net (fo=1, routed) 0.544 3.298 pixelClk/inst/clkfbout_clk_wiz_0
+ BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.029 3.327 f pixelClk/inst/clkf_buf/O
+ net (fo=1, routed) 0.824 4.151 pixelClk/inst/clkfbout_buf_clk_wiz_0
+ MMCME2_ADV_X1Y2 MMCME2_ADV f pixelClk/inst/mmcm_adv_inst/CLKFBIN
+ ------------------------------------------------------------------- -------------------
+
+
+
+
+
+Min Delay Paths
+--------------------------------------------------------------------------------------
+Slack: inf
+ Source: pixelClk/inst/mmcm_adv_inst/CLKFBOUT
+ (clock source 'clkfbout_clk_wiz_0' {rise@0.000ns fall@5.000ns period=10.000ns})
+ Destination: pixelClk/inst/mmcm_adv_inst/CLKFBIN
+ Path Group: (none)
+ Path Type: Min at Slow Process Corner
+ Data Path Delay: 3.236ns (logic 0.091ns (2.812%) route 3.145ns (97.188%))
+ Logic Levels: 1 (BUFG=1)
+ Clock Uncertainty: 0.156ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE
+ Total System Jitter (TSJ): 0.050ns
+ Discrete Jitter (DJ): 0.090ns
+ Phase Error (PE): 0.104ns
+
+ Location Delay type Incr(ns) Path(ns) Netlist Resource(s)
+ ------------------------------------------------------------------- -------------------
+ (clock clkfbout_clk_wiz_0 rise edge)
+ 0.000 0.000 r
+ E3 0.000 0.000 r clk (IN)
+ net (fo=0) 0.000 0.000 pixelClk/inst/clk_in1
+ E3 IBUF (Prop_ibuf_I_O) 1.411 1.411 r pixelClk/inst/clkin1_ibufg/O
+ net (fo=1, routed) 1.162 2.573 pixelClk/inst/clk_in1_clk_wiz_0
+ ------------------------------------------------------------------- -------------------
+ MMCME2_ADV_X1Y2 MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKFBOUT)
+ -7.324 -4.751 r pixelClk/inst/mmcm_adv_inst/CLKFBOUT
+ net (fo=1, routed) 1.639 -3.112 pixelClk/inst/clkfbout_clk_wiz_0
+ BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.091 -3.021 r pixelClk/inst/clkf_buf/O
+ net (fo=1, routed) 1.506 -1.515 pixelClk/inst/clkfbout_buf_clk_wiz_0
+ MMCME2_ADV_X1Y2 MMCME2_ADV r pixelClk/inst/mmcm_adv_inst/CLKFBIN
+ ------------------------------------------------------------------- -------------------
+
+
+
+
+
+--------------------------------------------------------------------------------------
+Path Group: (none)
+From Clock: clkfbout_clk_wiz_0_1
+ To Clock:
+
+Max Delay 1 Endpoint
+Min Delay 1 Endpoint
+--------------------------------------------------------------------------------------
+
+
+Max Delay Paths
+--------------------------------------------------------------------------------------
+Slack: inf
+ Source: pixelClk/inst/mmcm_adv_inst/CLKFBOUT
+ (clock source 'clkfbout_clk_wiz_0_1' {rise@0.000ns fall@5.000ns period=10.000ns})
+ Destination: pixelClk/inst/mmcm_adv_inst/CLKFBIN
+ Path Group: (none)
+ Path Type: Max at Fast Process Corner
+ Data Path Delay: 1.396ns (logic 0.029ns (2.077%) route 1.367ns (97.923%))
+ Logic Levels: 1 (BUFG=1)
+ Clock Uncertainty: 0.155ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE
+ Total System Jitter (TSJ): 0.050ns
+ Discrete Jitter (DJ): 0.088ns
+ Phase Error (PE): 0.104ns
+
+ Location Delay type Incr(ns) Path(ns) Netlist Resource(s)
+ ------------------------------------------------------------------- -------------------
+ (clock clkfbout_clk_wiz_0_1 fall edge)
+ 5.000 5.000 f
+ E3 0.000 5.000 f clk (IN)
+ net (fo=0) 0.000 5.000 pixelClk/inst/clk_in1
+ E3 IBUF (Prop_ibuf_I_O) 0.438 5.438 f pixelClk/inst/clkin1_ibufg/O
+ net (fo=1, routed) 0.480 5.918 pixelClk/inst/clk_in1_clk_wiz_0
+ ------------------------------------------------------------------- -------------------
+ MMCME2_ADV_X1Y2 MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKFBOUT)
+ -3.163 2.755 f pixelClk/inst/mmcm_adv_inst/CLKFBOUT
+ net (fo=1, routed) 0.544 3.298 pixelClk/inst/clkfbout_clk_wiz_0
+ BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.029 3.327 f pixelClk/inst/clkf_buf/O
+ net (fo=1, routed) 0.824 4.151 pixelClk/inst/clkfbout_buf_clk_wiz_0
+ MMCME2_ADV_X1Y2 MMCME2_ADV f pixelClk/inst/mmcm_adv_inst/CLKFBIN
+ ------------------------------------------------------------------- -------------------
+
+
+
+
+
+Min Delay Paths
+--------------------------------------------------------------------------------------
+Slack: inf
+ Source: pixelClk/inst/mmcm_adv_inst/CLKFBOUT
+ (clock source 'clkfbout_clk_wiz_0_1' {rise@0.000ns fall@5.000ns period=10.000ns})
+ Destination: pixelClk/inst/mmcm_adv_inst/CLKFBIN
+ Path Group: (none)
+ Path Type: Min at Slow Process Corner
+ Data Path Delay: 3.236ns (logic 0.091ns (2.812%) route 3.145ns (97.188%))
+ Logic Levels: 1 (BUFG=1)
+ Clock Uncertainty: 0.155ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE
+ Total System Jitter (TSJ): 0.050ns
+ Discrete Jitter (DJ): 0.088ns
+ Phase Error (PE): 0.104ns
+
+ Location Delay type Incr(ns) Path(ns) Netlist Resource(s)
+ ------------------------------------------------------------------- -------------------
+ (clock clkfbout_clk_wiz_0_1 rise edge)
+ 0.000 0.000 r
+ E3 0.000 0.000 r clk (IN)
+ net (fo=0) 0.000 0.000 pixelClk/inst/clk_in1
+ E3 IBUF (Prop_ibuf_I_O) 1.411 1.411 r pixelClk/inst/clkin1_ibufg/O
+ net (fo=1, routed) 1.162 2.573 pixelClk/inst/clk_in1_clk_wiz_0
+ ------------------------------------------------------------------- -------------------
+ MMCME2_ADV_X1Y2 MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKFBOUT)
+ -7.324 -4.751 r pixelClk/inst/mmcm_adv_inst/CLKFBOUT
+ net (fo=1, routed) 1.639 -3.112 pixelClk/inst/clkfbout_clk_wiz_0
+ BUFGCTRL_X0Y17 BUFG (Prop_bufg_I_O) 0.091 -3.021 r pixelClk/inst/clkf_buf/O
+ net (fo=1, routed) 1.506 -1.515 pixelClk/inst/clkfbout_buf_clk_wiz_0
+ MMCME2_ADV_X1Y2 MMCME2_ADV r pixelClk/inst/mmcm_adv_inst/CLKFBIN
+ ------------------------------------------------------------------- -------------------
+
+
+
+
+
+--------------------------------------------------------------------------------------
+Path Group: (none)
+From Clock:
+ To Clock: clk_out1_clk_wiz_0
+
+Max Delay 99 Endpoints
+Min Delay 99 Endpoints
+--------------------------------------------------------------------------------------
+
+
+Max Delay Paths
+--------------------------------------------------------------------------------------
+Slack: inf
+ Source: btnCpuReset
+ (input port)
+ Destination: runnerObject/fcount_edge_reg[0]/CLR
+ (recovery check against rising-edge clock clk_out1_clk_wiz_0 {rise@0.000ns fall@20.000ns period=40.000ns})
+ Path Group: (none)
+ Path Type: Recovery (Max at Slow Process Corner)
+ Data Path Delay: 9.447ns (logic 1.631ns (17.265%) route 7.816ns (82.735%))
+ Logic Levels: 2 (IBUF=1 LUT1=1)
+ Clock Path Skew: -1.419ns (DCD - SCD + CPR)
+ Destination Clock Delay (DCD): -1.419ns
+ Source Clock Delay (SCD): 0.000ns
+ Clock Pessimism Removal (CPR): 0.000ns
+ Clock Uncertainty: 0.199ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE
+ Total System Jitter (TSJ): 0.050ns
+ Discrete Jitter (DJ): 0.182ns
+ Phase Error (PE): 0.104ns
+
+ Location Delay type Incr(ns) Path(ns) Netlist Resource(s)
+ ------------------------------------------------------------------- -------------------
+ C12 0.000 0.000 r btnCpuReset (IN)
+ net (fo=0) 0.000 0.000 btnCpuReset
+ C12 IBUF (Prop_ibuf_I_O) 1.507 1.507 r btnCpuReset_IBUF_inst/O
+ net (fo=2, routed) 5.471 6.978 vgaInterface/resetn
+ SLICE_X86Y85 LUT1 (Prop_lut1_I0_O) 0.124 7.102 f vgaInterface/button_up_shift_reg[0]_i_1/O
+ net (fo=86, routed) 2.344 9.447 runnerObject/fcount_edge_reg[0]_1
+ SLICE_X88Y70 FDCE f runnerObject/fcount_edge_reg[0]/CLR
+ ------------------------------------------------------------------- -------------------
+
+ (clock clk_out1_clk_wiz_0 rise edge)
+ 0.000 0.000 r
+ E3 0.000 0.000 r clk (IN)
+ net (fo=0) 0.000 0.000 pixelClk/inst/clk_in1
+ E3 IBUF (Prop_ibuf_I_O) 1.411 1.411 r pixelClk/inst/clkin1_ibufg/O
+ net (fo=1, routed) 1.162 2.573 pixelClk/inst/clk_in1_clk_wiz_0
+ MMCME2_ADV_X1Y2 MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKOUT0)
+ -7.324 -4.751 r pixelClk/inst/mmcm_adv_inst/CLKOUT0
+ net (fo=1, routed) 1.639 -3.112 pixelClk/inst/clk_out1_clk_wiz_0
+ BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.091 -3.021 r pixelClk/inst/clkout1_buf/O
+ net (fo=127, routed) 1.601 -1.419 runnerObject/clk_out1
+ SLICE_X88Y70 FDCE r runnerObject/fcount_edge_reg[0]/C
+
+Slack: inf
+ Source: btnCpuReset
+ (input port)
+ Destination: runnerObject/fcount_edge_reg[1]/CLR
+ (recovery check against rising-edge clock clk_out1_clk_wiz_0 {rise@0.000ns fall@20.000ns period=40.000ns})
+ Path Group: (none)
+ Path Type: Recovery (Max at Slow Process Corner)
+ Data Path Delay: 9.447ns (logic 1.631ns (17.265%) route 7.816ns (82.735%))
+ Logic Levels: 2 (IBUF=1 LUT1=1)
+ Clock Path Skew: -1.419ns (DCD - SCD + CPR)
+ Destination Clock Delay (DCD): -1.419ns
+ Source Clock Delay (SCD): 0.000ns
+ Clock Pessimism Removal (CPR): 0.000ns
+ Clock Uncertainty: 0.199ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE
+ Total System Jitter (TSJ): 0.050ns
+ Discrete Jitter (DJ): 0.182ns
+ Phase Error (PE): 0.104ns
+
+ Location Delay type Incr(ns) Path(ns) Netlist Resource(s)
+ ------------------------------------------------------------------- -------------------
+ C12 0.000 0.000 r btnCpuReset (IN)
+ net (fo=0) 0.000 0.000 btnCpuReset
+ C12 IBUF (Prop_ibuf_I_O) 1.507 1.507 r btnCpuReset_IBUF_inst/O
+ net (fo=2, routed) 5.471 6.978 vgaInterface/resetn
+ SLICE_X86Y85 LUT1 (Prop_lut1_I0_O) 0.124 7.102 f vgaInterface/button_up_shift_reg[0]_i_1/O
+ net (fo=86, routed) 2.344 9.447 runnerObject/fcount_edge_reg[0]_1
+ SLICE_X88Y70 FDCE f runnerObject/fcount_edge_reg[1]/CLR
+ ------------------------------------------------------------------- -------------------
+
+ (clock clk_out1_clk_wiz_0 rise edge)
+ 0.000 0.000 r
+ E3 0.000 0.000 r clk (IN)
+ net (fo=0) 0.000 0.000 pixelClk/inst/clk_in1
+ E3 IBUF (Prop_ibuf_I_O) 1.411 1.411 r pixelClk/inst/clkin1_ibufg/O
+ net (fo=1, routed) 1.162 2.573 pixelClk/inst/clk_in1_clk_wiz_0
+ MMCME2_ADV_X1Y2 MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKOUT0)
+ -7.324 -4.751 r pixelClk/inst/mmcm_adv_inst/CLKOUT0
+ net (fo=1, routed) 1.639 -3.112 pixelClk/inst/clk_out1_clk_wiz_0
+ BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.091 -3.021 r pixelClk/inst/clkout1_buf/O
+ net (fo=127, routed) 1.601 -1.419 runnerObject/clk_out1
+ SLICE_X88Y70 FDCE r runnerObject/fcount_edge_reg[1]/C
+
+Slack: inf
+ Source: btnCpuReset
+ (input port)
+ Destination: runnerObject/fcount_edge_reg[2]/CLR
+ (recovery check against rising-edge clock clk_out1_clk_wiz_0 {rise@0.000ns fall@20.000ns period=40.000ns})
+ Path Group: (none)
+ Path Type: Recovery (Max at Slow Process Corner)
+ Data Path Delay: 9.447ns (logic 1.631ns (17.265%) route 7.816ns (82.735%))
+ Logic Levels: 2 (IBUF=1 LUT1=1)
+ Clock Path Skew: -1.419ns (DCD - SCD + CPR)
+ Destination Clock Delay (DCD): -1.419ns
+ Source Clock Delay (SCD): 0.000ns
+ Clock Pessimism Removal (CPR): 0.000ns
+ Clock Uncertainty: 0.199ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE
+ Total System Jitter (TSJ): 0.050ns
+ Discrete Jitter (DJ): 0.182ns
+ Phase Error (PE): 0.104ns
+
+ Location Delay type Incr(ns) Path(ns) Netlist Resource(s)
+ ------------------------------------------------------------------- -------------------
+ C12 0.000 0.000 r btnCpuReset (IN)
+ net (fo=0) 0.000 0.000 btnCpuReset
+ C12 IBUF (Prop_ibuf_I_O) 1.507 1.507 r btnCpuReset_IBUF_inst/O
+ net (fo=2, routed) 5.471 6.978 vgaInterface/resetn
+ SLICE_X86Y85 LUT1 (Prop_lut1_I0_O) 0.124 7.102 f vgaInterface/button_up_shift_reg[0]_i_1/O
+ net (fo=86, routed) 2.344 9.447 runnerObject/fcount_edge_reg[0]_1
+ SLICE_X88Y70 FDCE f runnerObject/fcount_edge_reg[2]/CLR
+ ------------------------------------------------------------------- -------------------
+
+ (clock clk_out1_clk_wiz_0 rise edge)
+ 0.000 0.000 r
+ E3 0.000 0.000 r clk (IN)
+ net (fo=0) 0.000 0.000 pixelClk/inst/clk_in1
+ E3 IBUF (Prop_ibuf_I_O) 1.411 1.411 r pixelClk/inst/clkin1_ibufg/O
+ net (fo=1, routed) 1.162 2.573 pixelClk/inst/clk_in1_clk_wiz_0
+ MMCME2_ADV_X1Y2 MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKOUT0)
+ -7.324 -4.751 r pixelClk/inst/mmcm_adv_inst/CLKOUT0
+ net (fo=1, routed) 1.639 -3.112 pixelClk/inst/clk_out1_clk_wiz_0
+ BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.091 -3.021 r pixelClk/inst/clkout1_buf/O
+ net (fo=127, routed) 1.601 -1.419 runnerObject/clk_out1
+ SLICE_X88Y70 FDCE r runnerObject/fcount_edge_reg[2]/C
+
+Slack: inf
+ Source: btnCpuReset
+ (input port)
+ Destination: runnerObject/fcount_edge_reg[3]/CLR
+ (recovery check against rising-edge clock clk_out1_clk_wiz_0 {rise@0.000ns fall@20.000ns period=40.000ns})
+ Path Group: (none)
+ Path Type: Recovery (Max at Slow Process Corner)
+ Data Path Delay: 9.447ns (logic 1.631ns (17.265%) route 7.816ns (82.735%))
+ Logic Levels: 2 (IBUF=1 LUT1=1)
+ Clock Path Skew: -1.419ns (DCD - SCD + CPR)
+ Destination Clock Delay (DCD): -1.419ns
+ Source Clock Delay (SCD): 0.000ns
+ Clock Pessimism Removal (CPR): 0.000ns
+ Clock Uncertainty: 0.199ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE
+ Total System Jitter (TSJ): 0.050ns
+ Discrete Jitter (DJ): 0.182ns
+ Phase Error (PE): 0.104ns
+
+ Location Delay type Incr(ns) Path(ns) Netlist Resource(s)
+ ------------------------------------------------------------------- -------------------
+ C12 0.000 0.000 r btnCpuReset (IN)
+ net (fo=0) 0.000 0.000 btnCpuReset
+ C12 IBUF (Prop_ibuf_I_O) 1.507 1.507 r btnCpuReset_IBUF_inst/O
+ net (fo=2, routed) 5.471 6.978 vgaInterface/resetn
+ SLICE_X86Y85 LUT1 (Prop_lut1_I0_O) 0.124 7.102 f vgaInterface/button_up_shift_reg[0]_i_1/O
+ net (fo=86, routed) 2.344 9.447 runnerObject/fcount_edge_reg[0]_1
+ SLICE_X88Y70 FDCE f runnerObject/fcount_edge_reg[3]/CLR
+ ------------------------------------------------------------------- -------------------
+
+ (clock clk_out1_clk_wiz_0 rise edge)
+ 0.000 0.000 r
+ E3 0.000 0.000 r clk (IN)
+ net (fo=0) 0.000 0.000 pixelClk/inst/clk_in1
+ E3 IBUF (Prop_ibuf_I_O) 1.411 1.411 r pixelClk/inst/clkin1_ibufg/O
+ net (fo=1, routed) 1.162 2.573 pixelClk/inst/clk_in1_clk_wiz_0
+ MMCME2_ADV_X1Y2 MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKOUT0)
+ -7.324 -4.751 r pixelClk/inst/mmcm_adv_inst/CLKOUT0
+ net (fo=1, routed) 1.639 -3.112 pixelClk/inst/clk_out1_clk_wiz_0
+ BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.091 -3.021 r pixelClk/inst/clkout1_buf/O
+ net (fo=127, routed) 1.601 -1.419 runnerObject/clk_out1
+ SLICE_X88Y70 FDCE r runnerObject/fcount_edge_reg[3]/C
+
+Slack: inf
+ Source: btnCpuReset
+ (input port)
+ Destination: vgaInterface/counter_f_reg[0]/CLR
+ (recovery check against rising-edge clock clk_out1_clk_wiz_0 {rise@0.000ns fall@20.000ns period=40.000ns})
+ Path Group: (none)
+ Path Type: Recovery (Max at Slow Process Corner)
+ Data Path Delay: 9.447ns (logic 1.631ns (17.265%) route 7.816ns (82.735%))
+ Logic Levels: 2 (IBUF=1 LUT1=1)
+ Clock Path Skew: -1.419ns (DCD - SCD + CPR)
+ Destination Clock Delay (DCD): -1.419ns
+ Source Clock Delay (SCD): 0.000ns
+ Clock Pessimism Removal (CPR): 0.000ns
+ Clock Uncertainty: 0.199ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE
+ Total System Jitter (TSJ): 0.050ns
+ Discrete Jitter (DJ): 0.182ns
+ Phase Error (PE): 0.104ns
+
+ Location Delay type Incr(ns) Path(ns) Netlist Resource(s)
+ ------------------------------------------------------------------- -------------------
+ C12 0.000 0.000 r btnCpuReset (IN)
+ net (fo=0) 0.000 0.000 btnCpuReset
+ C12 IBUF (Prop_ibuf_I_O) 1.507 1.507 r btnCpuReset_IBUF_inst/O
+ net (fo=2, routed) 5.471 6.978 vgaInterface/resetn
+ SLICE_X86Y85 LUT1 (Prop_lut1_I0_O) 0.124 7.102 f vgaInterface/button_up_shift_reg[0]_i_1/O
+ net (fo=86, routed) 2.344 9.447 vgaInterface/btnCpuReset
+ SLICE_X89Y70 FDCE f vgaInterface/counter_f_reg[0]/CLR
+ ------------------------------------------------------------------- -------------------
+
+ (clock clk_out1_clk_wiz_0 rise edge)
+ 0.000 0.000 r
+ E3 0.000 0.000 r clk (IN)
+ net (fo=0) 0.000 0.000 pixelClk/inst/clk_in1
+ E3 IBUF (Prop_ibuf_I_O) 1.411 1.411 r pixelClk/inst/clkin1_ibufg/O
+ net (fo=1, routed) 1.162 2.573 pixelClk/inst/clk_in1_clk_wiz_0
+ MMCME2_ADV_X1Y2 MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKOUT0)
+ -7.324 -4.751 r pixelClk/inst/mmcm_adv_inst/CLKOUT0
+ net (fo=1, routed) 1.639 -3.112 pixelClk/inst/clk_out1_clk_wiz_0
+ BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.091 -3.021 r pixelClk/inst/clkout1_buf/O
+ net (fo=127, routed) 1.601 -1.419 vgaInterface/clk_out1
+ SLICE_X89Y70 FDCE r vgaInterface/counter_f_reg[0]/C
+
+Slack: inf
+ Source: btnCpuReset
+ (input port)
+ Destination: vgaInterface/counter_f_reg[1]/CLR
+ (recovery check against rising-edge clock clk_out1_clk_wiz_0 {rise@0.000ns fall@20.000ns period=40.000ns})
+ Path Group: (none)
+ Path Type: Recovery (Max at Slow Process Corner)
+ Data Path Delay: 9.447ns (logic 1.631ns (17.265%) route 7.816ns (82.735%))
+ Logic Levels: 2 (IBUF=1 LUT1=1)
+ Clock Path Skew: -1.419ns (DCD - SCD + CPR)
+ Destination Clock Delay (DCD): -1.419ns
+ Source Clock Delay (SCD): 0.000ns
+ Clock Pessimism Removal (CPR): 0.000ns
+ Clock Uncertainty: 0.199ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE
+ Total System Jitter (TSJ): 0.050ns
+ Discrete Jitter (DJ): 0.182ns
+ Phase Error (PE): 0.104ns
+
+ Location Delay type Incr(ns) Path(ns) Netlist Resource(s)
+ ------------------------------------------------------------------- -------------------
+ C12 0.000 0.000 r btnCpuReset (IN)
+ net (fo=0) 0.000 0.000 btnCpuReset
+ C12 IBUF (Prop_ibuf_I_O) 1.507 1.507 r btnCpuReset_IBUF_inst/O
+ net (fo=2, routed) 5.471 6.978 vgaInterface/resetn
+ SLICE_X86Y85 LUT1 (Prop_lut1_I0_O) 0.124 7.102 f vgaInterface/button_up_shift_reg[0]_i_1/O
+ net (fo=86, routed) 2.344 9.447 vgaInterface/btnCpuReset
+ SLICE_X89Y70 FDCE f vgaInterface/counter_f_reg[1]/CLR
+ ------------------------------------------------------------------- -------------------
+
+ (clock clk_out1_clk_wiz_0 rise edge)
+ 0.000 0.000 r
+ E3 0.000 0.000 r clk (IN)
+ net (fo=0) 0.000 0.000 pixelClk/inst/clk_in1
+ E3 IBUF (Prop_ibuf_I_O) 1.411 1.411 r pixelClk/inst/clkin1_ibufg/O
+ net (fo=1, routed) 1.162 2.573 pixelClk/inst/clk_in1_clk_wiz_0
+ MMCME2_ADV_X1Y2 MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKOUT0)
+ -7.324 -4.751 r pixelClk/inst/mmcm_adv_inst/CLKOUT0
+ net (fo=1, routed) 1.639 -3.112 pixelClk/inst/clk_out1_clk_wiz_0
+ BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.091 -3.021 r pixelClk/inst/clkout1_buf/O
+ net (fo=127, routed) 1.601 -1.419 vgaInterface/clk_out1
+ SLICE_X89Y70 FDCE r vgaInterface/counter_f_reg[1]/C
+
+Slack: inf
+ Source: btnCpuReset
+ (input port)
+ Destination: vgaInterface/counter_f_reg[2]/CLR
+ (recovery check against rising-edge clock clk_out1_clk_wiz_0 {rise@0.000ns fall@20.000ns period=40.000ns})
+ Path Group: (none)
+ Path Type: Recovery (Max at Slow Process Corner)
+ Data Path Delay: 9.447ns (logic 1.631ns (17.265%) route 7.816ns (82.735%))
+ Logic Levels: 2 (IBUF=1 LUT1=1)
+ Clock Path Skew: -1.419ns (DCD - SCD + CPR)
+ Destination Clock Delay (DCD): -1.419ns
+ Source Clock Delay (SCD): 0.000ns
+ Clock Pessimism Removal (CPR): 0.000ns
+ Clock Uncertainty: 0.199ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE
+ Total System Jitter (TSJ): 0.050ns
+ Discrete Jitter (DJ): 0.182ns
+ Phase Error (PE): 0.104ns
+
+ Location Delay type Incr(ns) Path(ns) Netlist Resource(s)
+ ------------------------------------------------------------------- -------------------
+ C12 0.000 0.000 r btnCpuReset (IN)
+ net (fo=0) 0.000 0.000 btnCpuReset
+ C12 IBUF (Prop_ibuf_I_O) 1.507 1.507 r btnCpuReset_IBUF_inst/O
+ net (fo=2, routed) 5.471 6.978 vgaInterface/resetn
+ SLICE_X86Y85 LUT1 (Prop_lut1_I0_O) 0.124 7.102 f vgaInterface/button_up_shift_reg[0]_i_1/O
+ net (fo=86, routed) 2.344 9.447 vgaInterface/btnCpuReset
+ SLICE_X89Y70 FDCE f vgaInterface/counter_f_reg[2]/CLR
+ ------------------------------------------------------------------- -------------------
+
+ (clock clk_out1_clk_wiz_0 rise edge)
+ 0.000 0.000 r
+ E3 0.000 0.000 r clk (IN)
+ net (fo=0) 0.000 0.000 pixelClk/inst/clk_in1
+ E3 IBUF (Prop_ibuf_I_O) 1.411 1.411 r pixelClk/inst/clkin1_ibufg/O
+ net (fo=1, routed) 1.162 2.573 pixelClk/inst/clk_in1_clk_wiz_0
+ MMCME2_ADV_X1Y2 MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKOUT0)
+ -7.324 -4.751 r pixelClk/inst/mmcm_adv_inst/CLKOUT0
+ net (fo=1, routed) 1.639 -3.112 pixelClk/inst/clk_out1_clk_wiz_0
+ BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.091 -3.021 r pixelClk/inst/clkout1_buf/O
+ net (fo=127, routed) 1.601 -1.419 vgaInterface/clk_out1
+ SLICE_X89Y70 FDCE r vgaInterface/counter_f_reg[2]/C
+
+Slack: inf
+ Source: btnCpuReset
+ (input port)
+ Destination: vgaInterface/counter_f_reg[3]/CLR
+ (recovery check against rising-edge clock clk_out1_clk_wiz_0 {rise@0.000ns fall@20.000ns period=40.000ns})
+ Path Group: (none)
+ Path Type: Recovery (Max at Slow Process Corner)
+ Data Path Delay: 9.447ns (logic 1.631ns (17.265%) route 7.816ns (82.735%))
+ Logic Levels: 2 (IBUF=1 LUT1=1)
+ Clock Path Skew: -1.419ns (DCD - SCD + CPR)
+ Destination Clock Delay (DCD): -1.419ns
+ Source Clock Delay (SCD): 0.000ns
+ Clock Pessimism Removal (CPR): 0.000ns
+ Clock Uncertainty: 0.199ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE
+ Total System Jitter (TSJ): 0.050ns
+ Discrete Jitter (DJ): 0.182ns
+ Phase Error (PE): 0.104ns
+
+ Location Delay type Incr(ns) Path(ns) Netlist Resource(s)
+ ------------------------------------------------------------------- -------------------
+ C12 0.000 0.000 r btnCpuReset (IN)
+ net (fo=0) 0.000 0.000 btnCpuReset
+ C12 IBUF (Prop_ibuf_I_O) 1.507 1.507 r btnCpuReset_IBUF_inst/O
+ net (fo=2, routed) 5.471 6.978 vgaInterface/resetn
+ SLICE_X86Y85 LUT1 (Prop_lut1_I0_O) 0.124 7.102 f vgaInterface/button_up_shift_reg[0]_i_1/O
+ net (fo=86, routed) 2.344 9.447 vgaInterface/btnCpuReset
+ SLICE_X89Y70 FDCE f vgaInterface/counter_f_reg[3]/CLR
+ ------------------------------------------------------------------- -------------------
+
+ (clock clk_out1_clk_wiz_0 rise edge)
+ 0.000 0.000 r
+ E3 0.000 0.000 r clk (IN)
+ net (fo=0) 0.000 0.000 pixelClk/inst/clk_in1
+ E3 IBUF (Prop_ibuf_I_O) 1.411 1.411 r pixelClk/inst/clkin1_ibufg/O
+ net (fo=1, routed) 1.162 2.573 pixelClk/inst/clk_in1_clk_wiz_0
+ MMCME2_ADV_X1Y2 MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKOUT0)
+ -7.324 -4.751 r pixelClk/inst/mmcm_adv_inst/CLKOUT0
+ net (fo=1, routed) 1.639 -3.112 pixelClk/inst/clk_out1_clk_wiz_0
+ BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.091 -3.021 r pixelClk/inst/clkout1_buf/O
+ net (fo=127, routed) 1.601 -1.419 vgaInterface/clk_out1
+ SLICE_X89Y70 FDCE r vgaInterface/counter_f_reg[3]/C
+
+Slack: inf
+ Source: btnCpuReset
+ (input port)
+ Destination: collisionDetection/collision_cnt_reg[0]/CLR
+ (recovery check against rising-edge clock clk_out1_clk_wiz_0 {rise@0.000ns fall@20.000ns period=40.000ns})
+ Path Group: (none)
+ Path Type: Recovery (Max at Slow Process Corner)
+ Data Path Delay: 9.273ns (logic 1.631ns (17.589%) route 7.642ns (82.410%))
+ Logic Levels: 2 (IBUF=1 LUT1=1)
+ Clock Path Skew: -1.416ns (DCD - SCD + CPR)
+ Destination Clock Delay (DCD): -1.416ns
+ Source Clock Delay (SCD): 0.000ns
+ Clock Pessimism Removal (CPR): 0.000ns
+ Clock Uncertainty: 0.199ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE
+ Total System Jitter (TSJ): 0.050ns
+ Discrete Jitter (DJ): 0.182ns
+ Phase Error (PE): 0.104ns
+
+ Location Delay type Incr(ns) Path(ns) Netlist Resource(s)
+ ------------------------------------------------------------------- -------------------
+ C12 0.000 0.000 r btnCpuReset (IN)
+ net (fo=0) 0.000 0.000 btnCpuReset
+ C12 IBUF (Prop_ibuf_I_O) 1.507 1.507 r btnCpuReset_IBUF_inst/O
+ net (fo=2, routed) 5.471 6.978 vgaInterface/resetn
+ SLICE_X86Y85 LUT1 (Prop_lut1_I0_O) 0.124 7.102 f vgaInterface/button_up_shift_reg[0]_i_1/O
+ net (fo=86, routed) 2.170 9.273 collisionDetection/collision_cnt_reg[15]_0
+ SLICE_X89Y67 FDCE f collisionDetection/collision_cnt_reg[0]/CLR
+ ------------------------------------------------------------------- -------------------
+
+ (clock clk_out1_clk_wiz_0 rise edge)
+ 0.000 0.000 r
+ E3 0.000 0.000 r clk (IN)
+ net (fo=0) 0.000 0.000 pixelClk/inst/clk_in1
+ E3 IBUF (Prop_ibuf_I_O) 1.411 1.411 r pixelClk/inst/clkin1_ibufg/O
+ net (fo=1, routed) 1.162 2.573 pixelClk/inst/clk_in1_clk_wiz_0
+ MMCME2_ADV_X1Y2 MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKOUT0)
+ -7.324 -4.751 r pixelClk/inst/mmcm_adv_inst/CLKOUT0
+ net (fo=1, routed) 1.639 -3.112 pixelClk/inst/clk_out1_clk_wiz_0
+ BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.091 -3.021 r pixelClk/inst/clkout1_buf/O
+ net (fo=127, routed) 1.604 -1.416 collisionDetection/CLK
+ SLICE_X89Y67 FDCE r collisionDetection/collision_cnt_reg[0]/C
+
+Slack: inf
+ Source: btnCpuReset
+ (input port)
+ Destination: collisionDetection/collision_cnt_reg[11]/CLR
+ (recovery check against rising-edge clock clk_out1_clk_wiz_0 {rise@0.000ns fall@20.000ns period=40.000ns})
+ Path Group: (none)
+ Path Type: Recovery (Max at Slow Process Corner)
+ Data Path Delay: 9.273ns (logic 1.631ns (17.589%) route 7.642ns (82.410%))
+ Logic Levels: 2 (IBUF=1 LUT1=1)
+ Clock Path Skew: -1.416ns (DCD - SCD + CPR)
+ Destination Clock Delay (DCD): -1.416ns
+ Source Clock Delay (SCD): 0.000ns
+ Clock Pessimism Removal (CPR): 0.000ns
+ Clock Uncertainty: 0.199ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE
+ Total System Jitter (TSJ): 0.050ns
+ Discrete Jitter (DJ): 0.182ns
+ Phase Error (PE): 0.104ns
+
+ Location Delay type Incr(ns) Path(ns) Netlist Resource(s)
+ ------------------------------------------------------------------- -------------------
+ C12 0.000 0.000 r btnCpuReset (IN)
+ net (fo=0) 0.000 0.000 btnCpuReset
+ C12 IBUF (Prop_ibuf_I_O) 1.507 1.507 r btnCpuReset_IBUF_inst/O
+ net (fo=2, routed) 5.471 6.978 vgaInterface/resetn
+ SLICE_X86Y85 LUT1 (Prop_lut1_I0_O) 0.124 7.102 f vgaInterface/button_up_shift_reg[0]_i_1/O
+ net (fo=86, routed) 2.170 9.273 collisionDetection/collision_cnt_reg[15]_0
+ SLICE_X88Y67 FDCE f collisionDetection/collision_cnt_reg[11]/CLR
+ ------------------------------------------------------------------- -------------------
+
+ (clock clk_out1_clk_wiz_0 rise edge)
+ 0.000 0.000 r
+ E3 0.000 0.000 r clk (IN)
+ net (fo=0) 0.000 0.000 pixelClk/inst/clk_in1
+ E3 IBUF (Prop_ibuf_I_O) 1.411 1.411 r pixelClk/inst/clkin1_ibufg/O
+ net (fo=1, routed) 1.162 2.573 pixelClk/inst/clk_in1_clk_wiz_0
+ MMCME2_ADV_X1Y2 MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKOUT0)
+ -7.324 -4.751 r pixelClk/inst/mmcm_adv_inst/CLKOUT0
+ net (fo=1, routed) 1.639 -3.112 pixelClk/inst/clk_out1_clk_wiz_0
+ BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.091 -3.021 r pixelClk/inst/clkout1_buf/O
+ net (fo=127, routed) 1.604 -1.416 collisionDetection/CLK
+ SLICE_X88Y67 FDCE r collisionDetection/collision_cnt_reg[11]/C
+
+
+
+
+
+Min Delay Paths
+--------------------------------------------------------------------------------------
+Slack: inf
+ Source: btnU
+ (input port)
+ Destination: runnerObject/button_up_shift_reg_reg[0]/D
+ (rising edge-triggered cell FDCE clocked by clk_out1_clk_wiz_0 {rise@0.000ns fall@20.000ns period=40.000ns})
+ Path Group: (none)
+ Path Type: Hold (Min at Fast Process Corner)
+ Data Path Delay: 2.346ns (logic 0.241ns (10.267%) route 2.106ns (89.733%))
+ Logic Levels: 1 (IBUF=1)
+ Clock Path Skew: -0.810ns (DCD - SCD - CPR)
+ Destination Clock Delay (DCD): -0.810ns
+ Source Clock Delay (SCD): 0.000ns
+ Clock Pessimism Removal (CPR): -0.000ns
+
+ Location Delay type Incr(ns) Path(ns) Netlist Resource(s)
+ ------------------------------------------------------------------- -------------------
+ F15 0.000 0.000 r btnU (IN)
+ net (fo=0) 0.000 0.000 btnU
+ F15 IBUF (Prop_ibuf_I_O) 0.241 0.241 r btnU_IBUF_inst/O
+ net (fo=2, routed) 2.106 2.346 runnerObject/btnU_IBUF
+ SLICE_X86Y75 FDCE r runnerObject/button_up_shift_reg_reg[0]/D
+ ------------------------------------------------------------------- -------------------
+
+ (clock clk_out1_clk_wiz_0 rise edge)
+ 0.000 0.000 r
+ E3 0.000 0.000 r clk (IN)
+ net (fo=0) 0.000 0.000 pixelClk/inst/clk_in1
+ E3 IBUF (Prop_ibuf_I_O) 0.438 0.438 r pixelClk/inst/clkin1_ibufg/O
+ net (fo=1, routed) 0.480 0.918 pixelClk/inst/clk_in1_clk_wiz_0
+ MMCME2_ADV_X1Y2 MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKOUT0)
+ -3.163 -2.245 r pixelClk/inst/mmcm_adv_inst/CLKOUT0
+ net (fo=1, routed) 0.544 -1.702 pixelClk/inst/clk_out1_clk_wiz_0
+ BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.029 -1.673 r pixelClk/inst/clkout1_buf/O
+ net (fo=127, routed) 0.863 -0.810 runnerObject/clk_out1
+ SLICE_X86Y75 FDCE r runnerObject/button_up_shift_reg_reg[0]/C
+
+Slack: inf
+ Source: btnU
+ (input port)
+ Destination: runnerObject/fcount_edge_reg[10]/CE
+ (rising edge-triggered cell FDCE clocked by clk_out1_clk_wiz_0 {rise@0.000ns fall@20.000ns period=40.000ns})
+ Path Group: (none)
+ Path Type: Hold (Min at Fast Process Corner)
+ Data Path Delay: 2.637ns (logic 0.286ns (10.841%) route 2.352ns (89.159%))
+ Logic Levels: 2 (IBUF=1 LUT3=1)
+ Clock Path Skew: -0.807ns (DCD - SCD - CPR)
+ Destination Clock Delay (DCD): -0.807ns
+ Source Clock Delay (SCD): 0.000ns
+ Clock Pessimism Removal (CPR): -0.000ns
+
+ Location Delay type Incr(ns) Path(ns) Netlist Resource(s)
+ ------------------------------------------------------------------- -------------------
+ F15 0.000 0.000 r btnU (IN)
+ net (fo=0) 0.000 0.000 btnU
+ F15 IBUF (Prop_ibuf_I_O) 0.241 0.241 r btnU_IBUF_inst/O
+ net (fo=2, routed) 2.141 2.382 runnerObject/btnU_IBUF
+ SLICE_X86Y75 LUT3 (Prop_lut3_I0_O) 0.045 2.427 r runnerObject/fcount_edge0/O
+ net (fo=12, routed) 0.210 2.637 runnerObject/fcount_edge0__0
+ SLICE_X88Y72 FDCE r runnerObject/fcount_edge_reg[10]/CE
+ ------------------------------------------------------------------- -------------------
+
+ (clock clk_out1_clk_wiz_0 rise edge)
+ 0.000 0.000 r
+ E3 0.000 0.000 r clk (IN)
+ net (fo=0) 0.000 0.000 pixelClk/inst/clk_in1
+ E3 IBUF (Prop_ibuf_I_O) 0.438 0.438 r pixelClk/inst/clkin1_ibufg/O
+ net (fo=1, routed) 0.480 0.918 pixelClk/inst/clk_in1_clk_wiz_0
+ MMCME2_ADV_X1Y2 MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKOUT0)
+ -3.163 -2.245 r pixelClk/inst/mmcm_adv_inst/CLKOUT0
+ net (fo=1, routed) 0.544 -1.702 pixelClk/inst/clk_out1_clk_wiz_0
+ BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.029 -1.673 r pixelClk/inst/clkout1_buf/O
+ net (fo=127, routed) 0.866 -0.807 runnerObject/clk_out1
+ SLICE_X88Y72 FDCE r runnerObject/fcount_edge_reg[10]/C
+
+Slack: inf
+ Source: btnU
+ (input port)
+ Destination: runnerObject/fcount_edge_reg[11]/CE
+ (rising edge-triggered cell FDCE clocked by clk_out1_clk_wiz_0 {rise@0.000ns fall@20.000ns period=40.000ns})
+ Path Group: (none)
+ Path Type: Hold (Min at Fast Process Corner)
+ Data Path Delay: 2.637ns (logic 0.286ns (10.841%) route 2.352ns (89.159%))
+ Logic Levels: 2 (IBUF=1 LUT3=1)
+ Clock Path Skew: -0.807ns (DCD - SCD - CPR)
+ Destination Clock Delay (DCD): -0.807ns
+ Source Clock Delay (SCD): 0.000ns
+ Clock Pessimism Removal (CPR): -0.000ns
+
+ Location Delay type Incr(ns) Path(ns) Netlist Resource(s)
+ ------------------------------------------------------------------- -------------------
+ F15 0.000 0.000 r btnU (IN)
+ net (fo=0) 0.000 0.000 btnU
+ F15 IBUF (Prop_ibuf_I_O) 0.241 0.241 r btnU_IBUF_inst/O
+ net (fo=2, routed) 2.141 2.382 runnerObject/btnU_IBUF
+ SLICE_X86Y75 LUT3 (Prop_lut3_I0_O) 0.045 2.427 r runnerObject/fcount_edge0/O
+ net (fo=12, routed) 0.210 2.637 runnerObject/fcount_edge0__0
+ SLICE_X88Y72 FDCE r runnerObject/fcount_edge_reg[11]/CE
+ ------------------------------------------------------------------- -------------------
+
+ (clock clk_out1_clk_wiz_0 rise edge)
+ 0.000 0.000 r
+ E3 0.000 0.000 r clk (IN)
+ net (fo=0) 0.000 0.000 pixelClk/inst/clk_in1
+ E3 IBUF (Prop_ibuf_I_O) 0.438 0.438 r pixelClk/inst/clkin1_ibufg/O
+ net (fo=1, routed) 0.480 0.918 pixelClk/inst/clk_in1_clk_wiz_0
+ MMCME2_ADV_X1Y2 MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKOUT0)
+ -3.163 -2.245 r pixelClk/inst/mmcm_adv_inst/CLKOUT0
+ net (fo=1, routed) 0.544 -1.702 pixelClk/inst/clk_out1_clk_wiz_0
+ BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.029 -1.673 r pixelClk/inst/clkout1_buf/O
+ net (fo=127, routed) 0.866 -0.807 runnerObject/clk_out1
+ SLICE_X88Y72 FDCE r runnerObject/fcount_edge_reg[11]/C
+
+Slack: inf
+ Source: btnU
+ (input port)
+ Destination: runnerObject/fcount_edge_reg[8]/CE
+ (rising edge-triggered cell FDCE clocked by clk_out1_clk_wiz_0 {rise@0.000ns fall@20.000ns period=40.000ns})
+ Path Group: (none)
+ Path Type: Hold (Min at Fast Process Corner)
+ Data Path Delay: 2.637ns (logic 0.286ns (10.841%) route 2.352ns (89.159%))
+ Logic Levels: 2 (IBUF=1 LUT3=1)
+ Clock Path Skew: -0.807ns (DCD - SCD - CPR)
+ Destination Clock Delay (DCD): -0.807ns
+ Source Clock Delay (SCD): 0.000ns
+ Clock Pessimism Removal (CPR): -0.000ns
+
+ Location Delay type Incr(ns) Path(ns) Netlist Resource(s)
+ ------------------------------------------------------------------- -------------------
+ F15 0.000 0.000 r btnU (IN)
+ net (fo=0) 0.000 0.000 btnU
+ F15 IBUF (Prop_ibuf_I_O) 0.241 0.241 r btnU_IBUF_inst/O
+ net (fo=2, routed) 2.141 2.382 runnerObject/btnU_IBUF
+ SLICE_X86Y75 LUT3 (Prop_lut3_I0_O) 0.045 2.427 r runnerObject/fcount_edge0/O
+ net (fo=12, routed) 0.210 2.637 runnerObject/fcount_edge0__0
+ SLICE_X88Y72 FDCE r runnerObject/fcount_edge_reg[8]/CE
+ ------------------------------------------------------------------- -------------------
+
+ (clock clk_out1_clk_wiz_0 rise edge)
+ 0.000 0.000 r
+ E3 0.000 0.000 r clk (IN)
+ net (fo=0) 0.000 0.000 pixelClk/inst/clk_in1
+ E3 IBUF (Prop_ibuf_I_O) 0.438 0.438 r pixelClk/inst/clkin1_ibufg/O
+ net (fo=1, routed) 0.480 0.918 pixelClk/inst/clk_in1_clk_wiz_0
+ MMCME2_ADV_X1Y2 MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKOUT0)
+ -3.163 -2.245 r pixelClk/inst/mmcm_adv_inst/CLKOUT0
+ net (fo=1, routed) 0.544 -1.702 pixelClk/inst/clk_out1_clk_wiz_0
+ BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.029 -1.673 r pixelClk/inst/clkout1_buf/O
+ net (fo=127, routed) 0.866 -0.807 runnerObject/clk_out1
+ SLICE_X88Y72 FDCE r runnerObject/fcount_edge_reg[8]/C
+
+Slack: inf
+ Source: btnU
+ (input port)
+ Destination: runnerObject/fcount_edge_reg[9]/CE
+ (rising edge-triggered cell FDCE clocked by clk_out1_clk_wiz_0 {rise@0.000ns fall@20.000ns period=40.000ns})
+ Path Group: (none)
+ Path Type: Hold (Min at Fast Process Corner)
+ Data Path Delay: 2.637ns (logic 0.286ns (10.841%) route 2.352ns (89.159%))
+ Logic Levels: 2 (IBUF=1 LUT3=1)
+ Clock Path Skew: -0.807ns (DCD - SCD - CPR)
+ Destination Clock Delay (DCD): -0.807ns
+ Source Clock Delay (SCD): 0.000ns
+ Clock Pessimism Removal (CPR): -0.000ns
+
+ Location Delay type Incr(ns) Path(ns) Netlist Resource(s)
+ ------------------------------------------------------------------- -------------------
+ F15 0.000 0.000 r btnU (IN)
+ net (fo=0) 0.000 0.000 btnU
+ F15 IBUF (Prop_ibuf_I_O) 0.241 0.241 r btnU_IBUF_inst/O
+ net (fo=2, routed) 2.141 2.382 runnerObject/btnU_IBUF
+ SLICE_X86Y75 LUT3 (Prop_lut3_I0_O) 0.045 2.427 r runnerObject/fcount_edge0/O
+ net (fo=12, routed) 0.210 2.637 runnerObject/fcount_edge0__0
+ SLICE_X88Y72 FDCE r runnerObject/fcount_edge_reg[9]/CE
+ ------------------------------------------------------------------- -------------------
+
+ (clock clk_out1_clk_wiz_0 rise edge)
+ 0.000 0.000 r
+ E3 0.000 0.000 r clk (IN)
+ net (fo=0) 0.000 0.000 pixelClk/inst/clk_in1
+ E3 IBUF (Prop_ibuf_I_O) 0.438 0.438 r pixelClk/inst/clkin1_ibufg/O
+ net (fo=1, routed) 0.480 0.918 pixelClk/inst/clk_in1_clk_wiz_0
+ MMCME2_ADV_X1Y2 MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKOUT0)
+ -3.163 -2.245 r pixelClk/inst/mmcm_adv_inst/CLKOUT0
+ net (fo=1, routed) 0.544 -1.702 pixelClk/inst/clk_out1_clk_wiz_0
+ BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.029 -1.673 r pixelClk/inst/clkout1_buf/O
+ net (fo=127, routed) 0.866 -0.807 runnerObject/clk_out1
+ SLICE_X88Y72 FDCE r runnerObject/fcount_edge_reg[9]/C
+
+Slack: inf
+ Source: btnU
+ (input port)
+ Destination: runnerObject/fcount_edge_reg[4]/CE
+ (rising edge-triggered cell FDCE clocked by clk_out1_clk_wiz_0 {rise@0.000ns fall@20.000ns period=40.000ns})
+ Path Group: (none)
+ Path Type: Hold (Min at Fast Process Corner)
+ Data Path Delay: 2.681ns (logic 0.286ns (10.663%) route 2.395ns (89.337%))
+ Logic Levels: 2 (IBUF=1 LUT3=1)
+ Clock Path Skew: -0.806ns (DCD - SCD - CPR)
+ Destination Clock Delay (DCD): -0.806ns
+ Source Clock Delay (SCD): 0.000ns
+ Clock Pessimism Removal (CPR): -0.000ns
+
+ Location Delay type Incr(ns) Path(ns) Netlist Resource(s)
+ ------------------------------------------------------------------- -------------------
+ F15 0.000 0.000 r btnU (IN)
+ net (fo=0) 0.000 0.000 btnU
+ F15 IBUF (Prop_ibuf_I_O) 0.241 0.241 r btnU_IBUF_inst/O
+ net (fo=2, routed) 2.141 2.382 runnerObject/btnU_IBUF
+ SLICE_X86Y75 LUT3 (Prop_lut3_I0_O) 0.045 2.427 r runnerObject/fcount_edge0/O
+ net (fo=12, routed) 0.254 2.681 runnerObject/fcount_edge0__0
+ SLICE_X88Y71 FDCE r runnerObject/fcount_edge_reg[4]/CE
+ ------------------------------------------------------------------- -------------------
+
+ (clock clk_out1_clk_wiz_0 rise edge)
+ 0.000 0.000 r
+ E3 0.000 0.000 r clk (IN)
+ net (fo=0) 0.000 0.000 pixelClk/inst/clk_in1
+ E3 IBUF (Prop_ibuf_I_O) 0.438 0.438 r pixelClk/inst/clkin1_ibufg/O
+ net (fo=1, routed) 0.480 0.918 pixelClk/inst/clk_in1_clk_wiz_0
+ MMCME2_ADV_X1Y2 MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKOUT0)
+ -3.163 -2.245 r pixelClk/inst/mmcm_adv_inst/CLKOUT0
+ net (fo=1, routed) 0.544 -1.702 pixelClk/inst/clk_out1_clk_wiz_0
+ BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.029 -1.673 r pixelClk/inst/clkout1_buf/O
+ net (fo=127, routed) 0.867 -0.806 runnerObject/clk_out1
+ SLICE_X88Y71 FDCE r runnerObject/fcount_edge_reg[4]/C
+
+Slack: inf
+ Source: btnU
+ (input port)
+ Destination: runnerObject/fcount_edge_reg[5]/CE
+ (rising edge-triggered cell FDCE clocked by clk_out1_clk_wiz_0 {rise@0.000ns fall@20.000ns period=40.000ns})
+ Path Group: (none)
+ Path Type: Hold (Min at Fast Process Corner)
+ Data Path Delay: 2.681ns (logic 0.286ns (10.663%) route 2.395ns (89.337%))
+ Logic Levels: 2 (IBUF=1 LUT3=1)
+ Clock Path Skew: -0.806ns (DCD - SCD - CPR)
+ Destination Clock Delay (DCD): -0.806ns
+ Source Clock Delay (SCD): 0.000ns
+ Clock Pessimism Removal (CPR): -0.000ns
+
+ Location Delay type Incr(ns) Path(ns) Netlist Resource(s)
+ ------------------------------------------------------------------- -------------------
+ F15 0.000 0.000 r btnU (IN)
+ net (fo=0) 0.000 0.000 btnU
+ F15 IBUF (Prop_ibuf_I_O) 0.241 0.241 r btnU_IBUF_inst/O
+ net (fo=2, routed) 2.141 2.382 runnerObject/btnU_IBUF
+ SLICE_X86Y75 LUT3 (Prop_lut3_I0_O) 0.045 2.427 r runnerObject/fcount_edge0/O
+ net (fo=12, routed) 0.254 2.681 runnerObject/fcount_edge0__0
+ SLICE_X88Y71 FDCE r runnerObject/fcount_edge_reg[5]/CE
+ ------------------------------------------------------------------- -------------------
+
+ (clock clk_out1_clk_wiz_0 rise edge)
+ 0.000 0.000 r
+ E3 0.000 0.000 r clk (IN)
+ net (fo=0) 0.000 0.000 pixelClk/inst/clk_in1
+ E3 IBUF (Prop_ibuf_I_O) 0.438 0.438 r pixelClk/inst/clkin1_ibufg/O
+ net (fo=1, routed) 0.480 0.918 pixelClk/inst/clk_in1_clk_wiz_0
+ MMCME2_ADV_X1Y2 MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKOUT0)
+ -3.163 -2.245 r pixelClk/inst/mmcm_adv_inst/CLKOUT0
+ net (fo=1, routed) 0.544 -1.702 pixelClk/inst/clk_out1_clk_wiz_0
+ BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.029 -1.673 r pixelClk/inst/clkout1_buf/O
+ net (fo=127, routed) 0.867 -0.806 runnerObject/clk_out1
+ SLICE_X88Y71 FDCE r runnerObject/fcount_edge_reg[5]/C
+
+Slack: inf
+ Source: btnU
+ (input port)
+ Destination: runnerObject/fcount_edge_reg[6]/CE
+ (rising edge-triggered cell FDCE clocked by clk_out1_clk_wiz_0 {rise@0.000ns fall@20.000ns period=40.000ns})
+ Path Group: (none)
+ Path Type: Hold (Min at Fast Process Corner)
+ Data Path Delay: 2.681ns (logic 0.286ns (10.663%) route 2.395ns (89.337%))
+ Logic Levels: 2 (IBUF=1 LUT3=1)
+ Clock Path Skew: -0.806ns (DCD - SCD - CPR)
+ Destination Clock Delay (DCD): -0.806ns
+ Source Clock Delay (SCD): 0.000ns
+ Clock Pessimism Removal (CPR): -0.000ns
+
+ Location Delay type Incr(ns) Path(ns) Netlist Resource(s)
+ ------------------------------------------------------------------- -------------------
+ F15 0.000 0.000 r btnU (IN)
+ net (fo=0) 0.000 0.000 btnU
+ F15 IBUF (Prop_ibuf_I_O) 0.241 0.241 r btnU_IBUF_inst/O
+ net (fo=2, routed) 2.141 2.382 runnerObject/btnU_IBUF
+ SLICE_X86Y75 LUT3 (Prop_lut3_I0_O) 0.045 2.427 r runnerObject/fcount_edge0/O
+ net (fo=12, routed) 0.254 2.681 runnerObject/fcount_edge0__0
+ SLICE_X88Y71 FDCE r runnerObject/fcount_edge_reg[6]/CE
+ ------------------------------------------------------------------- -------------------
+
+ (clock clk_out1_clk_wiz_0 rise edge)
+ 0.000 0.000 r
+ E3 0.000 0.000 r clk (IN)
+ net (fo=0) 0.000 0.000 pixelClk/inst/clk_in1
+ E3 IBUF (Prop_ibuf_I_O) 0.438 0.438 r pixelClk/inst/clkin1_ibufg/O
+ net (fo=1, routed) 0.480 0.918 pixelClk/inst/clk_in1_clk_wiz_0
+ MMCME2_ADV_X1Y2 MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKOUT0)
+ -3.163 -2.245 r pixelClk/inst/mmcm_adv_inst/CLKOUT0
+ net (fo=1, routed) 0.544 -1.702 pixelClk/inst/clk_out1_clk_wiz_0
+ BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.029 -1.673 r pixelClk/inst/clkout1_buf/O
+ net (fo=127, routed) 0.867 -0.806 runnerObject/clk_out1
+ SLICE_X88Y71 FDCE r runnerObject/fcount_edge_reg[6]/C
+
+Slack: inf
+ Source: btnU
+ (input port)
+ Destination: runnerObject/fcount_edge_reg[7]/CE
+ (rising edge-triggered cell FDCE clocked by clk_out1_clk_wiz_0 {rise@0.000ns fall@20.000ns period=40.000ns})
+ Path Group: (none)
+ Path Type: Hold (Min at Fast Process Corner)
+ Data Path Delay: 2.681ns (logic 0.286ns (10.663%) route 2.395ns (89.337%))
+ Logic Levels: 2 (IBUF=1 LUT3=1)
+ Clock Path Skew: -0.806ns (DCD - SCD - CPR)
+ Destination Clock Delay (DCD): -0.806ns
+ Source Clock Delay (SCD): 0.000ns
+ Clock Pessimism Removal (CPR): -0.000ns
+
+ Location Delay type Incr(ns) Path(ns) Netlist Resource(s)
+ ------------------------------------------------------------------- -------------------
+ F15 0.000 0.000 r btnU (IN)
+ net (fo=0) 0.000 0.000 btnU
+ F15 IBUF (Prop_ibuf_I_O) 0.241 0.241 r btnU_IBUF_inst/O
+ net (fo=2, routed) 2.141 2.382 runnerObject/btnU_IBUF
+ SLICE_X86Y75 LUT3 (Prop_lut3_I0_O) 0.045 2.427 r runnerObject/fcount_edge0/O
+ net (fo=12, routed) 0.254 2.681 runnerObject/fcount_edge0__0
+ SLICE_X88Y71 FDCE r runnerObject/fcount_edge_reg[7]/CE
+ ------------------------------------------------------------------- -------------------
+
+ (clock clk_out1_clk_wiz_0 rise edge)
+ 0.000 0.000 r
+ E3 0.000 0.000 r clk (IN)
+ net (fo=0) 0.000 0.000 pixelClk/inst/clk_in1
+ E3 IBUF (Prop_ibuf_I_O) 0.438 0.438 r pixelClk/inst/clkin1_ibufg/O
+ net (fo=1, routed) 0.480 0.918 pixelClk/inst/clk_in1_clk_wiz_0
+ MMCME2_ADV_X1Y2 MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKOUT0)
+ -3.163 -2.245 r pixelClk/inst/mmcm_adv_inst/CLKOUT0
+ net (fo=1, routed) 0.544 -1.702 pixelClk/inst/clk_out1_clk_wiz_0
+ BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.029 -1.673 r pixelClk/inst/clkout1_buf/O
+ net (fo=127, routed) 0.867 -0.806 runnerObject/clk_out1
+ SLICE_X88Y71 FDCE r runnerObject/fcount_edge_reg[7]/C
+
+Slack: inf
+ Source: btnU
+ (input port)
+ Destination: runnerObject/fcount_edge_reg[0]/CE
+ (rising edge-triggered cell FDCE clocked by clk_out1_clk_wiz_0 {rise@0.000ns fall@20.000ns period=40.000ns})
+ Path Group: (none)
+ Path Type: Hold (Min at Fast Process Corner)
+ Data Path Delay: 2.696ns (logic 0.286ns (10.603%) route 2.411ns (89.397%))
+ Logic Levels: 2 (IBUF=1 LUT3=1)
+ Clock Path Skew: -0.805ns (DCD - SCD - CPR)
+ Destination Clock Delay (DCD): -0.805ns
+ Source Clock Delay (SCD): 0.000ns
+ Clock Pessimism Removal (CPR): -0.000ns
+
+ Location Delay type Incr(ns) Path(ns) Netlist Resource(s)
+ ------------------------------------------------------------------- -------------------
+ F15 0.000 0.000 r btnU (IN)
+ net (fo=0) 0.000 0.000 btnU
+ F15 IBUF (Prop_ibuf_I_O) 0.241 0.241 r btnU_IBUF_inst/O
+ net (fo=2, routed) 2.141 2.382 runnerObject/btnU_IBUF
+ SLICE_X86Y75 LUT3 (Prop_lut3_I0_O) 0.045 2.427 r runnerObject/fcount_edge0/O
+ net (fo=12, routed) 0.269 2.696 runnerObject/fcount_edge0__0
+ SLICE_X88Y70 FDCE r runnerObject/fcount_edge_reg[0]/CE
+ ------------------------------------------------------------------- -------------------
+
+ (clock clk_out1_clk_wiz_0 rise edge)
+ 0.000 0.000 r
+ E3 0.000 0.000 r clk (IN)
+ net (fo=0) 0.000 0.000 pixelClk/inst/clk_in1
+ E3 IBUF (Prop_ibuf_I_O) 0.438 0.438 r pixelClk/inst/clkin1_ibufg/O
+ net (fo=1, routed) 0.480 0.918 pixelClk/inst/clk_in1_clk_wiz_0
+ MMCME2_ADV_X1Y2 MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKOUT0)
+ -3.163 -2.245 r pixelClk/inst/mmcm_adv_inst/CLKOUT0
+ net (fo=1, routed) 0.544 -1.702 pixelClk/inst/clk_out1_clk_wiz_0
+ BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.029 -1.673 r pixelClk/inst/clkout1_buf/O
+ net (fo=127, routed) 0.868 -0.805 runnerObject/clk_out1
+ SLICE_X88Y70 FDCE r runnerObject/fcount_edge_reg[0]/C
+
+
+
+
+
+--------------------------------------------------------------------------------------
+Path Group: (none)
+From Clock:
+ To Clock: clk_out1_clk_wiz_0_1
+
+Max Delay 99 Endpoints
+Min Delay 99 Endpoints
+--------------------------------------------------------------------------------------
+
+
+Max Delay Paths
+--------------------------------------------------------------------------------------
+Slack: inf
+ Source: btnCpuReset
+ (input port)
+ Destination: runnerObject/fcount_edge_reg[0]/CLR
+ (recovery check against rising-edge clock clk_out1_clk_wiz_0_1 {rise@0.000ns fall@20.000ns period=40.000ns})
+ Path Group: (none)
+ Path Type: Recovery (Max at Slow Process Corner)
+ Data Path Delay: 9.447ns (logic 1.631ns (17.265%) route 7.816ns (82.735%))
+ Logic Levels: 2 (IBUF=1 LUT1=1)
+ Clock Path Skew: -1.419ns (DCD - SCD + CPR)
+ Destination Clock Delay (DCD): -1.419ns
+ Source Clock Delay (SCD): 0.000ns
+ Clock Pessimism Removal (CPR): 0.000ns
+ Clock Uncertainty: 0.195ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE
+ Total System Jitter (TSJ): 0.050ns
+ Discrete Jitter (DJ): 0.175ns
+ Phase Error (PE): 0.104ns
+
+ Location Delay type Incr(ns) Path(ns) Netlist Resource(s)
+ ------------------------------------------------------------------- -------------------
+ C12 0.000 0.000 r btnCpuReset (IN)
+ net (fo=0) 0.000 0.000 btnCpuReset
+ C12 IBUF (Prop_ibuf_I_O) 1.507 1.507 r btnCpuReset_IBUF_inst/O
+ net (fo=2, routed) 5.471 6.978 vgaInterface/resetn
+ SLICE_X86Y85 LUT1 (Prop_lut1_I0_O) 0.124 7.102 f vgaInterface/button_up_shift_reg[0]_i_1/O
+ net (fo=86, routed) 2.344 9.447 runnerObject/fcount_edge_reg[0]_1
+ SLICE_X88Y70 FDCE f runnerObject/fcount_edge_reg[0]/CLR
+ ------------------------------------------------------------------- -------------------
+
+ (clock clk_out1_clk_wiz_0_1 rise edge)
+ 0.000 0.000 r
+ E3 0.000 0.000 r clk (IN)
+ net (fo=0) 0.000 0.000 pixelClk/inst/clk_in1
+ E3 IBUF (Prop_ibuf_I_O) 1.411 1.411 r pixelClk/inst/clkin1_ibufg/O
+ net (fo=1, routed) 1.162 2.573 pixelClk/inst/clk_in1_clk_wiz_0
+ MMCME2_ADV_X1Y2 MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKOUT0)
+ -7.324 -4.751 r pixelClk/inst/mmcm_adv_inst/CLKOUT0
+ net (fo=1, routed) 1.639 -3.112 pixelClk/inst/clk_out1_clk_wiz_0
+ BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.091 -3.021 r pixelClk/inst/clkout1_buf/O
+ net (fo=127, routed) 1.601 -1.419 runnerObject/clk_out1
+ SLICE_X88Y70 FDCE r runnerObject/fcount_edge_reg[0]/C
+
+Slack: inf
+ Source: btnCpuReset
+ (input port)
+ Destination: runnerObject/fcount_edge_reg[1]/CLR
+ (recovery check against rising-edge clock clk_out1_clk_wiz_0_1 {rise@0.000ns fall@20.000ns period=40.000ns})
+ Path Group: (none)
+ Path Type: Recovery (Max at Slow Process Corner)
+ Data Path Delay: 9.447ns (logic 1.631ns (17.265%) route 7.816ns (82.735%))
+ Logic Levels: 2 (IBUF=1 LUT1=1)
+ Clock Path Skew: -1.419ns (DCD - SCD + CPR)
+ Destination Clock Delay (DCD): -1.419ns
+ Source Clock Delay (SCD): 0.000ns
+ Clock Pessimism Removal (CPR): 0.000ns
+ Clock Uncertainty: 0.195ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE
+ Total System Jitter (TSJ): 0.050ns
+ Discrete Jitter (DJ): 0.175ns
+ Phase Error (PE): 0.104ns
+
+ Location Delay type Incr(ns) Path(ns) Netlist Resource(s)
+ ------------------------------------------------------------------- -------------------
+ C12 0.000 0.000 r btnCpuReset (IN)
+ net (fo=0) 0.000 0.000 btnCpuReset
+ C12 IBUF (Prop_ibuf_I_O) 1.507 1.507 r btnCpuReset_IBUF_inst/O
+ net (fo=2, routed) 5.471 6.978 vgaInterface/resetn
+ SLICE_X86Y85 LUT1 (Prop_lut1_I0_O) 0.124 7.102 f vgaInterface/button_up_shift_reg[0]_i_1/O
+ net (fo=86, routed) 2.344 9.447 runnerObject/fcount_edge_reg[0]_1
+ SLICE_X88Y70 FDCE f runnerObject/fcount_edge_reg[1]/CLR
+ ------------------------------------------------------------------- -------------------
+
+ (clock clk_out1_clk_wiz_0_1 rise edge)
+ 0.000 0.000 r
+ E3 0.000 0.000 r clk (IN)
+ net (fo=0) 0.000 0.000 pixelClk/inst/clk_in1
+ E3 IBUF (Prop_ibuf_I_O) 1.411 1.411 r pixelClk/inst/clkin1_ibufg/O
+ net (fo=1, routed) 1.162 2.573 pixelClk/inst/clk_in1_clk_wiz_0
+ MMCME2_ADV_X1Y2 MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKOUT0)
+ -7.324 -4.751 r pixelClk/inst/mmcm_adv_inst/CLKOUT0
+ net (fo=1, routed) 1.639 -3.112 pixelClk/inst/clk_out1_clk_wiz_0
+ BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.091 -3.021 r pixelClk/inst/clkout1_buf/O
+ net (fo=127, routed) 1.601 -1.419 runnerObject/clk_out1
+ SLICE_X88Y70 FDCE r runnerObject/fcount_edge_reg[1]/C
+
+Slack: inf
+ Source: btnCpuReset
+ (input port)
+ Destination: runnerObject/fcount_edge_reg[2]/CLR
+ (recovery check against rising-edge clock clk_out1_clk_wiz_0_1 {rise@0.000ns fall@20.000ns period=40.000ns})
+ Path Group: (none)
+ Path Type: Recovery (Max at Slow Process Corner)
+ Data Path Delay: 9.447ns (logic 1.631ns (17.265%) route 7.816ns (82.735%))
+ Logic Levels: 2 (IBUF=1 LUT1=1)
+ Clock Path Skew: -1.419ns (DCD - SCD + CPR)
+ Destination Clock Delay (DCD): -1.419ns
+ Source Clock Delay (SCD): 0.000ns
+ Clock Pessimism Removal (CPR): 0.000ns
+ Clock Uncertainty: 0.195ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE
+ Total System Jitter (TSJ): 0.050ns
+ Discrete Jitter (DJ): 0.175ns
+ Phase Error (PE): 0.104ns
+
+ Location Delay type Incr(ns) Path(ns) Netlist Resource(s)
+ ------------------------------------------------------------------- -------------------
+ C12 0.000 0.000 r btnCpuReset (IN)
+ net (fo=0) 0.000 0.000 btnCpuReset
+ C12 IBUF (Prop_ibuf_I_O) 1.507 1.507 r btnCpuReset_IBUF_inst/O
+ net (fo=2, routed) 5.471 6.978 vgaInterface/resetn
+ SLICE_X86Y85 LUT1 (Prop_lut1_I0_O) 0.124 7.102 f vgaInterface/button_up_shift_reg[0]_i_1/O
+ net (fo=86, routed) 2.344 9.447 runnerObject/fcount_edge_reg[0]_1
+ SLICE_X88Y70 FDCE f runnerObject/fcount_edge_reg[2]/CLR
+ ------------------------------------------------------------------- -------------------
+
+ (clock clk_out1_clk_wiz_0_1 rise edge)
+ 0.000 0.000 r
+ E3 0.000 0.000 r clk (IN)
+ net (fo=0) 0.000 0.000 pixelClk/inst/clk_in1
+ E3 IBUF (Prop_ibuf_I_O) 1.411 1.411 r pixelClk/inst/clkin1_ibufg/O
+ net (fo=1, routed) 1.162 2.573 pixelClk/inst/clk_in1_clk_wiz_0
+ MMCME2_ADV_X1Y2 MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKOUT0)
+ -7.324 -4.751 r pixelClk/inst/mmcm_adv_inst/CLKOUT0
+ net (fo=1, routed) 1.639 -3.112 pixelClk/inst/clk_out1_clk_wiz_0
+ BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.091 -3.021 r pixelClk/inst/clkout1_buf/O
+ net (fo=127, routed) 1.601 -1.419 runnerObject/clk_out1
+ SLICE_X88Y70 FDCE r runnerObject/fcount_edge_reg[2]/C
+
+Slack: inf
+ Source: btnCpuReset
+ (input port)
+ Destination: runnerObject/fcount_edge_reg[3]/CLR
+ (recovery check against rising-edge clock clk_out1_clk_wiz_0_1 {rise@0.000ns fall@20.000ns period=40.000ns})
+ Path Group: (none)
+ Path Type: Recovery (Max at Slow Process Corner)
+ Data Path Delay: 9.447ns (logic 1.631ns (17.265%) route 7.816ns (82.735%))
+ Logic Levels: 2 (IBUF=1 LUT1=1)
+ Clock Path Skew: -1.419ns (DCD - SCD + CPR)
+ Destination Clock Delay (DCD): -1.419ns
+ Source Clock Delay (SCD): 0.000ns
+ Clock Pessimism Removal (CPR): 0.000ns
+ Clock Uncertainty: 0.195ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE
+ Total System Jitter (TSJ): 0.050ns
+ Discrete Jitter (DJ): 0.175ns
+ Phase Error (PE): 0.104ns
+
+ Location Delay type Incr(ns) Path(ns) Netlist Resource(s)
+ ------------------------------------------------------------------- -------------------
+ C12 0.000 0.000 r btnCpuReset (IN)
+ net (fo=0) 0.000 0.000 btnCpuReset
+ C12 IBUF (Prop_ibuf_I_O) 1.507 1.507 r btnCpuReset_IBUF_inst/O
+ net (fo=2, routed) 5.471 6.978 vgaInterface/resetn
+ SLICE_X86Y85 LUT1 (Prop_lut1_I0_O) 0.124 7.102 f vgaInterface/button_up_shift_reg[0]_i_1/O
+ net (fo=86, routed) 2.344 9.447 runnerObject/fcount_edge_reg[0]_1
+ SLICE_X88Y70 FDCE f runnerObject/fcount_edge_reg[3]/CLR
+ ------------------------------------------------------------------- -------------------
+
+ (clock clk_out1_clk_wiz_0_1 rise edge)
+ 0.000 0.000 r
+ E3 0.000 0.000 r clk (IN)
+ net (fo=0) 0.000 0.000 pixelClk/inst/clk_in1
+ E3 IBUF (Prop_ibuf_I_O) 1.411 1.411 r pixelClk/inst/clkin1_ibufg/O
+ net (fo=1, routed) 1.162 2.573 pixelClk/inst/clk_in1_clk_wiz_0
+ MMCME2_ADV_X1Y2 MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKOUT0)
+ -7.324 -4.751 r pixelClk/inst/mmcm_adv_inst/CLKOUT0
+ net (fo=1, routed) 1.639 -3.112 pixelClk/inst/clk_out1_clk_wiz_0
+ BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.091 -3.021 r pixelClk/inst/clkout1_buf/O
+ net (fo=127, routed) 1.601 -1.419 runnerObject/clk_out1
+ SLICE_X88Y70 FDCE r runnerObject/fcount_edge_reg[3]/C
+
+Slack: inf
+ Source: btnCpuReset
+ (input port)
+ Destination: vgaInterface/counter_f_reg[0]/CLR
+ (recovery check against rising-edge clock clk_out1_clk_wiz_0_1 {rise@0.000ns fall@20.000ns period=40.000ns})
+ Path Group: (none)
+ Path Type: Recovery (Max at Slow Process Corner)
+ Data Path Delay: 9.447ns (logic 1.631ns (17.265%) route 7.816ns (82.735%))
+ Logic Levels: 2 (IBUF=1 LUT1=1)
+ Clock Path Skew: -1.419ns (DCD - SCD + CPR)
+ Destination Clock Delay (DCD): -1.419ns
+ Source Clock Delay (SCD): 0.000ns
+ Clock Pessimism Removal (CPR): 0.000ns
+ Clock Uncertainty: 0.195ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE
+ Total System Jitter (TSJ): 0.050ns
+ Discrete Jitter (DJ): 0.175ns
+ Phase Error (PE): 0.104ns
+
+ Location Delay type Incr(ns) Path(ns) Netlist Resource(s)
+ ------------------------------------------------------------------- -------------------
+ C12 0.000 0.000 r btnCpuReset (IN)
+ net (fo=0) 0.000 0.000 btnCpuReset
+ C12 IBUF (Prop_ibuf_I_O) 1.507 1.507 r btnCpuReset_IBUF_inst/O
+ net (fo=2, routed) 5.471 6.978 vgaInterface/resetn
+ SLICE_X86Y85 LUT1 (Prop_lut1_I0_O) 0.124 7.102 f vgaInterface/button_up_shift_reg[0]_i_1/O
+ net (fo=86, routed) 2.344 9.447 vgaInterface/btnCpuReset
+ SLICE_X89Y70 FDCE f vgaInterface/counter_f_reg[0]/CLR
+ ------------------------------------------------------------------- -------------------
+
+ (clock clk_out1_clk_wiz_0_1 rise edge)
+ 0.000 0.000 r
+ E3 0.000 0.000 r clk (IN)
+ net (fo=0) 0.000 0.000 pixelClk/inst/clk_in1
+ E3 IBUF (Prop_ibuf_I_O) 1.411 1.411 r pixelClk/inst/clkin1_ibufg/O
+ net (fo=1, routed) 1.162 2.573 pixelClk/inst/clk_in1_clk_wiz_0
+ MMCME2_ADV_X1Y2 MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKOUT0)
+ -7.324 -4.751 r pixelClk/inst/mmcm_adv_inst/CLKOUT0
+ net (fo=1, routed) 1.639 -3.112 pixelClk/inst/clk_out1_clk_wiz_0
+ BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.091 -3.021 r pixelClk/inst/clkout1_buf/O
+ net (fo=127, routed) 1.601 -1.419 vgaInterface/clk_out1
+ SLICE_X89Y70 FDCE r vgaInterface/counter_f_reg[0]/C
+
+Slack: inf
+ Source: btnCpuReset
+ (input port)
+ Destination: vgaInterface/counter_f_reg[1]/CLR
+ (recovery check against rising-edge clock clk_out1_clk_wiz_0_1 {rise@0.000ns fall@20.000ns period=40.000ns})
+ Path Group: (none)
+ Path Type: Recovery (Max at Slow Process Corner)
+ Data Path Delay: 9.447ns (logic 1.631ns (17.265%) route 7.816ns (82.735%))
+ Logic Levels: 2 (IBUF=1 LUT1=1)
+ Clock Path Skew: -1.419ns (DCD - SCD + CPR)
+ Destination Clock Delay (DCD): -1.419ns
+ Source Clock Delay (SCD): 0.000ns
+ Clock Pessimism Removal (CPR): 0.000ns
+ Clock Uncertainty: 0.195ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE
+ Total System Jitter (TSJ): 0.050ns
+ Discrete Jitter (DJ): 0.175ns
+ Phase Error (PE): 0.104ns
+
+ Location Delay type Incr(ns) Path(ns) Netlist Resource(s)
+ ------------------------------------------------------------------- -------------------
+ C12 0.000 0.000 r btnCpuReset (IN)
+ net (fo=0) 0.000 0.000 btnCpuReset
+ C12 IBUF (Prop_ibuf_I_O) 1.507 1.507 r btnCpuReset_IBUF_inst/O
+ net (fo=2, routed) 5.471 6.978 vgaInterface/resetn
+ SLICE_X86Y85 LUT1 (Prop_lut1_I0_O) 0.124 7.102 f vgaInterface/button_up_shift_reg[0]_i_1/O
+ net (fo=86, routed) 2.344 9.447 vgaInterface/btnCpuReset
+ SLICE_X89Y70 FDCE f vgaInterface/counter_f_reg[1]/CLR
+ ------------------------------------------------------------------- -------------------
+
+ (clock clk_out1_clk_wiz_0_1 rise edge)
+ 0.000 0.000 r
+ E3 0.000 0.000 r clk (IN)
+ net (fo=0) 0.000 0.000 pixelClk/inst/clk_in1
+ E3 IBUF (Prop_ibuf_I_O) 1.411 1.411 r pixelClk/inst/clkin1_ibufg/O
+ net (fo=1, routed) 1.162 2.573 pixelClk/inst/clk_in1_clk_wiz_0
+ MMCME2_ADV_X1Y2 MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKOUT0)
+ -7.324 -4.751 r pixelClk/inst/mmcm_adv_inst/CLKOUT0
+ net (fo=1, routed) 1.639 -3.112 pixelClk/inst/clk_out1_clk_wiz_0
+ BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.091 -3.021 r pixelClk/inst/clkout1_buf/O
+ net (fo=127, routed) 1.601 -1.419 vgaInterface/clk_out1
+ SLICE_X89Y70 FDCE r vgaInterface/counter_f_reg[1]/C
+
+Slack: inf
+ Source: btnCpuReset
+ (input port)
+ Destination: vgaInterface/counter_f_reg[2]/CLR
+ (recovery check against rising-edge clock clk_out1_clk_wiz_0_1 {rise@0.000ns fall@20.000ns period=40.000ns})
+ Path Group: (none)
+ Path Type: Recovery (Max at Slow Process Corner)
+ Data Path Delay: 9.447ns (logic 1.631ns (17.265%) route 7.816ns (82.735%))
+ Logic Levels: 2 (IBUF=1 LUT1=1)
+ Clock Path Skew: -1.419ns (DCD - SCD + CPR)
+ Destination Clock Delay (DCD): -1.419ns
+ Source Clock Delay (SCD): 0.000ns
+ Clock Pessimism Removal (CPR): 0.000ns
+ Clock Uncertainty: 0.195ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE
+ Total System Jitter (TSJ): 0.050ns
+ Discrete Jitter (DJ): 0.175ns
+ Phase Error (PE): 0.104ns
+
+ Location Delay type Incr(ns) Path(ns) Netlist Resource(s)
+ ------------------------------------------------------------------- -------------------
+ C12 0.000 0.000 r btnCpuReset (IN)
+ net (fo=0) 0.000 0.000 btnCpuReset
+ C12 IBUF (Prop_ibuf_I_O) 1.507 1.507 r btnCpuReset_IBUF_inst/O
+ net (fo=2, routed) 5.471 6.978 vgaInterface/resetn
+ SLICE_X86Y85 LUT1 (Prop_lut1_I0_O) 0.124 7.102 f vgaInterface/button_up_shift_reg[0]_i_1/O
+ net (fo=86, routed) 2.344 9.447 vgaInterface/btnCpuReset
+ SLICE_X89Y70 FDCE f vgaInterface/counter_f_reg[2]/CLR
+ ------------------------------------------------------------------- -------------------
+
+ (clock clk_out1_clk_wiz_0_1 rise edge)
+ 0.000 0.000 r
+ E3 0.000 0.000 r clk (IN)
+ net (fo=0) 0.000 0.000 pixelClk/inst/clk_in1
+ E3 IBUF (Prop_ibuf_I_O) 1.411 1.411 r pixelClk/inst/clkin1_ibufg/O
+ net (fo=1, routed) 1.162 2.573 pixelClk/inst/clk_in1_clk_wiz_0
+ MMCME2_ADV_X1Y2 MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKOUT0)
+ -7.324 -4.751 r pixelClk/inst/mmcm_adv_inst/CLKOUT0
+ net (fo=1, routed) 1.639 -3.112 pixelClk/inst/clk_out1_clk_wiz_0
+ BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.091 -3.021 r pixelClk/inst/clkout1_buf/O
+ net (fo=127, routed) 1.601 -1.419 vgaInterface/clk_out1
+ SLICE_X89Y70 FDCE r vgaInterface/counter_f_reg[2]/C
+
+Slack: inf
+ Source: btnCpuReset
+ (input port)
+ Destination: vgaInterface/counter_f_reg[3]/CLR
+ (recovery check against rising-edge clock clk_out1_clk_wiz_0_1 {rise@0.000ns fall@20.000ns period=40.000ns})
+ Path Group: (none)
+ Path Type: Recovery (Max at Slow Process Corner)
+ Data Path Delay: 9.447ns (logic 1.631ns (17.265%) route 7.816ns (82.735%))
+ Logic Levels: 2 (IBUF=1 LUT1=1)
+ Clock Path Skew: -1.419ns (DCD - SCD + CPR)
+ Destination Clock Delay (DCD): -1.419ns
+ Source Clock Delay (SCD): 0.000ns
+ Clock Pessimism Removal (CPR): 0.000ns
+ Clock Uncertainty: 0.195ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE
+ Total System Jitter (TSJ): 0.050ns
+ Discrete Jitter (DJ): 0.175ns
+ Phase Error (PE): 0.104ns
+
+ Location Delay type Incr(ns) Path(ns) Netlist Resource(s)
+ ------------------------------------------------------------------- -------------------
+ C12 0.000 0.000 r btnCpuReset (IN)
+ net (fo=0) 0.000 0.000 btnCpuReset
+ C12 IBUF (Prop_ibuf_I_O) 1.507 1.507 r btnCpuReset_IBUF_inst/O
+ net (fo=2, routed) 5.471 6.978 vgaInterface/resetn
+ SLICE_X86Y85 LUT1 (Prop_lut1_I0_O) 0.124 7.102 f vgaInterface/button_up_shift_reg[0]_i_1/O
+ net (fo=86, routed) 2.344 9.447 vgaInterface/btnCpuReset
+ SLICE_X89Y70 FDCE f vgaInterface/counter_f_reg[3]/CLR
+ ------------------------------------------------------------------- -------------------
+
+ (clock clk_out1_clk_wiz_0_1 rise edge)
+ 0.000 0.000 r
+ E3 0.000 0.000 r clk (IN)
+ net (fo=0) 0.000 0.000 pixelClk/inst/clk_in1
+ E3 IBUF (Prop_ibuf_I_O) 1.411 1.411 r pixelClk/inst/clkin1_ibufg/O
+ net (fo=1, routed) 1.162 2.573 pixelClk/inst/clk_in1_clk_wiz_0
+ MMCME2_ADV_X1Y2 MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKOUT0)
+ -7.324 -4.751 r pixelClk/inst/mmcm_adv_inst/CLKOUT0
+ net (fo=1, routed) 1.639 -3.112 pixelClk/inst/clk_out1_clk_wiz_0
+ BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.091 -3.021 r pixelClk/inst/clkout1_buf/O
+ net (fo=127, routed) 1.601 -1.419 vgaInterface/clk_out1
+ SLICE_X89Y70 FDCE r vgaInterface/counter_f_reg[3]/C
+
+Slack: inf
+ Source: btnCpuReset
+ (input port)
+ Destination: collisionDetection/collision_cnt_reg[0]/CLR
+ (recovery check against rising-edge clock clk_out1_clk_wiz_0_1 {rise@0.000ns fall@20.000ns period=40.000ns})
+ Path Group: (none)
+ Path Type: Recovery (Max at Slow Process Corner)
+ Data Path Delay: 9.273ns (logic 1.631ns (17.589%) route 7.642ns (82.410%))
+ Logic Levels: 2 (IBUF=1 LUT1=1)
+ Clock Path Skew: -1.416ns (DCD - SCD + CPR)
+ Destination Clock Delay (DCD): -1.416ns
+ Source Clock Delay (SCD): 0.000ns
+ Clock Pessimism Removal (CPR): 0.000ns
+ Clock Uncertainty: 0.195ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE
+ Total System Jitter (TSJ): 0.050ns
+ Discrete Jitter (DJ): 0.175ns
+ Phase Error (PE): 0.104ns
+
+ Location Delay type Incr(ns) Path(ns) Netlist Resource(s)
+ ------------------------------------------------------------------- -------------------
+ C12 0.000 0.000 r btnCpuReset (IN)
+ net (fo=0) 0.000 0.000 btnCpuReset
+ C12 IBUF (Prop_ibuf_I_O) 1.507 1.507 r btnCpuReset_IBUF_inst/O
+ net (fo=2, routed) 5.471 6.978 vgaInterface/resetn
+ SLICE_X86Y85 LUT1 (Prop_lut1_I0_O) 0.124 7.102 f vgaInterface/button_up_shift_reg[0]_i_1/O
+ net (fo=86, routed) 2.170 9.273 collisionDetection/collision_cnt_reg[15]_0
+ SLICE_X89Y67 FDCE f collisionDetection/collision_cnt_reg[0]/CLR
+ ------------------------------------------------------------------- -------------------
+
+ (clock clk_out1_clk_wiz_0_1 rise edge)
+ 0.000 0.000 r
+ E3 0.000 0.000 r clk (IN)
+ net (fo=0) 0.000 0.000 pixelClk/inst/clk_in1
+ E3 IBUF (Prop_ibuf_I_O) 1.411 1.411 r pixelClk/inst/clkin1_ibufg/O
+ net (fo=1, routed) 1.162 2.573 pixelClk/inst/clk_in1_clk_wiz_0
+ MMCME2_ADV_X1Y2 MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKOUT0)
+ -7.324 -4.751 r pixelClk/inst/mmcm_adv_inst/CLKOUT0
+ net (fo=1, routed) 1.639 -3.112 pixelClk/inst/clk_out1_clk_wiz_0
+ BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.091 -3.021 r pixelClk/inst/clkout1_buf/O
+ net (fo=127, routed) 1.604 -1.416 collisionDetection/CLK
+ SLICE_X89Y67 FDCE r collisionDetection/collision_cnt_reg[0]/C
+
+Slack: inf
+ Source: btnCpuReset
+ (input port)
+ Destination: collisionDetection/collision_cnt_reg[11]/CLR
+ (recovery check against rising-edge clock clk_out1_clk_wiz_0_1 {rise@0.000ns fall@20.000ns period=40.000ns})
+ Path Group: (none)
+ Path Type: Recovery (Max at Slow Process Corner)
+ Data Path Delay: 9.273ns (logic 1.631ns (17.589%) route 7.642ns (82.410%))
+ Logic Levels: 2 (IBUF=1 LUT1=1)
+ Clock Path Skew: -1.416ns (DCD - SCD + CPR)
+ Destination Clock Delay (DCD): -1.416ns
+ Source Clock Delay (SCD): 0.000ns
+ Clock Pessimism Removal (CPR): 0.000ns
+ Clock Uncertainty: 0.195ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE
+ Total System Jitter (TSJ): 0.050ns
+ Discrete Jitter (DJ): 0.175ns
+ Phase Error (PE): 0.104ns
+
+ Location Delay type Incr(ns) Path(ns) Netlist Resource(s)
+ ------------------------------------------------------------------- -------------------
+ C12 0.000 0.000 r btnCpuReset (IN)
+ net (fo=0) 0.000 0.000 btnCpuReset
+ C12 IBUF (Prop_ibuf_I_O) 1.507 1.507 r btnCpuReset_IBUF_inst/O
+ net (fo=2, routed) 5.471 6.978 vgaInterface/resetn
+ SLICE_X86Y85 LUT1 (Prop_lut1_I0_O) 0.124 7.102 f vgaInterface/button_up_shift_reg[0]_i_1/O
+ net (fo=86, routed) 2.170 9.273 collisionDetection/collision_cnt_reg[15]_0
+ SLICE_X88Y67 FDCE f collisionDetection/collision_cnt_reg[11]/CLR
+ ------------------------------------------------------------------- -------------------
+
+ (clock clk_out1_clk_wiz_0_1 rise edge)
+ 0.000 0.000 r
+ E3 0.000 0.000 r clk (IN)
+ net (fo=0) 0.000 0.000 pixelClk/inst/clk_in1
+ E3 IBUF (Prop_ibuf_I_O) 1.411 1.411 r pixelClk/inst/clkin1_ibufg/O
+ net (fo=1, routed) 1.162 2.573 pixelClk/inst/clk_in1_clk_wiz_0
+ MMCME2_ADV_X1Y2 MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKOUT0)
+ -7.324 -4.751 r pixelClk/inst/mmcm_adv_inst/CLKOUT0
+ net (fo=1, routed) 1.639 -3.112 pixelClk/inst/clk_out1_clk_wiz_0
+ BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.091 -3.021 r pixelClk/inst/clkout1_buf/O
+ net (fo=127, routed) 1.604 -1.416 collisionDetection/CLK
+ SLICE_X88Y67 FDCE r collisionDetection/collision_cnt_reg[11]/C
+
+
+
+
+
+Min Delay Paths
+--------------------------------------------------------------------------------------
+Slack: inf
+ Source: btnU
+ (input port)
+ Destination: runnerObject/button_up_shift_reg_reg[0]/D
+ (rising edge-triggered cell FDCE clocked by clk_out1_clk_wiz_0_1 {rise@0.000ns fall@20.000ns period=40.000ns})
+ Path Group: (none)
+ Path Type: Hold (Min at Fast Process Corner)
+ Data Path Delay: 2.346ns (logic 0.241ns (10.267%) route 2.106ns (89.733%))
+ Logic Levels: 1 (IBUF=1)
+ Clock Path Skew: -0.810ns (DCD - SCD - CPR)
+ Destination Clock Delay (DCD): -0.810ns
+ Source Clock Delay (SCD): 0.000ns
+ Clock Pessimism Removal (CPR): -0.000ns
+
+ Location Delay type Incr(ns) Path(ns) Netlist Resource(s)
+ ------------------------------------------------------------------- -------------------
+ F15 0.000 0.000 r btnU (IN)
+ net (fo=0) 0.000 0.000 btnU
+ F15 IBUF (Prop_ibuf_I_O) 0.241 0.241 r btnU_IBUF_inst/O
+ net (fo=2, routed) 2.106 2.346 runnerObject/btnU_IBUF
+ SLICE_X86Y75 FDCE r runnerObject/button_up_shift_reg_reg[0]/D
+ ------------------------------------------------------------------- -------------------
+
+ (clock clk_out1_clk_wiz_0_1 rise edge)
+ 0.000 0.000 r
+ E3 0.000 0.000 r clk (IN)
+ net (fo=0) 0.000 0.000 pixelClk/inst/clk_in1
+ E3 IBUF (Prop_ibuf_I_O) 0.438 0.438 r pixelClk/inst/clkin1_ibufg/O
+ net (fo=1, routed) 0.480 0.918 pixelClk/inst/clk_in1_clk_wiz_0
+ MMCME2_ADV_X1Y2 MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKOUT0)
+ -3.163 -2.245 r pixelClk/inst/mmcm_adv_inst/CLKOUT0
+ net (fo=1, routed) 0.544 -1.702 pixelClk/inst/clk_out1_clk_wiz_0
+ BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.029 -1.673 r pixelClk/inst/clkout1_buf/O
+ net (fo=127, routed) 0.863 -0.810 runnerObject/clk_out1
+ SLICE_X86Y75 FDCE r runnerObject/button_up_shift_reg_reg[0]/C
+
+Slack: inf
+ Source: btnU
+ (input port)
+ Destination: runnerObject/fcount_edge_reg[10]/CE
+ (rising edge-triggered cell FDCE clocked by clk_out1_clk_wiz_0_1 {rise@0.000ns fall@20.000ns period=40.000ns})
+ Path Group: (none)
+ Path Type: Hold (Min at Fast Process Corner)
+ Data Path Delay: 2.637ns (logic 0.286ns (10.841%) route 2.352ns (89.159%))
+ Logic Levels: 2 (IBUF=1 LUT3=1)
+ Clock Path Skew: -0.807ns (DCD - SCD - CPR)
+ Destination Clock Delay (DCD): -0.807ns
+ Source Clock Delay (SCD): 0.000ns
+ Clock Pessimism Removal (CPR): -0.000ns
+
+ Location Delay type Incr(ns) Path(ns) Netlist Resource(s)
+ ------------------------------------------------------------------- -------------------
+ F15 0.000 0.000 r btnU (IN)
+ net (fo=0) 0.000 0.000 btnU
+ F15 IBUF (Prop_ibuf_I_O) 0.241 0.241 r btnU_IBUF_inst/O
+ net (fo=2, routed) 2.141 2.382 runnerObject/btnU_IBUF
+ SLICE_X86Y75 LUT3 (Prop_lut3_I0_O) 0.045 2.427 r runnerObject/fcount_edge0/O
+ net (fo=12, routed) 0.210 2.637 runnerObject/fcount_edge0__0
+ SLICE_X88Y72 FDCE r runnerObject/fcount_edge_reg[10]/CE
+ ------------------------------------------------------------------- -------------------
+
+ (clock clk_out1_clk_wiz_0_1 rise edge)
+ 0.000 0.000 r
+ E3 0.000 0.000 r clk (IN)
+ net (fo=0) 0.000 0.000 pixelClk/inst/clk_in1
+ E3 IBUF (Prop_ibuf_I_O) 0.438 0.438 r pixelClk/inst/clkin1_ibufg/O
+ net (fo=1, routed) 0.480 0.918 pixelClk/inst/clk_in1_clk_wiz_0
+ MMCME2_ADV_X1Y2 MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKOUT0)
+ -3.163 -2.245 r pixelClk/inst/mmcm_adv_inst/CLKOUT0
+ net (fo=1, routed) 0.544 -1.702 pixelClk/inst/clk_out1_clk_wiz_0
+ BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.029 -1.673 r pixelClk/inst/clkout1_buf/O
+ net (fo=127, routed) 0.866 -0.807 runnerObject/clk_out1
+ SLICE_X88Y72 FDCE r runnerObject/fcount_edge_reg[10]/C
+
+Slack: inf
+ Source: btnU
+ (input port)
+ Destination: runnerObject/fcount_edge_reg[11]/CE
+ (rising edge-triggered cell FDCE clocked by clk_out1_clk_wiz_0_1 {rise@0.000ns fall@20.000ns period=40.000ns})
+ Path Group: (none)
+ Path Type: Hold (Min at Fast Process Corner)
+ Data Path Delay: 2.637ns (logic 0.286ns (10.841%) route 2.352ns (89.159%))
+ Logic Levels: 2 (IBUF=1 LUT3=1)
+ Clock Path Skew: -0.807ns (DCD - SCD - CPR)
+ Destination Clock Delay (DCD): -0.807ns
+ Source Clock Delay (SCD): 0.000ns
+ Clock Pessimism Removal (CPR): -0.000ns
+
+ Location Delay type Incr(ns) Path(ns) Netlist Resource(s)
+ ------------------------------------------------------------------- -------------------
+ F15 0.000 0.000 r btnU (IN)
+ net (fo=0) 0.000 0.000 btnU
+ F15 IBUF (Prop_ibuf_I_O) 0.241 0.241 r btnU_IBUF_inst/O
+ net (fo=2, routed) 2.141 2.382 runnerObject/btnU_IBUF
+ SLICE_X86Y75 LUT3 (Prop_lut3_I0_O) 0.045 2.427 r runnerObject/fcount_edge0/O
+ net (fo=12, routed) 0.210 2.637 runnerObject/fcount_edge0__0
+ SLICE_X88Y72 FDCE r runnerObject/fcount_edge_reg[11]/CE
+ ------------------------------------------------------------------- -------------------
+
+ (clock clk_out1_clk_wiz_0_1 rise edge)
+ 0.000 0.000 r
+ E3 0.000 0.000 r clk (IN)
+ net (fo=0) 0.000 0.000 pixelClk/inst/clk_in1
+ E3 IBUF (Prop_ibuf_I_O) 0.438 0.438 r pixelClk/inst/clkin1_ibufg/O
+ net (fo=1, routed) 0.480 0.918 pixelClk/inst/clk_in1_clk_wiz_0
+ MMCME2_ADV_X1Y2 MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKOUT0)
+ -3.163 -2.245 r pixelClk/inst/mmcm_adv_inst/CLKOUT0
+ net (fo=1, routed) 0.544 -1.702 pixelClk/inst/clk_out1_clk_wiz_0
+ BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.029 -1.673 r pixelClk/inst/clkout1_buf/O
+ net (fo=127, routed) 0.866 -0.807 runnerObject/clk_out1
+ SLICE_X88Y72 FDCE r runnerObject/fcount_edge_reg[11]/C
+
+Slack: inf
+ Source: btnU
+ (input port)
+ Destination: runnerObject/fcount_edge_reg[8]/CE
+ (rising edge-triggered cell FDCE clocked by clk_out1_clk_wiz_0_1 {rise@0.000ns fall@20.000ns period=40.000ns})
+ Path Group: (none)
+ Path Type: Hold (Min at Fast Process Corner)
+ Data Path Delay: 2.637ns (logic 0.286ns (10.841%) route 2.352ns (89.159%))
+ Logic Levels: 2 (IBUF=1 LUT3=1)
+ Clock Path Skew: -0.807ns (DCD - SCD - CPR)
+ Destination Clock Delay (DCD): -0.807ns
+ Source Clock Delay (SCD): 0.000ns
+ Clock Pessimism Removal (CPR): -0.000ns
+
+ Location Delay type Incr(ns) Path(ns) Netlist Resource(s)
+ ------------------------------------------------------------------- -------------------
+ F15 0.000 0.000 r btnU (IN)
+ net (fo=0) 0.000 0.000 btnU
+ F15 IBUF (Prop_ibuf_I_O) 0.241 0.241 r btnU_IBUF_inst/O
+ net (fo=2, routed) 2.141 2.382 runnerObject/btnU_IBUF
+ SLICE_X86Y75 LUT3 (Prop_lut3_I0_O) 0.045 2.427 r runnerObject/fcount_edge0/O
+ net (fo=12, routed) 0.210 2.637 runnerObject/fcount_edge0__0
+ SLICE_X88Y72 FDCE r runnerObject/fcount_edge_reg[8]/CE
+ ------------------------------------------------------------------- -------------------
+
+ (clock clk_out1_clk_wiz_0_1 rise edge)
+ 0.000 0.000 r
+ E3 0.000 0.000 r clk (IN)
+ net (fo=0) 0.000 0.000 pixelClk/inst/clk_in1
+ E3 IBUF (Prop_ibuf_I_O) 0.438 0.438 r pixelClk/inst/clkin1_ibufg/O
+ net (fo=1, routed) 0.480 0.918 pixelClk/inst/clk_in1_clk_wiz_0
+ MMCME2_ADV_X1Y2 MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKOUT0)
+ -3.163 -2.245 r pixelClk/inst/mmcm_adv_inst/CLKOUT0
+ net (fo=1, routed) 0.544 -1.702 pixelClk/inst/clk_out1_clk_wiz_0
+ BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.029 -1.673 r pixelClk/inst/clkout1_buf/O
+ net (fo=127, routed) 0.866 -0.807 runnerObject/clk_out1
+ SLICE_X88Y72 FDCE r runnerObject/fcount_edge_reg[8]/C
+
+Slack: inf
+ Source: btnU
+ (input port)
+ Destination: runnerObject/fcount_edge_reg[9]/CE
+ (rising edge-triggered cell FDCE clocked by clk_out1_clk_wiz_0_1 {rise@0.000ns fall@20.000ns period=40.000ns})
+ Path Group: (none)
+ Path Type: Hold (Min at Fast Process Corner)
+ Data Path Delay: 2.637ns (logic 0.286ns (10.841%) route 2.352ns (89.159%))
+ Logic Levels: 2 (IBUF=1 LUT3=1)
+ Clock Path Skew: -0.807ns (DCD - SCD - CPR)
+ Destination Clock Delay (DCD): -0.807ns
+ Source Clock Delay (SCD): 0.000ns
+ Clock Pessimism Removal (CPR): -0.000ns
+
+ Location Delay type Incr(ns) Path(ns) Netlist Resource(s)
+ ------------------------------------------------------------------- -------------------
+ F15 0.000 0.000 r btnU (IN)
+ net (fo=0) 0.000 0.000 btnU
+ F15 IBUF (Prop_ibuf_I_O) 0.241 0.241 r btnU_IBUF_inst/O
+ net (fo=2, routed) 2.141 2.382 runnerObject/btnU_IBUF
+ SLICE_X86Y75 LUT3 (Prop_lut3_I0_O) 0.045 2.427 r runnerObject/fcount_edge0/O
+ net (fo=12, routed) 0.210 2.637 runnerObject/fcount_edge0__0
+ SLICE_X88Y72 FDCE r runnerObject/fcount_edge_reg[9]/CE
+ ------------------------------------------------------------------- -------------------
+
+ (clock clk_out1_clk_wiz_0_1 rise edge)
+ 0.000 0.000 r
+ E3 0.000 0.000 r clk (IN)
+ net (fo=0) 0.000 0.000 pixelClk/inst/clk_in1
+ E3 IBUF (Prop_ibuf_I_O) 0.438 0.438 r pixelClk/inst/clkin1_ibufg/O
+ net (fo=1, routed) 0.480 0.918 pixelClk/inst/clk_in1_clk_wiz_0
+ MMCME2_ADV_X1Y2 MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKOUT0)
+ -3.163 -2.245 r pixelClk/inst/mmcm_adv_inst/CLKOUT0
+ net (fo=1, routed) 0.544 -1.702 pixelClk/inst/clk_out1_clk_wiz_0
+ BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.029 -1.673 r pixelClk/inst/clkout1_buf/O
+ net (fo=127, routed) 0.866 -0.807 runnerObject/clk_out1
+ SLICE_X88Y72 FDCE r runnerObject/fcount_edge_reg[9]/C
+
+Slack: inf
+ Source: btnU
+ (input port)
+ Destination: runnerObject/fcount_edge_reg[4]/CE
+ (rising edge-triggered cell FDCE clocked by clk_out1_clk_wiz_0_1 {rise@0.000ns fall@20.000ns period=40.000ns})
+ Path Group: (none)
+ Path Type: Hold (Min at Fast Process Corner)
+ Data Path Delay: 2.681ns (logic 0.286ns (10.663%) route 2.395ns (89.337%))
+ Logic Levels: 2 (IBUF=1 LUT3=1)
+ Clock Path Skew: -0.806ns (DCD - SCD - CPR)
+ Destination Clock Delay (DCD): -0.806ns
+ Source Clock Delay (SCD): 0.000ns
+ Clock Pessimism Removal (CPR): -0.000ns
+
+ Location Delay type Incr(ns) Path(ns) Netlist Resource(s)
+ ------------------------------------------------------------------- -------------------
+ F15 0.000 0.000 r btnU (IN)
+ net (fo=0) 0.000 0.000 btnU
+ F15 IBUF (Prop_ibuf_I_O) 0.241 0.241 r btnU_IBUF_inst/O
+ net (fo=2, routed) 2.141 2.382 runnerObject/btnU_IBUF
+ SLICE_X86Y75 LUT3 (Prop_lut3_I0_O) 0.045 2.427 r runnerObject/fcount_edge0/O
+ net (fo=12, routed) 0.254 2.681 runnerObject/fcount_edge0__0
+ SLICE_X88Y71 FDCE r runnerObject/fcount_edge_reg[4]/CE
+ ------------------------------------------------------------------- -------------------
+
+ (clock clk_out1_clk_wiz_0_1 rise edge)
+ 0.000 0.000 r
+ E3 0.000 0.000 r clk (IN)
+ net (fo=0) 0.000 0.000 pixelClk/inst/clk_in1
+ E3 IBUF (Prop_ibuf_I_O) 0.438 0.438 r pixelClk/inst/clkin1_ibufg/O
+ net (fo=1, routed) 0.480 0.918 pixelClk/inst/clk_in1_clk_wiz_0
+ MMCME2_ADV_X1Y2 MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKOUT0)
+ -3.163 -2.245 r pixelClk/inst/mmcm_adv_inst/CLKOUT0
+ net (fo=1, routed) 0.544 -1.702 pixelClk/inst/clk_out1_clk_wiz_0
+ BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.029 -1.673 r pixelClk/inst/clkout1_buf/O
+ net (fo=127, routed) 0.867 -0.806 runnerObject/clk_out1
+ SLICE_X88Y71 FDCE r runnerObject/fcount_edge_reg[4]/C
+
+Slack: inf
+ Source: btnU
+ (input port)
+ Destination: runnerObject/fcount_edge_reg[5]/CE
+ (rising edge-triggered cell FDCE clocked by clk_out1_clk_wiz_0_1 {rise@0.000ns fall@20.000ns period=40.000ns})
+ Path Group: (none)
+ Path Type: Hold (Min at Fast Process Corner)
+ Data Path Delay: 2.681ns (logic 0.286ns (10.663%) route 2.395ns (89.337%))
+ Logic Levels: 2 (IBUF=1 LUT3=1)
+ Clock Path Skew: -0.806ns (DCD - SCD - CPR)
+ Destination Clock Delay (DCD): -0.806ns
+ Source Clock Delay (SCD): 0.000ns
+ Clock Pessimism Removal (CPR): -0.000ns
+
+ Location Delay type Incr(ns) Path(ns) Netlist Resource(s)
+ ------------------------------------------------------------------- -------------------
+ F15 0.000 0.000 r btnU (IN)
+ net (fo=0) 0.000 0.000 btnU
+ F15 IBUF (Prop_ibuf_I_O) 0.241 0.241 r btnU_IBUF_inst/O
+ net (fo=2, routed) 2.141 2.382 runnerObject/btnU_IBUF
+ SLICE_X86Y75 LUT3 (Prop_lut3_I0_O) 0.045 2.427 r runnerObject/fcount_edge0/O
+ net (fo=12, routed) 0.254 2.681 runnerObject/fcount_edge0__0
+ SLICE_X88Y71 FDCE r runnerObject/fcount_edge_reg[5]/CE
+ ------------------------------------------------------------------- -------------------
+
+ (clock clk_out1_clk_wiz_0_1 rise edge)
+ 0.000 0.000 r
+ E3 0.000 0.000 r clk (IN)
+ net (fo=0) 0.000 0.000 pixelClk/inst/clk_in1
+ E3 IBUF (Prop_ibuf_I_O) 0.438 0.438 r pixelClk/inst/clkin1_ibufg/O
+ net (fo=1, routed) 0.480 0.918 pixelClk/inst/clk_in1_clk_wiz_0
+ MMCME2_ADV_X1Y2 MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKOUT0)
+ -3.163 -2.245 r pixelClk/inst/mmcm_adv_inst/CLKOUT0
+ net (fo=1, routed) 0.544 -1.702 pixelClk/inst/clk_out1_clk_wiz_0
+ BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.029 -1.673 r pixelClk/inst/clkout1_buf/O
+ net (fo=127, routed) 0.867 -0.806 runnerObject/clk_out1
+ SLICE_X88Y71 FDCE r runnerObject/fcount_edge_reg[5]/C
+
+Slack: inf
+ Source: btnU
+ (input port)
+ Destination: runnerObject/fcount_edge_reg[6]/CE
+ (rising edge-triggered cell FDCE clocked by clk_out1_clk_wiz_0_1 {rise@0.000ns fall@20.000ns period=40.000ns})
+ Path Group: (none)
+ Path Type: Hold (Min at Fast Process Corner)
+ Data Path Delay: 2.681ns (logic 0.286ns (10.663%) route 2.395ns (89.337%))
+ Logic Levels: 2 (IBUF=1 LUT3=1)
+ Clock Path Skew: -0.806ns (DCD - SCD - CPR)
+ Destination Clock Delay (DCD): -0.806ns
+ Source Clock Delay (SCD): 0.000ns
+ Clock Pessimism Removal (CPR): -0.000ns
+
+ Location Delay type Incr(ns) Path(ns) Netlist Resource(s)
+ ------------------------------------------------------------------- -------------------
+ F15 0.000 0.000 r btnU (IN)
+ net (fo=0) 0.000 0.000 btnU
+ F15 IBUF (Prop_ibuf_I_O) 0.241 0.241 r btnU_IBUF_inst/O
+ net (fo=2, routed) 2.141 2.382 runnerObject/btnU_IBUF
+ SLICE_X86Y75 LUT3 (Prop_lut3_I0_O) 0.045 2.427 r runnerObject/fcount_edge0/O
+ net (fo=12, routed) 0.254 2.681 runnerObject/fcount_edge0__0
+ SLICE_X88Y71 FDCE r runnerObject/fcount_edge_reg[6]/CE
+ ------------------------------------------------------------------- -------------------
+
+ (clock clk_out1_clk_wiz_0_1 rise edge)
+ 0.000 0.000 r
+ E3 0.000 0.000 r clk (IN)
+ net (fo=0) 0.000 0.000 pixelClk/inst/clk_in1
+ E3 IBUF (Prop_ibuf_I_O) 0.438 0.438 r pixelClk/inst/clkin1_ibufg/O
+ net (fo=1, routed) 0.480 0.918 pixelClk/inst/clk_in1_clk_wiz_0
+ MMCME2_ADV_X1Y2 MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKOUT0)
+ -3.163 -2.245 r pixelClk/inst/mmcm_adv_inst/CLKOUT0
+ net (fo=1, routed) 0.544 -1.702 pixelClk/inst/clk_out1_clk_wiz_0
+ BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.029 -1.673 r pixelClk/inst/clkout1_buf/O
+ net (fo=127, routed) 0.867 -0.806 runnerObject/clk_out1
+ SLICE_X88Y71 FDCE r runnerObject/fcount_edge_reg[6]/C
+
+Slack: inf
+ Source: btnU
+ (input port)
+ Destination: runnerObject/fcount_edge_reg[7]/CE
+ (rising edge-triggered cell FDCE clocked by clk_out1_clk_wiz_0_1 {rise@0.000ns fall@20.000ns period=40.000ns})
+ Path Group: (none)
+ Path Type: Hold (Min at Fast Process Corner)
+ Data Path Delay: 2.681ns (logic 0.286ns (10.663%) route 2.395ns (89.337%))
+ Logic Levels: 2 (IBUF=1 LUT3=1)
+ Clock Path Skew: -0.806ns (DCD - SCD - CPR)
+ Destination Clock Delay (DCD): -0.806ns
+ Source Clock Delay (SCD): 0.000ns
+ Clock Pessimism Removal (CPR): -0.000ns
+
+ Location Delay type Incr(ns) Path(ns) Netlist Resource(s)
+ ------------------------------------------------------------------- -------------------
+ F15 0.000 0.000 r btnU (IN)
+ net (fo=0) 0.000 0.000 btnU
+ F15 IBUF (Prop_ibuf_I_O) 0.241 0.241 r btnU_IBUF_inst/O
+ net (fo=2, routed) 2.141 2.382 runnerObject/btnU_IBUF
+ SLICE_X86Y75 LUT3 (Prop_lut3_I0_O) 0.045 2.427 r runnerObject/fcount_edge0/O
+ net (fo=12, routed) 0.254 2.681 runnerObject/fcount_edge0__0
+ SLICE_X88Y71 FDCE r runnerObject/fcount_edge_reg[7]/CE
+ ------------------------------------------------------------------- -------------------
+
+ (clock clk_out1_clk_wiz_0_1 rise edge)
+ 0.000 0.000 r
+ E3 0.000 0.000 r clk (IN)
+ net (fo=0) 0.000 0.000 pixelClk/inst/clk_in1
+ E3 IBUF (Prop_ibuf_I_O) 0.438 0.438 r pixelClk/inst/clkin1_ibufg/O
+ net (fo=1, routed) 0.480 0.918 pixelClk/inst/clk_in1_clk_wiz_0
+ MMCME2_ADV_X1Y2 MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKOUT0)
+ -3.163 -2.245 r pixelClk/inst/mmcm_adv_inst/CLKOUT0
+ net (fo=1, routed) 0.544 -1.702 pixelClk/inst/clk_out1_clk_wiz_0
+ BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.029 -1.673 r pixelClk/inst/clkout1_buf/O
+ net (fo=127, routed) 0.867 -0.806 runnerObject/clk_out1
+ SLICE_X88Y71 FDCE r runnerObject/fcount_edge_reg[7]/C
+
+Slack: inf
+ Source: btnU
+ (input port)
+ Destination: runnerObject/fcount_edge_reg[0]/CE
+ (rising edge-triggered cell FDCE clocked by clk_out1_clk_wiz_0_1 {rise@0.000ns fall@20.000ns period=40.000ns})
+ Path Group: (none)
+ Path Type: Hold (Min at Fast Process Corner)
+ Data Path Delay: 2.696ns (logic 0.286ns (10.603%) route 2.411ns (89.397%))
+ Logic Levels: 2 (IBUF=1 LUT3=1)
+ Clock Path Skew: -0.805ns (DCD - SCD - CPR)
+ Destination Clock Delay (DCD): -0.805ns
+ Source Clock Delay (SCD): 0.000ns
+ Clock Pessimism Removal (CPR): -0.000ns
+
+ Location Delay type Incr(ns) Path(ns) Netlist Resource(s)
+ ------------------------------------------------------------------- -------------------
+ F15 0.000 0.000 r btnU (IN)
+ net (fo=0) 0.000 0.000 btnU
+ F15 IBUF (Prop_ibuf_I_O) 0.241 0.241 r btnU_IBUF_inst/O
+ net (fo=2, routed) 2.141 2.382 runnerObject/btnU_IBUF
+ SLICE_X86Y75 LUT3 (Prop_lut3_I0_O) 0.045 2.427 r runnerObject/fcount_edge0/O
+ net (fo=12, routed) 0.269 2.696 runnerObject/fcount_edge0__0
+ SLICE_X88Y70 FDCE r runnerObject/fcount_edge_reg[0]/CE
+ ------------------------------------------------------------------- -------------------
+
+ (clock clk_out1_clk_wiz_0_1 rise edge)
+ 0.000 0.000 r
+ E3 0.000 0.000 r clk (IN)
+ net (fo=0) 0.000 0.000 pixelClk/inst/clk_in1
+ E3 IBUF (Prop_ibuf_I_O) 0.438 0.438 r pixelClk/inst/clkin1_ibufg/O
+ net (fo=1, routed) 0.480 0.918 pixelClk/inst/clk_in1_clk_wiz_0
+ MMCME2_ADV_X1Y2 MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKOUT0)
+ -3.163 -2.245 r pixelClk/inst/mmcm_adv_inst/CLKOUT0
+ net (fo=1, routed) 0.544 -1.702 pixelClk/inst/clk_out1_clk_wiz_0
+ BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.029 -1.673 r pixelClk/inst/clkout1_buf/O
+ net (fo=127, routed) 0.868 -0.805 runnerObject/clk_out1
+ SLICE_X88Y70 FDCE r runnerObject/fcount_edge_reg[0]/C
+
+
+
+
+
diff --git a/game.runs/impl_1/TopModule_timing_summary_routed.rpx b/game.runs/impl_1/TopModule_timing_summary_routed.rpx
new file mode 100644
index 0000000000000000000000000000000000000000..f64138df26bdccba2618879064579df3893070c2
Binary files /dev/null and b/game.runs/impl_1/TopModule_timing_summary_routed.rpx differ
diff --git a/game.runs/impl_1/TopModule_utilization_placed.pb b/game.runs/impl_1/TopModule_utilization_placed.pb
new file mode 100644
index 0000000000000000000000000000000000000000..2647e46a5675bc46751bc002766f8d5c37e25efb
Binary files /dev/null and b/game.runs/impl_1/TopModule_utilization_placed.pb differ
diff --git a/game.runs/impl_1/TopModule_utilization_placed.rpt b/game.runs/impl_1/TopModule_utilization_placed.rpt
new file mode 100644
index 0000000000000000000000000000000000000000..459750f3ce2a59d969c6bbe66d82629daaa36ee2
--- /dev/null
+++ b/game.runs/impl_1/TopModule_utilization_placed.rpt
@@ -0,0 +1,214 @@
+Copyright 1986-2022 Xilinx, Inc. All Rights Reserved.
+---------------------------------------------------------------------------------------------------------------
+| Tool Version : Vivado v.2022.2 (lin64) Build 3671981 Fri Oct 14 04:59:54 MDT 2022
+| Date : Tue Feb 28 17:02:15 2023
+| Host : LikeUE06 running 64-bit Linux Mint 20.3
+| Command : report_utilization -file TopModule_utilization_placed.rpt -pb TopModule_utilization_placed.pb
+| Design : TopModule
+| Device : xc7a100tcsg324-1
+| Speed File : -1
+| Design State : Fully Placed
+---------------------------------------------------------------------------------------------------------------
+
+Utilization Design Information
+
+Table of Contents
+-----------------
+1. Slice Logic
+1.1 Summary of Registers by Type
+2. Slice Logic Distribution
+3. Memory
+4. DSP
+5. IO and GT Specific
+6. Clocking
+7. Specific Feature
+8. Primitives
+9. Black Boxes
+10. Instantiated Netlists
+
+1. Slice Logic
+--------------
+
++-------------------------+------+-------+------------+-----------+-------+
+| Site Type | Used | Fixed | Prohibited | Available | Util% |
++-------------------------+------+-------+------------+-----------+-------+
+| Slice LUTs | 325 | 0 | 0 | 63400 | 0.51 |
+| LUT as Logic | 325 | 0 | 0 | 63400 | 0.51 |
+| LUT as Memory | 0 | 0 | 0 | 19000 | 0.00 |
+| Slice Registers | 127 | 0 | 0 | 126800 | 0.10 |
+| Register as Flip Flop | 127 | 0 | 0 | 126800 | 0.10 |
+| Register as Latch | 0 | 0 | 0 | 126800 | 0.00 |
+| F7 Muxes | 0 | 0 | 0 | 31700 | 0.00 |
+| F8 Muxes | 0 | 0 | 0 | 15850 | 0.00 |
++-------------------------+------+-------+------------+-----------+-------+
+* Warning! LUT value is adjusted to account for LUT combining.
+
+
+1.1 Summary of Registers by Type
+--------------------------------
+
++-------+--------------+-------------+--------------+
+| Total | Clock Enable | Synchronous | Asynchronous |
++-------+--------------+-------------+--------------+
+| 0 | _ | - | - |
+| 0 | _ | - | Set |
+| 0 | _ | - | Reset |
+| 0 | _ | Set | - |
+| 0 | _ | Reset | - |
+| 0 | Yes | - | - |
+| 10 | Yes | - | Set |
+| 76 | Yes | - | Reset |
+| 6 | Yes | Set | - |
+| 35 | Yes | Reset | - |
++-------+--------------+-------------+--------------+
+
+
+2. Slice Logic Distribution
+---------------------------
+
++--------------------------------------------+------+-------+------------+-----------+-------+
+| Site Type | Used | Fixed | Prohibited | Available | Util% |
++--------------------------------------------+------+-------+------------+-----------+-------+
+| Slice | 103 | 0 | 0 | 15850 | 0.65 |
+| SLICEL | 71 | 0 | | | |
+| SLICEM | 32 | 0 | | | |
+| LUT as Logic | 325 | 0 | 0 | 63400 | 0.51 |
+| using O5 output only | 10 | | | | |
+| using O6 output only | 217 | | | | |
+| using O5 and O6 | 98 | | | | |
+| LUT as Memory | 0 | 0 | 0 | 19000 | 0.00 |
+| LUT as Distributed RAM | 0 | 0 | | | |
+| LUT as Shift Register | 0 | 0 | | | |
+| Slice Registers | 127 | 0 | 0 | 126800 | 0.10 |
+| Register driven from within the Slice | 80 | | | | |
+| Register driven from outside the Slice | 47 | | | | |
+| LUT in front of the register is unused | 8 | | | | |
+| LUT in front of the register is used | 39 | | | | |
+| Unique Control Sets | 9 | | 0 | 15850 | 0.06 |
++--------------------------------------------+------+-------+------------+-----------+-------+
+* * Note: Available Control Sets calculated as Slice * 1, Review the Control Sets Report for more information regarding control sets.
+
+
+3. Memory
+---------
+
++----------------+------+-------+------------+-----------+-------+
+| Site Type | Used | Fixed | Prohibited | Available | Util% |
++----------------+------+-------+------------+-----------+-------+
+| Block RAM Tile | 0 | 0 | 0 | 135 | 0.00 |
+| RAMB36/FIFO* | 0 | 0 | 0 | 135 | 0.00 |
+| RAMB18 | 0 | 0 | 0 | 270 | 0.00 |
++----------------+------+-------+------------+-----------+-------+
+* Note: Each Block RAM Tile only has one FIFO logic available and therefore can accommodate only one FIFO36E1 or one FIFO18E1. However, if a FIFO18E1 occupies a Block RAM Tile, that tile can still accommodate a RAMB18E1
+
+
+4. DSP
+------
+
++-----------+------+-------+------------+-----------+-------+
+| Site Type | Used | Fixed | Prohibited | Available | Util% |
++-----------+------+-------+------------+-----------+-------+
+| DSPs | 0 | 0 | 0 | 240 | 0.00 |
++-----------+------+-------+------------+-----------+-------+
+
+
+5. IO and GT Specific
+---------------------
+
++-----------------------------+------+-------+------------+-----------+-------+
+| Site Type | Used | Fixed | Prohibited | Available | Util% |
++-----------------------------+------+-------+------------+-----------+-------+
+| Bonded IOB | 33 | 33 | 0 | 210 | 15.71 |
+| IOB Master Pads | 15 | | | | |
+| IOB Slave Pads | 18 | | | | |
+| Bonded IPADs | 0 | 0 | 0 | 2 | 0.00 |
+| PHY_CONTROL | 0 | 0 | 0 | 6 | 0.00 |
+| PHASER_REF | 0 | 0 | 0 | 6 | 0.00 |
+| OUT_FIFO | 0 | 0 | 0 | 24 | 0.00 |
+| IN_FIFO | 0 | 0 | 0 | 24 | 0.00 |
+| IDELAYCTRL | 0 | 0 | 0 | 6 | 0.00 |
+| IBUFDS | 0 | 0 | 0 | 202 | 0.00 |
+| PHASER_OUT/PHASER_OUT_PHY | 0 | 0 | 0 | 24 | 0.00 |
+| PHASER_IN/PHASER_IN_PHY | 0 | 0 | 0 | 24 | 0.00 |
+| IDELAYE2/IDELAYE2_FINEDELAY | 0 | 0 | 0 | 300 | 0.00 |
+| ILOGIC | 0 | 0 | 0 | 210 | 0.00 |
+| OLOGIC | 0 | 0 | 0 | 210 | 0.00 |
++-----------------------------+------+-------+------------+-----------+-------+
+
+
+6. Clocking
+-----------
+
++------------+------+-------+------------+-----------+-------+
+| Site Type | Used | Fixed | Prohibited | Available | Util% |
++------------+------+-------+------------+-----------+-------+
+| BUFGCTRL | 2 | 0 | 0 | 32 | 6.25 |
+| BUFIO | 0 | 0 | 0 | 24 | 0.00 |
+| MMCME2_ADV | 1 | 0 | 0 | 6 | 16.67 |
+| PLLE2_ADV | 0 | 0 | 0 | 6 | 0.00 |
+| BUFMRCE | 0 | 0 | 0 | 12 | 0.00 |
+| BUFHCE | 0 | 0 | 0 | 96 | 0.00 |
+| BUFR | 0 | 0 | 0 | 24 | 0.00 |
++------------+------+-------+------------+-----------+-------+
+
+
+7. Specific Feature
+-------------------
+
++-------------+------+-------+------------+-----------+-------+
+| Site Type | Used | Fixed | Prohibited | Available | Util% |
++-------------+------+-------+------------+-----------+-------+
+| BSCANE2 | 0 | 0 | 0 | 4 | 0.00 |
+| CAPTUREE2 | 0 | 0 | 0 | 1 | 0.00 |
+| DNA_PORT | 0 | 0 | 0 | 1 | 0.00 |
+| EFUSE_USR | 0 | 0 | 0 | 1 | 0.00 |
+| FRAME_ECCE2 | 0 | 0 | 0 | 1 | 0.00 |
+| ICAPE2 | 0 | 0 | 0 | 2 | 0.00 |
+| PCIE_2_1 | 0 | 0 | 0 | 1 | 0.00 |
+| STARTUPE2 | 0 | 0 | 0 | 1 | 0.00 |
+| XADC | 0 | 0 | 0 | 1 | 0.00 |
++-------------+------+-------+------------+-----------+-------+
+
+
+8. Primitives
+-------------
+
++------------+------+---------------------+
+| Ref Name | Used | Functional Category |
++------------+------+---------------------+
+| LUT2 | 98 | LUT |
+| LUT6 | 88 | LUT |
+| LUT4 | 77 | LUT |
+| FDCE | 76 | Flop & Latch |
+| LUT3 | 64 | LUT |
+| CARRY4 | 56 | CarryLogic |
+| LUT5 | 51 | LUT |
+| LUT1 | 45 | LUT |
+| FDRE | 35 | Flop & Latch |
+| OBUF | 30 | IO |
+| FDPE | 10 | Flop & Latch |
+| FDSE | 6 | Flop & Latch |
+| IBUF | 3 | IO |
+| BUFG | 2 | Clock |
+| MMCME2_ADV | 1 | Clock |
++------------+------+---------------------+
+
+
+9. Black Boxes
+--------------
+
++----------+------+
+| Ref Name | Used |
++----------+------+
+
+
+10. Instantiated Netlists
+-------------------------
+
++-----------+------+
+| Ref Name | Used |
++-----------+------+
+| clk_wiz_0 | 1 |
++-----------+------+
+
+
diff --git a/game.runs/impl_1/gen_run.xml b/game.runs/impl_1/gen_run.xml
new file mode 100644
index 0000000000000000000000000000000000000000..5582686dc89bfc1a81e5c07c27bae70288730ac2
--- /dev/null
+++ b/game.runs/impl_1/gen_run.xml
@@ -0,0 +1,193 @@
+<?xml version="1.0" encoding="UTF-8"?>
+<GenRun Id="impl_1" LaunchPart="xc7a100tcsg324-1" LaunchTime="1677600053">
+ <File Type="POSTROUTE-PHYSOPT-RQS-RPT" Name="postroute_physopt_report_qor_suggestions_0.rpt"/>
+ <File Type="ROUTE-RQS-RPT" Name="route_report_qor_suggestions_0.rpt"/>
+ <File Type="POSTROUTE-PHYSOPT-RQS" Name="TopModule_postroute_physopted.rqs"/>
+ <File Type="ROUTE-RQS" Name="TopModule_routed.rqs"/>
+ <File Type="WBT-USG" Name="usage_statistics_webtalk.html"/>
+ <File Type="BG-DRC" Name="TopModule.drc"/>
+ <File Type="BG-BGN" Name="TopModule.bgn"/>
+ <File Type="BITSTR-SYSDEF" Name="TopModule.sysdef"/>
+ <File Type="BITSTR-LTX" Name="debug_nets.ltx"/>
+ <File Type="BITSTR-LTX" Name="TopModule.ltx"/>
+ <File Type="RBD_FILE" Name="TopModule.rbd"/>
+ <File Type="NPI_FILE" Name="TopModule.npi"/>
+ <File Type="RNPI_FILE" Name="TopModule.rnpi"/>
+ <File Type="CFI_FILE" Name="TopModule.cfi"/>
+ <File Type="RCFI_FILE" Name="TopModule.rcfi"/>
+ <File Type="RDI-RDI" Name="TopModule.vdi"/>
+ <File Type="PDI-FILE" Name="TopModule.pdi"/>
+ <File Type="BITSTR-MMI" Name="TopModule.mmi"/>
+ <File Type="BITSTR-BMM" Name="TopModule_bd.bmm"/>
+ <File Type="BITSTR-NKY" Name="TopModule.nky"/>
+ <File Type="BITSTR-RBT" Name="TopModule.rbt"/>
+ <File Type="BITSTR-MSK" Name="TopModule.msk"/>
+ <File Type="BG-BIN" Name="TopModule.bin"/>
+ <File Type="BG-BIT" Name="TopModule.bit"/>
+ <File Type="POSTROUTE-PHYSOPT-BUS-SKEW-RPX" Name="TopModule_bus_skew_postroute_physopted.rpx"/>
+ <File Type="POSTROUTE-PHYSOPT-BUS-SKEW-PB" Name="TopModule_bus_skew_postroute_physopted.pb"/>
+ <File Type="POSTROUTE-PHYSOPT-BUS-SKEW" Name="TopModule_bus_skew_postroute_physopted.rpt"/>
+ <File Type="POSTROUTE-PHYSOPT-TIMING-RPX" Name="TopModule_timing_summary_postroute_physopted.rpx"/>
+ <File Type="POSTROUTE-PHYSOPT-TIMING-PB" Name="TopModule_timing_summary_postroute_physopted.pb"/>
+ <File Type="POSTROUTE-PHYSOPT-TIMING" Name="TopModule_timing_summary_postroute_physopted.rpt"/>
+ <File Type="POSTROUTE-PHYSOPT-BLACKBOX-DCP" Name="TopModule_postroute_physopt_bb.dcp"/>
+ <File Type="POSTROUTE-PHYSOPT-DCP" Name="TopModule_postroute_physopt.dcp"/>
+ <File Type="ROUTE-BUS-SKEW-RPX" Name="TopModule_bus_skew_routed.rpx"/>
+ <File Type="ROUTE-BUS-SKEW-PB" Name="TopModule_bus_skew_routed.pb"/>
+ <File Type="ROUTE-BUS-SKEW" Name="TopModule_bus_skew_routed.rpt"/>
+ <File Type="ROUTE-CLK" Name="TopModule_clock_utilization_routed.rpt"/>
+ <File Type="ROUTE-SIMILARITY" Name="TopModule_incremental_reuse_routed.rpt"/>
+ <File Type="ROUTE-TIMING-RPX" Name="TopModule_timing_summary_routed.rpx"/>
+ <File Type="ROUTE-TIMING-PB" Name="TopModule_timing_summary_routed.pb"/>
+ <File Type="ROUTE-TIMINGSUMMARY" Name="TopModule_timing_summary_routed.rpt"/>
+ <File Type="ROUTE-STATUS-PB" Name="TopModule_route_status.pb"/>
+ <File Type="ROUTE-STATUS" Name="TopModule_route_status.rpt"/>
+ <File Type="ROUTE-PWR-RPX" Name="TopModule_power_routed.rpx"/>
+ <File Type="ROUTE-PWR-SUM" Name="TopModule_power_summary_routed.pb"/>
+ <File Type="ROUTE-PWR" Name="TopModule_power_routed.rpt"/>
+ <File Type="ROUTE-METHODOLOGY-DRC-PB" Name="TopModule_methodology_drc_routed.pb"/>
+ <File Type="ROUTE-METHODOLOGY-DRC-RPX" Name="TopModule_methodology_drc_routed.rpx"/>
+ <File Type="ROUTE-METHODOLOGY-DRC" Name="TopModule_methodology_drc_routed.rpt"/>
+ <File Type="ROUTE-DRC-RPX" Name="TopModule_drc_routed.rpx"/>
+ <File Type="ROUTE-DRC-PB" Name="TopModule_drc_routed.pb"/>
+ <File Type="ROUTE-DRC" Name="TopModule_drc_routed.rpt"/>
+ <File Type="ROUTE-BLACKBOX-DCP" Name="TopModule_routed_bb.dcp"/>
+ <File Type="ROUTE-DCP" Name="TopModule_routed.dcp"/>
+ <File Type="ROUTE-ERROR-DCP" Name="TopModule_routed_error.dcp"/>
+ <File Type="PHYSOPT-TIMING" Name="TopModule_timing_summary_physopted.rpt"/>
+ <File Type="PHYSOPT-DRC" Name="TopModule_drc_physopted.rpt"/>
+ <File Type="PHYSOPT-DCP" Name="TopModule_physopt.dcp"/>
+ <File Type="POSTPLACE-PWROPT-TIMING" Name="TopModule_timing_summary_postplace_pwropted.rpt"/>
+ <File Type="POSTPLACE-PWROPT-DCP" Name="TopModule_postplace_pwropt.dcp"/>
+ <File Type="PLACE-TIMING" Name="TopModule_timing_summary_placed.rpt"/>
+ <File Type="PLACE-PRE-SIMILARITY" Name="TopModule_incremental_reuse_pre_placed.rpt"/>
+ <File Type="PLACE-SIMILARITY" Name="TopModule_incremental_reuse_placed.rpt"/>
+ <File Type="PLACE-CTRL" Name="TopModule_control_sets_placed.rpt"/>
+ <File Type="PLACE-UTIL-PB" Name="TopModule_utilization_placed.pb"/>
+ <File Type="PLACE-UTIL" Name="TopModule_utilization_placed.rpt"/>
+ <File Type="PLACE-CLK" Name="TopModule_clock_utilization_placed.rpt"/>
+ <File Type="PLACE-IO" Name="TopModule_io_placed.rpt"/>
+ <File Type="PLACE-DCP" Name="TopModule_placed.dcp"/>
+ <File Type="PWROPT-TIMING" Name="TopModule_timing_summary_pwropted.rpt"/>
+ <File Type="PWROPT-DRC" Name="TopModule_drc_pwropted.rpt"/>
+ <File Type="PWROPT-DCP" Name="TopModule_pwropt.dcp"/>
+ <File Type="OPT-HWDEF" Name="TopModule.hwdef"/>
+ <File Type="OPT-METHODOLOGY-DRC" Name="TopModule_methodology_drc_opted.rpt"/>
+ <File Type="OPT-DRC" Name="TopModule_drc_opted.rpt"/>
+ <File Type="OPT-DCP" Name="TopModule_opt.dcp"/>
+ <File Type="OPT-TIMING" Name="TopModule_timing_summary_opted.rpt"/>
+ <File Type="REPORTS-TCL" Name="TopModule_reports.tcl"/>
+ <File Type="INIT-TIMING" Name="TopModule_timing_summary_init.rpt"/>
+ <File Type="PA-TCL" Name="TopModule.tcl"/>
+ <FileSet Name="sources" Type="DesignSrcs" RelSrcDir="$PSRCDIR/sources_1" RelGenDir="$PGENDIR/sources_1">
+ <Filter Type="Srcs"/>
+ <File Path="$PSRCDIR/sources_1/new/header.vhd">
+ <FileInfo>
+ <Attr Name="UsedIn" Val="synthesis"/>
+ <Attr Name="UsedIn" Val="simulation"/>
+ </FileInfo>
+ </File>
+ <File Path="$PSRCDIR/sources_1/new/background.vhd">
+ <FileInfo>
+ <Attr Name="UsedIn" Val="synthesis"/>
+ <Attr Name="UsedIn" Val="simulation"/>
+ </FileInfo>
+ </File>
+ <File Path="$PSRCDIR/sources_1/new/collision.vhd">
+ <FileInfo>
+ <Attr Name="UsedIn" Val="synthesis"/>
+ <Attr Name="UsedIn" Val="simulation"/>
+ </FileInfo>
+ </File>
+ <File Path="$PSRCDIR/sources_1/new/obstacle.vhd">
+ <FileInfo>
+ <Attr Name="UsedIn" Val="synthesis"/>
+ <Attr Name="UsedIn" Val="simulation"/>
+ </FileInfo>
+ </File>
+ <File Path="$PSRCDIR/sources_1/new/obstacle2.vhd">
+ <FileInfo>
+ <Attr Name="UsedIn" Val="synthesis"/>
+ <Attr Name="UsedIn" Val="simulation"/>
+ </FileInfo>
+ </File>
+ <File Path="$PSRCDIR/sources_1/new/priority.vhd">
+ <FileInfo>
+ <Attr Name="UsedIn" Val="synthesis"/>
+ <Attr Name="UsedIn" Val="simulation"/>
+ </FileInfo>
+ </File>
+ <File Path="$PSRCDIR/sources_1/new/runner.vhd">
+ <FileInfo>
+ <Attr Name="UsedIn" Val="synthesis"/>
+ <Attr Name="UsedIn" Val="simulation"/>
+ </FileInfo>
+ </File>
+ <File Path="$PSRCDIR/sources_1/new/vga.vhd">
+ <FileInfo>
+ <Attr Name="UsedIn" Val="synthesis"/>
+ <Attr Name="UsedIn" Val="simulation"/>
+ </FileInfo>
+ </File>
+ <File Path="$PSRCDIR/sources_1/new/TopModule.vhd">
+ <FileInfo>
+ <Attr Name="UsedIn" Val="synthesis"/>
+ <Attr Name="UsedIn" Val="simulation"/>
+ </FileInfo>
+ </File>
+ <File Path="$PSRCDIR/sources_1/ip/clk_wiz_1/clk_wiz_1.xci">
+ <FileInfo>
+ <Attr Name="AutoDisabled" Val="1"/>
+ <Attr Name="UsedIn" Val="synthesis"/>
+ <Attr Name="UsedIn" Val="implementation"/>
+ <Attr Name="UsedIn" Val="simulation"/>
+ </FileInfo>
+ </File>
+ <Config>
+ <Option Name="DesignMode" Val="RTL"/>
+ <Option Name="TopModule" Val="TopModule"/>
+ <Option Name="TopAutoSet" Val="TRUE"/>
+ </Config>
+ </FileSet>
+ <FileSet Name="constrs_in" Type="Constrs" RelSrcDir="$PSRCDIR/constrs_1">
+ <Filter Type="Constrs"/>
+ <File Path="$PSRCDIR/constrs_1/imports/PrASIC_Data/Nexys4_Master.xdc">
+ <FileInfo>
+ <Attr Name="ImportPath" Val="$PPRDIR/../Schreibtisch/PrASIC_Data/Nexys4_Master.xdc"/>
+ <Attr Name="ImportTime" Val="1378293982"/>
+ <Attr Name="UsedIn" Val="synthesis"/>
+ <Attr Name="UsedIn" Val="implementation"/>
+ </FileInfo>
+ </File>
+ <Config>
+ <Option Name="ConstrsType" Val="XDC"/>
+ </Config>
+ </FileSet>
+ <FileSet Name="utils" Type="Utils" RelSrcDir="$PSRCDIR/utils_1">
+ <Filter Type="Utils"/>
+ <File Path="$PSRCDIR/utils_1/imports/synth_1/TopModule.dcp">
+ <FileInfo>
+ <Attr Name="UsedIn" Val="synthesis"/>
+ <Attr Name="UsedIn" Val="implementation"/>
+ <Attr Name="UsedInSteps" Val="synth_1"/>
+ <Attr Name="AutoDcp" Val="1"/>
+ </FileInfo>
+ </File>
+ <Config>
+ <Option Name="TopAutoSet" Val="TRUE"/>
+ </Config>
+ </FileSet>
+ <Strategy Version="1" Minor="2">
+ <StratHandle Name="Vivado Implementation Defaults" Flow="Vivado Implementation 2022"/>
+ <Step Id="init_design"/>
+ <Step Id="opt_design"/>
+ <Step Id="power_opt_design"/>
+ <Step Id="place_design"/>
+ <Step Id="post_place_power_opt_design"/>
+ <Step Id="phys_opt_design"/>
+ <Step Id="route_design"/>
+ <Step Id="post_route_phys_opt_design"/>
+ <Step Id="write_bitstream"/>
+ </Strategy>
+ <BlockFileSet Type="BlockSrcs" Name="clk_wiz_0"/>
+</GenRun>
diff --git a/game.runs/impl_1/htr.txt b/game.runs/impl_1/htr.txt
new file mode 100644
index 0000000000000000000000000000000000000000..6de39999109de31dea7cfa2cc66ec59abb134bea
--- /dev/null
+++ b/game.runs/impl_1/htr.txt
@@ -0,0 +1,9 @@
+#
+# Vivado(TM)
+# htr.txt: a Vivado-generated description of how-to-repeat the
+# the basic steps of a run. Note that runme.bat/sh needs
+# to be invoked for Vivado to track run status.
+# Copyright 1986-2022 Xilinx, Inc. All Rights Reserved.
+#
+
+vivado -log TopModule.vdi -applog -m64 -product Vivado -messageDb vivado.pb -mode batch -source TopModule.tcl -notrace
diff --git a/game.runs/impl_1/init_design.pb b/game.runs/impl_1/init_design.pb
new file mode 100644
index 0000000000000000000000000000000000000000..a47140ea5b2c49352350e0049797bbdca51edda5
Binary files /dev/null and b/game.runs/impl_1/init_design.pb differ
diff --git a/game.runs/impl_1/opt_design.pb b/game.runs/impl_1/opt_design.pb
new file mode 100644
index 0000000000000000000000000000000000000000..1d7dc8f055dd7d0d83cb3af8a8a835825ed0540c
Binary files /dev/null and b/game.runs/impl_1/opt_design.pb differ
diff --git a/game.runs/impl_1/phys_opt_design.pb b/game.runs/impl_1/phys_opt_design.pb
new file mode 100644
index 0000000000000000000000000000000000000000..4bcb93b41b9697f96036a5973dd87a355b5b823d
Binary files /dev/null and b/game.runs/impl_1/phys_opt_design.pb differ
diff --git a/game.runs/impl_1/place_design.pb b/game.runs/impl_1/place_design.pb
new file mode 100644
index 0000000000000000000000000000000000000000..c7f6a8b9b62458e8b975fdb3f609fa5ae4dcd6d3
Binary files /dev/null and b/game.runs/impl_1/place_design.pb differ
diff --git a/game.runs/impl_1/project.wdf b/game.runs/impl_1/project.wdf
new file mode 100644
index 0000000000000000000000000000000000000000..2dda252df1d9127f51633f1444fab78f9818ef6d
--- /dev/null
+++ b/game.runs/impl_1/project.wdf
@@ -0,0 +1,32 @@
+version:1
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diff --git a/game.runs/impl_1/route_design.pb b/game.runs/impl_1/route_design.pb
new file mode 100644
index 0000000000000000000000000000000000000000..2265bd2caf4628e8e8a58cf1b5825cfa77e98dd3
Binary files /dev/null and b/game.runs/impl_1/route_design.pb differ
diff --git a/game.runs/impl_1/rundef.js b/game.runs/impl_1/rundef.js
new file mode 100644
index 0000000000000000000000000000000000000000..5e3ae51ad8685bea540f9325e7c5e6ea9b718773
--- /dev/null
+++ b/game.runs/impl_1/rundef.js
@@ -0,0 +1,44 @@
+//
+// Vivado(TM)
+// rundef.js: a Vivado-generated Runs Script for WSH 5.1/5.6
+// Copyright 1986-2022 Xilinx, Inc. All Rights Reserved.
+//
+
+echo "This script was generated under a different operating system."
+echo "Please update the PATH variable below, before executing this script"
+exit
+
+var WshShell = new ActiveXObject( "WScript.Shell" );
+var ProcEnv = WshShell.Environment( "Process" );
+var PathVal = ProcEnv("PATH");
+if ( PathVal.length == 0 ) {
+ PathVal = "/opt/Xilinx/Vivado/2022.2/ids_lite/ISE/bin/lin64;/opt/Xilinx/Vivado/2022.2/bin;";
+} else {
+ PathVal = "/opt/Xilinx/Vivado/2022.2/ids_lite/ISE/bin/lin64;/opt/Xilinx/Vivado/2022.2/bin;" + PathVal;
+}
+
+ProcEnv("PATH") = PathVal;
+
+var RDScrFP = WScript.ScriptFullName;
+var RDScrN = WScript.ScriptName;
+var RDScrDir = RDScrFP.substr( 0, RDScrFP.length - RDScrN.length - 1 );
+var ISEJScriptLib = RDScrDir + "/ISEWrap.js";
+eval( EAInclude(ISEJScriptLib) );
+
+
+// pre-commands:
+ISETouchFile( "init_design", "begin" );
+ISEStep( "vivado",
+ "-log TopModule.vdi -applog -m64 -product Vivado -messageDb vivado.pb -mode batch -source TopModule.tcl -notrace" );
+
+
+
+
+
+function EAInclude( EAInclFilename ) {
+ var EAFso = new ActiveXObject( "Scripting.FileSystemObject" );
+ var EAInclFile = EAFso.OpenTextFile( EAInclFilename );
+ var EAIFContents = EAInclFile.ReadAll();
+ EAInclFile.Close();
+ return EAIFContents;
+}
diff --git a/game.runs/impl_1/runme.bat b/game.runs/impl_1/runme.bat
new file mode 100644
index 0000000000000000000000000000000000000000..c51ae31743272e84250ece027d86207732473138
--- /dev/null
+++ b/game.runs/impl_1/runme.bat
@@ -0,0 +1,11 @@
+@echo off
+
+rem Vivado (TM)
+rem runme.bat: a Vivado-generated Script
+rem Copyright 1986-2022 Xilinx, Inc. All Rights Reserved.
+
+
+set HD_SDIR=%~dp0
+cd /d "%HD_SDIR%"
+set PATH=%SYSTEMROOT%\system32;%PATH%
+cscript /nologo /E:JScript "%HD_SDIR%\rundef.js" %*
diff --git a/game.runs/impl_1/runme.log b/game.runs/impl_1/runme.log
new file mode 100644
index 0000000000000000000000000000000000000000..fa18320fff10f3ef71cfb2f94bf5e22d3a9d5b00
--- /dev/null
+++ b/game.runs/impl_1/runme.log
@@ -0,0 +1,639 @@
+
+*** Running vivado
+ with args -log TopModule.vdi -applog -m64 -product Vivado -messageDb vivado.pb -mode batch -source TopModule.tcl -notrace
+
+
+****** Vivado v2022.2 (64-bit)
+ **** SW Build 3671981 on Fri Oct 14 04:59:54 MDT 2022
+ **** IP Build 3669848 on Fri Oct 14 08:30:02 MDT 2022
+ ** Copyright 1986-2022 Xilinx, Inc. All Rights Reserved.
+
+source TopModule.tcl -notrace
+Command: link_design -top TopModule -part xc7a100tcsg324-1
+Design is defaulting to srcset: sources_1
+Design is defaulting to constrset: constrs_1
+INFO: [Device 21-403] Loading part xc7a100tcsg324-1
+INFO: [Project 1-454] Reading design checkpoint '/home/prasic/game/game.gen/sources_1/ip/clk_wiz_0/clk_wiz_0.dcp' for cell 'pixelClk'
+Netlist sorting complete. Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.01 . Memory (MB): peak = 1606.039 ; gain = 0.000 ; free physical = 4908 ; free virtual = 31886
+INFO: [Netlist 29-17] Analyzing 57 Unisim elements for replacement
+INFO: [Netlist 29-28] Unisim Transformation completed in 0 CPU seconds
+INFO: [Project 1-479] Netlist was created with Vivado 2022.2
+INFO: [Project 1-570] Preparing netlist for logic optimization
+Parsing XDC File [/home/prasic/game/game.gen/sources_1/ip/clk_wiz_0/clk_wiz_0_board.xdc] for cell 'pixelClk/inst'
+Finished Parsing XDC File [/home/prasic/game/game.gen/sources_1/ip/clk_wiz_0/clk_wiz_0_board.xdc] for cell 'pixelClk/inst'
+Parsing XDC File [/home/prasic/game/game.gen/sources_1/ip/clk_wiz_0/clk_wiz_0.xdc] for cell 'pixelClk/inst'
+INFO: [Timing 38-35] Done setting XDC timing constraints. [/home/prasic/game/game.gen/sources_1/ip/clk_wiz_0/clk_wiz_0.xdc:57]
+INFO: [Timing 38-2] Deriving generated clocks [/home/prasic/game/game.gen/sources_1/ip/clk_wiz_0/clk_wiz_0.xdc:57]
+get_clocks: Time (s): cpu = 00:00:07 ; elapsed = 00:00:07 . Memory (MB): peak = 2300.449 ; gain = 548.789 ; free physical = 4424 ; free virtual = 31402
+Finished Parsing XDC File [/home/prasic/game/game.gen/sources_1/ip/clk_wiz_0/clk_wiz_0.xdc] for cell 'pixelClk/inst'
+Parsing XDC File [/home/prasic/game/game.srcs/constrs_1/imports/PrASIC_Data/Nexys4_Master.xdc]
+Finished Parsing XDC File [/home/prasic/game/game.srcs/constrs_1/imports/PrASIC_Data/Nexys4_Master.xdc]
+INFO: [Opt 31-138] Pushed 0 inverter(s) to 0 load pin(s).
+Netlist sorting complete. Time (s): cpu = 00:00:00 ; elapsed = 00:00:00 . Memory (MB): peak = 2300.449 ; gain = 0.000 ; free physical = 4423 ; free virtual = 31401
+INFO: [Project 1-111] Unisim Transformation Summary:
+No Unisim elements were transformed.
+
+10 Infos, 0 Warnings, 0 Critical Warnings and 0 Errors encountered.
+link_design completed successfully
+link_design: Time (s): cpu = 00:00:12 ; elapsed = 00:00:12 . Memory (MB): peak = 2300.449 ; gain = 1034.520 ; free physical = 4423 ; free virtual = 31401
+Command: opt_design
+Attempting to get a license for feature 'Implementation' and/or device 'xc7a100t'
+INFO: [Common 17-349] Got license for feature 'Implementation' and/or device 'xc7a100t'
+Running DRC as a precondition to command opt_design
+
+Starting DRC Task
+INFO: [DRC 23-27] Running DRC with 8 threads
+INFO: [Project 1-461] DRC finished with 0 Errors
+INFO: [Project 1-462] Please refer to the DRC report (report_drc) for more information.
+
+Time (s): cpu = 00:00:01 ; elapsed = 00:00:00.76 . Memory (MB): peak = 2364.480 ; gain = 64.031 ; free physical = 4413 ; free virtual = 31390
+
+Starting Cache Timing Information Task
+INFO: [Timing 38-35] Done setting XDC timing constraints.
+INFO: [Timing 38-2] Deriving generated clocks
+Ending Cache Timing Information Task | Checksum: 14d4bc14b
+
+Time (s): cpu = 00:00:00.05 ; elapsed = 00:00:00.03 . Memory (MB): peak = 2364.480 ; gain = 0.000 ; free physical = 4413 ; free virtual = 31390
+
+Starting Logic Optimization Task
+
+Phase 1 Retarget
+INFO: [Opt 31-1287] Pulled Inverter vgaInterface/vgaRed_OBUF[2]_inst_i_1 into driver instance vgaInterface/vgaRed_OBUF[3]_inst_i_3, which resulted in an inversion of 7 pins
+INFO: [Opt 31-138] Pushed 1 inverter(s) to 1 load pin(s).
+INFO: [Opt 31-49] Retargeted 0 cell(s).
+Phase 1 Retarget | Checksum: 18dadb2af
+
+Time (s): cpu = 00:00:00.1 ; elapsed = 00:00:00.04 . Memory (MB): peak = 2616.262 ; gain = 0.000 ; free physical = 4167 ; free virtual = 31144
+INFO: [Opt 31-389] Phase Retarget created 0 cells and removed 3 cells
+INFO: [Opt 31-1021] In phase Retarget, 1 netlist objects are constrained preventing optimization. Please run opt_design with -debug_log to get more detail.
+
+Phase 2 Constant propagation
+INFO: [Opt 31-138] Pushed 0 inverter(s) to 0 load pin(s).
+Phase 2 Constant propagation | Checksum: 18dadb2af
+
+Time (s): cpu = 00:00:00.1 ; elapsed = 00:00:00.05 . Memory (MB): peak = 2616.262 ; gain = 0.000 ; free physical = 4167 ; free virtual = 31144
+INFO: [Opt 31-389] Phase Constant propagation created 0 cells and removed 0 cells
+
+Phase 3 Sweep
+Phase 3 Sweep | Checksum: 1ae9a062c
+
+Time (s): cpu = 00:00:00.11 ; elapsed = 00:00:00.06 . Memory (MB): peak = 2616.262 ; gain = 0.000 ; free physical = 4167 ; free virtual = 31144
+INFO: [Opt 31-389] Phase Sweep created 3 cells and removed 0 cells
+
+Phase 4 BUFG optimization
+Phase 4 BUFG optimization | Checksum: 1ae9a062c
+
+Time (s): cpu = 00:00:00.12 ; elapsed = 00:00:00.06 . Memory (MB): peak = 2616.262 ; gain = 0.000 ; free physical = 4167 ; free virtual = 31144
+INFO: [Opt 31-662] Phase BUFG optimization created 0 cells of which 0 are BUFGs and removed 0 cells.
+
+Phase 5 Shift Register Optimization
+INFO: [Opt 31-1064] SRL Remap converted 0 SRLs to 0 registers and converted 0 registers of register chains to 0 SRLs
+Phase 5 Shift Register Optimization | Checksum: 1ae9a062c
+
+Time (s): cpu = 00:00:00.13 ; elapsed = 00:00:00.07 . Memory (MB): peak = 2616.262 ; gain = 0.000 ; free physical = 4167 ; free virtual = 31144
+INFO: [Opt 31-389] Phase Shift Register Optimization created 0 cells and removed 0 cells
+
+Phase 6 Post Processing Netlist
+Phase 6 Post Processing Netlist | Checksum: 173c369ee
+
+Time (s): cpu = 00:00:00.13 ; elapsed = 00:00:00.07 . Memory (MB): peak = 2616.262 ; gain = 0.000 ; free physical = 4167 ; free virtual = 31144
+INFO: [Opt 31-389] Phase Post Processing Netlist created 0 cells and removed 0 cells
+Opt_design Change Summary
+=========================
+
+
+-------------------------------------------------------------------------------------------------------------------------
+| Phase | #Cells created | #Cells Removed | #Constrained objects preventing optimizations |
+-------------------------------------------------------------------------------------------------------------------------
+| Retarget | 0 | 3 | 1 |
+| Constant propagation | 0 | 0 | 0 |
+| Sweep | 3 | 0 | 0 |
+| BUFG optimization | 0 | 0 | 0 |
+| Shift Register Optimization | 0 | 0 | 0 |
+| Post Processing Netlist | 0 | 0 | 0 |
+-------------------------------------------------------------------------------------------------------------------------
+
+
+
+Starting Connectivity Check Task
+
+Time (s): cpu = 00:00:00.01 ; elapsed = 00:00:00.01 . Memory (MB): peak = 2616.262 ; gain = 0.000 ; free physical = 4167 ; free virtual = 31144
+Ending Logic Optimization Task | Checksum: 1e32b2645
+
+Time (s): cpu = 00:00:00.17 ; elapsed = 00:00:00.1 . Memory (MB): peak = 2616.262 ; gain = 0.000 ; free physical = 4167 ; free virtual = 31144
+
+Starting Power Optimization Task
+INFO: [Pwropt 34-132] Skipping clock gating for clocks with a period < 2.00 ns.
+Ending Power Optimization Task | Checksum: 1e32b2645
+
+Time (s): cpu = 00:00:00 ; elapsed = 00:00:00 . Memory (MB): peak = 2616.262 ; gain = 0.000 ; free physical = 4167 ; free virtual = 31144
+
+Starting Final Cleanup Task
+Ending Final Cleanup Task | Checksum: 1e32b2645
+
+Time (s): cpu = 00:00:00 ; elapsed = 00:00:00 . Memory (MB): peak = 2616.262 ; gain = 0.000 ; free physical = 4167 ; free virtual = 31144
+
+Starting Netlist Obfuscation Task
+Netlist sorting complete. Time (s): cpu = 00:00:00 ; elapsed = 00:00:00 . Memory (MB): peak = 2616.262 ; gain = 0.000 ; free physical = 4167 ; free virtual = 31144
+Ending Netlist Obfuscation Task | Checksum: 1e32b2645
+
+Time (s): cpu = 00:00:00 ; elapsed = 00:00:00 . Memory (MB): peak = 2616.262 ; gain = 0.000 ; free physical = 4167 ; free virtual = 31144
+INFO: [Common 17-83] Releasing license: Implementation
+30 Infos, 0 Warnings, 0 Critical Warnings and 0 Errors encountered.
+opt_design completed successfully
+INFO: [Timing 38-480] Writing timing data to binary archive.
+Writing XDEF routing.
+Writing XDEF routing logical nets.
+Writing XDEF routing special nets.
+Write XDEF Complete: Time (s): cpu = 00:00:00.08 ; elapsed = 00:00:00.02 . Memory (MB): peak = 2648.277 ; gain = 24.012 ; free physical = 4161 ; free virtual = 31138
+INFO: [Common 17-1381] The checkpoint '/home/prasic/game/game.runs/impl_1/TopModule_opt.dcp' has been generated.
+INFO: [runtcl-4] Executing : report_drc -file TopModule_drc_opted.rpt -pb TopModule_drc_opted.pb -rpx TopModule_drc_opted.rpx
+Command: report_drc -file TopModule_drc_opted.rpt -pb TopModule_drc_opted.pb -rpx TopModule_drc_opted.rpx
+INFO: [IP_Flow 19-1839] IP Catalog is up to date.
+INFO: [DRC 23-27] Running DRC with 8 threads
+INFO: [Vivado_Tcl 2-168] The results of DRC are in file /home/prasic/game/game.runs/impl_1/TopModule_drc_opted.rpt.
+report_drc completed successfully
+Command: place_design
+Attempting to get a license for feature 'Implementation' and/or device 'xc7a100t'
+INFO: [Common 17-349] Got license for feature 'Implementation' and/or device 'xc7a100t'
+INFO: [DRC 23-27] Running DRC with 8 threads
+INFO: [Vivado_Tcl 4-198] DRC finished with 0 Errors
+INFO: [Vivado_Tcl 4-199] Please refer to the DRC report (report_drc) for more information.
+Running DRC as a precondition to command place_design
+INFO: [DRC 23-27] Running DRC with 8 threads
+INFO: [Vivado_Tcl 4-198] DRC finished with 0 Errors
+INFO: [Vivado_Tcl 4-199] Please refer to the DRC report (report_drc) for more information.
+
+Starting Placer Task
+INFO: [Place 30-611] Multithreading enabled for place_design using a maximum of 8 CPUs
+
+Phase 1 Placer Initialization
+
+Phase 1.1 Placer Initialization Netlist Sorting
+Netlist sorting complete. Time (s): cpu = 00:00:00 ; elapsed = 00:00:00 . Memory (MB): peak = 2720.312 ; gain = 0.000 ; free physical = 4145 ; free virtual = 31122
+Phase 1.1 Placer Initialization Netlist Sorting | Checksum: 15c9b26e4
+
+Time (s): cpu = 00:00:00.01 ; elapsed = 00:00:00.03 . Memory (MB): peak = 2720.312 ; gain = 0.000 ; free physical = 4145 ; free virtual = 31122
+Netlist sorting complete. Time (s): cpu = 00:00:00 ; elapsed = 00:00:00 . Memory (MB): peak = 2720.312 ; gain = 0.000 ; free physical = 4145 ; free virtual = 31122
+
+Phase 1.2 IO Placement/ Clock Placement/ Build Placer Device
+INFO: [Timing 38-35] Done setting XDC timing constraints.
+Phase 1.2 IO Placement/ Clock Placement/ Build Placer Device | Checksum: 105221de9
+
+Time (s): cpu = 00:00:00.25 ; elapsed = 00:00:00.19 . Memory (MB): peak = 2720.312 ; gain = 0.000 ; free physical = 4127 ; free virtual = 31105
+
+Phase 1.3 Build Placer Netlist Model
+Phase 1.3 Build Placer Netlist Model | Checksum: 12e30e91e
+
+Time (s): cpu = 00:00:00.49 ; elapsed = 00:00:00.32 . Memory (MB): peak = 2720.312 ; gain = 0.000 ; free physical = 4142 ; free virtual = 31120
+
+Phase 1.4 Constrain Clocks/Macros
+Phase 1.4 Constrain Clocks/Macros | Checksum: 12e30e91e
+
+Time (s): cpu = 00:00:00.5 ; elapsed = 00:00:00.32 . Memory (MB): peak = 2720.312 ; gain = 0.000 ; free physical = 4142 ; free virtual = 31120
+Phase 1 Placer Initialization | Checksum: 12e30e91e
+
+Time (s): cpu = 00:00:00.5 ; elapsed = 00:00:00.33 . Memory (MB): peak = 2720.312 ; gain = 0.000 ; free physical = 4142 ; free virtual = 31120
+
+Phase 2 Global Placement
+
+Phase 2.1 Floorplanning
+Phase 2.1 Floorplanning | Checksum: 1aac329f3
+
+Time (s): cpu = 00:00:00.65 ; elapsed = 00:00:00.38 . Memory (MB): peak = 2720.312 ; gain = 0.000 ; free physical = 4138 ; free virtual = 31116
+
+Phase 2.2 Update Timing before SLR Path Opt
+Phase 2.2 Update Timing before SLR Path Opt | Checksum: 160e19f20
+
+Time (s): cpu = 00:00:00.7 ; elapsed = 00:00:00.42 . Memory (MB): peak = 2720.312 ; gain = 0.000 ; free physical = 4139 ; free virtual = 31116
+
+Phase 2.3 Post-Processing in Floorplanning
+Phase 2.3 Post-Processing in Floorplanning | Checksum: 160e19f20
+
+Time (s): cpu = 00:00:00.71 ; elapsed = 00:00:00.42 . Memory (MB): peak = 2720.312 ; gain = 0.000 ; free physical = 4139 ; free virtual = 31116
+
+Phase 2.4 Global Placement Core
+
+Phase 2.4.1 UpdateTiming Before Physical Synthesis
+Phase 2.4.1 UpdateTiming Before Physical Synthesis | Checksum: 17a45fbe4
+
+Time (s): cpu = 00:00:03 ; elapsed = 00:00:01 . Memory (MB): peak = 2720.312 ; gain = 0.000 ; free physical = 4112 ; free virtual = 31089
+
+Phase 2.4.2 Physical Synthesis In Placer
+INFO: [Physopt 32-1035] Found 0 LUTNM shape to break, 3 LUT instances to create LUTNM shape
+INFO: [Physopt 32-1044] Break lutnm for timing: one critical 0, two critical 0, total 0, new lutff created 0
+INFO: [Physopt 32-1138] End 1 Pass. Optimized 1 net or LUT. Breaked 0 LUT, combined 1 existing LUT and moved 0 existing LUT
+INFO: [Physopt 32-65] No nets found for high-fanout optimization.
+INFO: [Physopt 32-232] Optimized 0 net. Created 0 new instance.
+INFO: [Physopt 32-775] End 1 Pass. Optimized 0 net or cell. Created 0 new cell, deleted 0 existing cell and moved 0 existing cell
+INFO: [Physopt 32-670] No setup violation found. DSP Register Optimization was not performed.
+INFO: [Physopt 32-670] No setup violation found. Shift Register to Pipeline Optimization was not performed.
+INFO: [Physopt 32-670] No setup violation found. Shift Register Optimization was not performed.
+INFO: [Physopt 32-670] No setup violation found. BRAM Register Optimization was not performed.
+INFO: [Physopt 32-670] No setup violation found. URAM Register Optimization was not performed.
+INFO: [Physopt 32-949] No candidate nets found for dynamic/static region interface net replication
+INFO: [Physopt 32-775] End 1 Pass. Optimized 0 net or cell. Created 0 new cell, deleted 0 existing cell and moved 0 existing cell
+Netlist sorting complete. Time (s): cpu = 00:00:00 ; elapsed = 00:00:00 . Memory (MB): peak = 2720.312 ; gain = 0.000 ; free physical = 4110 ; free virtual = 31088
+
+Summary of Physical Synthesis Optimizations
+============================================
+
+
+-----------------------------------------------------------------------------------------------------------------------------------------------------------
+| Optimization | Added Cells | Removed Cells | Optimized Cells/Nets | Dont Touch | Iterations | Elapsed |
+-----------------------------------------------------------------------------------------------------------------------------------------------------------
+| LUT Combining | 0 | 1 | 1 | 0 | 1 | 00:00:00 |
+| Retime | 0 | 0 | 0 | 0 | 1 | 00:00:00 |
+| Very High Fanout | 0 | 0 | 0 | 0 | 1 | 00:00:00 |
+| DSP Register | 0 | 0 | 0 | 0 | 0 | 00:00:00 |
+| Shift Register to Pipeline | 0 | 0 | 0 | 0 | 0 | 00:00:00 |
+| Shift Register | 0 | 0 | 0 | 0 | 0 | 00:00:00 |
+| BRAM Register | 0 | 0 | 0 | 0 | 0 | 00:00:00 |
+| URAM Register | 0 | 0 | 0 | 0 | 0 | 00:00:00 |
+| Dynamic/Static Region Interface Net Replication | 0 | 0 | 0 | 0 | 1 | 00:00:00 |
+| Total | 0 | 1 | 1 | 0 | 4 | 00:00:00 |
+-----------------------------------------------------------------------------------------------------------------------------------------------------------
+
+
+Phase 2.4.2 Physical Synthesis In Placer | Checksum: 1ec4d2c29
+
+Time (s): cpu = 00:00:04 ; elapsed = 00:00:02 . Memory (MB): peak = 2720.312 ; gain = 0.000 ; free physical = 4111 ; free virtual = 31088
+Phase 2.4 Global Placement Core | Checksum: 1697c68ea
+
+Time (s): cpu = 00:00:04 ; elapsed = 00:00:02 . Memory (MB): peak = 2720.312 ; gain = 0.000 ; free physical = 4110 ; free virtual = 31088
+Phase 2 Global Placement | Checksum: 1697c68ea
+
+Time (s): cpu = 00:00:04 ; elapsed = 00:00:02 . Memory (MB): peak = 2720.312 ; gain = 0.000 ; free physical = 4110 ; free virtual = 31088
+
+Phase 3 Detail Placement
+
+Phase 3.1 Commit Multi Column Macros
+Phase 3.1 Commit Multi Column Macros | Checksum: 179bc14ed
+
+Time (s): cpu = 00:00:04 ; elapsed = 00:00:02 . Memory (MB): peak = 2720.312 ; gain = 0.000 ; free physical = 4110 ; free virtual = 31088
+
+Phase 3.2 Commit Most Macros & LUTRAMs
+Phase 3.2 Commit Most Macros & LUTRAMs | Checksum: 2070ef4b2
+
+Time (s): cpu = 00:00:04 ; elapsed = 00:00:02 . Memory (MB): peak = 2720.312 ; gain = 0.000 ; free physical = 4110 ; free virtual = 31087
+
+Phase 3.3 Area Swap Optimization
+Phase 3.3 Area Swap Optimization | Checksum: 1b6d58336
+
+Time (s): cpu = 00:00:04 ; elapsed = 00:00:02 . Memory (MB): peak = 2720.312 ; gain = 0.000 ; free physical = 4110 ; free virtual = 31087
+
+Phase 3.4 Pipeline Register Optimization
+Phase 3.4 Pipeline Register Optimization | Checksum: 2647924a7
+
+Time (s): cpu = 00:00:04 ; elapsed = 00:00:02 . Memory (MB): peak = 2720.312 ; gain = 0.000 ; free physical = 4110 ; free virtual = 31087
+
+Phase 3.5 Small Shape Detail Placement
+Phase 3.5 Small Shape Detail Placement | Checksum: 1c3fcab4d
+
+Time (s): cpu = 00:00:04 ; elapsed = 00:00:02 . Memory (MB): peak = 2720.312 ; gain = 0.000 ; free physical = 4108 ; free virtual = 31085
+
+Phase 3.6 Re-assign LUT pins
+Phase 3.6 Re-assign LUT pins | Checksum: 1edbbe9db
+
+Time (s): cpu = 00:00:04 ; elapsed = 00:00:02 . Memory (MB): peak = 2720.312 ; gain = 0.000 ; free physical = 4108 ; free virtual = 31086
+
+Phase 3.7 Pipeline Register Optimization
+Phase 3.7 Pipeline Register Optimization | Checksum: 17c18496c
+
+Time (s): cpu = 00:00:04 ; elapsed = 00:00:02 . Memory (MB): peak = 2720.312 ; gain = 0.000 ; free physical = 4108 ; free virtual = 31086
+Phase 3 Detail Placement | Checksum: 17c18496c
+
+Time (s): cpu = 00:00:04 ; elapsed = 00:00:02 . Memory (MB): peak = 2720.312 ; gain = 0.000 ; free physical = 4108 ; free virtual = 31086
+
+Phase 4 Post Placement Optimization and Clean-Up
+
+Phase 4.1 Post Commit Optimization
+INFO: [Timing 38-35] Done setting XDC timing constraints.
+
+Phase 4.1.1 Post Placement Optimization
+Post Placement Optimization Initialization | Checksum: 109529687
+
+Phase 4.1.1.1 BUFG Insertion
+
+Starting Physical Synthesis Task
+
+Phase 1 Physical Synthesis Initialization
+INFO: [Physopt 32-721] Multithreading enabled for phys_opt_design using a maximum of 8 CPUs
+INFO: [Physopt 32-619] Estimated Timing Summary | WNS=26.291 | TNS=0.000 |
+Phase 1 Physical Synthesis Initialization | Checksum: 14543fbd3
+
+Time (s): cpu = 00:00:00.04 ; elapsed = 00:00:00.02 . Memory (MB): peak = 2720.312 ; gain = 0.000 ; free physical = 4108 ; free virtual = 31085
+INFO: [Place 46-56] BUFG insertion identified 0 candidate nets. Inserted BUFG: 0, Replicated BUFG Driver: 0, Skipped due to Placement/Routing Conflicts: 0, Skipped due to Timing Degradation: 0, Skipped due to Illegal Netlist: 0.
+Ending Physical Synthesis Task | Checksum: 15d4ad102
+
+Time (s): cpu = 00:00:00.05 ; elapsed = 00:00:00.02 . Memory (MB): peak = 2720.312 ; gain = 0.000 ; free physical = 4108 ; free virtual = 31085
+Phase 4.1.1.1 BUFG Insertion | Checksum: 109529687
+
+Time (s): cpu = 00:00:05 ; elapsed = 00:00:02 . Memory (MB): peak = 2720.312 ; gain = 0.000 ; free physical = 4108 ; free virtual = 31085
+
+Phase 4.1.1.2 Post Placement Timing Optimization
+INFO: [Place 30-746] Post Placement Timing Summary WNS=26.291. For the most accurate timing information please run report_timing.
+Phase 4.1.1.2 Post Placement Timing Optimization | Checksum: 1084ee129
+
+Time (s): cpu = 00:00:05 ; elapsed = 00:00:02 . Memory (MB): peak = 2720.312 ; gain = 0.000 ; free physical = 4108 ; free virtual = 31085
+
+Time (s): cpu = 00:00:05 ; elapsed = 00:00:02 . Memory (MB): peak = 2720.312 ; gain = 0.000 ; free physical = 4107 ; free virtual = 31085
+Phase 4.1 Post Commit Optimization | Checksum: 1084ee129
+
+Time (s): cpu = 00:00:05 ; elapsed = 00:00:02 . Memory (MB): peak = 2720.312 ; gain = 0.000 ; free physical = 4107 ; free virtual = 31085
+
+Phase 4.2 Post Placement Cleanup
+Phase 4.2 Post Placement Cleanup | Checksum: 1084ee129
+
+Time (s): cpu = 00:00:05 ; elapsed = 00:00:02 . Memory (MB): peak = 2720.312 ; gain = 0.000 ; free physical = 4108 ; free virtual = 31086
+
+Phase 4.3 Placer Reporting
+
+Phase 4.3.1 Print Estimated Congestion
+INFO: [Place 30-612] Post-Placement Estimated Congestion
+ ____________________________________________________
+| | Global Congestion | Short Congestion |
+| Direction | Region Size | Region Size |
+|___________|___________________|___________________|
+| North| 1x1| 1x1|
+|___________|___________________|___________________|
+| South| 1x1| 1x1|
+|___________|___________________|___________________|
+| East| 1x1| 1x1|
+|___________|___________________|___________________|
+| West| 1x1| 1x1|
+|___________|___________________|___________________|
+
+Phase 4.3.1 Print Estimated Congestion | Checksum: 1084ee129
+
+Time (s): cpu = 00:00:05 ; elapsed = 00:00:02 . Memory (MB): peak = 2720.312 ; gain = 0.000 ; free physical = 4108 ; free virtual = 31086
+Phase 4.3 Placer Reporting | Checksum: 1084ee129
+
+Time (s): cpu = 00:00:05 ; elapsed = 00:00:02 . Memory (MB): peak = 2720.312 ; gain = 0.000 ; free physical = 4108 ; free virtual = 31086
+
+Phase 4.4 Final Placement Cleanup
+Netlist sorting complete. Time (s): cpu = 00:00:00 ; elapsed = 00:00:00 . Memory (MB): peak = 2720.312 ; gain = 0.000 ; free physical = 4108 ; free virtual = 31086
+
+Time (s): cpu = 00:00:05 ; elapsed = 00:00:02 . Memory (MB): peak = 2720.312 ; gain = 0.000 ; free physical = 4108 ; free virtual = 31086
+Phase 4 Post Placement Optimization and Clean-Up | Checksum: b64880c0
+
+Time (s): cpu = 00:00:05 ; elapsed = 00:00:02 . Memory (MB): peak = 2720.312 ; gain = 0.000 ; free physical = 4108 ; free virtual = 31086
+Ending Placer Task | Checksum: 84b47138
+
+Time (s): cpu = 00:00:05 ; elapsed = 00:00:02 . Memory (MB): peak = 2720.312 ; gain = 0.000 ; free physical = 4108 ; free virtual = 31086
+INFO: [Common 17-83] Releasing license: Implementation
+65 Infos, 0 Warnings, 0 Critical Warnings and 0 Errors encountered.
+place_design completed successfully
+INFO: [Timing 38-480] Writing timing data to binary archive.
+Writing XDEF routing.
+Writing XDEF routing logical nets.
+Writing XDEF routing special nets.
+Write XDEF Complete: Time (s): cpu = 00:00:00.14 ; elapsed = 00:00:00.05 . Memory (MB): peak = 2720.312 ; gain = 0.000 ; free physical = 4134 ; free virtual = 31112
+INFO: [Common 17-1381] The checkpoint '/home/prasic/game/game.runs/impl_1/TopModule_placed.dcp' has been generated.
+INFO: [runtcl-4] Executing : report_io -file TopModule_io_placed.rpt
+report_io: Time (s): cpu = 00:00:00.13 ; elapsed = 00:00:00.17 . Memory (MB): peak = 2720.312 ; gain = 0.000 ; free physical = 4125 ; free virtual = 31103
+INFO: [runtcl-4] Executing : report_utilization -file TopModule_utilization_placed.rpt -pb TopModule_utilization_placed.pb
+INFO: [runtcl-4] Executing : report_control_sets -verbose -file TopModule_control_sets_placed.rpt
+report_control_sets: Time (s): cpu = 00:00:00.05 ; elapsed = 00:00:00.1 . Memory (MB): peak = 2720.312 ; gain = 0.000 ; free physical = 4133 ; free virtual = 31111
+Command: phys_opt_design
+Attempting to get a license for feature 'Implementation' and/or device 'xc7a100t'
+INFO: [Common 17-349] Got license for feature 'Implementation' and/or device 'xc7a100t'
+
+Starting Initial Update Timing Task
+
+Time (s): cpu = 00:00:00.2 ; elapsed = 00:00:00.1 . Memory (MB): peak = 2720.312 ; gain = 0.000 ; free physical = 4104 ; free virtual = 31081
+INFO: [Vivado_Tcl 4-383] Design worst setup slack (WNS) is greater than or equal to 0.000 ns. Skipping all physical synthesis optimizations.
+INFO: [Vivado_Tcl 4-232] No setup violation found. The netlist was not modified.
+INFO: [Common 17-83] Releasing license: Implementation
+74 Infos, 0 Warnings, 0 Critical Warnings and 0 Errors encountered.
+phys_opt_design completed successfully
+INFO: [Timing 38-480] Writing timing data to binary archive.
+Writing XDEF routing.
+Writing XDEF routing logical nets.
+Writing XDEF routing special nets.
+Write XDEF Complete: Time (s): cpu = 00:00:00.16 ; elapsed = 00:00:00.06 . Memory (MB): peak = 2720.312 ; gain = 0.000 ; free physical = 4099 ; free virtual = 31078
+INFO: [Common 17-1381] The checkpoint '/home/prasic/game/game.runs/impl_1/TopModule_physopt.dcp' has been generated.
+Command: route_design
+Attempting to get a license for feature 'Implementation' and/or device 'xc7a100t'
+INFO: [Common 17-349] Got license for feature 'Implementation' and/or device 'xc7a100t'
+Running DRC as a precondition to command route_design
+INFO: [DRC 23-27] Running DRC with 8 threads
+INFO: [Vivado_Tcl 4-198] DRC finished with 0 Errors
+INFO: [Vivado_Tcl 4-199] Please refer to the DRC report (report_drc) for more information.
+
+
+Starting Routing Task
+INFO: [Route 35-254] Multithreading enabled for route_design using a maximum of 8 CPUs
+
+Phase 1 Build RT Design
+Checksum: PlaceDB: 4a9e9a15 ConstDB: 0 ShapeSum: 3a15d723 RouteDB: 0
+Post Restoration Checksum: NetGraph: fcfe40d0 NumContArr: ada2d337 Constraints: 0 Timing: 0
+Phase 1 Build RT Design | Checksum: 1aaa11407
+
+Time (s): cpu = 00:00:26 ; elapsed = 00:00:22 . Memory (MB): peak = 2777.801 ; gain = 54.957 ; free physical = 3955 ; free virtual = 30934
+
+Phase 2 Router Initialization
+
+Phase 2.1 Fix Topology Constraints
+Phase 2.1 Fix Topology Constraints | Checksum: 1aaa11407
+
+Time (s): cpu = 00:00:26 ; elapsed = 00:00:22 . Memory (MB): peak = 2810.801 ; gain = 87.957 ; free physical = 3921 ; free virtual = 30899
+
+Phase 2.2 Pre Route Cleanup
+Phase 2.2 Pre Route Cleanup | Checksum: 1aaa11407
+
+Time (s): cpu = 00:00:26 ; elapsed = 00:00:22 . Memory (MB): peak = 2810.801 ; gain = 87.957 ; free physical = 3921 ; free virtual = 30899
+ Number of Nodes with overlaps = 0
+
+Phase 2.3 Update Timing
+Phase 2.3 Update Timing | Checksum: 1be465fec
+
+Time (s): cpu = 00:00:26 ; elapsed = 00:00:22 . Memory (MB): peak = 2826.098 ; gain = 103.254 ; free physical = 3910 ; free virtual = 30889
+INFO: [Route 35-416] Intermediate Timing Summary | WNS=26.479 | TNS=0.000 | WHS=-0.254 | THS=-14.153|
+
+
+Router Utilization Summary
+ Global Vertical Routing Utilization = 0 %
+ Global Horizontal Routing Utilization = 0 %
+ Routable Net Status*
+ *Does not include unroutable nets such as driverless and loadless.
+ Run report_route_status for detailed report.
+ Number of Failed Nets = 381
+ (Failed Nets is the sum of unrouted and partially routed nets)
+ Number of Unrouted Nets = 381
+ Number of Partially Routed Nets = 0
+ Number of Node Overlaps = 0
+
+Phase 2 Router Initialization | Checksum: 2470b9ba4
+
+Time (s): cpu = 00:00:27 ; elapsed = 00:00:22 . Memory (MB): peak = 2831.129 ; gain = 108.285 ; free physical = 3907 ; free virtual = 30885
+
+Phase 3 Initial Routing
+
+Phase 3.1 Global Routing
+Phase 3.1 Global Routing | Checksum: 2470b9ba4
+
+Time (s): cpu = 00:00:27 ; elapsed = 00:00:22 . Memory (MB): peak = 2831.129 ; gain = 108.285 ; free physical = 3907 ; free virtual = 30885
+Phase 3 Initial Routing | Checksum: 19684a300
+
+Time (s): cpu = 00:00:28 ; elapsed = 00:00:23 . Memory (MB): peak = 2831.129 ; gain = 108.285 ; free physical = 3906 ; free virtual = 30884
+
+Phase 4 Rip-up And Reroute
+
+Phase 4.1 Global Iteration 0
+ Number of Nodes with overlaps = 21
+ Number of Nodes with overlaps = 0
+INFO: [Route 35-416] Intermediate Timing Summary | WNS=24.829 | TNS=0.000 | WHS=N/A | THS=N/A |
+
+Phase 4.1 Global Iteration 0 | Checksum: be565e86
+
+Time (s): cpu = 00:00:28 ; elapsed = 00:00:23 . Memory (MB): peak = 2831.129 ; gain = 108.285 ; free physical = 3905 ; free virtual = 30884
+Phase 4 Rip-up And Reroute | Checksum: be565e86
+
+Time (s): cpu = 00:00:28 ; elapsed = 00:00:23 . Memory (MB): peak = 2831.129 ; gain = 108.285 ; free physical = 3905 ; free virtual = 30884
+
+Phase 5 Delay and Skew Optimization
+
+Phase 5.1 Delay CleanUp
+Phase 5.1 Delay CleanUp | Checksum: be565e86
+
+Time (s): cpu = 00:00:28 ; elapsed = 00:00:23 . Memory (MB): peak = 2831.129 ; gain = 108.285 ; free physical = 3905 ; free virtual = 30884
+
+Phase 5.2 Clock Skew Optimization
+Phase 5.2 Clock Skew Optimization | Checksum: be565e86
+
+Time (s): cpu = 00:00:28 ; elapsed = 00:00:23 . Memory (MB): peak = 2831.129 ; gain = 108.285 ; free physical = 3905 ; free virtual = 30884
+Phase 5 Delay and Skew Optimization | Checksum: be565e86
+
+Time (s): cpu = 00:00:28 ; elapsed = 00:00:23 . Memory (MB): peak = 2831.129 ; gain = 108.285 ; free physical = 3905 ; free virtual = 30884
+
+Phase 6 Post Hold Fix
+
+Phase 6.1 Hold Fix Iter
+
+Phase 6.1.1 Update Timing
+Phase 6.1.1 Update Timing | Checksum: baf05697
+
+Time (s): cpu = 00:00:28 ; elapsed = 00:00:23 . Memory (MB): peak = 2831.129 ; gain = 108.285 ; free physical = 3905 ; free virtual = 30884
+INFO: [Route 35-416] Intermediate Timing Summary | WNS=24.908 | TNS=0.000 | WHS=0.057 | THS=0.000 |
+
+Phase 6.1 Hold Fix Iter | Checksum: baf05697
+
+Time (s): cpu = 00:00:28 ; elapsed = 00:00:23 . Memory (MB): peak = 2831.129 ; gain = 108.285 ; free physical = 3905 ; free virtual = 30884
+Phase 6 Post Hold Fix | Checksum: baf05697
+
+Time (s): cpu = 00:00:28 ; elapsed = 00:00:23 . Memory (MB): peak = 2831.129 ; gain = 108.285 ; free physical = 3905 ; free virtual = 30884
+
+Phase 7 Route finalize
+
+Router Utilization Summary
+ Global Vertical Routing Utilization = 0.0907864 %
+ Global Horizontal Routing Utilization = 0.0622336 %
+ Routable Net Status*
+ *Does not include unroutable nets such as driverless and loadless.
+ Run report_route_status for detailed report.
+ Number of Failed Nets = 0
+ (Failed Nets is the sum of unrouted and partially routed nets)
+ Number of Unrouted Nets = 0
+ Number of Partially Routed Nets = 0
+ Number of Node Overlaps = 0
+
+Phase 7 Route finalize | Checksum: ae742c66
+
+Time (s): cpu = 00:00:28 ; elapsed = 00:00:23 . Memory (MB): peak = 2831.129 ; gain = 108.285 ; free physical = 3905 ; free virtual = 30884
+
+Phase 8 Verifying routed nets
+
+ Verification completed successfully
+Phase 8 Verifying routed nets | Checksum: ae742c66
+
+Time (s): cpu = 00:00:28 ; elapsed = 00:00:23 . Memory (MB): peak = 2831.129 ; gain = 108.285 ; free physical = 3904 ; free virtual = 30883
+
+Phase 9 Depositing Routes
+Phase 9 Depositing Routes | Checksum: e93cd8e7
+
+Time (s): cpu = 00:00:28 ; elapsed = 00:00:23 . Memory (MB): peak = 2847.137 ; gain = 124.293 ; free physical = 3904 ; free virtual = 30883
+
+Phase 10 Post Router Timing
+INFO: [Route 35-57] Estimated Timing Summary | WNS=24.908 | TNS=0.000 | WHS=0.057 | THS=0.000 |
+
+INFO: [Route 35-327] The final timing numbers are based on the router estimated timing analysis. For a complete and accurate timing signoff, please run report_timing_summary.
+Phase 10 Post Router Timing | Checksum: e93cd8e7
+
+Time (s): cpu = 00:00:28 ; elapsed = 00:00:23 . Memory (MB): peak = 2847.137 ; gain = 124.293 ; free physical = 3905 ; free virtual = 30884
+INFO: [Route 35-16] Router Completed Successfully
+
+Time (s): cpu = 00:00:28 ; elapsed = 00:00:23 . Memory (MB): peak = 2847.137 ; gain = 124.293 ; free physical = 3944 ; free virtual = 30922
+
+Routing Is Done.
+INFO: [Common 17-83] Releasing license: Implementation
+88 Infos, 0 Warnings, 0 Critical Warnings and 0 Errors encountered.
+route_design completed successfully
+route_design: Time (s): cpu = 00:00:29 ; elapsed = 00:00:23 . Memory (MB): peak = 2847.137 ; gain = 126.824 ; free physical = 3944 ; free virtual = 30922
+INFO: [Timing 38-480] Writing timing data to binary archive.
+Writing XDEF routing.
+Writing XDEF routing logical nets.
+Writing XDEF routing special nets.
+Write XDEF Complete: Time (s): cpu = 00:00:00.15 ; elapsed = 00:00:00.06 . Memory (MB): peak = 2847.137 ; gain = 0.000 ; free physical = 3939 ; free virtual = 30919
+INFO: [Common 17-1381] The checkpoint '/home/prasic/game/game.runs/impl_1/TopModule_routed.dcp' has been generated.
+INFO: [runtcl-4] Executing : report_drc -file TopModule_drc_routed.rpt -pb TopModule_drc_routed.pb -rpx TopModule_drc_routed.rpx
+Command: report_drc -file TopModule_drc_routed.rpt -pb TopModule_drc_routed.pb -rpx TopModule_drc_routed.rpx
+INFO: [IP_Flow 19-1839] IP Catalog is up to date.
+INFO: [DRC 23-27] Running DRC with 8 threads
+INFO: [Vivado_Tcl 2-168] The results of DRC are in file /home/prasic/game/game.runs/impl_1/TopModule_drc_routed.rpt.
+report_drc completed successfully
+INFO: [runtcl-4] Executing : report_methodology -file TopModule_methodology_drc_routed.rpt -pb TopModule_methodology_drc_routed.pb -rpx TopModule_methodology_drc_routed.rpx
+Command: report_methodology -file TopModule_methodology_drc_routed.rpt -pb TopModule_methodology_drc_routed.pb -rpx TopModule_methodology_drc_routed.rpx
+INFO: [Timing 38-35] Done setting XDC timing constraints.
+INFO: [DRC 23-133] Running Methodology with 8 threads
+INFO: [Vivado_Tcl 2-1520] The results of Report Methodology are in file /home/prasic/game/game.runs/impl_1/TopModule_methodology_drc_routed.rpt.
+report_methodology completed successfully
+INFO: [runtcl-4] Executing : report_power -file TopModule_power_routed.rpt -pb TopModule_power_summary_routed.pb -rpx TopModule_power_routed.rpx
+Command: report_power -file TopModule_power_routed.rpt -pb TopModule_power_summary_routed.pb -rpx TopModule_power_routed.rpx
+INFO: [Timing 38-35] Done setting XDC timing constraints.
+Running Vector-less Activity Propagation...
+
+Finished Running Vector-less Activity Propagation
+100 Infos, 0 Warnings, 0 Critical Warnings and 0 Errors encountered.
+report_power completed successfully
+INFO: [runtcl-4] Executing : report_route_status -file TopModule_route_status.rpt -pb TopModule_route_status.pb
+INFO: [runtcl-4] Executing : report_timing_summary -max_paths 10 -report_unconstrained -file TopModule_timing_summary_routed.rpt -pb TopModule_timing_summary_routed.pb -rpx TopModule_timing_summary_routed.rpx -warn_on_violation
+INFO: [Timing 38-91] UpdateTimingParams: Speed grade: -1, Delay Type: min_max.
+INFO: [Timing 38-191] Multithreading enabled for timing update using a maximum of 8 CPUs
+INFO: [runtcl-4] Executing : report_incremental_reuse -file TopModule_incremental_reuse_routed.rpt
+INFO: [Vivado_Tcl 4-1062] Incremental flow is disabled. No incremental reuse Info to report.
+INFO: [runtcl-4] Executing : report_clock_utilization -file TopModule_clock_utilization_routed.rpt
+INFO: [runtcl-4] Executing : report_bus_skew -warn_on_violation -file TopModule_bus_skew_routed.rpt -pb TopModule_bus_skew_routed.pb -rpx TopModule_bus_skew_routed.rpx
+INFO: [Timing 38-91] UpdateTimingParams: Speed grade: -1, Delay Type: min_max.
+INFO: [Timing 38-191] Multithreading enabled for timing update using a maximum of 8 CPUs
+Command: write_bitstream -force TopModule.bit
+Attempting to get a license for feature 'Implementation' and/or device 'xc7a100t'
+INFO: [Common 17-349] Got license for feature 'Implementation' and/or device 'xc7a100t'
+Running DRC as a precondition to command write_bitstream
+INFO: [IP_Flow 19-1839] IP Catalog is up to date.
+INFO: [DRC 23-27] Running DRC with 8 threads
+WARNING: [DRC CFGBVS-1] Missing CFGBVS and CONFIG_VOLTAGE Design Properties: Neither the CFGBVS nor CONFIG_VOLTAGE voltage property is set in the current_design. Configuration bank voltage select (CFGBVS) must be set to VCCO or GND, and CONFIG_VOLTAGE must be set to the correct configuration voltage, in order to determine the I/O voltage support for the pins in bank 0. It is suggested to specify these either using the 'Edit Device Properties' function in the GUI or directly in the XDC file using the following syntax:
+
+ set_property CFGBVS value1 [current_design]
+ #where value1 is either VCCO or GND
+
+ set_property CONFIG_VOLTAGE value2 [current_design]
+ #where value2 is the voltage provided to configuration bank 0
+
+Refer to the device configuration user guide for more information.
+INFO: [Vivado 12-3199] DRC finished with 0 Errors, 1 Warnings
+INFO: [Vivado 12-3200] Please refer to the DRC report (report_drc) for more information.
+INFO: [Designutils 20-2272] Running write_bitstream with 8 threads.
+Loading data files...
+Loading site data...
+Loading route data...
+Processing options...
+Creating bitmap...
+Creating bitstream...
+Writing bitstream ./TopModule.bit...
+INFO: [Vivado 12-1842] Bitgen Completed Successfully.
+INFO: [Common 17-83] Releasing license: Implementation
+11 Infos, 1 Warnings, 0 Critical Warnings and 0 Errors encountered.
+write_bitstream completed successfully
+write_bitstream: Time (s): cpu = 00:00:11 ; elapsed = 00:00:18 . Memory (MB): peak = 3175.145 ; gain = 233.242 ; free physical = 3916 ; free virtual = 30901
+INFO: [Common 17-206] Exiting Vivado at Tue Feb 28 17:03:00 2023...
diff --git a/game.runs/impl_1/runme.sh b/game.runs/impl_1/runme.sh
new file mode 100755
index 0000000000000000000000000000000000000000..1ec2fa21ef2bcf85088408010258e55bae79e54f
--- /dev/null
+++ b/game.runs/impl_1/runme.sh
@@ -0,0 +1,43 @@
+#!/bin/sh
+
+#
+# Vivado(TM)
+# runme.sh: a Vivado-generated Runs Script for UNIX
+# Copyright 1986-2022 Xilinx, Inc. All Rights Reserved.
+#
+
+if [ -z "$PATH" ]; then
+ PATH=/opt/Xilinx/Vivado/2022.2/ids_lite/ISE/bin/lin64:/opt/Xilinx/Vivado/2022.2/bin
+else
+ PATH=/opt/Xilinx/Vivado/2022.2/ids_lite/ISE/bin/lin64:/opt/Xilinx/Vivado/2022.2/bin:$PATH
+fi
+export PATH
+
+if [ -z "$LD_LIBRARY_PATH" ]; then
+ LD_LIBRARY_PATH=
+else
+ LD_LIBRARY_PATH=:$LD_LIBRARY_PATH
+fi
+export LD_LIBRARY_PATH
+
+HD_PWD='/home/prasic/game/game.runs/impl_1'
+cd "$HD_PWD"
+
+HD_LOG=runme.log
+/bin/touch $HD_LOG
+
+ISEStep="./ISEWrap.sh"
+EAStep()
+{
+ $ISEStep $HD_LOG "$@" >> $HD_LOG 2>&1
+ if [ $? -ne 0 ]
+ then
+ exit
+ fi
+}
+
+# pre-commands:
+/bin/touch .init_design.begin.rst
+EAStep vivado -log TopModule.vdi -applog -m64 -product Vivado -messageDb vivado.pb -mode batch -source TopModule.tcl -notrace
+
+
diff --git a/game.runs/impl_1/vivado.jou b/game.runs/impl_1/vivado.jou
new file mode 100644
index 0000000000000000000000000000000000000000..578a1b8b8c6c83ecf441c68ec8faf5bff45ed392
--- /dev/null
+++ b/game.runs/impl_1/vivado.jou
@@ -0,0 +1,13 @@
+#-----------------------------------------------------------
+# Vivado v2022.2 (64-bit)
+# SW Build 3671981 on Fri Oct 14 04:59:54 MDT 2022
+# IP Build 3669848 on Fri Oct 14 08:30:02 MDT 2022
+# Start of session at: Tue Feb 28 17:01:47 2023
+# Process ID: 238972
+# Current directory: /home/prasic/game/game.runs/impl_1
+# Command line: vivado -log TopModule.vdi -applog -product Vivado -messageDb vivado.pb -mode batch -source TopModule.tcl -notrace
+# Log file: /home/prasic/game/game.runs/impl_1/TopModule.vdi
+# Journal file: /home/prasic/game/game.runs/impl_1/vivado.jou
+# Running On: LikeUE06, OS: Linux, CPU Frequency: 3077.891 MHz, CPU Physical cores: 4, Host memory: 16699 MB
+#-----------------------------------------------------------
+source TopModule.tcl -notrace
diff --git a/game.runs/impl_1/vivado.pb b/game.runs/impl_1/vivado.pb
new file mode 100644
index 0000000000000000000000000000000000000000..8ed3be766b9e3055f422e72d60c1a93d142df5f0
Binary files /dev/null and b/game.runs/impl_1/vivado.pb differ
diff --git a/game.runs/impl_1/write_bitstream.pb b/game.runs/impl_1/write_bitstream.pb
new file mode 100644
index 0000000000000000000000000000000000000000..9e20f7dbb93f60679d0a2534396144ca00aac232
Binary files /dev/null and b/game.runs/impl_1/write_bitstream.pb differ
diff --git a/game.runs/synth_1/.Vivado_Synthesis.queue.rst b/game.runs/synth_1/.Vivado_Synthesis.queue.rst
new file mode 100644
index 0000000000000000000000000000000000000000..e69de29bb2d1d6434b8b29ae775ad8c2e48c5391
diff --git a/game.runs/synth_1/.Xil/TopModule_propImpl.xdc b/game.runs/synth_1/.Xil/TopModule_propImpl.xdc
new file mode 100644
index 0000000000000000000000000000000000000000..56009706171ddef863a430d0a6db4eef50c36538
--- /dev/null
+++ b/game.runs/synth_1/.Xil/TopModule_propImpl.xdc
@@ -0,0 +1,67 @@
+set_property SRC_FILE_INFO {cfile:/home/prasic/game/game.srcs/constrs_1/imports/PrASIC_Data/Nexys4_Master.xdc rfile:../../../game.srcs/constrs_1/imports/PrASIC_Data/Nexys4_Master.xdc id:1} [current_design]
+set_property src_info {type:XDC file:1 line:8 export:INPUT save:INPUT read:READ} [current_design]
+set_property PACKAGE_PIN E3 [get_ports clk]
+set_property src_info {type:XDC file:1 line:66 export:INPUT save:INPUT read:READ} [current_design]
+set_property PACKAGE_PIN T8 [get_ports {led[0]}]
+set_property src_info {type:XDC file:1 line:69 export:INPUT save:INPUT read:READ} [current_design]
+set_property PACKAGE_PIN V9 [get_ports {led[1]}]
+set_property src_info {type:XDC file:1 line:72 export:INPUT save:INPUT read:READ} [current_design]
+set_property PACKAGE_PIN R8 [get_ports {led[2]}]
+set_property src_info {type:XDC file:1 line:75 export:INPUT save:INPUT read:READ} [current_design]
+set_property PACKAGE_PIN T6 [get_ports {led[3]}]
+set_property src_info {type:XDC file:1 line:78 export:INPUT save:INPUT read:READ} [current_design]
+set_property PACKAGE_PIN T5 [get_ports {led[4]}]
+set_property src_info {type:XDC file:1 line:81 export:INPUT save:INPUT read:READ} [current_design]
+set_property PACKAGE_PIN T4 [get_ports {led[5]}]
+set_property src_info {type:XDC file:1 line:84 export:INPUT save:INPUT read:READ} [current_design]
+set_property PACKAGE_PIN U7 [get_ports {led[6]}]
+set_property src_info {type:XDC file:1 line:87 export:INPUT save:INPUT read:READ} [current_design]
+set_property PACKAGE_PIN U6 [get_ports {led[7]}]
+set_property src_info {type:XDC file:1 line:90 export:INPUT save:INPUT read:READ} [current_design]
+set_property PACKAGE_PIN V4 [get_ports {led[8]}]
+set_property src_info {type:XDC file:1 line:93 export:INPUT save:INPUT read:READ} [current_design]
+set_property PACKAGE_PIN U3 [get_ports {led[9]}]
+set_property src_info {type:XDC file:1 line:96 export:INPUT save:INPUT read:READ} [current_design]
+set_property PACKAGE_PIN V1 [get_ports {led[10]}]
+set_property src_info {type:XDC file:1 line:99 export:INPUT save:INPUT read:READ} [current_design]
+set_property PACKAGE_PIN R1 [get_ports {led[11]}]
+set_property src_info {type:XDC file:1 line:102 export:INPUT save:INPUT read:READ} [current_design]
+set_property PACKAGE_PIN P5 [get_ports {led[12]}]
+set_property src_info {type:XDC file:1 line:105 export:INPUT save:INPUT read:READ} [current_design]
+set_property PACKAGE_PIN U1 [get_ports {led[13]}]
+set_property src_info {type:XDC file:1 line:108 export:INPUT save:INPUT read:READ} [current_design]
+set_property PACKAGE_PIN R2 [get_ports {led[14]}]
+set_property src_info {type:XDC file:1 line:111 export:INPUT save:INPUT read:READ} [current_design]
+set_property PACKAGE_PIN P2 [get_ports {led[15]}]
+set_property src_info {type:XDC file:1 line:191 export:INPUT save:INPUT read:READ} [current_design]
+set_property PACKAGE_PIN C12 [get_ports btnCpuReset]
+set_property src_info {type:XDC file:1 line:197 export:INPUT save:INPUT read:READ} [current_design]
+set_property PACKAGE_PIN F15 [get_ports btnU]
+set_property src_info {type:XDC file:1 line:353 export:INPUT save:INPUT read:READ} [current_design]
+set_property PACKAGE_PIN A3 [get_ports {vgaRed[0]}]
+set_property src_info {type:XDC file:1 line:356 export:INPUT save:INPUT read:READ} [current_design]
+set_property PACKAGE_PIN B4 [get_ports {vgaRed[1]}]
+set_property src_info {type:XDC file:1 line:359 export:INPUT save:INPUT read:READ} [current_design]
+set_property PACKAGE_PIN C5 [get_ports {vgaRed[2]}]
+set_property src_info {type:XDC file:1 line:362 export:INPUT save:INPUT read:READ} [current_design]
+set_property PACKAGE_PIN A4 [get_ports {vgaRed[3]}]
+set_property src_info {type:XDC file:1 line:365 export:INPUT save:INPUT read:READ} [current_design]
+set_property PACKAGE_PIN B7 [get_ports {vgaBlue[0]}]
+set_property src_info {type:XDC file:1 line:368 export:INPUT save:INPUT read:READ} [current_design]
+set_property PACKAGE_PIN C7 [get_ports {vgaBlue[1]}]
+set_property src_info {type:XDC file:1 line:371 export:INPUT save:INPUT read:READ} [current_design]
+set_property PACKAGE_PIN D7 [get_ports {vgaBlue[2]}]
+set_property src_info {type:XDC file:1 line:374 export:INPUT save:INPUT read:READ} [current_design]
+set_property PACKAGE_PIN D8 [get_ports {vgaBlue[3]}]
+set_property src_info {type:XDC file:1 line:377 export:INPUT save:INPUT read:READ} [current_design]
+set_property PACKAGE_PIN C6 [get_ports {vgaGreen[0]}]
+set_property src_info {type:XDC file:1 line:380 export:INPUT save:INPUT read:READ} [current_design]
+set_property PACKAGE_PIN A5 [get_ports {vgaGreen[1]}]
+set_property src_info {type:XDC file:1 line:383 export:INPUT save:INPUT read:READ} [current_design]
+set_property PACKAGE_PIN B6 [get_ports {vgaGreen[2]}]
+set_property src_info {type:XDC file:1 line:386 export:INPUT save:INPUT read:READ} [current_design]
+set_property PACKAGE_PIN A6 [get_ports {vgaGreen[3]}]
+set_property src_info {type:XDC file:1 line:389 export:INPUT save:INPUT read:READ} [current_design]
+set_property PACKAGE_PIN B11 [get_ports Hsync]
+set_property src_info {type:XDC file:1 line:392 export:INPUT save:INPUT read:READ} [current_design]
+set_property PACKAGE_PIN B12 [get_ports Vsync]
diff --git a/game.runs/synth_1/.vivado.begin.rst b/game.runs/synth_1/.vivado.begin.rst
new file mode 100644
index 0000000000000000000000000000000000000000..3a302b602f13fada2e976a7e80591c1d975b2b15
--- /dev/null
+++ b/game.runs/synth_1/.vivado.begin.rst
@@ -0,0 +1,5 @@
+<?xml version="1.0"?>
+<ProcessHandle Version="1" Minor="0">
+ <Process Command="vivado" Owner="prasic" Host="LikeUE06" Pid="238709" HostCore="8" HostMemory="16307816">
+ </Process>
+</ProcessHandle>
diff --git a/game.runs/synth_1/.vivado.end.rst b/game.runs/synth_1/.vivado.end.rst
new file mode 100644
index 0000000000000000000000000000000000000000..e69de29bb2d1d6434b8b29ae775ad8c2e48c5391
diff --git a/game.runs/synth_1/ISEWrap.js b/game.runs/synth_1/ISEWrap.js
new file mode 100755
index 0000000000000000000000000000000000000000..db0a51077cfb3a198d0bcb1b84080b9210b5b593
--- /dev/null
+++ b/game.runs/synth_1/ISEWrap.js
@@ -0,0 +1,269 @@
+//
+// Vivado(TM)
+// ISEWrap.js: Vivado Runs Script for WSH 5.1/5.6
+// Copyright 1986-1999, 2001-2013,2015 Xilinx, Inc. All Rights Reserved.
+//
+
+// GLOBAL VARIABLES
+var ISEShell = new ActiveXObject( "WScript.Shell" );
+var ISEFileSys = new ActiveXObject( "Scripting.FileSystemObject" );
+var ISERunDir = "";
+var ISELogFile = "runme.log";
+var ISELogFileStr = null;
+var ISELogEcho = true;
+var ISEOldVersionWSH = false;
+
+
+
+// BOOTSTRAP
+ISEInit();
+
+
+
+//
+// ISE FUNCTIONS
+//
+function ISEInit() {
+
+ // 1. RUN DIR setup
+ var ISEScrFP = WScript.ScriptFullName;
+ var ISEScrN = WScript.ScriptName;
+ ISERunDir =
+ ISEScrFP.substr( 0, ISEScrFP.length - ISEScrN.length - 1 );
+
+ // 2. LOG file setup
+ ISELogFileStr = ISEOpenFile( ISELogFile );
+
+ // 3. LOG echo?
+ var ISEScriptArgs = WScript.Arguments;
+ for ( var loopi=0; loopi<ISEScriptArgs.length; loopi++ ) {
+ if ( ISEScriptArgs(loopi) == "-quiet" ) {
+ ISELogEcho = false;
+ break;
+ }
+ }
+
+ // 4. WSH version check
+ var ISEOptimalVersionWSH = 5.6;
+ var ISECurrentVersionWSH = WScript.Version;
+ if ( ISECurrentVersionWSH < ISEOptimalVersionWSH ) {
+
+ ISEStdErr( "" );
+ ISEStdErr( "Warning: ExploreAhead works best with Microsoft WSH " +
+ ISEOptimalVersionWSH + " or higher. Downloads" );
+ ISEStdErr( " for upgrading your Windows Scripting Host can be found here: " );
+ ISEStdErr( " http://msdn.microsoft.com/downloads/list/webdev.asp" );
+ ISEStdErr( "" );
+
+ ISEOldVersionWSH = true;
+ }
+
+}
+
+function ISEStep( ISEProg, ISEArgs ) {
+
+ // CHECK for a STOP FILE
+ if ( ISEFileSys.FileExists(ISERunDir + "/.stop.rst") ) {
+ ISEStdErr( "" );
+ ISEStdErr( "*** Halting run - EA reset detected ***" );
+ ISEStdErr( "" );
+ WScript.Quit( 1 );
+ }
+
+ // WRITE STEP HEADER to LOG
+ ISEStdOut( "" );
+ ISEStdOut( "*** Running " + ISEProg );
+ ISEStdOut( " with args " + ISEArgs );
+ ISEStdOut( "" );
+
+ // LAUNCH!
+ var ISEExitCode = ISEExec( ISEProg, ISEArgs );
+ if ( ISEExitCode != 0 ) {
+ WScript.Quit( ISEExitCode );
+ }
+
+}
+
+function ISEExec( ISEProg, ISEArgs ) {
+
+ var ISEStep = ISEProg;
+ if (ISEProg == "realTimeFpga" || ISEProg == "planAhead" || ISEProg == "vivado") {
+ ISEProg += ".bat";
+ }
+
+ var ISECmdLine = ISEProg + " " + ISEArgs;
+ var ISEExitCode = 1;
+
+ if ( ISEOldVersionWSH ) { // WSH 5.1
+
+ // BEGIN file creation
+ ISETouchFile( ISEStep, "begin" );
+
+ // LAUNCH!
+ ISELogFileStr.Close();
+ ISECmdLine =
+ "%comspec% /c " + ISECmdLine + " >> " + ISELogFile + " 2>&1";
+ ISEExitCode = ISEShell.Run( ISECmdLine, 0, true );
+ ISELogFileStr = ISEOpenFile( ISELogFile );
+
+ } else { // WSH 5.6
+
+ // LAUNCH!
+ ISEShell.CurrentDirectory = ISERunDir;
+
+ // Redirect STDERR to STDOUT
+ ISECmdLine = "%comspec% /c " + ISECmdLine + " 2>&1";
+ var ISEProcess = ISEShell.Exec( ISECmdLine );
+
+ // BEGIN file creation
+ var wbemFlagReturnImmediately = 0x10;
+ var wbemFlagForwardOnly = 0x20;
+ var objWMIService = GetObject ("winmgmts:{impersonationLevel=impersonate, (Systemtime)}!//./root/cimv2");
+ var processor = objWMIService.ExecQuery("SELECT * FROM Win32_Processor", "WQL",wbemFlagReturnImmediately | wbemFlagForwardOnly);
+ var computerSystem = objWMIService.ExecQuery("SELECT * FROM Win32_ComputerSystem", "WQL", wbemFlagReturnImmediately | wbemFlagForwardOnly);
+ var NOC = 0;
+ var NOLP = 0;
+ var TPM = 0;
+ var cpuInfos = new Enumerator(processor);
+ for(;!cpuInfos.atEnd(); cpuInfos.moveNext()) {
+ var cpuInfo = cpuInfos.item();
+ NOC += cpuInfo.NumberOfCores;
+ NOLP += cpuInfo.NumberOfLogicalProcessors;
+ }
+ var csInfos = new Enumerator(computerSystem);
+ for(;!csInfos.atEnd(); csInfos.moveNext()) {
+ var csInfo = csInfos.item();
+ TPM += csInfo.TotalPhysicalMemory;
+ }
+
+ var ISEHOSTCORE = NOLP
+ var ISEMEMTOTAL = TPM
+
+ var ISENetwork = WScript.CreateObject( "WScript.Network" );
+ var ISEHost = ISENetwork.ComputerName;
+ var ISEUser = ISENetwork.UserName;
+ var ISEPid = ISEProcess.ProcessID;
+ var ISEBeginFile = ISEOpenFile( "." + ISEStep + ".begin.rst" );
+ ISEBeginFile.WriteLine( "<?xml version=\"1.0\"?>" );
+ ISEBeginFile.WriteLine( "<ProcessHandle Version=\"1\" Minor=\"0\">" );
+ ISEBeginFile.WriteLine( " <Process Command=\"" + ISEProg +
+ "\" Owner=\"" + ISEUser +
+ "\" Host=\"" + ISEHost +
+ "\" Pid=\"" + ISEPid +
+ "\" HostCore=\"" + ISEHOSTCORE +
+ "\" HostMemory=\"" + ISEMEMTOTAL +
+ "\">" );
+ ISEBeginFile.WriteLine( " </Process>" );
+ ISEBeginFile.WriteLine( "</ProcessHandle>" );
+ ISEBeginFile.Close();
+
+ var ISEOutStr = ISEProcess.StdOut;
+ var ISEErrStr = ISEProcess.StdErr;
+
+ // WAIT for ISEStep to finish
+ while ( ISEProcess.Status == 0 ) {
+
+ // dump stdout then stderr - feels a little arbitrary
+ while ( !ISEOutStr.AtEndOfStream ) {
+ ISEStdOut( ISEOutStr.ReadLine() );
+ }
+
+ WScript.Sleep( 100 );
+ }
+
+ ISEExitCode = ISEProcess.ExitCode;
+ }
+
+ ISELogFileStr.Close();
+
+ // END/ERROR file creation
+ if ( ISEExitCode != 0 ) {
+ ISETouchFile( ISEStep, "error" );
+
+ } else {
+ ISETouchFile( ISEStep, "end" );
+ }
+
+ return ISEExitCode;
+}
+
+
+//
+// UTILITIES
+//
+function ISEStdOut( ISELine ) {
+
+ ISELogFileStr.WriteLine( ISELine );
+
+ if ( ISELogEcho ) {
+ WScript.StdOut.WriteLine( ISELine );
+ }
+}
+
+function ISEStdErr( ISELine ) {
+
+ ISELogFileStr.WriteLine( ISELine );
+
+ if ( ISELogEcho ) {
+ WScript.StdErr.WriteLine( ISELine );
+ }
+}
+
+function ISETouchFile( ISERoot, ISEStatus ) {
+
+ var ISETFile =
+ ISEOpenFile( "." + ISERoot + "." + ISEStatus + ".rst" );
+ ISETFile.Close();
+}
+
+function ISEOpenFile( ISEFilename ) {
+
+ // This function has been updated to deal with a problem seen in CR #870871.
+ // In that case the user runs a script that runs impl_1, and then turns around
+ // and runs impl_1 -to_step write_bitstream. That second run takes place in
+ // the same directory, which means we may hit some of the same files, and in
+ // particular, we will open the runme.log file. Even though this script closes
+ // the file (now), we see cases where a subsequent attempt to open the file
+ // fails. Perhaps the OS is slow to release the lock, or the disk comes into
+ // play? In any case, we try to work around this by first waiting if the file
+ // is already there for an arbitrary 5 seconds. Then we use a try-catch block
+ // and try to open the file 10 times with a one second delay after each attempt.
+ // Again, 10 is arbitrary. But these seem to stop the hang in CR #870871.
+ // If there is an unrecognized exception when trying to open the file, we output
+ // an error message and write details to an exception.log file.
+ var ISEFullPath = ISERunDir + "/" + ISEFilename;
+ if (ISEFileSys.FileExists(ISEFullPath)) {
+ // File is already there. This could be a problem. Wait in case it is still in use.
+ WScript.Sleep(5000);
+ }
+ var i;
+ for (i = 0; i < 10; ++i) {
+ try {
+ return ISEFileSys.OpenTextFile(ISEFullPath, 8, true);
+ } catch (exception) {
+ var error_code = exception.number & 0xFFFF; // The other bits are a facility code.
+ if (error_code == 52) { // 52 is bad file name or number.
+ // Wait a second and try again.
+ WScript.Sleep(1000);
+ continue;
+ } else {
+ WScript.StdErr.WriteLine("ERROR: Exception caught trying to open file " + ISEFullPath);
+ var exceptionFilePath = ISERunDir + "/exception.log";
+ if (!ISEFileSys.FileExists(exceptionFilePath)) {
+ WScript.StdErr.WriteLine("See file " + exceptionFilePath + " for details.");
+ var exceptionFile = ISEFileSys.OpenTextFile(exceptionFilePath, 8, true);
+ exceptionFile.WriteLine("ERROR: Exception caught trying to open file " + ISEFullPath);
+ exceptionFile.WriteLine("\tException name: " + exception.name);
+ exceptionFile.WriteLine("\tException error code: " + error_code);
+ exceptionFile.WriteLine("\tException message: " + exception.message);
+ exceptionFile.Close();
+ }
+ throw exception;
+ }
+ }
+ }
+ // If we reached this point, we failed to open the file after 10 attempts.
+ // We need to error out.
+ WScript.StdErr.WriteLine("ERROR: Failed to open file " + ISEFullPath);
+ WScript.Quit(1);
+}
diff --git a/game.runs/synth_1/ISEWrap.sh b/game.runs/synth_1/ISEWrap.sh
new file mode 100755
index 0000000000000000000000000000000000000000..c2fbbb6098d6a14cfa1bdac6a65050244f5a6c7d
--- /dev/null
+++ b/game.runs/synth_1/ISEWrap.sh
@@ -0,0 +1,84 @@
+#!/bin/sh
+
+#
+# Vivado(TM)
+# ISEWrap.sh: Vivado Runs Script for UNIX
+# Copyright 1986-1999, 2001-2013 Xilinx, Inc. All Rights Reserved.
+#
+
+cmd_exists()
+{
+ command -v "$1" >/dev/null 2>&1
+}
+
+HD_LOG=$1
+shift
+
+# CHECK for a STOP FILE
+if [ -f .stop.rst ]
+then
+echo "" >> $HD_LOG
+echo "*** Halting run - EA reset detected ***" >> $HD_LOG
+echo "" >> $HD_LOG
+exit 1
+fi
+
+ISE_STEP=$1
+shift
+
+# WRITE STEP HEADER to LOG
+echo "" >> $HD_LOG
+echo "*** Running $ISE_STEP" >> $HD_LOG
+echo " with args $@" >> $HD_LOG
+echo "" >> $HD_LOG
+
+# LAUNCH!
+$ISE_STEP "$@" >> $HD_LOG 2>&1 &
+
+# BEGIN file creation
+ISE_PID=$!
+
+HostNameFile=/proc/sys/kernel/hostname
+if cmd_exists hostname
+then
+ISE_HOST=$(hostname)
+elif cmd_exists uname
+then
+ISE_HOST=$(uname -n)
+elif [ -f "$HostNameFile" ] && [ -r $HostNameFile ] && [ -s $HostNameFile ]
+then
+ISE_HOST=$(cat $HostNameFile)
+elif [ X != X$HOSTNAME ]
+then
+ISE_HOST=$HOSTNAME #bash
+else
+ISE_HOST=$HOST #csh
+fi
+
+ISE_USER=$USER
+
+ISE_HOSTCORE=$(awk '/^processor/{print $3}' /proc/cpuinfo | wc -l)
+ISE_MEMTOTAL=$(awk '/MemTotal/ {print $2}' /proc/meminfo)
+
+ISE_BEGINFILE=.$ISE_STEP.begin.rst
+/bin/touch $ISE_BEGINFILE
+echo "<?xml version=\"1.0\"?>" >> $ISE_BEGINFILE
+echo "<ProcessHandle Version=\"1\" Minor=\"0\">" >> $ISE_BEGINFILE
+echo " <Process Command=\"$ISE_STEP\" Owner=\"$ISE_USER\" Host=\"$ISE_HOST\" Pid=\"$ISE_PID\" HostCore=\"$ISE_HOSTCORE\" HostMemory=\"$ISE_MEMTOTAL\">" >> $ISE_BEGINFILE
+echo " </Process>" >> $ISE_BEGINFILE
+echo "</ProcessHandle>" >> $ISE_BEGINFILE
+
+# WAIT for ISEStep to finish
+wait $ISE_PID
+
+# END/ERROR file creation
+RETVAL=$?
+if [ $RETVAL -eq 0 ]
+then
+ /bin/touch .$ISE_STEP.end.rst
+else
+ /bin/touch .$ISE_STEP.error.rst
+fi
+
+exit $RETVAL
+
diff --git a/game.runs/synth_1/TopModule.dcp b/game.runs/synth_1/TopModule.dcp
new file mode 100644
index 0000000000000000000000000000000000000000..b35d7f037deed1c41aa380343059967096c24e1c
Binary files /dev/null and b/game.runs/synth_1/TopModule.dcp differ
diff --git a/game.runs/synth_1/TopModule.tcl b/game.runs/synth_1/TopModule.tcl
new file mode 100644
index 0000000000000000000000000000000000000000..514b28a744b929833773c4e79d7e7ab835b8b0b6
--- /dev/null
+++ b/game.runs/synth_1/TopModule.tcl
@@ -0,0 +1,147 @@
+#
+# Synthesis run script generated by Vivado
+#
+
+set TIME_start [clock seconds]
+namespace eval ::optrace {
+ variable script "/home/prasic/game/game.runs/synth_1/TopModule.tcl"
+ variable category "vivado_synth"
+}
+
+# Try to connect to running dispatch if we haven't done so already.
+# This code assumes that the Tcl interpreter is not using threads,
+# since the ::dispatch::connected variable isn't mutex protected.
+if {![info exists ::dispatch::connected]} {
+ namespace eval ::dispatch {
+ variable connected false
+ if {[llength [array get env XILINX_CD_CONNECT_ID]] > 0} {
+ set result "true"
+ if {[catch {
+ if {[lsearch -exact [package names] DispatchTcl] < 0} {
+ set result [load librdi_cd_clienttcl[info sharedlibextension]]
+ }
+ if {$result eq "false"} {
+ puts "WARNING: Could not load dispatch client library"
+ }
+ set connect_id [ ::dispatch::init_client -mode EXISTING_SERVER ]
+ if { $connect_id eq "" } {
+ puts "WARNING: Could not initialize dispatch client"
+ } else {
+ puts "INFO: Dispatch client connection id - $connect_id"
+ set connected true
+ }
+ } catch_res]} {
+ puts "WARNING: failed to connect to dispatch server - $catch_res"
+ }
+ }
+ }
+}
+if {$::dispatch::connected} {
+ # Remove the dummy proc if it exists.
+ if { [expr {[llength [info procs ::OPTRACE]] > 0}] } {
+ rename ::OPTRACE ""
+ }
+ proc ::OPTRACE { task action {tags {} } } {
+ ::vitis_log::op_trace "$task" $action -tags $tags -script $::optrace::script -category $::optrace::category
+ }
+ # dispatch is generic. We specifically want to attach logging.
+ ::vitis_log::connect_client
+} else {
+ # Add dummy proc if it doesn't exist.
+ if { [expr {[llength [info procs ::OPTRACE]] == 0}] } {
+ proc ::OPTRACE {{arg1 \"\" } {arg2 \"\"} {arg3 \"\" } {arg4 \"\"} {arg5 \"\" } {arg6 \"\"}} {
+ # Do nothing
+ }
+ }
+}
+
+proc create_report { reportName command } {
+ set status "."
+ append status $reportName ".fail"
+ if { [file exists $status] } {
+ eval file delete [glob $status]
+ }
+ send_msg_id runtcl-4 info "Executing : $command"
+ set retval [eval catch { $command } msg]
+ if { $retval != 0 } {
+ set fp [open $status w]
+ close $fp
+ send_msg_id runtcl-5 warning "$msg"
+ }
+}
+OPTRACE "synth_1" START { ROLLUP_AUTO }
+set_param xicom.use_bs_reader 1
+set_param chipscope.maxJobs 2
+set_param checkpoint.writeSynthRtdsInDcp 1
+set_param synth.incrementalSynthesisCache ./.Xil/Vivado-73025-LikeUE06/incrSyn
+set_msg_config -id {Common 17-41} -limit 10000000
+set_msg_config -id {Synth 8-256} -limit 10000
+set_msg_config -id {Synth 8-638} -limit 10000
+OPTRACE "Creating in-memory project" START { }
+create_project -in_memory -part xc7a100tcsg324-1
+
+set_param project.singleFileAddWarning.threshold 0
+set_param project.compositeFile.enableAutoGeneration 0
+set_param synth.vivado.isSynthRun true
+set_msg_config -source 4 -id {IP_Flow 19-2162} -severity warning -new_severity info
+set_property webtalk.parent_dir /home/prasic/game/game.cache/wt [current_project]
+set_property parent.project_path /home/prasic/game/game.xpr [current_project]
+set_property XPM_LIBRARIES XPM_CDC [current_project]
+set_property default_lib xil_defaultlib [current_project]
+set_property target_language VHDL [current_project]
+set_property ip_output_repo /home/prasic/game/game.cache/ip [current_project]
+set_property ip_cache_permissions {read write} [current_project]
+OPTRACE "Creating in-memory project" END { }
+OPTRACE "Adding files" START { }
+read_vhdl -library xil_defaultlib {
+ /home/prasic/game/game.srcs/sources_1/new/header.vhd
+ /home/prasic/game/game.srcs/sources_1/new/background.vhd
+ /home/prasic/game/game.srcs/sources_1/new/collision.vhd
+ /home/prasic/game/game.srcs/sources_1/new/obstacle.vhd
+ /home/prasic/game/game.srcs/sources_1/new/obstacle2.vhd
+ /home/prasic/game/game.srcs/sources_1/new/priority.vhd
+ /home/prasic/game/game.srcs/sources_1/new/runner.vhd
+ /home/prasic/game/game.srcs/sources_1/new/vga.vhd
+ /home/prasic/game/game.srcs/sources_1/new/TopModule.vhd
+}
+read_ip -quiet /home/prasic/game/game.srcs/sources_1/ip/clk_wiz_0/clk_wiz_0.xci
+set_property used_in_implementation false [get_files -all /home/prasic/game/game.gen/sources_1/ip/clk_wiz_0/clk_wiz_0_board.xdc]
+set_property used_in_implementation false [get_files -all /home/prasic/game/game.gen/sources_1/ip/clk_wiz_0/clk_wiz_0.xdc]
+set_property used_in_implementation false [get_files -all /home/prasic/game/game.gen/sources_1/ip/clk_wiz_0/clk_wiz_0_ooc.xdc]
+
+OPTRACE "Adding files" END { }
+# Mark all dcp files as not used in implementation to prevent them from being
+# stitched into the results of this synthesis run. Any black boxes in the
+# design are intentionally left as such for best results. Dcp files will be
+# stitched into the design at a later time, either when this synthesis run is
+# opened, or when it is stitched into a dependent implementation run.
+foreach dcp [get_files -quiet -all -filter file_type=="Design\ Checkpoint"] {
+ set_property used_in_implementation false $dcp
+}
+read_xdc /home/prasic/game/game.srcs/constrs_1/imports/PrASIC_Data/Nexys4_Master.xdc
+set_property used_in_implementation false [get_files /home/prasic/game/game.srcs/constrs_1/imports/PrASIC_Data/Nexys4_Master.xdc]
+
+set_param ips.enableIPCacheLiteLoad 1
+
+read_checkpoint -auto_incremental -incremental /home/prasic/game/game.srcs/utils_1/imports/synth_1/TopModule.dcp
+close [open __synthesis_is_running__ w]
+
+OPTRACE "synth_design" START { }
+synth_design -top TopModule -part xc7a100tcsg324-1
+OPTRACE "synth_design" END { }
+if { [get_msg_config -count -severity {CRITICAL WARNING}] > 0 } {
+ send_msg_id runtcl-6 info "Synthesis results are not added to the cache due to CRITICAL_WARNING"
+}
+
+
+OPTRACE "write_checkpoint" START { CHECKPOINT }
+# disable binary constraint mode for synth run checkpoints
+set_param constraints.enableBinaryConstraints false
+write_checkpoint -force -noxdef TopModule.dcp
+OPTRACE "write_checkpoint" END { }
+OPTRACE "synth reports" START { REPORT }
+create_report "synth_1_synth_report_utilization_0" "report_utilization -file TopModule_utilization_synth.rpt -pb TopModule_utilization_synth.pb"
+OPTRACE "synth reports" END { }
+file delete __synthesis_is_running__
+close [open __synthesis_is_complete__ w]
+OPTRACE "synth_1" END { }
diff --git a/game.runs/synth_1/TopModule.vds b/game.runs/synth_1/TopModule.vds
new file mode 100644
index 0000000000000000000000000000000000000000..c30c4dde73df1f35c01820ff0ea82fc2b6de8e71
--- /dev/null
+++ b/game.runs/synth_1/TopModule.vds
@@ -0,0 +1,394 @@
+#-----------------------------------------------------------
+# Vivado v2022.2 (64-bit)
+# SW Build 3671981 on Fri Oct 14 04:59:54 MDT 2022
+# IP Build 3669848 on Fri Oct 14 08:30:02 MDT 2022
+# Start of session at: Tue Feb 28 17:00:56 2023
+# Process ID: 238750
+# Current directory: /home/prasic/game/game.runs/synth_1
+# Command line: vivado -log TopModule.vds -product Vivado -mode batch -messageDb vivado.pb -notrace -source TopModule.tcl
+# Log file: /home/prasic/game/game.runs/synth_1/TopModule.vds
+# Journal file: /home/prasic/game/game.runs/synth_1/vivado.jou
+# Running On: LikeUE06, OS: Linux, CPU Frequency: 2482.416 MHz, CPU Physical cores: 4, Host memory: 16699 MB
+#-----------------------------------------------------------
+source TopModule.tcl -notrace
+Command: read_checkpoint -auto_incremental -incremental /home/prasic/game/game.srcs/utils_1/imports/synth_1/TopModule.dcp
+INFO: [Vivado 12-5825] Read reference checkpoint from /home/prasic/game/game.srcs/utils_1/imports/synth_1/TopModule.dcp for incremental synthesis
+INFO: [Vivado 12-7989] Please ensure there are no constraint changes
+Command: synth_design -top TopModule -part xc7a100tcsg324-1
+Starting synth_design
+Attempting to get a license for feature 'Synthesis' and/or device 'xc7a100t'
+INFO: [Common 17-349] Got license for feature 'Synthesis' and/or device 'xc7a100t'
+INFO: [Device 21-403] Loading part xc7a100tcsg324-1
+INFO: [Designutils 20-5440] No compile time benefit to using incremental synthesis; A full resynthesis will be run
+INFO: [Designutils 20-4379] Flow is switching to default flow due to incremental criteria not met. If you would like to alter this behaviour and have the flow terminate instead, please set the following parameter config_implementation {autoIncr.Synth.RejectBehavior Terminate}
+INFO: [Synth 8-7079] Multithreading enabled for synth_design using a maximum of 4 processes.
+INFO: [Synth 8-7078] Launching helper process for spawning children vivado processes
+INFO: [Synth 8-7075] Helper process launched with PID 238787
+INFO: [Synth 8-11241] undeclared symbol 'REGCCE', assumed default net type 'wire' [/opt/Xilinx/Vivado/2022.2/data/verilog/src/unimacro/BRAM_SINGLE_MACRO.v:2170]
+---------------------------------------------------------------------------------
+Starting RTL Elaboration : Time (s): cpu = 00:00:04 ; elapsed = 00:00:04 . Memory (MB): peak = 1958.719 ; gain = 372.586 ; free physical = 4425 ; free virtual = 31401
+Synthesis current peak Physical Memory [PSS] (MB): peak = 1387.041; parent = 1175.688; children = 211.354
+Synthesis current peak Virtual Memory [VSS] (MB): peak = 2964.164; parent = 1961.691; children = 1002.473
+---------------------------------------------------------------------------------
+INFO: [Synth 8-638] synthesizing module 'TopModule' [/home/prasic/game/game.srcs/sources_1/new/TopModule.vhd:46]
+INFO: [Synth 8-3491] module 'clk_wiz_0' declared at '/home/prasic/game/game.runs/synth_1/.Xil/Vivado-238750-LikeUE06/realtime/clk_wiz_0_stub.vhdl:5' bound to instance 'pixelClk' of component 'clk_wiz_0' [/home/prasic/game/game.srcs/sources_1/new/TopModule.vhd:167]
+INFO: [Synth 8-638] synthesizing module 'clk_wiz_0' [/home/prasic/game/game.runs/synth_1/.Xil/Vivado-238750-LikeUE06/realtime/clk_wiz_0_stub.vhdl:14]
+INFO: [Synth 8-3491] module 'vga' declared at '/home/prasic/game/game.srcs/sources_1/new/vga.vhd:34' bound to instance 'vgaInterface' of component 'vga' [/home/prasic/game/game.srcs/sources_1/new/TopModule.vhd:172]
+INFO: [Synth 8-638] synthesizing module 'vga' [/home/prasic/game/game.srcs/sources_1/new/vga.vhd:48]
+WARNING: [Synth 8-614] signal 'color' is read in the process but is not in the sensitivity list [/home/prasic/game/game.srcs/sources_1/new/vga.vhd:91]
+INFO: [Synth 8-256] done synthesizing module 'vga' (0#1) [/home/prasic/game/game.srcs/sources_1/new/vga.vhd:48]
+WARNING: [Synth 8-7043] port width mismatch for port 'FCounter': port width = 12, actual width = 16 (integer) [/home/prasic/game/game.srcs/sources_1/new/TopModule.vhd:65]
+INFO: [Synth 8-3491] module 'priority' declared at '/home/prasic/game/game.srcs/sources_1/new/priority.vhd:34' bound to instance 'priorityLogic' of component 'priority' [/home/prasic/game/game.srcs/sources_1/new/TopModule.vhd:188]
+INFO: [Synth 8-638] synthesizing module 'priority' [/home/prasic/game/game.srcs/sources_1/new/priority.vhd:48]
+WARNING: [Synth 8-614] signal 'color_runner' is read in the process but is not in the sensitivity list [/home/prasic/game/game.srcs/sources_1/new/priority.vhd:52]
+WARNING: [Synth 8-614] signal 'en_obstacleS' is read in the process but is not in the sensitivity list [/home/prasic/game/game.srcs/sources_1/new/priority.vhd:52]
+WARNING: [Synth 8-614] signal 'color_obstacleS' is read in the process but is not in the sensitivity list [/home/prasic/game/game.srcs/sources_1/new/priority.vhd:52]
+WARNING: [Synth 8-614] signal 'en_obstacleL' is read in the process but is not in the sensitivity list [/home/prasic/game/game.srcs/sources_1/new/priority.vhd:52]
+WARNING: [Synth 8-614] signal 'color_obstacleL' is read in the process but is not in the sensitivity list [/home/prasic/game/game.srcs/sources_1/new/priority.vhd:52]
+WARNING: [Synth 8-614] signal 'en_back' is read in the process but is not in the sensitivity list [/home/prasic/game/game.srcs/sources_1/new/priority.vhd:52]
+WARNING: [Synth 8-614] signal 'color_back' is read in the process but is not in the sensitivity list [/home/prasic/game/game.srcs/sources_1/new/priority.vhd:52]
+INFO: [Synth 8-256] done synthesizing module 'priority' (0#1) [/home/prasic/game/game.srcs/sources_1/new/priority.vhd:48]
+INFO: [Synth 8-3491] module 'runner' declared at '/home/prasic/game/game.srcs/sources_1/new/runner.vhd:36' bound to instance 'runnerObject' of component 'runner' [/home/prasic/game/game.srcs/sources_1/new/TopModule.vhd:201]
+INFO: [Synth 8-638] synthesizing module 'runner' [/home/prasic/game/game.srcs/sources_1/new/runner.vhd:50]
+WARNING: [Synth 8-614] signal 'pos_object_x_actual' is read in the process but is not in the sensitivity list [/home/prasic/game/game.srcs/sources_1/new/runner.vhd:73]
+WARNING: [Synth 8-614] signal 'pos_object_y_actual' is read in the process but is not in the sensitivity list [/home/prasic/game/game.srcs/sources_1/new/runner.vhd:73]
+WARNING: [Synth 8-614] signal 'btnCpuReset_r' is read in the process but is not in the sensitivity list [/home/prasic/game/game.srcs/sources_1/new/runner.vhd:85]
+INFO: [Synth 8-256] done synthesizing module 'runner' (0#1) [/home/prasic/game/game.srcs/sources_1/new/runner.vhd:50]
+INFO: [Synth 8-3491] module 'background' declared at '/home/prasic/game/game.srcs/sources_1/new/background.vhd:35' bound to instance 'backgroundObject' of component 'background' [/home/prasic/game/game.srcs/sources_1/new/TopModule.vhd:214]
+INFO: [Synth 8-638] synthesizing module 'background' [/home/prasic/game/game.srcs/sources_1/new/background.vhd:45]
+INFO: [Synth 8-256] done synthesizing module 'background' (0#1) [/home/prasic/game/game.srcs/sources_1/new/background.vhd:45]
+INFO: [Synth 8-3491] module 'obstacle_S' declared at '/home/prasic/game/game.srcs/sources_1/new/obstacle.vhd:36' bound to instance 'smallObstacle' of component 'obstacle_S' [/home/prasic/game/game.srcs/sources_1/new/TopModule.vhd:225]
+INFO: [Synth 8-638] synthesizing module 'obstacle_S' [/home/prasic/game/game.srcs/sources_1/new/obstacle.vhd:47]
+WARNING: [Synth 8-614] signal 'pos_object_x_actual' is read in the process but is not in the sensitivity list [/home/prasic/game/game.srcs/sources_1/new/obstacle.vhd:81]
+WARNING: [Synth 8-614] signal 'pos_object_y_actual' is read in the process but is not in the sensitivity list [/home/prasic/game/game.srcs/sources_1/new/obstacle.vhd:81]
+WARNING: [Synth 8-614] signal 'btnCpuReset_o' is read in the process but is not in the sensitivity list [/home/prasic/game/game.srcs/sources_1/new/obstacle.vhd:93]
+INFO: [Synth 8-256] done synthesizing module 'obstacle_S' (0#1) [/home/prasic/game/game.srcs/sources_1/new/obstacle.vhd:47]
+INFO: [Synth 8-3491] module 'obstacle_L' declared at '/home/prasic/game/game.srcs/sources_1/new/obstacle2.vhd:36' bound to instance 'largeObstacle' of component 'obstacle_L' [/home/prasic/game/game.srcs/sources_1/new/TopModule.vhd:235]
+INFO: [Synth 8-638] synthesizing module 'obstacle_L' [/home/prasic/game/game.srcs/sources_1/new/obstacle2.vhd:47]
+WARNING: [Synth 8-614] signal 'pos_object_x_actual' is read in the process but is not in the sensitivity list [/home/prasic/game/game.srcs/sources_1/new/obstacle2.vhd:81]
+WARNING: [Synth 8-614] signal 'pos_object_y_actual' is read in the process but is not in the sensitivity list [/home/prasic/game/game.srcs/sources_1/new/obstacle2.vhd:81]
+WARNING: [Synth 8-614] signal 'btnCpuReset_o' is read in the process but is not in the sensitivity list [/home/prasic/game/game.srcs/sources_1/new/obstacle2.vhd:93]
+INFO: [Synth 8-256] done synthesizing module 'obstacle_L' (0#1) [/home/prasic/game/game.srcs/sources_1/new/obstacle2.vhd:47]
+INFO: [Synth 8-3491] module 'collision' declared at '/home/prasic/game/game.srcs/sources_1/new/collision.vhd:34' bound to instance 'collisionDetection' of component 'collision' [/home/prasic/game/game.srcs/sources_1/new/TopModule.vhd:247]
+INFO: [Synth 8-638] synthesizing module 'collision' [/home/prasic/game/game.srcs/sources_1/new/collision.vhd:45]
+WARNING: [Synth 8-614] signal 'btnCpuReset_c' is read in the process but is not in the sensitivity list [/home/prasic/game/game.srcs/sources_1/new/collision.vhd:51]
+INFO: [Synth 8-256] done synthesizing module 'collision' (0#1) [/home/prasic/game/game.srcs/sources_1/new/collision.vhd:45]
+INFO: [Synth 8-256] done synthesizing module 'TopModule' (0#1) [/home/prasic/game/game.srcs/sources_1/new/TopModule.vhd:46]
+WARNING: [Synth 8-5863] Implementing Library version of Mod/Rem due to signed path. This typically leads to poor QOR. Check RTL to see if unsigned path for the operator is possible [/home/prasic/game/game.srcs/sources_1/new/runner.vhd:105]
+WARNING: [Synth 8-7129] Port FCounter_o[15] in module obstacle_L is either unconnected or has no load
+WARNING: [Synth 8-7129] Port FCounter_o[14] in module obstacle_L is either unconnected or has no load
+WARNING: [Synth 8-7129] Port FCounter_o[13] in module obstacle_L is either unconnected or has no load
+WARNING: [Synth 8-7129] Port FCounter_o[12] in module obstacle_L is either unconnected or has no load
+WARNING: [Synth 8-7129] Port FCounter_o[11] in module obstacle_L is either unconnected or has no load
+WARNING: [Synth 8-7129] Port FCounter_o[10] in module obstacle_L is either unconnected or has no load
+WARNING: [Synth 8-7129] Port FCounter_o[9] in module obstacle_L is either unconnected or has no load
+WARNING: [Synth 8-7129] Port FCounter_o[8] in module obstacle_L is either unconnected or has no load
+WARNING: [Synth 8-7129] Port FCounter_o[7] in module obstacle_L is either unconnected or has no load
+WARNING: [Synth 8-7129] Port FCounter_o[6] in module obstacle_L is either unconnected or has no load
+WARNING: [Synth 8-7129] Port FCounter_o[5] in module obstacle_L is either unconnected or has no load
+WARNING: [Synth 8-7129] Port FCounter_o[4] in module obstacle_L is either unconnected or has no load
+WARNING: [Synth 8-7129] Port FCounter_o[3] in module obstacle_L is either unconnected or has no load
+WARNING: [Synth 8-7129] Port FCounter_o[2] in module obstacle_L is either unconnected or has no load
+WARNING: [Synth 8-7129] Port FCounter_o[1] in module obstacle_L is either unconnected or has no load
+WARNING: [Synth 8-7129] Port FCounter_o[0] in module obstacle_L is either unconnected or has no load
+WARNING: [Synth 8-7129] Port FCounter_o[15] in module obstacle_S is either unconnected or has no load
+WARNING: [Synth 8-7129] Port FCounter_o[14] in module obstacle_S is either unconnected or has no load
+WARNING: [Synth 8-7129] Port FCounter_o[13] in module obstacle_S is either unconnected or has no load
+WARNING: [Synth 8-7129] Port FCounter_o[12] in module obstacle_S is either unconnected or has no load
+WARNING: [Synth 8-7129] Port FCounter_o[11] in module obstacle_S is either unconnected or has no load
+WARNING: [Synth 8-7129] Port FCounter_o[10] in module obstacle_S is either unconnected or has no load
+WARNING: [Synth 8-7129] Port FCounter_o[9] in module obstacle_S is either unconnected or has no load
+WARNING: [Synth 8-7129] Port FCounter_o[8] in module obstacle_S is either unconnected or has no load
+WARNING: [Synth 8-7129] Port FCounter_o[7] in module obstacle_S is either unconnected or has no load
+WARNING: [Synth 8-7129] Port FCounter_o[6] in module obstacle_S is either unconnected or has no load
+WARNING: [Synth 8-7129] Port FCounter_o[5] in module obstacle_S is either unconnected or has no load
+WARNING: [Synth 8-7129] Port FCounter_o[4] in module obstacle_S is either unconnected or has no load
+WARNING: [Synth 8-7129] Port FCounter_o[3] in module obstacle_S is either unconnected or has no load
+WARNING: [Synth 8-7129] Port FCounter_o[2] in module obstacle_S is either unconnected or has no load
+WARNING: [Synth 8-7129] Port FCounter_o[1] in module obstacle_S is either unconnected or has no load
+WARNING: [Synth 8-7129] Port FCounter_o[0] in module obstacle_S is either unconnected or has no load
+WARNING: [Synth 8-7129] Port clk_pixel in module background is either unconnected or has no load
+WARNING: [Synth 8-7129] Port btnCpuReset_b in module background is either unconnected or has no load
+WARNING: [Synth 8-7129] Port HCounter_b[9] in module background is either unconnected or has no load
+WARNING: [Synth 8-7129] Port HCounter_b[8] in module background is either unconnected or has no load
+WARNING: [Synth 8-7129] Port HCounter_b[7] in module background is either unconnected or has no load
+WARNING: [Synth 8-7129] Port HCounter_b[6] in module background is either unconnected or has no load
+WARNING: [Synth 8-7129] Port HCounter_b[5] in module background is either unconnected or has no load
+WARNING: [Synth 8-7129] Port HCounter_b[4] in module background is either unconnected or has no load
+WARNING: [Synth 8-7129] Port HCounter_b[3] in module background is either unconnected or has no load
+WARNING: [Synth 8-7129] Port HCounter_b[2] in module background is either unconnected or has no load
+WARNING: [Synth 8-7129] Port HCounter_b[1] in module background is either unconnected or has no load
+WARNING: [Synth 8-7129] Port HCounter_b[0] in module background is either unconnected or has no load
+WARNING: [Synth 8-7129] Port FCounter_b[11] in module background is either unconnected or has no load
+WARNING: [Synth 8-7129] Port FCounter_b[10] in module background is either unconnected or has no load
+WARNING: [Synth 8-7129] Port FCounter_b[9] in module background is either unconnected or has no load
+WARNING: [Synth 8-7129] Port FCounter_b[8] in module background is either unconnected or has no load
+WARNING: [Synth 8-7129] Port FCounter_b[7] in module background is either unconnected or has no load
+WARNING: [Synth 8-7129] Port FCounter_b[6] in module background is either unconnected or has no load
+WARNING: [Synth 8-7129] Port FCounter_b[5] in module background is either unconnected or has no load
+WARNING: [Synth 8-7129] Port FCounter_b[4] in module background is either unconnected or has no load
+WARNING: [Synth 8-7129] Port FCounter_b[3] in module background is either unconnected or has no load
+WARNING: [Synth 8-7129] Port FCounter_b[2] in module background is either unconnected or has no load
+WARNING: [Synth 8-7129] Port FCounter_b[1] in module background is either unconnected or has no load
+WARNING: [Synth 8-7129] Port FCounter_b[0] in module background is either unconnected or has no load
+WARNING: [Synth 8-7129] Port FStrobe_b in module background is either unconnected or has no load
+---------------------------------------------------------------------------------
+Finished RTL Elaboration : Time (s): cpu = 00:00:06 ; elapsed = 00:00:06 . Memory (MB): peak = 2029.656 ; gain = 443.523 ; free physical = 4516 ; free virtual = 31493
+Synthesis current peak Physical Memory [PSS] (MB): peak = 1387.041; parent = 1175.688; children = 211.354
+Synthesis current peak Virtual Memory [VSS] (MB): peak = 3032.133; parent = 2029.660; children = 1002.473
+---------------------------------------------------------------------------------
+---------------------------------------------------------------------------------
+Start Handling Custom Attributes
+---------------------------------------------------------------------------------
+---------------------------------------------------------------------------------
+Finished Handling Custom Attributes : Time (s): cpu = 00:00:06 ; elapsed = 00:00:06 . Memory (MB): peak = 2047.469 ; gain = 461.336 ; free physical = 4515 ; free virtual = 31493
+Synthesis current peak Physical Memory [PSS] (MB): peak = 1387.041; parent = 1175.688; children = 211.354
+Synthesis current peak Virtual Memory [VSS] (MB): peak = 3049.945; parent = 2047.473; children = 1002.473
+---------------------------------------------------------------------------------
+---------------------------------------------------------------------------------
+Finished RTL Optimization Phase 1 : Time (s): cpu = 00:00:06 ; elapsed = 00:00:06 . Memory (MB): peak = 2047.469 ; gain = 461.336 ; free physical = 4515 ; free virtual = 31493
+Synthesis current peak Physical Memory [PSS] (MB): peak = 1387.041; parent = 1175.688; children = 211.354
+Synthesis current peak Virtual Memory [VSS] (MB): peak = 3049.945; parent = 2047.473; children = 1002.473
+---------------------------------------------------------------------------------
+Netlist sorting complete. Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.01 . Memory (MB): peak = 2047.469 ; gain = 0.000 ; free physical = 4509 ; free virtual = 31486
+INFO: [Project 1-570] Preparing netlist for logic optimization
+
+Processing XDC Constraints
+Initializing timing engine
+Parsing XDC File [/home/prasic/game/game.gen/sources_1/ip/clk_wiz_0/clk_wiz_0/clk_wiz_0_in_context.xdc] for cell 'pixelClk'
+Finished Parsing XDC File [/home/prasic/game/game.gen/sources_1/ip/clk_wiz_0/clk_wiz_0/clk_wiz_0_in_context.xdc] for cell 'pixelClk'
+Parsing XDC File [/home/prasic/game/game.srcs/constrs_1/imports/PrASIC_Data/Nexys4_Master.xdc]
+Finished Parsing XDC File [/home/prasic/game/game.srcs/constrs_1/imports/PrASIC_Data/Nexys4_Master.xdc]
+INFO: [Project 1-236] Implementation specific constraints were found while reading constraint file [/home/prasic/game/game.srcs/constrs_1/imports/PrASIC_Data/Nexys4_Master.xdc]. These constraints will be ignored for synthesis but will be used in implementation. Impacted constraints are listed in the file [.Xil/TopModule_propImpl.xdc].
+Resolution: To avoid this warning, move constraints listed in [.Xil/TopModule_propImpl.xdc] to another XDC file and exclude this new file from synthesis with the used_in_synthesis property (File Properties dialog in GUI) and re-run elaboration/synthesis.
+Completed Processing XDC Constraints
+
+Netlist sorting complete. Time (s): cpu = 00:00:00 ; elapsed = 00:00:00 . Memory (MB): peak = 2204.219 ; gain = 0.000 ; free physical = 4423 ; free virtual = 31400
+INFO: [Project 1-111] Unisim Transformation Summary:
+No Unisim elements were transformed.
+
+Constraint Validation Runtime : Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.01 . Memory (MB): peak = 2204.219 ; gain = 0.000 ; free physical = 4423 ; free virtual = 31400
+INFO: [Designutils 20-5440] No compile time benefit to using incremental synthesis; A full resynthesis will be run
+INFO: [Designutils 20-4379] Flow is switching to default flow due to incremental criteria not met. If you would like to alter this behaviour and have the flow terminate instead, please set the following parameter config_implementation {autoIncr.Synth.RejectBehavior Terminate}
+INFO: [Synth 8-11241] undeclared symbol 'REGCCE', assumed default net type 'wire' [/opt/Xilinx/Vivado/2022.2/data/verilog/src/unimacro/BRAM_SINGLE_MACRO.v:2170]
+---------------------------------------------------------------------------------
+Finished Constraint Validation : Time (s): cpu = 00:00:12 ; elapsed = 00:00:13 . Memory (MB): peak = 2204.219 ; gain = 618.086 ; free physical = 4489 ; free virtual = 31466
+Synthesis current peak Physical Memory [PSS] (MB): peak = 1387.041; parent = 1175.688; children = 211.354
+Synthesis current peak Virtual Memory [VSS] (MB): peak = 3174.680; parent = 2172.207; children = 1002.473
+---------------------------------------------------------------------------------
+---------------------------------------------------------------------------------
+Start Loading Part and Timing Information
+---------------------------------------------------------------------------------
+Loading part: xc7a100tcsg324-1
+---------------------------------------------------------------------------------
+Finished Loading Part and Timing Information : Time (s): cpu = 00:00:12 ; elapsed = 00:00:13 . Memory (MB): peak = 2204.219 ; gain = 618.086 ; free physical = 4489 ; free virtual = 31466
+Synthesis current peak Physical Memory [PSS] (MB): peak = 1387.041; parent = 1175.688; children = 211.354
+Synthesis current peak Virtual Memory [VSS] (MB): peak = 3174.680; parent = 2172.207; children = 1002.473
+---------------------------------------------------------------------------------
+---------------------------------------------------------------------------------
+Start Applying 'set_property' XDC Constraints
+---------------------------------------------------------------------------------
+Applied set_property IO_BUFFER_TYPE = NONE for clk. (constraint file /home/prasic/game/game.gen/sources_1/ip/clk_wiz_0/clk_wiz_0/clk_wiz_0_in_context.xdc, line 3).
+Applied set_property CLOCK_BUFFER_TYPE = NONE for clk. (constraint file /home/prasic/game/game.gen/sources_1/ip/clk_wiz_0/clk_wiz_0/clk_wiz_0_in_context.xdc, line 4).
+Applied set_property KEEP_HIERARCHY = SOFT for pixelClk. (constraint file auto generated constraint).
+---------------------------------------------------------------------------------
+Finished applying 'set_property' XDC Constraints : Time (s): cpu = 00:00:12 ; elapsed = 00:00:13 . Memory (MB): peak = 2204.219 ; gain = 618.086 ; free physical = 4489 ; free virtual = 31466
+Synthesis current peak Physical Memory [PSS] (MB): peak = 1387.041; parent = 1175.688; children = 211.354
+Synthesis current peak Virtual Memory [VSS] (MB): peak = 3174.680; parent = 2172.207; children = 1002.473
+---------------------------------------------------------------------------------
+---------------------------------------------------------------------------------
+Finished RTL Optimization Phase 2 : Time (s): cpu = 00:00:12 ; elapsed = 00:00:13 . Memory (MB): peak = 2204.219 ; gain = 618.086 ; free physical = 4480 ; free virtual = 31458
+Synthesis current peak Physical Memory [PSS] (MB): peak = 1387.041; parent = 1175.688; children = 211.354
+Synthesis current peak Virtual Memory [VSS] (MB): peak = 3174.680; parent = 2172.207; children = 1002.473
+---------------------------------------------------------------------------------
+---------------------------------------------------------------------------------
+Start RTL Component Statistics
+---------------------------------------------------------------------------------
+Detailed RTL Component Info :
++---Adders :
+ 3 Input 33 Bit Adders := 3
+ 2 Input 20 Bit Adders := 1
+ 2 Input 18 Bit Adders := 1
+ 3 Input 17 Bit Adders := 1
+ 2 Input 17 Bit Adders := 1
+ 2 Input 16 Bit Adders := 1
+ 2 Input 11 Bit Adders := 5
+ 2 Input 10 Bit Adders := 5
+ 2 Input 9 Bit Adders := 2
++---Registers :
+ 16 Bit Registers := 2
+ 11 Bit Registers := 2
+ 10 Bit Registers := 5
+ 9 Bit Registers := 4
+ 2 Bit Registers := 1
+ 1 Bit Registers := 1
++---Muxes :
+ 2 Input 18 Bit Muxes := 4
+ 2 Input 17 Bit Muxes := 1
+ 2 Input 16 Bit Muxes := 1
+ 2 Input 11 Bit Muxes := 3
+ 2 Input 10 Bit Muxes := 2
+ 2 Input 9 Bit Muxes := 1
+ 2 Input 4 Bit Muxes := 9
+ 2 Input 1 Bit Muxes := 1
+---------------------------------------------------------------------------------
+Finished RTL Component Statistics
+---------------------------------------------------------------------------------
+---------------------------------------------------------------------------------
+Start Part Resource Summary
+---------------------------------------------------------------------------------
+Part Resources:
+DSPs: 240 (col length:80)
+BRAMs: 270 (col length: RAMB18 80 RAMB36 40)
+---------------------------------------------------------------------------------
+Finished Part Resource Summary
+---------------------------------------------------------------------------------
+---------------------------------------------------------------------------------
+Start Cross Boundary and Area Optimization
+---------------------------------------------------------------------------------
+WARNING: [Synth 8-7080] Parallel synthesis criteria is not met
+---------------------------------------------------------------------------------
+Finished Cross Boundary and Area Optimization : Time (s): cpu = 00:00:14 ; elapsed = 00:00:15 . Memory (MB): peak = 2204.219 ; gain = 618.086 ; free physical = 4462 ; free virtual = 31445
+Synthesis current peak Physical Memory [PSS] (MB): peak = 1387.041; parent = 1175.688; children = 211.354
+Synthesis current peak Virtual Memory [VSS] (MB): peak = 3174.680; parent = 2172.207; children = 1002.473
+---------------------------------------------------------------------------------
+---------------------------------------------------------------------------------
+Start Applying XDC Timing Constraints
+---------------------------------------------------------------------------------
+---------------------------------------------------------------------------------
+Finished Applying XDC Timing Constraints : Time (s): cpu = 00:00:19 ; elapsed = 00:00:20 . Memory (MB): peak = 2204.219 ; gain = 618.086 ; free physical = 4343 ; free virtual = 31325
+Synthesis current peak Physical Memory [PSS] (MB): peak = 1483.411; parent = 1272.714; children = 211.354
+Synthesis current peak Virtual Memory [VSS] (MB): peak = 3174.680; parent = 2172.207; children = 1002.473
+---------------------------------------------------------------------------------
+---------------------------------------------------------------------------------
+Start Timing Optimization
+---------------------------------------------------------------------------------
+---------------------------------------------------------------------------------
+Finished Timing Optimization : Time (s): cpu = 00:00:20 ; elapsed = 00:00:22 . Memory (MB): peak = 2204.219 ; gain = 618.086 ; free physical = 4333 ; free virtual = 31315
+Synthesis current peak Physical Memory [PSS] (MB): peak = 1493.198; parent = 1282.507; children = 211.354
+Synthesis current peak Virtual Memory [VSS] (MB): peak = 3174.680; parent = 2172.207; children = 1002.473
+---------------------------------------------------------------------------------
+---------------------------------------------------------------------------------
+Start Technology Mapping
+---------------------------------------------------------------------------------
+---------------------------------------------------------------------------------
+Finished Technology Mapping : Time (s): cpu = 00:00:21 ; elapsed = 00:00:22 . Memory (MB): peak = 2204.219 ; gain = 618.086 ; free physical = 4332 ; free virtual = 31315
+Synthesis current peak Physical Memory [PSS] (MB): peak = 1493.198; parent = 1282.507; children = 211.354
+Synthesis current peak Virtual Memory [VSS] (MB): peak = 3174.680; parent = 2172.207; children = 1002.473
+---------------------------------------------------------------------------------
+---------------------------------------------------------------------------------
+Start IO Insertion
+---------------------------------------------------------------------------------
+---------------------------------------------------------------------------------
+Start Flattening Before IO Insertion
+---------------------------------------------------------------------------------
+---------------------------------------------------------------------------------
+Finished Flattening Before IO Insertion
+---------------------------------------------------------------------------------
+---------------------------------------------------------------------------------
+Start Final Netlist Cleanup
+---------------------------------------------------------------------------------
+---------------------------------------------------------------------------------
+Finished Final Netlist Cleanup
+---------------------------------------------------------------------------------
+---------------------------------------------------------------------------------
+Finished IO Insertion : Time (s): cpu = 00:00:24 ; elapsed = 00:00:25 . Memory (MB): peak = 2204.219 ; gain = 618.086 ; free physical = 4334 ; free virtual = 31316
+Synthesis current peak Physical Memory [PSS] (MB): peak = 1493.366; parent = 1282.675; children = 211.354
+Synthesis current peak Virtual Memory [VSS] (MB): peak = 3174.680; parent = 2172.207; children = 1002.473
+---------------------------------------------------------------------------------
+---------------------------------------------------------------------------------
+Start Renaming Generated Instances
+---------------------------------------------------------------------------------
+---------------------------------------------------------------------------------
+Finished Renaming Generated Instances : Time (s): cpu = 00:00:24 ; elapsed = 00:00:25 . Memory (MB): peak = 2204.219 ; gain = 618.086 ; free physical = 4334 ; free virtual = 31316
+Synthesis current peak Physical Memory [PSS] (MB): peak = 1493.366; parent = 1282.675; children = 211.354
+Synthesis current peak Virtual Memory [VSS] (MB): peak = 3174.680; parent = 2172.207; children = 1002.473
+---------------------------------------------------------------------------------
+---------------------------------------------------------------------------------
+Start Rebuilding User Hierarchy
+---------------------------------------------------------------------------------
+---------------------------------------------------------------------------------
+Finished Rebuilding User Hierarchy : Time (s): cpu = 00:00:24 ; elapsed = 00:00:25 . Memory (MB): peak = 2204.219 ; gain = 618.086 ; free physical = 4334 ; free virtual = 31316
+Synthesis current peak Physical Memory [PSS] (MB): peak = 1493.366; parent = 1282.675; children = 211.354
+Synthesis current peak Virtual Memory [VSS] (MB): peak = 3174.680; parent = 2172.207; children = 1002.473
+---------------------------------------------------------------------------------
+---------------------------------------------------------------------------------
+Start Renaming Generated Ports
+---------------------------------------------------------------------------------
+---------------------------------------------------------------------------------
+Finished Renaming Generated Ports : Time (s): cpu = 00:00:24 ; elapsed = 00:00:25 . Memory (MB): peak = 2204.219 ; gain = 618.086 ; free physical = 4334 ; free virtual = 31317
+Synthesis current peak Physical Memory [PSS] (MB): peak = 1493.366; parent = 1282.675; children = 211.354
+Synthesis current peak Virtual Memory [VSS] (MB): peak = 3174.680; parent = 2172.207; children = 1002.473
+---------------------------------------------------------------------------------
+---------------------------------------------------------------------------------
+Start Handling Custom Attributes
+---------------------------------------------------------------------------------
+---------------------------------------------------------------------------------
+Finished Handling Custom Attributes : Time (s): cpu = 00:00:24 ; elapsed = 00:00:25 . Memory (MB): peak = 2204.219 ; gain = 618.086 ; free physical = 4334 ; free virtual = 31317
+Synthesis current peak Physical Memory [PSS] (MB): peak = 1493.366; parent = 1282.675; children = 211.354
+Synthesis current peak Virtual Memory [VSS] (MB): peak = 3174.680; parent = 2172.207; children = 1002.473
+---------------------------------------------------------------------------------
+---------------------------------------------------------------------------------
+Start Renaming Generated Nets
+---------------------------------------------------------------------------------
+---------------------------------------------------------------------------------
+Finished Renaming Generated Nets : Time (s): cpu = 00:00:24 ; elapsed = 00:00:25 . Memory (MB): peak = 2204.219 ; gain = 618.086 ; free physical = 4334 ; free virtual = 31317
+Synthesis current peak Physical Memory [PSS] (MB): peak = 1493.366; parent = 1282.675; children = 211.354
+Synthesis current peak Virtual Memory [VSS] (MB): peak = 3174.680; parent = 2172.207; children = 1002.473
+---------------------------------------------------------------------------------
+---------------------------------------------------------------------------------
+Start Writing Synthesis Report
+---------------------------------------------------------------------------------
+
+Report BlackBoxes:
++------+--------------+----------+
+| |BlackBox name |Instances |
++------+--------------+----------+
+|1 |clk_wiz_0 | 1|
++------+--------------+----------+
+
+Report Cell Usage:
++------+---------------+------+
+| |Cell |Count |
++------+---------------+------+
+|1 |clk_wiz_0_bbox | 1|
+|2 |CARRY4 | 56|
+|3 |LUT1 | 47|
+|4 |LUT2 | 98|
+|5 |LUT3 | 64|
+|6 |LUT4 | 77|
+|7 |LUT5 | 51|
+|8 |LUT6 | 88|
+|9 |FDCE | 73|
+|10 |FDPE | 10|
+|11 |FDRE | 35|
+|12 |FDSE | 6|
+|13 |IBUF | 2|
+|14 |OBUF | 30|
++------+---------------+------+
+---------------------------------------------------------------------------------
+Finished Writing Synthesis Report : Time (s): cpu = 00:00:24 ; elapsed = 00:00:26 . Memory (MB): peak = 2204.219 ; gain = 618.086 ; free physical = 4334 ; free virtual = 31317
+Synthesis current peak Physical Memory [PSS] (MB): peak = 1493.366; parent = 1282.675; children = 211.354
+Synthesis current peak Virtual Memory [VSS] (MB): peak = 3174.680; parent = 2172.207; children = 1002.473
+---------------------------------------------------------------------------------
+Synthesis finished with 0 errors, 0 critical warnings and 1 warnings.
+Synthesis Optimization Runtime : Time (s): cpu = 00:00:22 ; elapsed = 00:00:24 . Memory (MB): peak = 2204.219 ; gain = 461.336 ; free physical = 4385 ; free virtual = 31367
+Synthesis Optimization Complete : Time (s): cpu = 00:00:24 ; elapsed = 00:00:26 . Memory (MB): peak = 2204.219 ; gain = 618.086 ; free physical = 4385 ; free virtual = 31367
+INFO: [Project 1-571] Translating synthesized netlist
+Netlist sorting complete. Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.01 . Memory (MB): peak = 2204.219 ; gain = 0.000 ; free physical = 4491 ; free virtual = 31474
+INFO: [Netlist 29-17] Analyzing 56 Unisim elements for replacement
+INFO: [Netlist 29-28] Unisim Transformation completed in 0 CPU seconds
+INFO: [Project 1-570] Preparing netlist for logic optimization
+INFO: [Opt 31-138] Pushed 0 inverter(s) to 0 load pin(s).
+Netlist sorting complete. Time (s): cpu = 00:00:00 ; elapsed = 00:00:00 . Memory (MB): peak = 2204.219 ; gain = 0.000 ; free physical = 4433 ; free virtual = 31416
+INFO: [Project 1-111] Unisim Transformation Summary:
+No Unisim elements were transformed.
+
+Synth Design complete, checksum: 66caa5c
+INFO: [Common 17-83] Releasing license: Synthesis
+48 Infos, 78 Warnings, 0 Critical Warnings and 0 Errors encountered.
+synth_design completed successfully
+synth_design: Time (s): cpu = 00:00:32 ; elapsed = 00:00:30 . Memory (MB): peak = 2204.219 ; gain = 879.715 ; free physical = 4651 ; free virtual = 31633
+INFO: [Common 17-1381] The checkpoint '/home/prasic/game/game.runs/synth_1/TopModule.dcp' has been generated.
+INFO: [runtcl-4] Executing : report_utilization -file TopModule_utilization_synth.rpt -pb TopModule_utilization_synth.pb
+INFO: [Common 17-206] Exiting Vivado at Tue Feb 28 17:01:35 2023...
diff --git a/game.runs/synth_1/TopModule_utilization_synth.pb b/game.runs/synth_1/TopModule_utilization_synth.pb
new file mode 100644
index 0000000000000000000000000000000000000000..5b3d30e2d3ae7dad73d0cce7b1e3898f7e08bd57
Binary files /dev/null and b/game.runs/synth_1/TopModule_utilization_synth.pb differ
diff --git a/game.runs/synth_1/TopModule_utilization_synth.rpt b/game.runs/synth_1/TopModule_utilization_synth.rpt
new file mode 100644
index 0000000000000000000000000000000000000000..86bec31c52da2e41edb3fcdaa62dba75dc66b4bf
--- /dev/null
+++ b/game.runs/synth_1/TopModule_utilization_synth.rpt
@@ -0,0 +1,184 @@
+Copyright 1986-2022 Xilinx, Inc. All Rights Reserved.
+-------------------------------------------------------------------------------------------------------------
+| Tool Version : Vivado v.2022.2 (lin64) Build 3671981 Fri Oct 14 04:59:54 MDT 2022
+| Date : Tue Feb 28 17:01:35 2023
+| Host : LikeUE06 running 64-bit Linux Mint 20.3
+| Command : report_utilization -file TopModule_utilization_synth.rpt -pb TopModule_utilization_synth.pb
+| Design : TopModule
+| Device : xc7a100tcsg324-1
+| Speed File : -1
+| Design State : Synthesized
+-------------------------------------------------------------------------------------------------------------
+
+Utilization Design Information
+
+Table of Contents
+-----------------
+1. Slice Logic
+1.1 Summary of Registers by Type
+2. Memory
+3. DSP
+4. IO and GT Specific
+5. Clocking
+6. Specific Feature
+7. Primitives
+8. Black Boxes
+9. Instantiated Netlists
+
+1. Slice Logic
+--------------
+
++-------------------------+------+-------+------------+-----------+-------+
+| Site Type | Used | Fixed | Prohibited | Available | Util% |
++-------------------------+------+-------+------------+-----------+-------+
+| Slice LUTs* | 326 | 0 | 0 | 63400 | 0.51 |
+| LUT as Logic | 326 | 0 | 0 | 63400 | 0.51 |
+| LUT as Memory | 0 | 0 | 0 | 19000 | 0.00 |
+| Slice Registers | 124 | 0 | 0 | 126800 | 0.10 |
+| Register as Flip Flop | 124 | 0 | 0 | 126800 | 0.10 |
+| Register as Latch | 0 | 0 | 0 | 126800 | 0.00 |
+| F7 Muxes | 0 | 0 | 0 | 31700 | 0.00 |
+| F8 Muxes | 0 | 0 | 0 | 15850 | 0.00 |
++-------------------------+------+-------+------------+-----------+-------+
+* Warning! The Final LUT count, after physical optimizations and full implementation, is typically lower. Run opt_design after synthesis, if not already completed, for a more realistic count.
+Warning! LUT value is adjusted to account for LUT combining.
+
+
+1.1 Summary of Registers by Type
+--------------------------------
+
++-------+--------------+-------------+--------------+
+| Total | Clock Enable | Synchronous | Asynchronous |
++-------+--------------+-------------+--------------+
+| 0 | _ | - | - |
+| 0 | _ | - | Set |
+| 0 | _ | - | Reset |
+| 0 | _ | Set | - |
+| 0 | _ | Reset | - |
+| 0 | Yes | - | - |
+| 10 | Yes | - | Set |
+| 73 | Yes | - | Reset |
+| 6 | Yes | Set | - |
+| 35 | Yes | Reset | - |
++-------+--------------+-------------+--------------+
+
+
+2. Memory
+---------
+
++----------------+------+-------+------------+-----------+-------+
+| Site Type | Used | Fixed | Prohibited | Available | Util% |
++----------------+------+-------+------------+-----------+-------+
+| Block RAM Tile | 0 | 0 | 0 | 135 | 0.00 |
+| RAMB36/FIFO* | 0 | 0 | 0 | 135 | 0.00 |
+| RAMB18 | 0 | 0 | 0 | 270 | 0.00 |
++----------------+------+-------+------------+-----------+-------+
+* Note: Each Block RAM Tile only has one FIFO logic available and therefore can accommodate only one FIFO36E1 or one FIFO18E1. However, if a FIFO18E1 occupies a Block RAM Tile, that tile can still accommodate a RAMB18E1
+
+
+3. DSP
+------
+
++-----------+------+-------+------------+-----------+-------+
+| Site Type | Used | Fixed | Prohibited | Available | Util% |
++-----------+------+-------+------------+-----------+-------+
+| DSPs | 0 | 0 | 0 | 240 | 0.00 |
++-----------+------+-------+------------+-----------+-------+
+
+
+4. IO and GT Specific
+---------------------
+
++-----------------------------+------+-------+------------+-----------+-------+
+| Site Type | Used | Fixed | Prohibited | Available | Util% |
++-----------------------------+------+-------+------------+-----------+-------+
+| Bonded IOB | 32 | 0 | 0 | 210 | 15.24 |
+| Bonded IPADs | 0 | 0 | 0 | 2 | 0.00 |
+| PHY_CONTROL | 0 | 0 | 0 | 6 | 0.00 |
+| PHASER_REF | 0 | 0 | 0 | 6 | 0.00 |
+| OUT_FIFO | 0 | 0 | 0 | 24 | 0.00 |
+| IN_FIFO | 0 | 0 | 0 | 24 | 0.00 |
+| IDELAYCTRL | 0 | 0 | 0 | 6 | 0.00 |
+| IBUFDS | 0 | 0 | 0 | 202 | 0.00 |
+| PHASER_OUT/PHASER_OUT_PHY | 0 | 0 | 0 | 24 | 0.00 |
+| PHASER_IN/PHASER_IN_PHY | 0 | 0 | 0 | 24 | 0.00 |
+| IDELAYE2/IDELAYE2_FINEDELAY | 0 | 0 | 0 | 300 | 0.00 |
+| ILOGIC | 0 | 0 | 0 | 210 | 0.00 |
+| OLOGIC | 0 | 0 | 0 | 210 | 0.00 |
++-----------------------------+------+-------+------------+-----------+-------+
+
+
+5. Clocking
+-----------
+
++------------+------+-------+------------+-----------+-------+
+| Site Type | Used | Fixed | Prohibited | Available | Util% |
++------------+------+-------+------------+-----------+-------+
+| BUFGCTRL | 0 | 0 | 0 | 32 | 0.00 |
+| BUFIO | 0 | 0 | 0 | 24 | 0.00 |
+| MMCME2_ADV | 0 | 0 | 0 | 6 | 0.00 |
+| PLLE2_ADV | 0 | 0 | 0 | 6 | 0.00 |
+| BUFMRCE | 0 | 0 | 0 | 12 | 0.00 |
+| BUFHCE | 0 | 0 | 0 | 96 | 0.00 |
+| BUFR | 0 | 0 | 0 | 24 | 0.00 |
++------------+------+-------+------------+-----------+-------+
+
+
+6. Specific Feature
+-------------------
+
++-------------+------+-------+------------+-----------+-------+
+| Site Type | Used | Fixed | Prohibited | Available | Util% |
++-------------+------+-------+------------+-----------+-------+
+| BSCANE2 | 0 | 0 | 0 | 4 | 0.00 |
+| CAPTUREE2 | 0 | 0 | 0 | 1 | 0.00 |
+| DNA_PORT | 0 | 0 | 0 | 1 | 0.00 |
+| EFUSE_USR | 0 | 0 | 0 | 1 | 0.00 |
+| FRAME_ECCE2 | 0 | 0 | 0 | 1 | 0.00 |
+| ICAPE2 | 0 | 0 | 0 | 2 | 0.00 |
+| PCIE_2_1 | 0 | 0 | 0 | 1 | 0.00 |
+| STARTUPE2 | 0 | 0 | 0 | 1 | 0.00 |
+| XADC | 0 | 0 | 0 | 1 | 0.00 |
++-------------+------+-------+------------+-----------+-------+
+
+
+7. Primitives
+-------------
+
++----------+------+---------------------+
+| Ref Name | Used | Functional Category |
++----------+------+---------------------+
+| LUT2 | 98 | LUT |
+| LUT6 | 88 | LUT |
+| LUT4 | 77 | LUT |
+| FDCE | 73 | Flop & Latch |
+| LUT3 | 64 | LUT |
+| CARRY4 | 56 | CarryLogic |
+| LUT5 | 51 | LUT |
+| LUT1 | 47 | LUT |
+| FDRE | 35 | Flop & Latch |
+| OBUF | 30 | IO |
+| FDPE | 10 | Flop & Latch |
+| FDSE | 6 | Flop & Latch |
+| IBUF | 2 | IO |
++----------+------+---------------------+
+
+
+8. Black Boxes
+--------------
+
++-----------+------+
+| Ref Name | Used |
++-----------+------+
+| clk_wiz_0 | 1 |
++-----------+------+
+
+
+9. Instantiated Netlists
+------------------------
+
++----------+------+
+| Ref Name | Used |
++----------+------+
+
+
diff --git a/game.runs/synth_1/__synthesis_is_complete__ b/game.runs/synth_1/__synthesis_is_complete__
new file mode 100644
index 0000000000000000000000000000000000000000..e69de29bb2d1d6434b8b29ae775ad8c2e48c5391
diff --git a/game.runs/synth_1/gen_run.xml b/game.runs/synth_1/gen_run.xml
new file mode 100644
index 0000000000000000000000000000000000000000..0a472337c1911782ba4e8501e7febe4fa81ad77c
--- /dev/null
+++ b/game.runs/synth_1/gen_run.xml
@@ -0,0 +1,115 @@
+<?xml version="1.0" encoding="UTF-8"?>
+<GenRun Id="synth_1" LaunchPart="xc7a100tcsg324-1" LaunchTime="1677600053" LaunchIncrCheckpoint="$PSRCDIR/utils_1/imports/synth_1/TopModule.dcp">
+ <File Type="VDS-TIMINGSUMMARY" Name="TopModule_timing_summary_synth.rpt"/>
+ <File Type="RDS-DCP" Name="TopModule.dcp"/>
+ <File Type="RDS-UTIL-PB" Name="TopModule_utilization_synth.pb"/>
+ <File Type="RDS-UTIL" Name="TopModule_utilization_synth.rpt"/>
+ <File Type="RDS-PROPCONSTRS" Name="TopModule_drc_synth.rpt"/>
+ <File Type="RDS-RDS" Name="TopModule.vds"/>
+ <File Type="REPORTS-TCL" Name="TopModule_reports.tcl"/>
+ <File Type="VDS-TIMING-PB" Name="TopModule_timing_summary_synth.pb"/>
+ <File Type="PA-TCL" Name="TopModule.tcl"/>
+ <FileSet Name="sources" Type="DesignSrcs" RelSrcDir="$PSRCDIR/sources_1" RelGenDir="$PGENDIR/sources_1">
+ <Filter Type="Srcs"/>
+ <File Path="$PSRCDIR/sources_1/new/header.vhd">
+ <FileInfo>
+ <Attr Name="UsedIn" Val="synthesis"/>
+ <Attr Name="UsedIn" Val="simulation"/>
+ </FileInfo>
+ </File>
+ <File Path="$PSRCDIR/sources_1/new/background.vhd">
+ <FileInfo>
+ <Attr Name="UsedIn" Val="synthesis"/>
+ <Attr Name="UsedIn" Val="simulation"/>
+ </FileInfo>
+ </File>
+ <File Path="$PSRCDIR/sources_1/new/collision.vhd">
+ <FileInfo>
+ <Attr Name="UsedIn" Val="synthesis"/>
+ <Attr Name="UsedIn" Val="simulation"/>
+ </FileInfo>
+ </File>
+ <File Path="$PSRCDIR/sources_1/new/obstacle.vhd">
+ <FileInfo>
+ <Attr Name="UsedIn" Val="synthesis"/>
+ <Attr Name="UsedIn" Val="simulation"/>
+ </FileInfo>
+ </File>
+ <File Path="$PSRCDIR/sources_1/new/obstacle2.vhd">
+ <FileInfo>
+ <Attr Name="UsedIn" Val="synthesis"/>
+ <Attr Name="UsedIn" Val="simulation"/>
+ </FileInfo>
+ </File>
+ <File Path="$PSRCDIR/sources_1/new/priority.vhd">
+ <FileInfo>
+ <Attr Name="UsedIn" Val="synthesis"/>
+ <Attr Name="UsedIn" Val="simulation"/>
+ </FileInfo>
+ </File>
+ <File Path="$PSRCDIR/sources_1/new/runner.vhd">
+ <FileInfo>
+ <Attr Name="UsedIn" Val="synthesis"/>
+ <Attr Name="UsedIn" Val="simulation"/>
+ </FileInfo>
+ </File>
+ <File Path="$PSRCDIR/sources_1/new/vga.vhd">
+ <FileInfo>
+ <Attr Name="UsedIn" Val="synthesis"/>
+ <Attr Name="UsedIn" Val="simulation"/>
+ </FileInfo>
+ </File>
+ <File Path="$PSRCDIR/sources_1/new/TopModule.vhd">
+ <FileInfo>
+ <Attr Name="UsedIn" Val="synthesis"/>
+ <Attr Name="UsedIn" Val="simulation"/>
+ </FileInfo>
+ </File>
+ <File Path="$PSRCDIR/sources_1/ip/clk_wiz_1/clk_wiz_1.xci">
+ <FileInfo>
+ <Attr Name="AutoDisabled" Val="1"/>
+ <Attr Name="UsedIn" Val="synthesis"/>
+ <Attr Name="UsedIn" Val="implementation"/>
+ <Attr Name="UsedIn" Val="simulation"/>
+ </FileInfo>
+ </File>
+ <Config>
+ <Option Name="DesignMode" Val="RTL"/>
+ <Option Name="TopModule" Val="TopModule"/>
+ <Option Name="TopAutoSet" Val="TRUE"/>
+ </Config>
+ </FileSet>
+ <FileSet Name="constrs_in" Type="Constrs" RelSrcDir="$PSRCDIR/constrs_1">
+ <Filter Type="Constrs"/>
+ <File Path="$PSRCDIR/constrs_1/imports/PrASIC_Data/Nexys4_Master.xdc">
+ <FileInfo>
+ <Attr Name="ImportPath" Val="$PPRDIR/../Schreibtisch/PrASIC_Data/Nexys4_Master.xdc"/>
+ <Attr Name="ImportTime" Val="1378293982"/>
+ <Attr Name="UsedIn" Val="synthesis"/>
+ <Attr Name="UsedIn" Val="implementation"/>
+ </FileInfo>
+ </File>
+ <Config>
+ <Option Name="ConstrsType" Val="XDC"/>
+ </Config>
+ </FileSet>
+ <FileSet Name="utils" Type="Utils" RelSrcDir="$PSRCDIR/utils_1">
+ <Filter Type="Utils"/>
+ <File Path="$PSRCDIR/utils_1/imports/synth_1/TopModule.dcp">
+ <FileInfo>
+ <Attr Name="UsedIn" Val="synthesis"/>
+ <Attr Name="UsedIn" Val="implementation"/>
+ <Attr Name="UsedInSteps" Val="synth_1"/>
+ <Attr Name="AutoDcp" Val="1"/>
+ </FileInfo>
+ </File>
+ <Config>
+ <Option Name="TopAutoSet" Val="TRUE"/>
+ </Config>
+ </FileSet>
+ <Strategy Version="1" Minor="2">
+ <StratHandle Name="Vivado Synthesis Defaults" Flow="Vivado Synthesis 2022"/>
+ <Step Id="synth_design"/>
+ </Strategy>
+ <BlockFileSet Type="BlockSrcs" Name="clk_wiz_0"/>
+</GenRun>
diff --git a/game.runs/synth_1/htr.txt b/game.runs/synth_1/htr.txt
new file mode 100644
index 0000000000000000000000000000000000000000..9db90aa28621c53dcc19c52c6e0d0e6c9a0f3810
--- /dev/null
+++ b/game.runs/synth_1/htr.txt
@@ -0,0 +1,9 @@
+#
+# Vivado(TM)
+# htr.txt: a Vivado-generated description of how-to-repeat the
+# the basic steps of a run. Note that runme.bat/sh needs
+# to be invoked for Vivado to track run status.
+# Copyright 1986-2022 Xilinx, Inc. All Rights Reserved.
+#
+
+vivado -log TopModule.vds -m64 -product Vivado -mode batch -messageDb vivado.pb -notrace -source TopModule.tcl
diff --git a/game.runs/synth_1/incr_synth_reason.pb b/game.runs/synth_1/incr_synth_reason.pb
new file mode 100644
index 0000000000000000000000000000000000000000..4cb4ed43e865edf4e8dcb3c9857bfe8acfc68b23
--- /dev/null
+++ b/game.runs/synth_1/incr_synth_reason.pb
@@ -0,0 +1 @@
+� 6No compile time benefit to using incremental synthesis
\ No newline at end of file
diff --git a/game.runs/synth_1/rundef.js b/game.runs/synth_1/rundef.js
new file mode 100644
index 0000000000000000000000000000000000000000..f1b61053de493acb61065c9d2eda77f24e2bff96
--- /dev/null
+++ b/game.runs/synth_1/rundef.js
@@ -0,0 +1,40 @@
+//
+// Vivado(TM)
+// rundef.js: a Vivado-generated Runs Script for WSH 5.1/5.6
+// Copyright 1986-2022 Xilinx, Inc. All Rights Reserved.
+//
+
+echo "This script was generated under a different operating system."
+echo "Please update the PATH variable below, before executing this script"
+exit
+
+var WshShell = new ActiveXObject( "WScript.Shell" );
+var ProcEnv = WshShell.Environment( "Process" );
+var PathVal = ProcEnv("PATH");
+if ( PathVal.length == 0 ) {
+ PathVal = "/opt/Xilinx/Vivado/2022.2/ids_lite/ISE/bin/lin64;/opt/Xilinx/Vivado/2022.2/bin;";
+} else {
+ PathVal = "/opt/Xilinx/Vivado/2022.2/ids_lite/ISE/bin/lin64;/opt/Xilinx/Vivado/2022.2/bin;" + PathVal;
+}
+
+ProcEnv("PATH") = PathVal;
+
+var RDScrFP = WScript.ScriptFullName;
+var RDScrN = WScript.ScriptName;
+var RDScrDir = RDScrFP.substr( 0, RDScrFP.length - RDScrN.length - 1 );
+var ISEJScriptLib = RDScrDir + "/ISEWrap.js";
+eval( EAInclude(ISEJScriptLib) );
+
+
+ISEStep( "vivado",
+ "-log TopModule.vds -m64 -product Vivado -mode batch -messageDb vivado.pb -notrace -source TopModule.tcl" );
+
+
+
+function EAInclude( EAInclFilename ) {
+ var EAFso = new ActiveXObject( "Scripting.FileSystemObject" );
+ var EAInclFile = EAFso.OpenTextFile( EAInclFilename );
+ var EAIFContents = EAInclFile.ReadAll();
+ EAInclFile.Close();
+ return EAIFContents;
+}
diff --git a/game.runs/synth_1/runme.bat b/game.runs/synth_1/runme.bat
new file mode 100644
index 0000000000000000000000000000000000000000..c51ae31743272e84250ece027d86207732473138
--- /dev/null
+++ b/game.runs/synth_1/runme.bat
@@ -0,0 +1,11 @@
+@echo off
+
+rem Vivado (TM)
+rem runme.bat: a Vivado-generated Script
+rem Copyright 1986-2022 Xilinx, Inc. All Rights Reserved.
+
+
+set HD_SDIR=%~dp0
+cd /d "%HD_SDIR%"
+set PATH=%SYSTEMROOT%\system32;%PATH%
+cscript /nologo /E:JScript "%HD_SDIR%\rundef.js" %*
diff --git a/game.runs/synth_1/runme.log b/game.runs/synth_1/runme.log
new file mode 100644
index 0000000000000000000000000000000000000000..ecec201354afbfa56c1d9054e55c0ec8c1e88052
--- /dev/null
+++ b/game.runs/synth_1/runme.log
@@ -0,0 +1,392 @@
+
+*** Running vivado
+ with args -log TopModule.vds -m64 -product Vivado -mode batch -messageDb vivado.pb -notrace -source TopModule.tcl
+
+
+****** Vivado v2022.2 (64-bit)
+ **** SW Build 3671981 on Fri Oct 14 04:59:54 MDT 2022
+ **** IP Build 3669848 on Fri Oct 14 08:30:02 MDT 2022
+ ** Copyright 1986-2022 Xilinx, Inc. All Rights Reserved.
+
+source TopModule.tcl -notrace
+Command: read_checkpoint -auto_incremental -incremental /home/prasic/game/game.srcs/utils_1/imports/synth_1/TopModule.dcp
+INFO: [Vivado 12-5825] Read reference checkpoint from /home/prasic/game/game.srcs/utils_1/imports/synth_1/TopModule.dcp for incremental synthesis
+INFO: [Vivado 12-7989] Please ensure there are no constraint changes
+Command: synth_design -top TopModule -part xc7a100tcsg324-1
+Starting synth_design
+Attempting to get a license for feature 'Synthesis' and/or device 'xc7a100t'
+INFO: [Common 17-349] Got license for feature 'Synthesis' and/or device 'xc7a100t'
+INFO: [Device 21-403] Loading part xc7a100tcsg324-1
+INFO: [Designutils 20-5440] No compile time benefit to using incremental synthesis; A full resynthesis will be run
+INFO: [Designutils 20-4379] Flow is switching to default flow due to incremental criteria not met. If you would like to alter this behaviour and have the flow terminate instead, please set the following parameter config_implementation {autoIncr.Synth.RejectBehavior Terminate}
+INFO: [Synth 8-7079] Multithreading enabled for synth_design using a maximum of 4 processes.
+INFO: [Synth 8-7078] Launching helper process for spawning children vivado processes
+INFO: [Synth 8-7075] Helper process launched with PID 238787
+INFO: [Synth 8-11241] undeclared symbol 'REGCCE', assumed default net type 'wire' [/opt/Xilinx/Vivado/2022.2/data/verilog/src/unimacro/BRAM_SINGLE_MACRO.v:2170]
+---------------------------------------------------------------------------------
+Starting RTL Elaboration : Time (s): cpu = 00:00:04 ; elapsed = 00:00:04 . Memory (MB): peak = 1958.719 ; gain = 372.586 ; free physical = 4425 ; free virtual = 31401
+Synthesis current peak Physical Memory [PSS] (MB): peak = 1387.041; parent = 1175.688; children = 211.354
+Synthesis current peak Virtual Memory [VSS] (MB): peak = 2964.164; parent = 1961.691; children = 1002.473
+---------------------------------------------------------------------------------
+INFO: [Synth 8-638] synthesizing module 'TopModule' [/home/prasic/game/game.srcs/sources_1/new/TopModule.vhd:46]
+INFO: [Synth 8-3491] module 'clk_wiz_0' declared at '/home/prasic/game/game.runs/synth_1/.Xil/Vivado-238750-LikeUE06/realtime/clk_wiz_0_stub.vhdl:5' bound to instance 'pixelClk' of component 'clk_wiz_0' [/home/prasic/game/game.srcs/sources_1/new/TopModule.vhd:167]
+INFO: [Synth 8-638] synthesizing module 'clk_wiz_0' [/home/prasic/game/game.runs/synth_1/.Xil/Vivado-238750-LikeUE06/realtime/clk_wiz_0_stub.vhdl:14]
+INFO: [Synth 8-3491] module 'vga' declared at '/home/prasic/game/game.srcs/sources_1/new/vga.vhd:34' bound to instance 'vgaInterface' of component 'vga' [/home/prasic/game/game.srcs/sources_1/new/TopModule.vhd:172]
+INFO: [Synth 8-638] synthesizing module 'vga' [/home/prasic/game/game.srcs/sources_1/new/vga.vhd:48]
+WARNING: [Synth 8-614] signal 'color' is read in the process but is not in the sensitivity list [/home/prasic/game/game.srcs/sources_1/new/vga.vhd:91]
+INFO: [Synth 8-256] done synthesizing module 'vga' (0#1) [/home/prasic/game/game.srcs/sources_1/new/vga.vhd:48]
+WARNING: [Synth 8-7043] port width mismatch for port 'FCounter': port width = 12, actual width = 16 (integer) [/home/prasic/game/game.srcs/sources_1/new/TopModule.vhd:65]
+INFO: [Synth 8-3491] module 'priority' declared at '/home/prasic/game/game.srcs/sources_1/new/priority.vhd:34' bound to instance 'priorityLogic' of component 'priority' [/home/prasic/game/game.srcs/sources_1/new/TopModule.vhd:188]
+INFO: [Synth 8-638] synthesizing module 'priority' [/home/prasic/game/game.srcs/sources_1/new/priority.vhd:48]
+WARNING: [Synth 8-614] signal 'color_runner' is read in the process but is not in the sensitivity list [/home/prasic/game/game.srcs/sources_1/new/priority.vhd:52]
+WARNING: [Synth 8-614] signal 'en_obstacleS' is read in the process but is not in the sensitivity list [/home/prasic/game/game.srcs/sources_1/new/priority.vhd:52]
+WARNING: [Synth 8-614] signal 'color_obstacleS' is read in the process but is not in the sensitivity list [/home/prasic/game/game.srcs/sources_1/new/priority.vhd:52]
+WARNING: [Synth 8-614] signal 'en_obstacleL' is read in the process but is not in the sensitivity list [/home/prasic/game/game.srcs/sources_1/new/priority.vhd:52]
+WARNING: [Synth 8-614] signal 'color_obstacleL' is read in the process but is not in the sensitivity list [/home/prasic/game/game.srcs/sources_1/new/priority.vhd:52]
+WARNING: [Synth 8-614] signal 'en_back' is read in the process but is not in the sensitivity list [/home/prasic/game/game.srcs/sources_1/new/priority.vhd:52]
+WARNING: [Synth 8-614] signal 'color_back' is read in the process but is not in the sensitivity list [/home/prasic/game/game.srcs/sources_1/new/priority.vhd:52]
+INFO: [Synth 8-256] done synthesizing module 'priority' (0#1) [/home/prasic/game/game.srcs/sources_1/new/priority.vhd:48]
+INFO: [Synth 8-3491] module 'runner' declared at '/home/prasic/game/game.srcs/sources_1/new/runner.vhd:36' bound to instance 'runnerObject' of component 'runner' [/home/prasic/game/game.srcs/sources_1/new/TopModule.vhd:201]
+INFO: [Synth 8-638] synthesizing module 'runner' [/home/prasic/game/game.srcs/sources_1/new/runner.vhd:50]
+WARNING: [Synth 8-614] signal 'pos_object_x_actual' is read in the process but is not in the sensitivity list [/home/prasic/game/game.srcs/sources_1/new/runner.vhd:73]
+WARNING: [Synth 8-614] signal 'pos_object_y_actual' is read in the process but is not in the sensitivity list [/home/prasic/game/game.srcs/sources_1/new/runner.vhd:73]
+WARNING: [Synth 8-614] signal 'btnCpuReset_r' is read in the process but is not in the sensitivity list [/home/prasic/game/game.srcs/sources_1/new/runner.vhd:85]
+INFO: [Synth 8-256] done synthesizing module 'runner' (0#1) [/home/prasic/game/game.srcs/sources_1/new/runner.vhd:50]
+INFO: [Synth 8-3491] module 'background' declared at '/home/prasic/game/game.srcs/sources_1/new/background.vhd:35' bound to instance 'backgroundObject' of component 'background' [/home/prasic/game/game.srcs/sources_1/new/TopModule.vhd:214]
+INFO: [Synth 8-638] synthesizing module 'background' [/home/prasic/game/game.srcs/sources_1/new/background.vhd:45]
+INFO: [Synth 8-256] done synthesizing module 'background' (0#1) [/home/prasic/game/game.srcs/sources_1/new/background.vhd:45]
+INFO: [Synth 8-3491] module 'obstacle_S' declared at '/home/prasic/game/game.srcs/sources_1/new/obstacle.vhd:36' bound to instance 'smallObstacle' of component 'obstacle_S' [/home/prasic/game/game.srcs/sources_1/new/TopModule.vhd:225]
+INFO: [Synth 8-638] synthesizing module 'obstacle_S' [/home/prasic/game/game.srcs/sources_1/new/obstacle.vhd:47]
+WARNING: [Synth 8-614] signal 'pos_object_x_actual' is read in the process but is not in the sensitivity list [/home/prasic/game/game.srcs/sources_1/new/obstacle.vhd:81]
+WARNING: [Synth 8-614] signal 'pos_object_y_actual' is read in the process but is not in the sensitivity list [/home/prasic/game/game.srcs/sources_1/new/obstacle.vhd:81]
+WARNING: [Synth 8-614] signal 'btnCpuReset_o' is read in the process but is not in the sensitivity list [/home/prasic/game/game.srcs/sources_1/new/obstacle.vhd:93]
+INFO: [Synth 8-256] done synthesizing module 'obstacle_S' (0#1) [/home/prasic/game/game.srcs/sources_1/new/obstacle.vhd:47]
+INFO: [Synth 8-3491] module 'obstacle_L' declared at '/home/prasic/game/game.srcs/sources_1/new/obstacle2.vhd:36' bound to instance 'largeObstacle' of component 'obstacle_L' [/home/prasic/game/game.srcs/sources_1/new/TopModule.vhd:235]
+INFO: [Synth 8-638] synthesizing module 'obstacle_L' [/home/prasic/game/game.srcs/sources_1/new/obstacle2.vhd:47]
+WARNING: [Synth 8-614] signal 'pos_object_x_actual' is read in the process but is not in the sensitivity list [/home/prasic/game/game.srcs/sources_1/new/obstacle2.vhd:81]
+WARNING: [Synth 8-614] signal 'pos_object_y_actual' is read in the process but is not in the sensitivity list [/home/prasic/game/game.srcs/sources_1/new/obstacle2.vhd:81]
+WARNING: [Synth 8-614] signal 'btnCpuReset_o' is read in the process but is not in the sensitivity list [/home/prasic/game/game.srcs/sources_1/new/obstacle2.vhd:93]
+INFO: [Synth 8-256] done synthesizing module 'obstacle_L' (0#1) [/home/prasic/game/game.srcs/sources_1/new/obstacle2.vhd:47]
+INFO: [Synth 8-3491] module 'collision' declared at '/home/prasic/game/game.srcs/sources_1/new/collision.vhd:34' bound to instance 'collisionDetection' of component 'collision' [/home/prasic/game/game.srcs/sources_1/new/TopModule.vhd:247]
+INFO: [Synth 8-638] synthesizing module 'collision' [/home/prasic/game/game.srcs/sources_1/new/collision.vhd:45]
+WARNING: [Synth 8-614] signal 'btnCpuReset_c' is read in the process but is not in the sensitivity list [/home/prasic/game/game.srcs/sources_1/new/collision.vhd:51]
+INFO: [Synth 8-256] done synthesizing module 'collision' (0#1) [/home/prasic/game/game.srcs/sources_1/new/collision.vhd:45]
+INFO: [Synth 8-256] done synthesizing module 'TopModule' (0#1) [/home/prasic/game/game.srcs/sources_1/new/TopModule.vhd:46]
+WARNING: [Synth 8-5863] Implementing Library version of Mod/Rem due to signed path. This typically leads to poor QOR. Check RTL to see if unsigned path for the operator is possible [/home/prasic/game/game.srcs/sources_1/new/runner.vhd:105]
+WARNING: [Synth 8-7129] Port FCounter_o[15] in module obstacle_L is either unconnected or has no load
+WARNING: [Synth 8-7129] Port FCounter_o[14] in module obstacle_L is either unconnected or has no load
+WARNING: [Synth 8-7129] Port FCounter_o[13] in module obstacle_L is either unconnected or has no load
+WARNING: [Synth 8-7129] Port FCounter_o[12] in module obstacle_L is either unconnected or has no load
+WARNING: [Synth 8-7129] Port FCounter_o[11] in module obstacle_L is either unconnected or has no load
+WARNING: [Synth 8-7129] Port FCounter_o[10] in module obstacle_L is either unconnected or has no load
+WARNING: [Synth 8-7129] Port FCounter_o[9] in module obstacle_L is either unconnected or has no load
+WARNING: [Synth 8-7129] Port FCounter_o[8] in module obstacle_L is either unconnected or has no load
+WARNING: [Synth 8-7129] Port FCounter_o[7] in module obstacle_L is either unconnected or has no load
+WARNING: [Synth 8-7129] Port FCounter_o[6] in module obstacle_L is either unconnected or has no load
+WARNING: [Synth 8-7129] Port FCounter_o[5] in module obstacle_L is either unconnected or has no load
+WARNING: [Synth 8-7129] Port FCounter_o[4] in module obstacle_L is either unconnected or has no load
+WARNING: [Synth 8-7129] Port FCounter_o[3] in module obstacle_L is either unconnected or has no load
+WARNING: [Synth 8-7129] Port FCounter_o[2] in module obstacle_L is either unconnected or has no load
+WARNING: [Synth 8-7129] Port FCounter_o[1] in module obstacle_L is either unconnected or has no load
+WARNING: [Synth 8-7129] Port FCounter_o[0] in module obstacle_L is either unconnected or has no load
+WARNING: [Synth 8-7129] Port FCounter_o[15] in module obstacle_S is either unconnected or has no load
+WARNING: [Synth 8-7129] Port FCounter_o[14] in module obstacle_S is either unconnected or has no load
+WARNING: [Synth 8-7129] Port FCounter_o[13] in module obstacle_S is either unconnected or has no load
+WARNING: [Synth 8-7129] Port FCounter_o[12] in module obstacle_S is either unconnected or has no load
+WARNING: [Synth 8-7129] Port FCounter_o[11] in module obstacle_S is either unconnected or has no load
+WARNING: [Synth 8-7129] Port FCounter_o[10] in module obstacle_S is either unconnected or has no load
+WARNING: [Synth 8-7129] Port FCounter_o[9] in module obstacle_S is either unconnected or has no load
+WARNING: [Synth 8-7129] Port FCounter_o[8] in module obstacle_S is either unconnected or has no load
+WARNING: [Synth 8-7129] Port FCounter_o[7] in module obstacle_S is either unconnected or has no load
+WARNING: [Synth 8-7129] Port FCounter_o[6] in module obstacle_S is either unconnected or has no load
+WARNING: [Synth 8-7129] Port FCounter_o[5] in module obstacle_S is either unconnected or has no load
+WARNING: [Synth 8-7129] Port FCounter_o[4] in module obstacle_S is either unconnected or has no load
+WARNING: [Synth 8-7129] Port FCounter_o[3] in module obstacle_S is either unconnected or has no load
+WARNING: [Synth 8-7129] Port FCounter_o[2] in module obstacle_S is either unconnected or has no load
+WARNING: [Synth 8-7129] Port FCounter_o[1] in module obstacle_S is either unconnected or has no load
+WARNING: [Synth 8-7129] Port FCounter_o[0] in module obstacle_S is either unconnected or has no load
+WARNING: [Synth 8-7129] Port clk_pixel in module background is either unconnected or has no load
+WARNING: [Synth 8-7129] Port btnCpuReset_b in module background is either unconnected or has no load
+WARNING: [Synth 8-7129] Port HCounter_b[9] in module background is either unconnected or has no load
+WARNING: [Synth 8-7129] Port HCounter_b[8] in module background is either unconnected or has no load
+WARNING: [Synth 8-7129] Port HCounter_b[7] in module background is either unconnected or has no load
+WARNING: [Synth 8-7129] Port HCounter_b[6] in module background is either unconnected or has no load
+WARNING: [Synth 8-7129] Port HCounter_b[5] in module background is either unconnected or has no load
+WARNING: [Synth 8-7129] Port HCounter_b[4] in module background is either unconnected or has no load
+WARNING: [Synth 8-7129] Port HCounter_b[3] in module background is either unconnected or has no load
+WARNING: [Synth 8-7129] Port HCounter_b[2] in module background is either unconnected or has no load
+WARNING: [Synth 8-7129] Port HCounter_b[1] in module background is either unconnected or has no load
+WARNING: [Synth 8-7129] Port HCounter_b[0] in module background is either unconnected or has no load
+WARNING: [Synth 8-7129] Port FCounter_b[11] in module background is either unconnected or has no load
+WARNING: [Synth 8-7129] Port FCounter_b[10] in module background is either unconnected or has no load
+WARNING: [Synth 8-7129] Port FCounter_b[9] in module background is either unconnected or has no load
+WARNING: [Synth 8-7129] Port FCounter_b[8] in module background is either unconnected or has no load
+WARNING: [Synth 8-7129] Port FCounter_b[7] in module background is either unconnected or has no load
+WARNING: [Synth 8-7129] Port FCounter_b[6] in module background is either unconnected or has no load
+WARNING: [Synth 8-7129] Port FCounter_b[5] in module background is either unconnected or has no load
+WARNING: [Synth 8-7129] Port FCounter_b[4] in module background is either unconnected or has no load
+WARNING: [Synth 8-7129] Port FCounter_b[3] in module background is either unconnected or has no load
+WARNING: [Synth 8-7129] Port FCounter_b[2] in module background is either unconnected or has no load
+WARNING: [Synth 8-7129] Port FCounter_b[1] in module background is either unconnected or has no load
+WARNING: [Synth 8-7129] Port FCounter_b[0] in module background is either unconnected or has no load
+WARNING: [Synth 8-7129] Port FStrobe_b in module background is either unconnected or has no load
+---------------------------------------------------------------------------------
+Finished RTL Elaboration : Time (s): cpu = 00:00:06 ; elapsed = 00:00:06 . Memory (MB): peak = 2029.656 ; gain = 443.523 ; free physical = 4516 ; free virtual = 31493
+Synthesis current peak Physical Memory [PSS] (MB): peak = 1387.041; parent = 1175.688; children = 211.354
+Synthesis current peak Virtual Memory [VSS] (MB): peak = 3032.133; parent = 2029.660; children = 1002.473
+---------------------------------------------------------------------------------
+---------------------------------------------------------------------------------
+Start Handling Custom Attributes
+---------------------------------------------------------------------------------
+---------------------------------------------------------------------------------
+Finished Handling Custom Attributes : Time (s): cpu = 00:00:06 ; elapsed = 00:00:06 . Memory (MB): peak = 2047.469 ; gain = 461.336 ; free physical = 4515 ; free virtual = 31493
+Synthesis current peak Physical Memory [PSS] (MB): peak = 1387.041; parent = 1175.688; children = 211.354
+Synthesis current peak Virtual Memory [VSS] (MB): peak = 3049.945; parent = 2047.473; children = 1002.473
+---------------------------------------------------------------------------------
+---------------------------------------------------------------------------------
+Finished RTL Optimization Phase 1 : Time (s): cpu = 00:00:06 ; elapsed = 00:00:06 . Memory (MB): peak = 2047.469 ; gain = 461.336 ; free physical = 4515 ; free virtual = 31493
+Synthesis current peak Physical Memory [PSS] (MB): peak = 1387.041; parent = 1175.688; children = 211.354
+Synthesis current peak Virtual Memory [VSS] (MB): peak = 3049.945; parent = 2047.473; children = 1002.473
+---------------------------------------------------------------------------------
+Netlist sorting complete. Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.01 . Memory (MB): peak = 2047.469 ; gain = 0.000 ; free physical = 4509 ; free virtual = 31486
+INFO: [Project 1-570] Preparing netlist for logic optimization
+
+Processing XDC Constraints
+Initializing timing engine
+Parsing XDC File [/home/prasic/game/game.gen/sources_1/ip/clk_wiz_0/clk_wiz_0/clk_wiz_0_in_context.xdc] for cell 'pixelClk'
+Finished Parsing XDC File [/home/prasic/game/game.gen/sources_1/ip/clk_wiz_0/clk_wiz_0/clk_wiz_0_in_context.xdc] for cell 'pixelClk'
+Parsing XDC File [/home/prasic/game/game.srcs/constrs_1/imports/PrASIC_Data/Nexys4_Master.xdc]
+Finished Parsing XDC File [/home/prasic/game/game.srcs/constrs_1/imports/PrASIC_Data/Nexys4_Master.xdc]
+INFO: [Project 1-236] Implementation specific constraints were found while reading constraint file [/home/prasic/game/game.srcs/constrs_1/imports/PrASIC_Data/Nexys4_Master.xdc]. These constraints will be ignored for synthesis but will be used in implementation. Impacted constraints are listed in the file [.Xil/TopModule_propImpl.xdc].
+Resolution: To avoid this warning, move constraints listed in [.Xil/TopModule_propImpl.xdc] to another XDC file and exclude this new file from synthesis with the used_in_synthesis property (File Properties dialog in GUI) and re-run elaboration/synthesis.
+Completed Processing XDC Constraints
+
+Netlist sorting complete. Time (s): cpu = 00:00:00 ; elapsed = 00:00:00 . Memory (MB): peak = 2204.219 ; gain = 0.000 ; free physical = 4423 ; free virtual = 31400
+INFO: [Project 1-111] Unisim Transformation Summary:
+No Unisim elements were transformed.
+
+Constraint Validation Runtime : Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.01 . Memory (MB): peak = 2204.219 ; gain = 0.000 ; free physical = 4423 ; free virtual = 31400
+INFO: [Designutils 20-5440] No compile time benefit to using incremental synthesis; A full resynthesis will be run
+INFO: [Designutils 20-4379] Flow is switching to default flow due to incremental criteria not met. If you would like to alter this behaviour and have the flow terminate instead, please set the following parameter config_implementation {autoIncr.Synth.RejectBehavior Terminate}
+INFO: [Synth 8-11241] undeclared symbol 'REGCCE', assumed default net type 'wire' [/opt/Xilinx/Vivado/2022.2/data/verilog/src/unimacro/BRAM_SINGLE_MACRO.v:2170]
+---------------------------------------------------------------------------------
+Finished Constraint Validation : Time (s): cpu = 00:00:12 ; elapsed = 00:00:13 . Memory (MB): peak = 2204.219 ; gain = 618.086 ; free physical = 4489 ; free virtual = 31466
+Synthesis current peak Physical Memory [PSS] (MB): peak = 1387.041; parent = 1175.688; children = 211.354
+Synthesis current peak Virtual Memory [VSS] (MB): peak = 3174.680; parent = 2172.207; children = 1002.473
+---------------------------------------------------------------------------------
+---------------------------------------------------------------------------------
+Start Loading Part and Timing Information
+---------------------------------------------------------------------------------
+Loading part: xc7a100tcsg324-1
+---------------------------------------------------------------------------------
+Finished Loading Part and Timing Information : Time (s): cpu = 00:00:12 ; elapsed = 00:00:13 . Memory (MB): peak = 2204.219 ; gain = 618.086 ; free physical = 4489 ; free virtual = 31466
+Synthesis current peak Physical Memory [PSS] (MB): peak = 1387.041; parent = 1175.688; children = 211.354
+Synthesis current peak Virtual Memory [VSS] (MB): peak = 3174.680; parent = 2172.207; children = 1002.473
+---------------------------------------------------------------------------------
+---------------------------------------------------------------------------------
+Start Applying 'set_property' XDC Constraints
+---------------------------------------------------------------------------------
+Applied set_property IO_BUFFER_TYPE = NONE for clk. (constraint file /home/prasic/game/game.gen/sources_1/ip/clk_wiz_0/clk_wiz_0/clk_wiz_0_in_context.xdc, line 3).
+Applied set_property CLOCK_BUFFER_TYPE = NONE for clk. (constraint file /home/prasic/game/game.gen/sources_1/ip/clk_wiz_0/clk_wiz_0/clk_wiz_0_in_context.xdc, line 4).
+Applied set_property KEEP_HIERARCHY = SOFT for pixelClk. (constraint file auto generated constraint).
+---------------------------------------------------------------------------------
+Finished applying 'set_property' XDC Constraints : Time (s): cpu = 00:00:12 ; elapsed = 00:00:13 . Memory (MB): peak = 2204.219 ; gain = 618.086 ; free physical = 4489 ; free virtual = 31466
+Synthesis current peak Physical Memory [PSS] (MB): peak = 1387.041; parent = 1175.688; children = 211.354
+Synthesis current peak Virtual Memory [VSS] (MB): peak = 3174.680; parent = 2172.207; children = 1002.473
+---------------------------------------------------------------------------------
+---------------------------------------------------------------------------------
+Finished RTL Optimization Phase 2 : Time (s): cpu = 00:00:12 ; elapsed = 00:00:13 . Memory (MB): peak = 2204.219 ; gain = 618.086 ; free physical = 4480 ; free virtual = 31458
+Synthesis current peak Physical Memory [PSS] (MB): peak = 1387.041; parent = 1175.688; children = 211.354
+Synthesis current peak Virtual Memory [VSS] (MB): peak = 3174.680; parent = 2172.207; children = 1002.473
+---------------------------------------------------------------------------------
+---------------------------------------------------------------------------------
+Start RTL Component Statistics
+---------------------------------------------------------------------------------
+Detailed RTL Component Info :
++---Adders :
+ 3 Input 33 Bit Adders := 3
+ 2 Input 20 Bit Adders := 1
+ 2 Input 18 Bit Adders := 1
+ 3 Input 17 Bit Adders := 1
+ 2 Input 17 Bit Adders := 1
+ 2 Input 16 Bit Adders := 1
+ 2 Input 11 Bit Adders := 5
+ 2 Input 10 Bit Adders := 5
+ 2 Input 9 Bit Adders := 2
++---Registers :
+ 16 Bit Registers := 2
+ 11 Bit Registers := 2
+ 10 Bit Registers := 5
+ 9 Bit Registers := 4
+ 2 Bit Registers := 1
+ 1 Bit Registers := 1
++---Muxes :
+ 2 Input 18 Bit Muxes := 4
+ 2 Input 17 Bit Muxes := 1
+ 2 Input 16 Bit Muxes := 1
+ 2 Input 11 Bit Muxes := 3
+ 2 Input 10 Bit Muxes := 2
+ 2 Input 9 Bit Muxes := 1
+ 2 Input 4 Bit Muxes := 9
+ 2 Input 1 Bit Muxes := 1
+---------------------------------------------------------------------------------
+Finished RTL Component Statistics
+---------------------------------------------------------------------------------
+---------------------------------------------------------------------------------
+Start Part Resource Summary
+---------------------------------------------------------------------------------
+Part Resources:
+DSPs: 240 (col length:80)
+BRAMs: 270 (col length: RAMB18 80 RAMB36 40)
+---------------------------------------------------------------------------------
+Finished Part Resource Summary
+---------------------------------------------------------------------------------
+---------------------------------------------------------------------------------
+Start Cross Boundary and Area Optimization
+---------------------------------------------------------------------------------
+WARNING: [Synth 8-7080] Parallel synthesis criteria is not met
+---------------------------------------------------------------------------------
+Finished Cross Boundary and Area Optimization : Time (s): cpu = 00:00:14 ; elapsed = 00:00:15 . Memory (MB): peak = 2204.219 ; gain = 618.086 ; free physical = 4462 ; free virtual = 31445
+Synthesis current peak Physical Memory [PSS] (MB): peak = 1387.041; parent = 1175.688; children = 211.354
+Synthesis current peak Virtual Memory [VSS] (MB): peak = 3174.680; parent = 2172.207; children = 1002.473
+---------------------------------------------------------------------------------
+---------------------------------------------------------------------------------
+Start Applying XDC Timing Constraints
+---------------------------------------------------------------------------------
+---------------------------------------------------------------------------------
+Finished Applying XDC Timing Constraints : Time (s): cpu = 00:00:19 ; elapsed = 00:00:20 . Memory (MB): peak = 2204.219 ; gain = 618.086 ; free physical = 4343 ; free virtual = 31325
+Synthesis current peak Physical Memory [PSS] (MB): peak = 1483.411; parent = 1272.714; children = 211.354
+Synthesis current peak Virtual Memory [VSS] (MB): peak = 3174.680; parent = 2172.207; children = 1002.473
+---------------------------------------------------------------------------------
+---------------------------------------------------------------------------------
+Start Timing Optimization
+---------------------------------------------------------------------------------
+---------------------------------------------------------------------------------
+Finished Timing Optimization : Time (s): cpu = 00:00:20 ; elapsed = 00:00:22 . Memory (MB): peak = 2204.219 ; gain = 618.086 ; free physical = 4333 ; free virtual = 31315
+Synthesis current peak Physical Memory [PSS] (MB): peak = 1493.198; parent = 1282.507; children = 211.354
+Synthesis current peak Virtual Memory [VSS] (MB): peak = 3174.680; parent = 2172.207; children = 1002.473
+---------------------------------------------------------------------------------
+---------------------------------------------------------------------------------
+Start Technology Mapping
+---------------------------------------------------------------------------------
+---------------------------------------------------------------------------------
+Finished Technology Mapping : Time (s): cpu = 00:00:21 ; elapsed = 00:00:22 . Memory (MB): peak = 2204.219 ; gain = 618.086 ; free physical = 4332 ; free virtual = 31315
+Synthesis current peak Physical Memory [PSS] (MB): peak = 1493.198; parent = 1282.507; children = 211.354
+Synthesis current peak Virtual Memory [VSS] (MB): peak = 3174.680; parent = 2172.207; children = 1002.473
+---------------------------------------------------------------------------------
+---------------------------------------------------------------------------------
+Start IO Insertion
+---------------------------------------------------------------------------------
+---------------------------------------------------------------------------------
+Start Flattening Before IO Insertion
+---------------------------------------------------------------------------------
+---------------------------------------------------------------------------------
+Finished Flattening Before IO Insertion
+---------------------------------------------------------------------------------
+---------------------------------------------------------------------------------
+Start Final Netlist Cleanup
+---------------------------------------------------------------------------------
+---------------------------------------------------------------------------------
+Finished Final Netlist Cleanup
+---------------------------------------------------------------------------------
+---------------------------------------------------------------------------------
+Finished IO Insertion : Time (s): cpu = 00:00:24 ; elapsed = 00:00:25 . Memory (MB): peak = 2204.219 ; gain = 618.086 ; free physical = 4334 ; free virtual = 31316
+Synthesis current peak Physical Memory [PSS] (MB): peak = 1493.366; parent = 1282.675; children = 211.354
+Synthesis current peak Virtual Memory [VSS] (MB): peak = 3174.680; parent = 2172.207; children = 1002.473
+---------------------------------------------------------------------------------
+---------------------------------------------------------------------------------
+Start Renaming Generated Instances
+---------------------------------------------------------------------------------
+---------------------------------------------------------------------------------
+Finished Renaming Generated Instances : Time (s): cpu = 00:00:24 ; elapsed = 00:00:25 . Memory (MB): peak = 2204.219 ; gain = 618.086 ; free physical = 4334 ; free virtual = 31316
+Synthesis current peak Physical Memory [PSS] (MB): peak = 1493.366; parent = 1282.675; children = 211.354
+Synthesis current peak Virtual Memory [VSS] (MB): peak = 3174.680; parent = 2172.207; children = 1002.473
+---------------------------------------------------------------------------------
+---------------------------------------------------------------------------------
+Start Rebuilding User Hierarchy
+---------------------------------------------------------------------------------
+---------------------------------------------------------------------------------
+Finished Rebuilding User Hierarchy : Time (s): cpu = 00:00:24 ; elapsed = 00:00:25 . Memory (MB): peak = 2204.219 ; gain = 618.086 ; free physical = 4334 ; free virtual = 31316
+Synthesis current peak Physical Memory [PSS] (MB): peak = 1493.366; parent = 1282.675; children = 211.354
+Synthesis current peak Virtual Memory [VSS] (MB): peak = 3174.680; parent = 2172.207; children = 1002.473
+---------------------------------------------------------------------------------
+---------------------------------------------------------------------------------
+Start Renaming Generated Ports
+---------------------------------------------------------------------------------
+---------------------------------------------------------------------------------
+Finished Renaming Generated Ports : Time (s): cpu = 00:00:24 ; elapsed = 00:00:25 . Memory (MB): peak = 2204.219 ; gain = 618.086 ; free physical = 4334 ; free virtual = 31317
+Synthesis current peak Physical Memory [PSS] (MB): peak = 1493.366; parent = 1282.675; children = 211.354
+Synthesis current peak Virtual Memory [VSS] (MB): peak = 3174.680; parent = 2172.207; children = 1002.473
+---------------------------------------------------------------------------------
+---------------------------------------------------------------------------------
+Start Handling Custom Attributes
+---------------------------------------------------------------------------------
+---------------------------------------------------------------------------------
+Finished Handling Custom Attributes : Time (s): cpu = 00:00:24 ; elapsed = 00:00:25 . Memory (MB): peak = 2204.219 ; gain = 618.086 ; free physical = 4334 ; free virtual = 31317
+Synthesis current peak Physical Memory [PSS] (MB): peak = 1493.366; parent = 1282.675; children = 211.354
+Synthesis current peak Virtual Memory [VSS] (MB): peak = 3174.680; parent = 2172.207; children = 1002.473
+---------------------------------------------------------------------------------
+---------------------------------------------------------------------------------
+Start Renaming Generated Nets
+---------------------------------------------------------------------------------
+---------------------------------------------------------------------------------
+Finished Renaming Generated Nets : Time (s): cpu = 00:00:24 ; elapsed = 00:00:25 . Memory (MB): peak = 2204.219 ; gain = 618.086 ; free physical = 4334 ; free virtual = 31317
+Synthesis current peak Physical Memory [PSS] (MB): peak = 1493.366; parent = 1282.675; children = 211.354
+Synthesis current peak Virtual Memory [VSS] (MB): peak = 3174.680; parent = 2172.207; children = 1002.473
+---------------------------------------------------------------------------------
+---------------------------------------------------------------------------------
+Start Writing Synthesis Report
+---------------------------------------------------------------------------------
+
+Report BlackBoxes:
++------+--------------+----------+
+| |BlackBox name |Instances |
++------+--------------+----------+
+|1 |clk_wiz_0 | 1|
++------+--------------+----------+
+
+Report Cell Usage:
++------+---------------+------+
+| |Cell |Count |
++------+---------------+------+
+|1 |clk_wiz_0_bbox | 1|
+|2 |CARRY4 | 56|
+|3 |LUT1 | 47|
+|4 |LUT2 | 98|
+|5 |LUT3 | 64|
+|6 |LUT4 | 77|
+|7 |LUT5 | 51|
+|8 |LUT6 | 88|
+|9 |FDCE | 73|
+|10 |FDPE | 10|
+|11 |FDRE | 35|
+|12 |FDSE | 6|
+|13 |IBUF | 2|
+|14 |OBUF | 30|
++------+---------------+------+
+---------------------------------------------------------------------------------
+Finished Writing Synthesis Report : Time (s): cpu = 00:00:24 ; elapsed = 00:00:26 . Memory (MB): peak = 2204.219 ; gain = 618.086 ; free physical = 4334 ; free virtual = 31317
+Synthesis current peak Physical Memory [PSS] (MB): peak = 1493.366; parent = 1282.675; children = 211.354
+Synthesis current peak Virtual Memory [VSS] (MB): peak = 3174.680; parent = 2172.207; children = 1002.473
+---------------------------------------------------------------------------------
+Synthesis finished with 0 errors, 0 critical warnings and 1 warnings.
+Synthesis Optimization Runtime : Time (s): cpu = 00:00:22 ; elapsed = 00:00:24 . Memory (MB): peak = 2204.219 ; gain = 461.336 ; free physical = 4385 ; free virtual = 31367
+Synthesis Optimization Complete : Time (s): cpu = 00:00:24 ; elapsed = 00:00:26 . Memory (MB): peak = 2204.219 ; gain = 618.086 ; free physical = 4385 ; free virtual = 31367
+INFO: [Project 1-571] Translating synthesized netlist
+Netlist sorting complete. Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.01 . Memory (MB): peak = 2204.219 ; gain = 0.000 ; free physical = 4491 ; free virtual = 31474
+INFO: [Netlist 29-17] Analyzing 56 Unisim elements for replacement
+INFO: [Netlist 29-28] Unisim Transformation completed in 0 CPU seconds
+INFO: [Project 1-570] Preparing netlist for logic optimization
+INFO: [Opt 31-138] Pushed 0 inverter(s) to 0 load pin(s).
+Netlist sorting complete. Time (s): cpu = 00:00:00 ; elapsed = 00:00:00 . Memory (MB): peak = 2204.219 ; gain = 0.000 ; free physical = 4433 ; free virtual = 31416
+INFO: [Project 1-111] Unisim Transformation Summary:
+No Unisim elements were transformed.
+
+Synth Design complete, checksum: 66caa5c
+INFO: [Common 17-83] Releasing license: Synthesis
+48 Infos, 78 Warnings, 0 Critical Warnings and 0 Errors encountered.
+synth_design completed successfully
+synth_design: Time (s): cpu = 00:00:32 ; elapsed = 00:00:30 . Memory (MB): peak = 2204.219 ; gain = 879.715 ; free physical = 4651 ; free virtual = 31633
+INFO: [Common 17-1381] The checkpoint '/home/prasic/game/game.runs/synth_1/TopModule.dcp' has been generated.
+INFO: [runtcl-4] Executing : report_utilization -file TopModule_utilization_synth.rpt -pb TopModule_utilization_synth.pb
+INFO: [Common 17-206] Exiting Vivado at Tue Feb 28 17:01:35 2023...
diff --git a/game.runs/synth_1/runme.sh b/game.runs/synth_1/runme.sh
new file mode 100755
index 0000000000000000000000000000000000000000..659a555440317370e89795fab5d3d311d0c88ed4
--- /dev/null
+++ b/game.runs/synth_1/runme.sh
@@ -0,0 +1,39 @@
+#!/bin/sh
+
+#
+# Vivado(TM)
+# runme.sh: a Vivado-generated Runs Script for UNIX
+# Copyright 1986-2022 Xilinx, Inc. All Rights Reserved.
+#
+
+if [ -z "$PATH" ]; then
+ PATH=/opt/Xilinx/Vivado/2022.2/ids_lite/ISE/bin/lin64:/opt/Xilinx/Vivado/2022.2/bin
+else
+ PATH=/opt/Xilinx/Vivado/2022.2/ids_lite/ISE/bin/lin64:/opt/Xilinx/Vivado/2022.2/bin:$PATH
+fi
+export PATH
+
+if [ -z "$LD_LIBRARY_PATH" ]; then
+ LD_LIBRARY_PATH=
+else
+ LD_LIBRARY_PATH=:$LD_LIBRARY_PATH
+fi
+export LD_LIBRARY_PATH
+
+HD_PWD='/home/prasic/game/game.runs/synth_1'
+cd "$HD_PWD"
+
+HD_LOG=runme.log
+/bin/touch $HD_LOG
+
+ISEStep="./ISEWrap.sh"
+EAStep()
+{
+ $ISEStep $HD_LOG "$@" >> $HD_LOG 2>&1
+ if [ $? -ne 0 ]
+ then
+ exit
+ fi
+}
+
+EAStep vivado -log TopModule.vds -m64 -product Vivado -mode batch -messageDb vivado.pb -notrace -source TopModule.tcl
diff --git a/game.runs/synth_1/vivado.jou b/game.runs/synth_1/vivado.jou
new file mode 100644
index 0000000000000000000000000000000000000000..2fb91f7ec2bf3a3bc37be48400023c7123e4c0e4
--- /dev/null
+++ b/game.runs/synth_1/vivado.jou
@@ -0,0 +1,13 @@
+#-----------------------------------------------------------
+# Vivado v2022.2 (64-bit)
+# SW Build 3671981 on Fri Oct 14 04:59:54 MDT 2022
+# IP Build 3669848 on Fri Oct 14 08:30:02 MDT 2022
+# Start of session at: Tue Feb 28 17:00:56 2023
+# Process ID: 238750
+# Current directory: /home/prasic/game/game.runs/synth_1
+# Command line: vivado -log TopModule.vds -product Vivado -mode batch -messageDb vivado.pb -notrace -source TopModule.tcl
+# Log file: /home/prasic/game/game.runs/synth_1/TopModule.vds
+# Journal file: /home/prasic/game/game.runs/synth_1/vivado.jou
+# Running On: LikeUE06, OS: Linux, CPU Frequency: 2482.416 MHz, CPU Physical cores: 4, Host memory: 16699 MB
+#-----------------------------------------------------------
+source TopModule.tcl -notrace
diff --git a/game.runs/synth_1/vivado.pb b/game.runs/synth_1/vivado.pb
new file mode 100644
index 0000000000000000000000000000000000000000..8db73f0c0f643056e4176a55cf095e6e7b69bca4
Binary files /dev/null and b/game.runs/synth_1/vivado.pb differ
diff --git a/game.sim/sim_1/behav/xsim/TopModule_tb.tcl b/game.sim/sim_1/behav/xsim/TopModule_tb.tcl
new file mode 100644
index 0000000000000000000000000000000000000000..1094e45dcf2527b60296acfc006fb85a3e752cba
--- /dev/null
+++ b/game.sim/sim_1/behav/xsim/TopModule_tb.tcl
@@ -0,0 +1,11 @@
+set curr_wave [current_wave_config]
+if { [string length $curr_wave] == 0 } {
+ if { [llength [get_objects]] > 0} {
+ add_wave /
+ set_property needs_save false [current_wave_config]
+ } else {
+ send_msg_id Add_Wave-1 WARNING "No top level signals found. Simulator will start without a wave window. If you want to open a wave window go to 'File->New Waveform Configuration' or type 'create_wave_config' in the TCL console."
+ }
+}
+
+run 1000ns
diff --git a/game.sim/sim_1/behav/xsim/TopModule_tb_behav.wdb b/game.sim/sim_1/behav/xsim/TopModule_tb_behav.wdb
new file mode 100644
index 0000000000000000000000000000000000000000..fc35bd39176e60cb146bb74e7d823fe867240cc3
Binary files /dev/null and b/game.sim/sim_1/behav/xsim/TopModule_tb_behav.wdb differ
diff --git a/game.sim/sim_1/behav/xsim/TopModule_tb_vhdl.prj b/game.sim/sim_1/behav/xsim/TopModule_tb_vhdl.prj
new file mode 100644
index 0000000000000000000000000000000000000000..07ee4b6f52c4799bc81646e8138d68011b09a2c7
--- /dev/null
+++ b/game.sim/sim_1/behav/xsim/TopModule_tb_vhdl.prj
@@ -0,0 +1,12 @@
+# compile vhdl design source files
+vhdl xil_defaultlib \
+"../../../../game.gen/sources_1/ip/clk_wiz_0/clk_wiz_0_sim_netlist.vhdl" \
+"../../../../game.srcs/sources_1/new/TopModule.vhd" \
+"../../../../game.srcs/sources_1/new/background.vhd" \
+"../../../../game.srcs/sources_1/new/priority.vhd" \
+"../../../../game.srcs/sources_1/new/runner.vhd" \
+"../../../../game.srcs/sources_1/new/vga.vhd" \
+"../../../../game.srcs/sim_1/new/TopModule_tb.vhd" \
+
+# Do not sort compile order
+nosort
diff --git a/game.sim/sim_1/behav/xsim/TopModule_tb_vlog.prj b/game.sim/sim_1/behav/xsim/TopModule_tb_vlog.prj
new file mode 100644
index 0000000000000000000000000000000000000000..76b7b44dc43d8c2ac4225817062df62fde72e7e5
--- /dev/null
+++ b/game.sim/sim_1/behav/xsim/TopModule_tb_vlog.prj
@@ -0,0 +1,7 @@
+# compile verilog/system verilog design source files
+
+# compile glbl module
+verilog xil_defaultlib "glbl.v"
+
+# Do not sort compile order
+nosort
diff --git a/game.sim/sim_1/behav/xsim/compile.log b/game.sim/sim_1/behav/xsim/compile.log
new file mode 100644
index 0000000000000000000000000000000000000000..1b4ecdab156140987e6dbd0399e74d458aeff7ef
--- /dev/null
+++ b/game.sim/sim_1/behav/xsim/compile.log
@@ -0,0 +1,2 @@
+INFO: [VRFC 10-163] Analyzing VHDL file "/home/prasic/game/game.srcs/sources_1/new/runner.vhd" into library xil_defaultlib
+INFO: [VRFC 10-3107] analyzing entity 'runner'
diff --git a/game.sim/sim_1/behav/xsim/compile.sh b/game.sim/sim_1/behav/xsim/compile.sh
new file mode 100755
index 0000000000000000000000000000000000000000..f5df86184947b5621850ec4e804bf3a8595bf850
--- /dev/null
+++ b/game.sim/sim_1/behav/xsim/compile.sh
@@ -0,0 +1,27 @@
+#!/bin/bash -f
+# ****************************************************************************
+# Vivado (TM) v2022.2 (64-bit)
+#
+# Filename : compile.sh
+# Simulator : Xilinx Vivado Simulator
+# Description : Script for compiling the simulation design source files
+#
+# Generated by Vivado on Tue Feb 28 13:01:27 CET 2023
+# SW Build 3671981 on Fri Oct 14 04:59:54 MDT 2022
+#
+# IP Build 3669848 on Fri Oct 14 08:30:02 MDT 2022
+#
+# usage: compile.sh
+#
+# ****************************************************************************
+set -Eeuo pipefail
+# compile Verilog/System Verilog design sources
+echo "xvlog --incr --relax -prj TopModule_tb_vlog.prj"
+xvlog --incr --relax -prj TopModule_tb_vlog.prj 2>&1 | tee compile.log
+
+# compile VHDL design sources
+echo "xvhdl --incr --relax -prj TopModule_tb_vhdl.prj"
+xvhdl --incr --relax -prj TopModule_tb_vhdl.prj 2>&1 | tee -a compile.log
+
+echo "Waiting for jobs to finish..."
+echo "No pending jobs, compilation finished."
diff --git a/game.sim/sim_1/behav/xsim/elaborate.log b/game.sim/sim_1/behav/xsim/elaborate.log
new file mode 100644
index 0000000000000000000000000000000000000000..2d6449717d0ab18e277cb401729a8a2d93b76aaa
--- /dev/null
+++ b/game.sim/sim_1/behav/xsim/elaborate.log
@@ -0,0 +1,34 @@
+Vivado Simulator v2022.2
+Copyright 1986-1999, 2001-2022 Xilinx, Inc. All Rights Reserved.
+Running: /opt/Xilinx/Vivado/2022.2/bin/unwrapped/lnx64.o/xelab --incr --debug typical --relax --mt 8 -L xil_defaultlib -L unisims_ver -L unimacro_ver -L secureip -L xpm --snapshot TopModule_tb_behav xil_defaultlib.TopModule_tb xil_defaultlib.glbl -log elaborate.log
+Using 8 slave threads.
+Starting static elaboration
+Pass Through NonSizing Optimizer
+Completed static elaboration
+Starting simulation data flow analysis
+Completed simulation data flow analysis
+Time Resolution for simulation is 1ps
+Compiling package std.standard
+Compiling package std.textio
+Compiling package ieee.std_logic_1164
+Compiling package ieee.numeric_std
+Compiling package unisim.vcomponents
+Compiling package ieee.std_logic_arith
+Compiling package ieee.std_logic_signed
+Compiling package ieee.vital_timing
+Compiling package ieee.vital_primitives
+Compiling package unisim.vpkg
+Compiling module xil_defaultlib.glbl
+Compiling architecture bufg_v of entity unisim.BUFG [bufg_default]
+Compiling architecture ibuf_v of entity unisim.IBUF [\IBUF(1,4)(1,9)(1,1)(1,4)(1,7)\]
+Compiling architecture mmcme2_adv_v of entity unisim.MMCME2_ADV [\MMCME2_ADV(clkfbout_mult_f=9.12...]
+Compiling architecture lut1_v of entity unisim.LUT1 [\LUT1(init="0001")(0,3)\]
+Compiling architecture structure of entity xil_defaultlib.clk_wiz_0_clk_wiz [clk_wiz_0_clk_wiz_default]
+Compiling architecture structure of entity xil_defaultlib.clk_wiz_0 [clk_wiz_0_default]
+Compiling architecture behavioral of entity xil_defaultlib.vga [vga_default]
+Compiling architecture behavioral of entity xil_defaultlib.priority [priority_default]
+Compiling architecture behavioral of entity xil_defaultlib.runner [runner_default]
+Compiling architecture behavioral of entity xil_defaultlib.background [background_default]
+Compiling architecture behavioral of entity xil_defaultlib.TopModule [topmodule_default]
+Compiling architecture test of entity xil_defaultlib.topmodule_tb
+Built simulation snapshot TopModule_tb_behav
diff --git a/game.sim/sim_1/behav/xsim/elaborate.sh b/game.sim/sim_1/behav/xsim/elaborate.sh
new file mode 100755
index 0000000000000000000000000000000000000000..a657024b0916e4f26b0a9746c6929456e34b06c0
--- /dev/null
+++ b/game.sim/sim_1/behav/xsim/elaborate.sh
@@ -0,0 +1,21 @@
+#!/bin/bash -f
+# ****************************************************************************
+# Vivado (TM) v2022.2 (64-bit)
+#
+# Filename : elaborate.sh
+# Simulator : Xilinx Vivado Simulator
+# Description : Script for elaborating the compiled design
+#
+# Generated by Vivado on Tue Feb 28 13:01:30 CET 2023
+# SW Build 3671981 on Fri Oct 14 04:59:54 MDT 2022
+#
+# IP Build 3669848 on Fri Oct 14 08:30:02 MDT 2022
+#
+# usage: elaborate.sh
+#
+# ****************************************************************************
+set -Eeuo pipefail
+# elaborate design
+echo "xelab --incr --debug typical --relax --mt 8 -L xil_defaultlib -L unisims_ver -L unimacro_ver -L secureip -L xpm --snapshot TopModule_tb_behav xil_defaultlib.TopModule_tb xil_defaultlib.glbl -log elaborate.log"
+xelab --incr --debug typical --relax --mt 8 -L xil_defaultlib -L unisims_ver -L unimacro_ver -L secureip -L xpm --snapshot TopModule_tb_behav xil_defaultlib.TopModule_tb xil_defaultlib.glbl -log elaborate.log
+
diff --git a/game.sim/sim_1/behav/xsim/glbl.v b/game.sim/sim_1/behav/xsim/glbl.v
new file mode 100644
index 0000000000000000000000000000000000000000..ed3b249ceef65a0d1b42790def9ee8179363679c
--- /dev/null
+++ b/game.sim/sim_1/behav/xsim/glbl.v
@@ -0,0 +1,84 @@
+// $Header: /devl/xcs/repo/env/Databases/CAEInterfaces/verunilibs/data/glbl.v,v 1.14 2010/10/28 20:44:00 fphillip Exp $
+`ifndef GLBL
+`define GLBL
+`timescale 1 ps / 1 ps
+
+module glbl ();
+
+ parameter ROC_WIDTH = 100000;
+ parameter TOC_WIDTH = 0;
+ parameter GRES_WIDTH = 10000;
+ parameter GRES_START = 10000;
+
+//-------- STARTUP Globals --------------
+ wire GSR;
+ wire GTS;
+ wire GWE;
+ wire PRLD;
+ wire GRESTORE;
+ tri1 p_up_tmp;
+ tri (weak1, strong0) PLL_LOCKG = p_up_tmp;
+
+ wire PROGB_GLBL;
+ wire CCLKO_GLBL;
+ wire FCSBO_GLBL;
+ wire [3:0] DO_GLBL;
+ wire [3:0] DI_GLBL;
+
+ reg GSR_int;
+ reg GTS_int;
+ reg PRLD_int;
+ reg GRESTORE_int;
+
+//-------- JTAG Globals --------------
+ wire JTAG_TDO_GLBL;
+ wire JTAG_TCK_GLBL;
+ wire JTAG_TDI_GLBL;
+ wire JTAG_TMS_GLBL;
+ wire JTAG_TRST_GLBL;
+
+ reg JTAG_CAPTURE_GLBL;
+ reg JTAG_RESET_GLBL;
+ reg JTAG_SHIFT_GLBL;
+ reg JTAG_UPDATE_GLBL;
+ reg JTAG_RUNTEST_GLBL;
+
+ reg JTAG_SEL1_GLBL = 0;
+ reg JTAG_SEL2_GLBL = 0 ;
+ reg JTAG_SEL3_GLBL = 0;
+ reg JTAG_SEL4_GLBL = 0;
+
+ reg JTAG_USER_TDO1_GLBL = 1'bz;
+ reg JTAG_USER_TDO2_GLBL = 1'bz;
+ reg JTAG_USER_TDO3_GLBL = 1'bz;
+ reg JTAG_USER_TDO4_GLBL = 1'bz;
+
+ assign (strong1, weak0) GSR = GSR_int;
+ assign (strong1, weak0) GTS = GTS_int;
+ assign (weak1, weak0) PRLD = PRLD_int;
+ assign (strong1, weak0) GRESTORE = GRESTORE_int;
+
+ initial begin
+ GSR_int = 1'b1;
+ PRLD_int = 1'b1;
+ #(ROC_WIDTH)
+ GSR_int = 1'b0;
+ PRLD_int = 1'b0;
+ end
+
+ initial begin
+ GTS_int = 1'b1;
+ #(TOC_WIDTH)
+ GTS_int = 1'b0;
+ end
+
+ initial begin
+ GRESTORE_int = 1'b0;
+ #(GRES_START);
+ GRESTORE_int = 1'b1;
+ #(GRES_WIDTH);
+ GRESTORE_int = 1'b0;
+ end
+
+endmodule
+`endif
diff --git a/game.sim/sim_1/behav/xsim/simulate.log b/game.sim/sim_1/behav/xsim/simulate.log
new file mode 100644
index 0000000000000000000000000000000000000000..3a14ee624a9f4bdaa2d11739bbf5670fa4d48b6c
--- /dev/null
+++ b/game.sim/sim_1/behav/xsim/simulate.log
@@ -0,0 +1 @@
+Time resolution is 1 ps
diff --git a/game.sim/sim_1/behav/xsim/simulate.sh b/game.sim/sim_1/behav/xsim/simulate.sh
new file mode 100755
index 0000000000000000000000000000000000000000..a9cea1bc4090993aef82c8da614121981f824edc
--- /dev/null
+++ b/game.sim/sim_1/behav/xsim/simulate.sh
@@ -0,0 +1,21 @@
+#!/bin/bash -f
+# ****************************************************************************
+# Vivado (TM) v2022.2 (64-bit)
+#
+# Filename : simulate.sh
+# Simulator : Xilinx Vivado Simulator
+# Description : Script for simulating the design by launching the simulator
+#
+# Generated by Vivado on Tue Feb 28 13:01:34 CET 2023
+# SW Build 3671981 on Fri Oct 14 04:59:54 MDT 2022
+#
+# IP Build 3669848 on Fri Oct 14 08:30:02 MDT 2022
+#
+# usage: simulate.sh
+#
+# ****************************************************************************
+set -Eeuo pipefail
+# simulate design
+echo "xsim TopModule_tb_behav -key {Behavioral:sim_1:Functional:TopModule_tb} -tclbatch TopModule_tb.tcl -view /home/prasic/game/TopModule_tb_behav.wcfg -log simulate.log"
+xsim TopModule_tb_behav -key {Behavioral:sim_1:Functional:TopModule_tb} -tclbatch TopModule_tb.tcl -view /home/prasic/game/TopModule_tb_behav.wcfg -log simulate.log
+
diff --git a/game.sim/sim_1/behav/xsim/xelab.pb b/game.sim/sim_1/behav/xsim/xelab.pb
new file mode 100644
index 0000000000000000000000000000000000000000..9025e1fbd4137473e90bdb089c0c532d30c21fab
Binary files /dev/null and b/game.sim/sim_1/behav/xsim/xelab.pb differ
diff --git a/game.sim/sim_1/behav/xsim/xsim.dir/TopModule_tb_behav/Compile_Options.txt b/game.sim/sim_1/behav/xsim/xsim.dir/TopModule_tb_behav/Compile_Options.txt
new file mode 100644
index 0000000000000000000000000000000000000000..5944f9ea6fd9c40b8d275a61999cc2e352340dec
--- /dev/null
+++ b/game.sim/sim_1/behav/xsim/xsim.dir/TopModule_tb_behav/Compile_Options.txt
@@ -0,0 +1 @@
+--incr --debug "typical" --relax --mt "8" -L "xil_defaultlib" -L "unisims_ver" -L "unimacro_ver" -L "secureip" -L "xpm" --snapshot "TopModule_tb_behav" "xil_defaultlib.TopModule_tb" "xil_defaultlib.glbl" -log "elaborate.log"
diff --git a/game.sim/sim_1/behav/xsim/xsim.dir/TopModule_tb_behav/TempBreakPointFile.txt b/game.sim/sim_1/behav/xsim/xsim.dir/TopModule_tb_behav/TempBreakPointFile.txt
new file mode 100644
index 0000000000000000000000000000000000000000..fdbc612e3497473d6b58c7f0c1432b55416f6136
--- /dev/null
+++ b/game.sim/sim_1/behav/xsim/xsim.dir/TopModule_tb_behav/TempBreakPointFile.txt
@@ -0,0 +1 @@
+Breakpoint File Version 1.0
diff --git a/game.sim/sim_1/behav/xsim/xsim.dir/TopModule_tb_behav/obj/xsim_0.lnx64.o b/game.sim/sim_1/behav/xsim/xsim.dir/TopModule_tb_behav/obj/xsim_0.lnx64.o
new file mode 100644
index 0000000000000000000000000000000000000000..b85db7b85b9595ae2218fa9fbec616676b063ce0
Binary files /dev/null and b/game.sim/sim_1/behav/xsim/xsim.dir/TopModule_tb_behav/obj/xsim_0.lnx64.o differ
diff --git a/game.sim/sim_1/behav/xsim/xsim.dir/TopModule_tb_behav/obj/xsim_1.c b/game.sim/sim_1/behav/xsim/xsim.dir/TopModule_tb_behav/obj/xsim_1.c
new file mode 100644
index 0000000000000000000000000000000000000000..3e4643f711fbf084c57161e3cca640dd168c1e2e
--- /dev/null
+++ b/game.sim/sim_1/behav/xsim/xsim.dir/TopModule_tb_behav/obj/xsim_1.c
@@ -0,0 +1,345 @@
+/**********************************************************************/
+/* ____ ____ */
+/* / /\/ / */
+/* /___/ \ / */
+/* \ \ \/ */
+/* \ \ Copyright (c) 2003-2020 Xilinx, Inc. */
+/* / / All Right Reserved. */
+/* /---/ /\ */
+/* \ \ / \ */
+/* \___\/\___\ */
+/**********************************************************************/
+
+#if defined(_WIN32)
+ #include "stdio.h"
+ #define IKI_DLLESPEC __declspec(dllimport)
+#else
+ #define IKI_DLLESPEC
+#endif
+#include "iki.h"
+#include <string.h>
+#include <math.h>
+#ifdef __GNUC__
+#include <stdlib.h>
+#else
+#include <malloc.h>
+#define alloca _alloca
+#endif
+/**********************************************************************/
+/* ____ ____ */
+/* / /\/ / */
+/* /___/ \ / */
+/* \ \ \/ */
+/* \ \ Copyright (c) 2003-2020 Xilinx, Inc. */
+/* / / All Right Reserved. */
+/* /---/ /\ */
+/* \ \ / \ */
+/* \___\/\___\ */
+/**********************************************************************/
+
+#if defined(_WIN32)
+ #include "stdio.h"
+ #define IKI_DLLESPEC __declspec(dllimport)
+#else
+ #define IKI_DLLESPEC
+#endif
+#include "iki.h"
+#include <string.h>
+#include <math.h>
+#ifdef __GNUC__
+#include <stdlib.h>
+#else
+#include <malloc.h>
+#define alloca _alloca
+#endif
+typedef void (*funcp)(char *, char *);
+extern int main(int, char**);
+IKI_DLLESPEC extern void execute_2(char*, char *);
+IKI_DLLESPEC extern void execute_3(char*, char *);
+IKI_DLLESPEC extern void execute_4(char*, char *);
+IKI_DLLESPEC extern void execute_5(char*, char *);
+IKI_DLLESPEC extern void execute_6(char*, char *);
+IKI_DLLESPEC extern void execute_7(char*, char *);
+IKI_DLLESPEC extern void execute_8(char*, char *);
+IKI_DLLESPEC extern void execute_9(char*, char *);
+IKI_DLLESPEC extern void execute_10(char*, char *);
+IKI_DLLESPEC extern void execute_11(char*, char *);
+IKI_DLLESPEC extern void execute_246(char*, char *);
+IKI_DLLESPEC extern void execute_247(char*, char *);
+IKI_DLLESPEC extern void execute_38(char*, char *);
+IKI_DLLESPEC extern void execute_40(char*, char *);
+IKI_DLLESPEC extern void execute_41(char*, char *);
+IKI_DLLESPEC extern void execute_68(char*, char *);
+IKI_DLLESPEC extern void execute_69(char*, char *);
+IKI_DLLESPEC extern void execute_70(char*, char *);
+IKI_DLLESPEC extern void execute_71(char*, char *);
+IKI_DLLESPEC extern void execute_72(char*, char *);
+IKI_DLLESPEC extern void execute_73(char*, char *);
+IKI_DLLESPEC extern void execute_74(char*, char *);
+IKI_DLLESPEC extern void execute_75(char*, char *);
+IKI_DLLESPEC extern void execute_76(char*, char *);
+IKI_DLLESPEC extern void execute_77(char*, char *);
+IKI_DLLESPEC extern void execute_78(char*, char *);
+IKI_DLLESPEC extern void execute_79(char*, char *);
+IKI_DLLESPEC extern void execute_80(char*, char *);
+IKI_DLLESPEC extern void execute_81(char*, char *);
+IKI_DLLESPEC extern void execute_82(char*, char *);
+IKI_DLLESPEC extern void execute_83(char*, char *);
+IKI_DLLESPEC extern void execute_84(char*, char *);
+IKI_DLLESPEC extern void execute_85(char*, char *);
+IKI_DLLESPEC extern void execute_86(char*, char *);
+IKI_DLLESPEC extern void execute_87(char*, char *);
+IKI_DLLESPEC extern void execute_88(char*, char *);
+IKI_DLLESPEC extern void execute_89(char*, char *);
+IKI_DLLESPEC extern void execute_90(char*, char *);
+IKI_DLLESPEC extern void execute_91(char*, char *);
+IKI_DLLESPEC extern void execute_92(char*, char *);
+IKI_DLLESPEC extern void execute_93(char*, char *);
+IKI_DLLESPEC extern void execute_94(char*, char *);
+IKI_DLLESPEC extern void execute_95(char*, char *);
+IKI_DLLESPEC extern void execute_96(char*, char *);
+IKI_DLLESPEC extern void execute_97(char*, char *);
+IKI_DLLESPEC extern void execute_98(char*, char *);
+IKI_DLLESPEC extern void execute_99(char*, char *);
+IKI_DLLESPEC extern void execute_100(char*, char *);
+IKI_DLLESPEC extern void execute_101(char*, char *);
+IKI_DLLESPEC extern void execute_102(char*, char *);
+IKI_DLLESPEC extern void execute_103(char*, char *);
+IKI_DLLESPEC extern void execute_104(char*, char *);
+IKI_DLLESPEC extern void execute_105(char*, char *);
+IKI_DLLESPEC extern void execute_106(char*, char *);
+IKI_DLLESPEC extern void execute_107(char*, char *);
+IKI_DLLESPEC extern void execute_108(char*, char *);
+IKI_DLLESPEC extern void execute_109(char*, char *);
+IKI_DLLESPEC extern void execute_110(char*, char *);
+IKI_DLLESPEC extern void execute_111(char*, char *);
+IKI_DLLESPEC extern void execute_112(char*, char *);
+IKI_DLLESPEC extern void execute_113(char*, char *);
+IKI_DLLESPEC extern void execute_114(char*, char *);
+IKI_DLLESPEC extern void execute_115(char*, char *);
+IKI_DLLESPEC extern void execute_116(char*, char *);
+IKI_DLLESPEC extern void execute_117(char*, char *);
+IKI_DLLESPEC extern void execute_118(char*, char *);
+IKI_DLLESPEC extern void execute_119(char*, char *);
+IKI_DLLESPEC extern void execute_120(char*, char *);
+IKI_DLLESPEC extern void execute_121(char*, char *);
+IKI_DLLESPEC extern void execute_122(char*, char *);
+IKI_DLLESPEC extern void execute_123(char*, char *);
+IKI_DLLESPEC extern void execute_124(char*, char *);
+IKI_DLLESPEC extern void execute_125(char*, char *);
+IKI_DLLESPEC extern void execute_126(char*, char *);
+IKI_DLLESPEC extern void execute_127(char*, char *);
+IKI_DLLESPEC extern void execute_128(char*, char *);
+IKI_DLLESPEC extern void execute_129(char*, char *);
+IKI_DLLESPEC extern void execute_130(char*, char *);
+IKI_DLLESPEC extern void execute_131(char*, char *);
+IKI_DLLESPEC extern void execute_132(char*, char *);
+IKI_DLLESPEC extern void execute_133(char*, char *);
+IKI_DLLESPEC extern void execute_134(char*, char *);
+IKI_DLLESPEC extern void execute_135(char*, char *);
+IKI_DLLESPEC extern void execute_136(char*, char *);
+IKI_DLLESPEC extern void execute_137(char*, char *);
+IKI_DLLESPEC extern void execute_138(char*, char *);
+IKI_DLLESPEC extern void execute_139(char*, char *);
+IKI_DLLESPEC extern void execute_140(char*, char *);
+IKI_DLLESPEC extern void execute_141(char*, char *);
+IKI_DLLESPEC extern void execute_142(char*, char *);
+IKI_DLLESPEC extern void execute_143(char*, char *);
+IKI_DLLESPEC extern void execute_144(char*, char *);
+IKI_DLLESPEC extern void execute_145(char*, char *);
+IKI_DLLESPEC extern void execute_146(char*, char *);
+IKI_DLLESPEC extern void execute_147(char*, char *);
+IKI_DLLESPEC extern void execute_148(char*, char *);
+IKI_DLLESPEC extern void execute_149(char*, char *);
+IKI_DLLESPEC extern void execute_150(char*, char *);
+IKI_DLLESPEC extern void execute_151(char*, char *);
+IKI_DLLESPEC extern void execute_152(char*, char *);
+IKI_DLLESPEC extern void execute_153(char*, char *);
+IKI_DLLESPEC extern void execute_154(char*, char *);
+IKI_DLLESPEC extern void execute_155(char*, char *);
+IKI_DLLESPEC extern void execute_156(char*, char *);
+IKI_DLLESPEC extern void execute_157(char*, char *);
+IKI_DLLESPEC extern void execute_158(char*, char *);
+IKI_DLLESPEC extern void execute_159(char*, char *);
+IKI_DLLESPEC extern void execute_160(char*, char *);
+IKI_DLLESPEC extern void execute_161(char*, char *);
+IKI_DLLESPEC extern void execute_162(char*, char *);
+IKI_DLLESPEC extern void execute_163(char*, char *);
+IKI_DLLESPEC extern void execute_164(char*, char *);
+IKI_DLLESPEC extern void execute_165(char*, char *);
+IKI_DLLESPEC extern void execute_166(char*, char *);
+IKI_DLLESPEC extern void execute_167(char*, char *);
+IKI_DLLESPEC extern void execute_168(char*, char *);
+IKI_DLLESPEC extern void execute_169(char*, char *);
+IKI_DLLESPEC extern void execute_170(char*, char *);
+IKI_DLLESPEC extern void execute_171(char*, char *);
+IKI_DLLESPEC extern void execute_172(char*, char *);
+IKI_DLLESPEC extern void execute_173(char*, char *);
+IKI_DLLESPEC extern void execute_174(char*, char *);
+IKI_DLLESPEC extern void execute_175(char*, char *);
+IKI_DLLESPEC extern void execute_176(char*, char *);
+IKI_DLLESPEC extern void execute_177(char*, char *);
+IKI_DLLESPEC extern void execute_178(char*, char *);
+IKI_DLLESPEC extern void execute_179(char*, char *);
+IKI_DLLESPEC extern void execute_180(char*, char *);
+IKI_DLLESPEC extern void execute_181(char*, char *);
+IKI_DLLESPEC extern void execute_182(char*, char *);
+IKI_DLLESPEC extern void execute_183(char*, char *);
+IKI_DLLESPEC extern void execute_184(char*, char *);
+IKI_DLLESPEC extern void execute_185(char*, char *);
+IKI_DLLESPEC extern void execute_186(char*, char *);
+IKI_DLLESPEC extern void execute_187(char*, char *);
+IKI_DLLESPEC extern void execute_188(char*, char *);
+IKI_DLLESPEC extern void execute_189(char*, char *);
+IKI_DLLESPEC extern void execute_190(char*, char *);
+IKI_DLLESPEC extern void execute_191(char*, char *);
+IKI_DLLESPEC extern void execute_192(char*, char *);
+IKI_DLLESPEC extern void execute_193(char*, char *);
+IKI_DLLESPEC extern void execute_194(char*, char *);
+IKI_DLLESPEC extern void execute_195(char*, char *);
+IKI_DLLESPEC extern void execute_196(char*, char *);
+IKI_DLLESPEC extern void execute_197(char*, char *);
+IKI_DLLESPEC extern void execute_198(char*, char *);
+IKI_DLLESPEC extern void execute_199(char*, char *);
+IKI_DLLESPEC extern void execute_200(char*, char *);
+IKI_DLLESPEC extern void execute_201(char*, char *);
+IKI_DLLESPEC extern void execute_202(char*, char *);
+IKI_DLLESPEC extern void execute_203(char*, char *);
+IKI_DLLESPEC extern void execute_204(char*, char *);
+IKI_DLLESPEC extern void execute_205(char*, char *);
+IKI_DLLESPEC extern void execute_206(char*, char *);
+IKI_DLLESPEC extern void execute_207(char*, char *);
+IKI_DLLESPEC extern void execute_208(char*, char *);
+IKI_DLLESPEC extern void execute_209(char*, char *);
+IKI_DLLESPEC extern void execute_210(char*, char *);
+IKI_DLLESPEC extern void execute_211(char*, char *);
+IKI_DLLESPEC extern void execute_212(char*, char *);
+IKI_DLLESPEC extern void execute_213(char*, char *);
+IKI_DLLESPEC extern void execute_214(char*, char *);
+IKI_DLLESPEC extern void execute_215(char*, char *);
+IKI_DLLESPEC extern void execute_216(char*, char *);
+IKI_DLLESPEC extern void execute_217(char*, char *);
+IKI_DLLESPEC extern void execute_218(char*, char *);
+IKI_DLLESPEC extern void execute_219(char*, char *);
+IKI_DLLESPEC extern void execute_220(char*, char *);
+IKI_DLLESPEC extern void execute_221(char*, char *);
+IKI_DLLESPEC extern void execute_222(char*, char *);
+IKI_DLLESPEC extern void execute_223(char*, char *);
+IKI_DLLESPEC extern void execute_224(char*, char *);
+IKI_DLLESPEC extern void execute_226(char*, char *);
+IKI_DLLESPEC extern void execute_228(char*, char *);
+IKI_DLLESPEC extern void execute_229(char*, char *);
+IKI_DLLESPEC extern void execute_230(char*, char *);
+IKI_DLLESPEC extern void execute_231(char*, char *);
+IKI_DLLESPEC extern void execute_232(char*, char *);
+IKI_DLLESPEC extern void execute_234(char*, char *);
+IKI_DLLESPEC extern void execute_236(char*, char *);
+IKI_DLLESPEC extern void execute_237(char*, char *);
+IKI_DLLESPEC extern void execute_238(char*, char *);
+IKI_DLLESPEC extern void execute_239(char*, char *);
+IKI_DLLESPEC extern void execute_240(char*, char *);
+IKI_DLLESPEC extern void execute_241(char*, char *);
+IKI_DLLESPEC extern void execute_242(char*, char *);
+IKI_DLLESPEC extern void execute_244(char*, char *);
+IKI_DLLESPEC extern void execute_245(char*, char *);
+IKI_DLLESPEC extern void vlog_transfunc_eventcallback(char*, char*, unsigned, unsigned, unsigned, char *);
+IKI_DLLESPEC extern void vhdl_transfunc_eventcallback(char*, char*, unsigned, unsigned, unsigned, char *);
+IKI_DLLESPEC extern void transaction_42(char*, char*, unsigned, unsigned, unsigned);
+IKI_DLLESPEC extern void transaction_102(char*, char*, unsigned, unsigned, unsigned);
+IKI_DLLESPEC extern void transaction_105(char*, char*, unsigned, unsigned, unsigned);
+IKI_DLLESPEC extern void transaction_108(char*, char*, unsigned, unsigned, unsigned);
+IKI_DLLESPEC extern void transaction_143(char*, char*, unsigned, unsigned, unsigned);
+IKI_DLLESPEC extern void transaction_144(char*, char*, unsigned, unsigned, unsigned);
+IKI_DLLESPEC extern void transaction_152(char*, char*, unsigned, unsigned, unsigned);
+IKI_DLLESPEC extern void transaction_155(char*, char*, unsigned, unsigned, unsigned);
+IKI_DLLESPEC extern void transaction_177(char*, char*, unsigned, unsigned, unsigned);
+IKI_DLLESPEC extern void transaction_180(char*, char*, unsigned, unsigned, unsigned);
+IKI_DLLESPEC extern void transaction_181(char*, char*, unsigned, unsigned, unsigned);
+IKI_DLLESPEC extern void transaction_184(char*, char*, unsigned, unsigned, unsigned);
+IKI_DLLESPEC extern void transaction_187(char*, char*, unsigned, unsigned, unsigned);
+IKI_DLLESPEC extern void transaction_188(char*, char*, unsigned, unsigned, unsigned);
+IKI_DLLESPEC extern void transaction_190(char*, char*, unsigned, unsigned, unsigned);
+IKI_DLLESPEC extern void transaction_193(char*, char*, unsigned, unsigned, unsigned);
+IKI_DLLESPEC extern void transaction_196(char*, char*, unsigned, unsigned, unsigned);
+IKI_DLLESPEC extern void transaction_203(char*, char*, unsigned, unsigned, unsigned);
+IKI_DLLESPEC extern void transaction_204(char*, char*, unsigned, unsigned, unsigned);
+IKI_DLLESPEC extern void transaction_205(char*, char*, unsigned, unsigned, unsigned);
+IKI_DLLESPEC extern void transaction_206(char*, char*, unsigned, unsigned, unsigned);
+IKI_DLLESPEC extern void transaction_207(char*, char*, unsigned, unsigned, unsigned);
+IKI_DLLESPEC extern void transaction_208(char*, char*, unsigned, unsigned, unsigned);
+IKI_DLLESPEC extern void transaction_209(char*, char*, unsigned, unsigned, unsigned);
+IKI_DLLESPEC extern void transaction_210(char*, char*, unsigned, unsigned, unsigned);
+IKI_DLLESPEC extern void transaction_243(char*, char*, unsigned, unsigned, unsigned);
+IKI_DLLESPEC extern void transaction_273(char*, char*, unsigned, unsigned, unsigned);
+IKI_DLLESPEC extern void transaction_292(char*, char*, unsigned, unsigned, unsigned);
+IKI_DLLESPEC extern void transaction_293(char*, char*, unsigned, unsigned, unsigned);
+IKI_DLLESPEC extern void transaction_294(char*, char*, unsigned, unsigned, unsigned);
+IKI_DLLESPEC extern void transaction_304(char*, char*, unsigned, unsigned, unsigned);
+IKI_DLLESPEC extern void transaction_346(char*, char*, unsigned, unsigned, unsigned);
+IKI_DLLESPEC extern void transaction_348(char*, char*, unsigned, unsigned, unsigned);
+IKI_DLLESPEC extern void transaction_523(char*, char*, unsigned, unsigned, unsigned);
+IKI_DLLESPEC extern void transaction_524(char*, char*, unsigned, unsigned, unsigned);
+IKI_DLLESPEC extern void transaction_530(char*, char*, unsigned, unsigned, unsigned);
+IKI_DLLESPEC extern void transaction_531(char*, char*, unsigned, unsigned, unsigned);
+IKI_DLLESPEC extern void transaction_533(char*, char*, unsigned, unsigned, unsigned);
+IKI_DLLESPEC extern void transaction_534(char*, char*, unsigned, unsigned, unsigned);
+IKI_DLLESPEC extern void transaction_535(char*, char*, unsigned, unsigned, unsigned);
+IKI_DLLESPEC extern void transaction_540(char*, char*, unsigned, unsigned, unsigned);
+funcp funcTab[231] = {(funcp)execute_2, (funcp)execute_3, (funcp)execute_4, (funcp)execute_5, (funcp)execute_6, (funcp)execute_7, (funcp)execute_8, (funcp)execute_9, (funcp)execute_10, (funcp)execute_11, (funcp)execute_246, (funcp)execute_247, (funcp)execute_38, (funcp)execute_40, (funcp)execute_41, (funcp)execute_68, (funcp)execute_69, (funcp)execute_70, (funcp)execute_71, (funcp)execute_72, (funcp)execute_73, (funcp)execute_74, (funcp)execute_75, (funcp)execute_76, (funcp)execute_77, (funcp)execute_78, (funcp)execute_79, (funcp)execute_80, (funcp)execute_81, (funcp)execute_82, (funcp)execute_83, (funcp)execute_84, (funcp)execute_85, (funcp)execute_86, (funcp)execute_87, (funcp)execute_88, (funcp)execute_89, (funcp)execute_90, (funcp)execute_91, (funcp)execute_92, (funcp)execute_93, (funcp)execute_94, (funcp)execute_95, (funcp)execute_96, (funcp)execute_97, (funcp)execute_98, (funcp)execute_99, (funcp)execute_100, (funcp)execute_101, (funcp)execute_102, (funcp)execute_103, (funcp)execute_104, (funcp)execute_105, (funcp)execute_106, (funcp)execute_107, (funcp)execute_108, (funcp)execute_109, (funcp)execute_110, (funcp)execute_111, (funcp)execute_112, (funcp)execute_113, (funcp)execute_114, (funcp)execute_115, (funcp)execute_116, (funcp)execute_117, (funcp)execute_118, (funcp)execute_119, (funcp)execute_120, (funcp)execute_121, (funcp)execute_122, (funcp)execute_123, (funcp)execute_124, (funcp)execute_125, (funcp)execute_126, (funcp)execute_127, (funcp)execute_128, (funcp)execute_129, (funcp)execute_130, (funcp)execute_131, (funcp)execute_132, (funcp)execute_133, (funcp)execute_134, (funcp)execute_135, (funcp)execute_136, (funcp)execute_137, (funcp)execute_138, (funcp)execute_139, (funcp)execute_140, (funcp)execute_141, (funcp)execute_142, (funcp)execute_143, (funcp)execute_144, (funcp)execute_145, (funcp)execute_146, (funcp)execute_147, (funcp)execute_148, (funcp)execute_149, (funcp)execute_150, (funcp)execute_151, (funcp)execute_152, (funcp)execute_153, (funcp)execute_154, (funcp)execute_155, (funcp)execute_156, (funcp)execute_157, (funcp)execute_158, (funcp)execute_159, (funcp)execute_160, (funcp)execute_161, (funcp)execute_162, (funcp)execute_163, (funcp)execute_164, (funcp)execute_165, (funcp)execute_166, (funcp)execute_167, (funcp)execute_168, (funcp)execute_169, (funcp)execute_170, (funcp)execute_171, (funcp)execute_172, (funcp)execute_173, (funcp)execute_174, (funcp)execute_175, (funcp)execute_176, (funcp)execute_177, (funcp)execute_178, (funcp)execute_179, (funcp)execute_180, (funcp)execute_181, (funcp)execute_182, (funcp)execute_183, (funcp)execute_184, (funcp)execute_185, (funcp)execute_186, (funcp)execute_187, (funcp)execute_188, (funcp)execute_189, (funcp)execute_190, (funcp)execute_191, (funcp)execute_192, (funcp)execute_193, (funcp)execute_194, (funcp)execute_195, (funcp)execute_196, (funcp)execute_197, (funcp)execute_198, (funcp)execute_199, (funcp)execute_200, (funcp)execute_201, (funcp)execute_202, (funcp)execute_203, (funcp)execute_204, (funcp)execute_205, (funcp)execute_206, (funcp)execute_207, (funcp)execute_208, (funcp)execute_209, (funcp)execute_210, (funcp)execute_211, (funcp)execute_212, (funcp)execute_213, (funcp)execute_214, (funcp)execute_215, (funcp)execute_216, (funcp)execute_217, (funcp)execute_218, (funcp)execute_219, (funcp)execute_220, (funcp)execute_221, (funcp)execute_222, (funcp)execute_223, (funcp)execute_224, (funcp)execute_226, (funcp)execute_228, (funcp)execute_229, (funcp)execute_230, (funcp)execute_231, (funcp)execute_232, (funcp)execute_234, (funcp)execute_236, (funcp)execute_237, (funcp)execute_238, (funcp)execute_239, (funcp)execute_240, (funcp)execute_241, (funcp)execute_242, (funcp)execute_244, (funcp)execute_245, (funcp)vlog_transfunc_eventcallback, (funcp)vhdl_transfunc_eventcallback, (funcp)transaction_42, (funcp)transaction_102, (funcp)transaction_105, (funcp)transaction_108, (funcp)transaction_143, (funcp)transaction_144, (funcp)transaction_152, (funcp)transaction_155, (funcp)transaction_177, (funcp)transaction_180, (funcp)transaction_181, (funcp)transaction_184, (funcp)transaction_187, (funcp)transaction_188, (funcp)transaction_190, (funcp)transaction_193, (funcp)transaction_196, (funcp)transaction_203, (funcp)transaction_204, (funcp)transaction_205, (funcp)transaction_206, (funcp)transaction_207, (funcp)transaction_208, (funcp)transaction_209, (funcp)transaction_210, (funcp)transaction_243, (funcp)transaction_273, (funcp)transaction_292, (funcp)transaction_293, (funcp)transaction_294, (funcp)transaction_304, (funcp)transaction_346, (funcp)transaction_348, (funcp)transaction_523, (funcp)transaction_524, (funcp)transaction_530, (funcp)transaction_531, (funcp)transaction_533, (funcp)transaction_534, (funcp)transaction_535, (funcp)transaction_540};
+const int NumRelocateId= 231;
+
+void relocate(char *dp)
+{
+ iki_relocate(dp, "xsim.dir/TopModule_tb_behav/xsim.reloc", (void **)funcTab, 231);
+ iki_vhdl_file_variable_register(dp + 134312);
+ iki_vhdl_file_variable_register(dp + 134368);
+
+
+ /*Populate the transaction function pointer field in the whole net structure */
+}
+
+void sensitize(char *dp)
+{
+ iki_sensitize(dp, "xsim.dir/TopModule_tb_behav/xsim.reloc");
+}
+
+ // Initialize Verilog nets in mixed simulation, for the cases when the value at time 0 should be propagated from the mixed language Vhdl net
+
+void wrapper_func_0(char *dp)
+
+{
+
+}
+
+void simulate(char *dp)
+{
+ iki_schedule_processes_at_time_zero(dp, "xsim.dir/TopModule_tb_behav/xsim.reloc");
+ wrapper_func_0(dp);
+
+ iki_execute_processes();
+
+ // Schedule resolution functions for the multiply driven Verilog nets that have strength
+ // Schedule transaction functions for the singly driven Verilog nets that have strength
+
+}
+#include "iki_bridge.h"
+void relocate(char *);
+
+void sensitize(char *);
+
+void simulate(char *);
+
+extern SYSTEMCLIB_IMP_DLLSPEC void local_register_implicit_channel(int, char*);
+extern SYSTEMCLIB_IMP_DLLSPEC int xsim_argc_copy ;
+extern SYSTEMCLIB_IMP_DLLSPEC char** xsim_argv_copy ;
+
+int main(int argc, char **argv)
+{
+ iki_heap_initialize("ms", "isimmm", 0, 2147483648) ;
+ iki_set_sv_type_file_path_name("xsim.dir/TopModule_tb_behav/xsim.svtype");
+ iki_set_crvs_dump_file_path_name("xsim.dir/TopModule_tb_behav/xsim.crvsdump");
+ void* design_handle = iki_create_design("xsim.dir/TopModule_tb_behav/xsim.mem", (void *)relocate, (void *)sensitize, (void *)simulate, (void*)0, 0, isimBridge_getWdbWriter(), 0, argc, argv);
+ iki_set_rc_trial_count(100);
+ (void) design_handle;
+ return iki_simulate_design();
+}
diff --git a/game.sim/sim_1/behav/xsim/xsim.dir/TopModule_tb_behav/obj/xsim_1.lnx64.o b/game.sim/sim_1/behav/xsim/xsim.dir/TopModule_tb_behav/obj/xsim_1.lnx64.o
new file mode 100644
index 0000000000000000000000000000000000000000..d6ea04dbc096282cfd7269802137ff71035f8dd9
Binary files /dev/null and b/game.sim/sim_1/behav/xsim/xsim.dir/TopModule_tb_behav/obj/xsim_1.lnx64.o differ
diff --git a/game.sim/sim_1/behav/xsim/xsim.dir/TopModule_tb_behav/xsim.dbg b/game.sim/sim_1/behav/xsim/xsim.dir/TopModule_tb_behav/xsim.dbg
new file mode 100644
index 0000000000000000000000000000000000000000..073f676e2bc6951946ddaf4deeea61c018280904
Binary files /dev/null and b/game.sim/sim_1/behav/xsim/xsim.dir/TopModule_tb_behav/xsim.dbg differ
diff --git a/game.sim/sim_1/behav/xsim/xsim.dir/TopModule_tb_behav/xsim.mem b/game.sim/sim_1/behav/xsim/xsim.dir/TopModule_tb_behav/xsim.mem
new file mode 100644
index 0000000000000000000000000000000000000000..5d2ec7946d373c864141f96e9f9b57a4f2318717
Binary files /dev/null and b/game.sim/sim_1/behav/xsim/xsim.dir/TopModule_tb_behav/xsim.mem differ
diff --git a/game.sim/sim_1/behav/xsim/xsim.dir/TopModule_tb_behav/xsim.reloc b/game.sim/sim_1/behav/xsim/xsim.dir/TopModule_tb_behav/xsim.reloc
new file mode 100644
index 0000000000000000000000000000000000000000..e5720e1ab211f92b5138ae2140f994dc3da14d77
Binary files /dev/null and b/game.sim/sim_1/behav/xsim/xsim.dir/TopModule_tb_behav/xsim.reloc differ
diff --git a/game.sim/sim_1/behav/xsim/xsim.dir/TopModule_tb_behav/xsim.rlx b/game.sim/sim_1/behav/xsim/xsim.dir/TopModule_tb_behav/xsim.rlx
new file mode 100644
index 0000000000000000000000000000000000000000..90a69e52298c90c6a718d947585a425bed1c67f8
--- /dev/null
+++ b/game.sim/sim_1/behav/xsim/xsim.dir/TopModule_tb_behav/xsim.rlx
@@ -0,0 +1,12 @@
+
+{
+ crc : 16804384305805465068 ,
+ ccp_crc : 0 ,
+ cmdline : " --incr --debug typical --relax --mt 8 -L xil_defaultlib -L unisims_ver -L unimacro_ver -L secureip -L xpm --snapshot TopModule_tb_behav xil_defaultlib.TopModule_tb xil_defaultlib.glbl" ,
+ buildDate : "Oct 14 2022" ,
+ buildTime : "05:07:14" ,
+ linkCmd : "/usr/bin/gcc -Wa,-W -O -fPIC -m64 -Wl,--no-as-needed -Wl,--unresolved-symbols=ignore-all -o \"xsim.dir/TopModule_tb_behav/xsimk\" \"xsim.dir/TopModule_tb_behav/obj/xsim_0.lnx64.o\" \"xsim.dir/TopModule_tb_behav/obj/xsim_1.lnx64.o\" -L\"/opt/Xilinx/Vivado/2022.2/lib/lnx64.o\" -lrdi_simulator_kernel -lrdi_simbridge_kernel" ,
+ aggregate_nets :
+ [
+ ]
+}
\ No newline at end of file
diff --git a/game.sim/sim_1/behav/xsim/xsim.dir/TopModule_tb_behav/xsim.rtti b/game.sim/sim_1/behav/xsim/xsim.dir/TopModule_tb_behav/xsim.rtti
new file mode 100644
index 0000000000000000000000000000000000000000..bb491e0b603edaba4314a70e9c9d7686d56dff33
Binary files /dev/null and b/game.sim/sim_1/behav/xsim/xsim.dir/TopModule_tb_behav/xsim.rtti differ
diff --git a/game.sim/sim_1/behav/xsim/xsim.dir/TopModule_tb_behav/xsim.svtype b/game.sim/sim_1/behav/xsim/xsim.dir/TopModule_tb_behav/xsim.svtype
new file mode 100644
index 0000000000000000000000000000000000000000..7c62b4eaf2065362ca4b433deed275cf688ee99e
Binary files /dev/null and b/game.sim/sim_1/behav/xsim/xsim.dir/TopModule_tb_behav/xsim.svtype differ
diff --git a/game.sim/sim_1/behav/xsim/xsim.dir/TopModule_tb_behav/xsim.type b/game.sim/sim_1/behav/xsim/xsim.dir/TopModule_tb_behav/xsim.type
new file mode 100644
index 0000000000000000000000000000000000000000..94b06af20bc0275b77d6c304ce9e8e8eb6aa0808
Binary files /dev/null and b/game.sim/sim_1/behav/xsim/xsim.dir/TopModule_tb_behav/xsim.type differ
diff --git a/game.sim/sim_1/behav/xsim/xsim.dir/TopModule_tb_behav/xsim.xdbg b/game.sim/sim_1/behav/xsim/xsim.dir/TopModule_tb_behav/xsim.xdbg
new file mode 100644
index 0000000000000000000000000000000000000000..07aa228f168630181279c105b54412aea4c00a17
Binary files /dev/null and b/game.sim/sim_1/behav/xsim/xsim.dir/TopModule_tb_behav/xsim.xdbg differ
diff --git a/game.sim/sim_1/behav/xsim/xsim.dir/TopModule_tb_behav/xsimSettings.ini b/game.sim/sim_1/behav/xsim/xsim.dir/TopModule_tb_behav/xsimSettings.ini
new file mode 100644
index 0000000000000000000000000000000000000000..ee979984f430d005005a56c43eafd21c16928668
--- /dev/null
+++ b/game.sim/sim_1/behav/xsim/xsim.dir/TopModule_tb_behav/xsimSettings.ini
@@ -0,0 +1,50 @@
+[General]
+ARRAY_DISPLAY_LIMIT=1024
+RADIX=hex
+TIME_UNIT=ns
+TRACE_LIMIT=65536
+VHDL_ENTITY_SCOPE_FILTER=true
+VHDL_PACKAGE_SCOPE_FILTER=false
+VHDL_BLOCK_SCOPE_FILTER=true
+VHDL_PROCESS_SCOPE_FILTER=false
+VHDL_PROCEDURE_SCOPE_FILTER=false
+VERILOG_MODULE_SCOPE_FILTER=true
+VERILOG_PACKAGE_SCOPE_FILTER=false
+VERILOG_BLOCK_SCOPE_FILTER=false
+VERILOG_TASK_SCOPE_FILTER=false
+VERILOG_PROCESS_SCOPE_FILTER=false
+INPUT_OBJECT_FILTER=true
+OUTPUT_OBJECT_FILTER=true
+INOUT_OBJECT_FILTER=true
+INTERNAL_OBJECT_FILTER=true
+CONSTANT_OBJECT_FILTER=true
+VARIABLE_OBJECT_FILTER=true
+INPUT_PROTOINST_FILTER=true
+OUTPUT_PROTOINST_FILTER=true
+INOUT_PROTOINST_FILTER=true
+INTERNAL_PROTOINST_FILTER=true
+CONSTANT_PROTOINST_FILTER=true
+VARIABLE_PROTOINST_FILTER=true
+SCOPE_NAME_COLUMN_WIDTH=127
+SCOPE_DESIGN_UNIT_COLUMN_WIDTH=204
+SCOPE_BLOCK_TYPE_COLUMN_WIDTH=75
+OBJECT_NAME_COLUMN_WIDTH=75
+OBJECT_VALUE_COLUMN_WIDTH=75
+OBJECT_DATA_TYPE_COLUMN_WIDTH=75
+PROCESS_NAME_COLUMN_WIDTH=75
+PROCESS_TYPE_COLUMN_WIDTH=75
+FRAME_INDEX_COLUMN_WIDTH=75
+FRAME_NAME_COLUMN_WIDTH=75
+FRAME_FILE_NAME_COLUMN_WIDTH=75
+FRAME_LINE_NUM_COLUMN_WIDTH=168
+LOCAL_NAME_COLUMN_WIDTH=75
+LOCAL_VALUE_COLUMN_WIDTH=75
+LOCAL_DATA_TYPE_COLUMN_WIDTH=0
+PROTO_NAME_COLUMN_WIDTH=0
+PROTO_VALUE_COLUMN_WIDTH=0
+INPUT_LOCAL_FILTER=1
+OUTPUT_LOCAL_FILTER=1
+INOUT_LOCAL_FILTER=1
+INTERNAL_LOCAL_FILTER=1
+CONSTANT_LOCAL_FILTER=1
+VARIABLE_LOCAL_FILTER=1
diff --git a/game.sim/sim_1/behav/xsim/xsim.dir/TopModule_tb_behav/xsimcrash.log b/game.sim/sim_1/behav/xsim/xsim.dir/TopModule_tb_behav/xsimcrash.log
new file mode 100644
index 0000000000000000000000000000000000000000..e69de29bb2d1d6434b8b29ae775ad8c2e48c5391
diff --git a/game.sim/sim_1/behav/xsim/xsim.dir/TopModule_tb_behav/xsimk b/game.sim/sim_1/behav/xsim/xsim.dir/TopModule_tb_behav/xsimk
new file mode 100755
index 0000000000000000000000000000000000000000..b8bb42b486b08fa2315bb1ee7ca928a923f615d3
Binary files /dev/null and b/game.sim/sim_1/behav/xsim/xsim.dir/TopModule_tb_behav/xsimk differ
diff --git a/game.sim/sim_1/behav/xsim/xsim.dir/TopModule_tb_behav/xsimkernel.log b/game.sim/sim_1/behav/xsim/xsim.dir/TopModule_tb_behav/xsimkernel.log
new file mode 100644
index 0000000000000000000000000000000000000000..c784f4b4587fb3f6bb388f21cf4ee6d2cbea0249
--- /dev/null
+++ b/game.sim/sim_1/behav/xsim/xsim.dir/TopModule_tb_behav/xsimkernel.log
@@ -0,0 +1,7 @@
+Running: xsim.dir/TopModule_tb_behav/xsimk -simmode gui -wdb TopModule_tb_behav.wdb -simrunnum 0 -socket 54249
+Design successfully loaded
+Design Loading Memory Usage: 29852 KB (Peak: 29852 KB)
+Design Loading CPU Usage: 10 ms
+Simulation completed
+Simulation Memory Usage: 115688 KB (Peak: 169120 KB)
+Simulation CPU Usage: 90 ms
diff --git a/game.sim/sim_1/behav/xsim/xsim.dir/xil_defaultlib/background.vdb b/game.sim/sim_1/behav/xsim/xsim.dir/xil_defaultlib/background.vdb
new file mode 100644
index 0000000000000000000000000000000000000000..afd62b07aafe6af1cd80d83cd0b0b4aa172e485b
Binary files /dev/null and b/game.sim/sim_1/behav/xsim/xsim.dir/xil_defaultlib/background.vdb differ
diff --git a/game.sim/sim_1/behav/xsim/xsim.dir/xil_defaultlib/clk_wiz_0.vdb b/game.sim/sim_1/behav/xsim/xsim.dir/xil_defaultlib/clk_wiz_0.vdb
new file mode 100644
index 0000000000000000000000000000000000000000..d737d6b7aa96356e3b4b23f613604aebc02662c7
Binary files /dev/null and b/game.sim/sim_1/behav/xsim/xsim.dir/xil_defaultlib/clk_wiz_0.vdb differ
diff --git a/game.sim/sim_1/behav/xsim/xsim.dir/xil_defaultlib/clk_wiz_0_clk_wiz.vdb b/game.sim/sim_1/behav/xsim/xsim.dir/xil_defaultlib/clk_wiz_0_clk_wiz.vdb
new file mode 100644
index 0000000000000000000000000000000000000000..287fdd7345f95a2d75abbd244534f929495ff7d3
Binary files /dev/null and b/game.sim/sim_1/behav/xsim/xsim.dir/xil_defaultlib/clk_wiz_0_clk_wiz.vdb differ
diff --git a/game.sim/sim_1/behav/xsim/xsim.dir/xil_defaultlib/glbl.sdb b/game.sim/sim_1/behav/xsim/xsim.dir/xil_defaultlib/glbl.sdb
new file mode 100644
index 0000000000000000000000000000000000000000..9f7e3b7ec996c78ae7118751e7d55cfcc43a3c81
Binary files /dev/null and b/game.sim/sim_1/behav/xsim/xsim.dir/xil_defaultlib/glbl.sdb differ
diff --git a/game.sim/sim_1/behav/xsim/xsim.dir/xil_defaultlib/priority.vdb b/game.sim/sim_1/behav/xsim/xsim.dir/xil_defaultlib/priority.vdb
new file mode 100644
index 0000000000000000000000000000000000000000..aa7c44441e6afc64aa0e4d2a0618e80604ebe559
Binary files /dev/null and b/game.sim/sim_1/behav/xsim/xsim.dir/xil_defaultlib/priority.vdb differ
diff --git a/game.sim/sim_1/behav/xsim/xsim.dir/xil_defaultlib/runner.vdb b/game.sim/sim_1/behav/xsim/xsim.dir/xil_defaultlib/runner.vdb
new file mode 100644
index 0000000000000000000000000000000000000000..e7157e49f5bd55f8f0fb72ce5b2bc1bb57a5f6c7
Binary files /dev/null and b/game.sim/sim_1/behav/xsim/xsim.dir/xil_defaultlib/runner.vdb differ
diff --git a/game.sim/sim_1/behav/xsim/xsim.dir/xil_defaultlib/topmodule.vdb b/game.sim/sim_1/behav/xsim/xsim.dir/xil_defaultlib/topmodule.vdb
new file mode 100644
index 0000000000000000000000000000000000000000..680f12312d336c7885c1ab2283b5636ef8b58ef3
Binary files /dev/null and b/game.sim/sim_1/behav/xsim/xsim.dir/xil_defaultlib/topmodule.vdb differ
diff --git a/game.sim/sim_1/behav/xsim/xsim.dir/xil_defaultlib/topmodule_tb.vdb b/game.sim/sim_1/behav/xsim/xsim.dir/xil_defaultlib/topmodule_tb.vdb
new file mode 100644
index 0000000000000000000000000000000000000000..ff6fc3f9c0a3acef16b5668646a4e81e53052d03
Binary files /dev/null and b/game.sim/sim_1/behav/xsim/xsim.dir/xil_defaultlib/topmodule_tb.vdb differ
diff --git a/game.sim/sim_1/behav/xsim/xsim.dir/xil_defaultlib/vga.vdb b/game.sim/sim_1/behav/xsim/xsim.dir/xil_defaultlib/vga.vdb
new file mode 100644
index 0000000000000000000000000000000000000000..c771ad4bb4b270ebf43b9350e3c5cbff978527aa
Binary files /dev/null and b/game.sim/sim_1/behav/xsim/xsim.dir/xil_defaultlib/vga.vdb differ
diff --git a/game.sim/sim_1/behav/xsim/xsim.dir/xil_defaultlib/xil_defaultlib.rlx b/game.sim/sim_1/behav/xsim/xsim.dir/xil_defaultlib/xil_defaultlib.rlx
new file mode 100644
index 0000000000000000000000000000000000000000..468baefb98617970dd1edec6632bad563e3869bb
--- /dev/null
+++ b/game.sim/sim_1/behav/xsim/xsim.dir/xil_defaultlib/xil_defaultlib.rlx
@@ -0,0 +1,12 @@
+0.7
+2020.2
+Oct 14 2022
+05:07:14
+/home/prasic/game/game.gen/sources_1/ip/clk_wiz_0/clk_wiz_0_sim_netlist.vhdl,1677491212,vhdl,,,,clk_wiz_0;clk_wiz_0_clk_wiz,,,,,,,,
+/home/prasic/game/game.sim/sim_1/behav/xsim/glbl.v,1665704903,verilog,,,,glbl,,,,,,,,
+/home/prasic/game/game.srcs/sim_1/new/TopModule_tb.vhd,1677574173,vhdl,,,,topmodule_tb,,,,,,,,
+/home/prasic/game/game.srcs/sources_1/new/TopModule.vhd,1677572796,vhdl,,,,topmodule,,,,,,,,
+/home/prasic/game/game.srcs/sources_1/new/background.vhd,1677512568,vhdl,,,,background,,,,,,,,
+/home/prasic/game/game.srcs/sources_1/new/priority.vhd,1677512351,vhdl,,,,priority,,,,,,,,
+/home/prasic/game/game.srcs/sources_1/new/runner.vhd,1677585676,vhdl,,,,runner,,,,,,,,
+/home/prasic/game/game.srcs/sources_1/new/vga.vhd,1677505217,vhdl,,,,vga,,,,,,,,
diff --git a/game.sim/sim_1/behav/xsim/xsim.ini b/game.sim/sim_1/behav/xsim/xsim.ini
new file mode 100644
index 0000000000000000000000000000000000000000..b80378eeddd5196a846bc727f7a7cc03b1a637bc
--- /dev/null
+++ b/game.sim/sim_1/behav/xsim/xsim.ini
@@ -0,0 +1,498 @@
+std=$RDI_DATADIR/xsim/vhdl/std
+ieee=$RDI_DATADIR/xsim/vhdl/ieee
+ieee_proposed=$RDI_DATADIR/xsim/vhdl/ieee_proposed
+vl=$RDI_DATADIR/xsim/vhdl/vl
+synopsys=$RDI_DATADIR/xsim/vhdl/synopsys
+uvm=$RDI_DATADIR/xsim/system_verilog/uvm
+secureip=$RDI_DATADIR/xsim/verilog/secureip
+unisim=$RDI_DATADIR/xsim/vhdl/unisim
+unimacro=$RDI_DATADIR/xsim/vhdl/unimacro
+unifast=$RDI_DATADIR/xsim/vhdl/unifast
+unisims_ver=$RDI_DATADIR/xsim/verilog/unisims_ver
+unimacro_ver=$RDI_DATADIR/xsim/verilog/unimacro_ver
+unifast_ver=$RDI_DATADIR/xsim/verilog/unifast_ver
+simprims_ver=$RDI_DATADIR/xsim/verilog/simprims_ver
+ilknf_v1_2_0=$RDI_DATADIR/xsim/ip/ilknf_v1_2_0
+pci64_v5_0_11=$RDI_DATADIR/xsim/ip/pci64_v5_0_11
+axis_ila_txns_cntr_v1_0_0=$RDI_DATADIR/xsim/ip/axis_ila_txns_cntr_v1_0_0
+qdriv_pl_v1_0_8=$RDI_DATADIR/xsim/ip/qdriv_pl_v1_0_8
+axis_switch_sc_v1_1=$RDI_DATADIR/xsim/ip/axis_switch_sc_v1_1
+uram_rd_back_v1_0_2=$RDI_DATADIR/xsim/ip/uram_rd_back_v1_0_2
+interlaken_v2_4_12=$RDI_DATADIR/xsim/ip/interlaken_v2_4_12
+axis_register_slice_v1_1_27=$RDI_DATADIR/xsim/ip/axis_register_slice_v1_1_27
+c_gate_bit_v12_0_6=$RDI_DATADIR/xsim/ip/c_gate_bit_v12_0_6
+cmac_v2_6_8=$RDI_DATADIR/xsim/ip/cmac_v2_6_8
+axi_bram_ctrl_v4_1_7=$RDI_DATADIR/xsim/ip/axi_bram_ctrl_v4_1_7
+tmr_inject_v1_0_4=$RDI_DATADIR/xsim/ip/tmr_inject_v1_0_4
+mdm_v3_2_23=$RDI_DATADIR/xsim/ip/mdm_v3_2_23
+axi_quad_spi_v3_2_26=$RDI_DATADIR/xsim/ip/axi_quad_spi_v3_2_26
+noc_npp_rptr_v1_0_0=$RDI_DATADIR/xsim/ip/noc_npp_rptr_v1_0_0
+xlconcat_v2_1_4=$RDI_DATADIR/xsim/ip/xlconcat_v2_1_4
+xbip_multadd_v3_0_17=$RDI_DATADIR/xsim/ip/xbip_multadd_v3_0_17
+c_counter_binary_v12_0_15=$RDI_DATADIR/xsim/ip/c_counter_binary_v12_0_15
+ieee802d3_200g_rs_fec_v2_0_6=$RDI_DATADIR/xsim/ip/ieee802d3_200g_rs_fec_v2_0_6
+dsp_macro_v1_0_2=$RDI_DATADIR/xsim/ip/dsp_macro_v1_0_2
+cmac_usplus_v3_1_10=$RDI_DATADIR/xsim/ip/cmac_usplus_v3_1_10
+noc2_nsu_v1_0_0=$RDI_DATADIR/xsim/ip/noc2_nsu_v1_0_0
+sid_v8_0_17=$RDI_DATADIR/xsim/ip/sid_v8_0_17
+v_frmbuf_wr_v2_4_0=$RDI_DATADIR/xsim/ip/v_frmbuf_wr_v2_4_0
+axi_pcie3_v3_0_23=$RDI_DATADIR/xsim/ip/axi_pcie3_v3_0_23
+axi_mmu_v2_1_25=$RDI_DATADIR/xsim/ip/axi_mmu_v2_1_25
+axis_data_fifo_v2_0_9=$RDI_DATADIR/xsim/ip/axis_data_fifo_v2_0_9
+jtag_axi=$RDI_DATADIR/xsim/ip/jtag_axi
+quadsgmii_v3_5_9=$RDI_DATADIR/xsim/ip/quadsgmii_v3_5_9
+g975_efec_i7_v2_0_19=$RDI_DATADIR/xsim/ip/g975_efec_i7_v2_0_19
+audio_tpg_v1_0_0=$RDI_DATADIR/xsim/ip/audio_tpg_v1_0_0
+axi_c2c_v1_0_4=$RDI_DATADIR/xsim/ip/axi_c2c_v1_0_4
+emc_common_v3_0_5=$RDI_DATADIR/xsim/ip/emc_common_v3_0_5
+ptp_1588_timer_syncer_v2_0_4=$RDI_DATADIR/xsim/ip/ptp_1588_timer_syncer_v2_0_4
+xdfe_cc_mixer_v2_0_0=$RDI_DATADIR/xsim/ip/xdfe_cc_mixer_v2_0_0
+xtlm=$RDI_DATADIR/xsim/ip/xtlm
+pcie_axi4lite_tap_v1_0_1=$RDI_DATADIR/xsim/ip/pcie_axi4lite_tap_v1_0_1
+hdcp22_rng_v1_0_1=$RDI_DATADIR/xsim/ip/hdcp22_rng_v1_0_1
+axi_ethernet_buffer_v2_0_24=$RDI_DATADIR/xsim/ip/axi_ethernet_buffer_v2_0_24
+v_vid_in_axi4s_v4_0_9=$RDI_DATADIR/xsim/ip/v_vid_in_axi4s_v4_0_9
+axi_firewall_v1_1_6=$RDI_DATADIR/xsim/ip/axi_firewall_v1_1_6
+sim_ipc_multi_intf_v1_0=$RDI_DATADIR/xsim/ip/sim_ipc_multi_intf_v1_0
+axis_subset_converter_v1_1_27=$RDI_DATADIR/xsim/ip/axis_subset_converter_v1_1_27
+videoaxi4s_bridge_v1_0_5=$RDI_DATADIR/xsim/ip/videoaxi4s_bridge_v1_0_5
+ieee802d3_400g_rs_fec_v2_0_9=$RDI_DATADIR/xsim/ip/ieee802d3_400g_rs_fec_v2_0_9
+axi_timer_v2_0_29=$RDI_DATADIR/xsim/ip/axi_timer_v2_0_29
+noc2_xbr4x2_v1_0_0=$RDI_DATADIR/xsim/ip/noc2_xbr4x2_v1_0_0
+remote_port_sc_v4=$RDI_DATADIR/xsim/ip/remote_port_sc_v4
+axi_tft_v2_0_25=$RDI_DATADIR/xsim/ip/axi_tft_v2_0_25
+v_smpte_uhdsdi_tx_v1_0_2=$RDI_DATADIR/xsim/ip/v_smpte_uhdsdi_tx_v1_0_2
+pc_cfr_v7_2_0=$RDI_DATADIR/xsim/ip/pc_cfr_v7_2_0
+v_frmbuf_rd_v2_4_0=$RDI_DATADIR/xsim/ip/v_frmbuf_rd_v2_4_0
+g709_rs_decoder_v2_2_10=$RDI_DATADIR/xsim/ip/g709_rs_decoder_v2_2_10
+axi_msg_v1_0_8=$RDI_DATADIR/xsim/ip/axi_msg_v1_0_8
+dprx_fec_8b10b_v1_0_1=$RDI_DATADIR/xsim/ip/dprx_fec_8b10b_v1_0_1
+v_dp_axi4s_vid_out_v1_0_5=$RDI_DATADIR/xsim/ip/v_dp_axi4s_vid_out_v1_0_5
+v_scenechange_v1_1_4=$RDI_DATADIR/xsim/ip/v_scenechange_v1_1_4
+versal_cips_v3_3_0=$RDI_DATADIR/xsim/ip/versal_cips_v3_3_0
+axi_register_slice_v2_1_27=$RDI_DATADIR/xsim/ip/axi_register_slice_v2_1_27
+axis_dwidth_converter_v1_1_26=$RDI_DATADIR/xsim/ip/axis_dwidth_converter_v1_1_26
+mipi_dphy_v4_3_5=$RDI_DATADIR/xsim/ip/mipi_dphy_v4_3_5
+system_cache_v5_0_8=$RDI_DATADIR/xsim/ip/system_cache_v5_0_8
+axi_pmon_v1_0_0=$RDI_DATADIR/xsim/ip/axi_pmon_v1_0_0
+oddr_v1_0_2=$RDI_DATADIR/xsim/ip/oddr_v1_0_2
+vitis_net_p4_v1_2_0=$RDI_DATADIR/xsim/ip/vitis_net_p4_v1_2_0
+smartconnect_v1_0=$RDI_DATADIR/xsim/ip/smartconnect_v1_0
+axis_switch_v1_1_27=$RDI_DATADIR/xsim/ip/axis_switch_v1_1_27
+v_frmbuf_wr_v2_3_2=$RDI_DATADIR/xsim/ip/v_frmbuf_wr_v2_3_2
+cmpy_v6_0_21=$RDI_DATADIR/xsim/ip/cmpy_v6_0_21
+common_rpc_v1=$RDI_DATADIR/xsim/ip/common_rpc_v1
+gtwizard_ultrascale_v1_5_4=$RDI_DATADIR/xsim/ip/gtwizard_ultrascale_v1_5_4
+debug_tcp_server_v1=$RDI_DATADIR/xsim/ip/debug_tcp_server_v1
+v_tpg_v8_1_6=$RDI_DATADIR/xsim/ip/v_tpg_v8_1_6
+mipi_csi2_tx_ctrl_v1_0_4=$RDI_DATADIR/xsim/ip/mipi_csi2_tx_ctrl_v1_0_4
+floating_point_v7_0_20=$RDI_DATADIR/xsim/ip/floating_point_v7_0_20
+mpegtsmux_v1_1_5=$RDI_DATADIR/xsim/ip/mpegtsmux_v1_1_5
+noc_nps4_v1_0_0=$RDI_DATADIR/xsim/ip/noc_nps4_v1_0_0
+an_lt_v1_0_7=$RDI_DATADIR/xsim/ip/an_lt_v1_0_7
+picxo=$RDI_DATADIR/xsim/ip/picxo
+axi_bram_ctrl_v4_0_14=$RDI_DATADIR/xsim/ip/axi_bram_ctrl_v4_0_14
+axi_vdma_v6_3_15=$RDI_DATADIR/xsim/ip/axi_vdma_v6_3_15
+dbg_intf=$RDI_DATADIR/xsim/ip/dbg_intf
+xsdbs_v1_0_2=$RDI_DATADIR/xsim/ip/xsdbs_v1_0_2
+v_axi4s_remap_v1_0_20=$RDI_DATADIR/xsim/ip/v_axi4s_remap_v1_0_20
+pc_cfr_v6_4_2=$RDI_DATADIR/xsim/ip/pc_cfr_v6_4_2
+v_csc_v1_1_6=$RDI_DATADIR/xsim/ip/v_csc_v1_1_6
+xbip_addsub_v3_0_6=$RDI_DATADIR/xsim/ip/xbip_addsub_v3_0_6
+vitis_deadlock_detector_v1_0_1=$RDI_DATADIR/xsim/ip/vitis_deadlock_detector_v1_0_1
+vid_edid_v1_0_0=$RDI_DATADIR/xsim/ip/vid_edid_v1_0_0
+axi4svideo_bridge_v1_0_15=$RDI_DATADIR/xsim/ip/axi4svideo_bridge_v1_0_15
+ethernet_1_10_25g_v2_7_6=$RDI_DATADIR/xsim/ip/ethernet_1_10_25g_v2_7_6
+xdfe_cc_filter_v1_1_0=$RDI_DATADIR/xsim/ip/xdfe_cc_filter_v1_1_0
+axi_clock_converter_v2_1_26=$RDI_DATADIR/xsim/ip/axi_clock_converter_v2_1_26
+axi_hwicap_v3_0_31=$RDI_DATADIR/xsim/ip/axi_hwicap_v3_0_31
+xscl=$RDI_DATADIR/xsim/ip/xscl
+noc_nsu_v1_0_0=$RDI_DATADIR/xsim/ip/noc_nsu_v1_0_0
+fec_5g_common_v1_1_1=$RDI_DATADIR/xsim/ip/fec_5g_common_v1_1_1
+in_system_ibert_v1_0_17=$RDI_DATADIR/xsim/ip/in_system_ibert_v1_0_17
+displayport_v8_1_5=$RDI_DATADIR/xsim/ip/displayport_v8_1_5
+bs_switch_v1_0_1=$RDI_DATADIR/xsim/ip/bs_switch_v1_0_1
+sim_cpu_v1_0=$RDI_DATADIR/xsim/ip/sim_cpu_v1_0
+dfx_controller_v1_0_3=$RDI_DATADIR/xsim/ip/dfx_controller_v1_0_3
+polar_v1_0_10=$RDI_DATADIR/xsim/ip/polar_v1_0_10
+axi_sideband_util_v1_0_11=$RDI_DATADIR/xsim/ip/axi_sideband_util_v1_0_11
+ltlib_v1_0_0=$RDI_DATADIR/xsim/ip/ltlib_v1_0_0
+shell_utils_msp432_bsl_crc_gen_v1_0_0=$RDI_DATADIR/xsim/ip/shell_utils_msp432_bsl_crc_gen_v1_0_0
+adc_dac_if_phy_v1_0_0=$RDI_DATADIR/xsim/ip/adc_dac_if_phy_v1_0_0
+hdcp22_cipher_v1_0_3=$RDI_DATADIR/xsim/ip/hdcp22_cipher_v1_0_3
+axi_uartlite_v2_0_31=$RDI_DATADIR/xsim/ip/axi_uartlite_v2_0_31
+audio_clock_recovery_unit_v1_0_2=$RDI_DATADIR/xsim/ip/audio_clock_recovery_unit_v1_0_2
+g709_rs_encoder_v2_2_8=$RDI_DATADIR/xsim/ip/g709_rs_encoder_v2_2_8
+v_smpte_uhdsdi_v1_0_9=$RDI_DATADIR/xsim/ip/v_smpte_uhdsdi_v1_0_9
+zynq_ultra_ps_e_v3_4_1=$RDI_DATADIR/xsim/ip/zynq_ultra_ps_e_v3_4_1
+v_multi_scaler_v1_2_3=$RDI_DATADIR/xsim/ip/v_multi_scaler_v1_2_3
+nvme_tc_v3_0_2=$RDI_DATADIR/xsim/ip/nvme_tc_v3_0_2
+axi_iic_v2_1_3=$RDI_DATADIR/xsim/ip/axi_iic_v2_1_3
+bs_mux_v1_0_0=$RDI_DATADIR/xsim/ip/bs_mux_v1_0_0
+sim_qdma_cpp_v1_0=$RDI_DATADIR/xsim/ip/sim_qdma_cpp_v1_0
+aurora_8b10b_versal_v1_0_1=$RDI_DATADIR/xsim/ip/aurora_8b10b_versal_v1_0_1
+rld3_pl_phy_v1_0_0=$RDI_DATADIR/xsim/ip/rld3_pl_phy_v1_0_0
+remote_port_c_v4=$RDI_DATADIR/xsim/ip/remote_port_c_v4
+util_ff_v1_0_1=$RDI_DATADIR/xsim/ip/util_ff_v1_0_1
+xbip_dsp48_wrapper_v3_0_4=$RDI_DATADIR/xsim/ip/xbip_dsp48_wrapper_v3_0_4
+mem_pl_v1_0_0=$RDI_DATADIR/xsim/ip/mem_pl_v1_0_0
+dft_v4_0_16=$RDI_DATADIR/xsim/ip/dft_v4_0_16
+axi_sg_v4_1_15=$RDI_DATADIR/xsim/ip/axi_sg_v4_1_15
+xdfe_equalizer_v1_0_5=$RDI_DATADIR/xsim/ip/xdfe_equalizer_v1_0_5
+v_vid_gt_bridge_v2_0_0=$RDI_DATADIR/xsim/ip/v_vid_gt_bridge_v2_0_0
+sim_trig_v1_0_8=$RDI_DATADIR/xsim/ip/sim_trig_v1_0_8
+axi_stream_monitor_v1_1_0=$RDI_DATADIR/xsim/ip/axi_stream_monitor_v1_1_0
+axi_gpio_v2_0_29=$RDI_DATADIR/xsim/ip/axi_gpio_v2_0_29
+axi_memory_init_v1_0_8=$RDI_DATADIR/xsim/ip/axi_memory_init_v1_0_8
+c_reg_fd_v12_0_6=$RDI_DATADIR/xsim/ip/c_reg_fd_v12_0_6
+stm_v1_0=$RDI_DATADIR/xsim/ip/stm_v1_0
+sem_ultra_v3_1_24=$RDI_DATADIR/xsim/ip/sem_ultra_v3_1_24
+axi_vip_v1_1_13=$RDI_DATADIR/xsim/ip/axi_vip_v1_1_13
+axis_broadcaster_v1_1_26=$RDI_DATADIR/xsim/ip/axis_broadcaster_v1_1_26
+gig_ethernet_pcs_pma_v16_2_9=$RDI_DATADIR/xsim/ip/gig_ethernet_pcs_pma_v16_2_9
+tcc_decoder_3gpplte_v3_0_6=$RDI_DATADIR/xsim/ip/tcc_decoder_3gpplte_v3_0_6
+axi_data_fifo_v2_1_26=$RDI_DATADIR/xsim/ip/axi_data_fifo_v2_1_26
+ernic_v3_1_2=$RDI_DATADIR/xsim/ip/ernic_v3_1_2
+axis_dbg_sync_v1_0_0=$RDI_DATADIR/xsim/ip/axis_dbg_sync_v1_0_0
+ten_gig_eth_pcs_pma_v6_0_23=$RDI_DATADIR/xsim/ip/ten_gig_eth_pcs_pma_v6_0_23
+lmb_bram_if_cntlr_v4_0_21=$RDI_DATADIR/xsim/ip/lmb_bram_if_cntlr_v4_0_21
+axi_usb2_device_v5_0_28=$RDI_DATADIR/xsim/ip/axi_usb2_device_v5_0_28
+pc_cfr_v7_1_0=$RDI_DATADIR/xsim/ip/pc_cfr_v7_1_0
+rs_decoder_v9_0_18=$RDI_DATADIR/xsim/ip/rs_decoder_v9_0_18
+cam_v2_4_0=$RDI_DATADIR/xsim/ip/cam_v2_4_0
+ll_compress_v1_1_0=$RDI_DATADIR/xsim/ip/ll_compress_v1_1_0
+v_tc_v6_1_13=$RDI_DATADIR/xsim/ip/v_tc_v6_1_13
+cpm5_v1_0_9=$RDI_DATADIR/xsim/ip/cpm5_v1_0_9
+hsdp_trace_v1_0_0=$RDI_DATADIR/xsim/ip/hsdp_trace_v1_0_0
+tmr_comparator_v1_0_5=$RDI_DATADIR/xsim/ip/tmr_comparator_v1_0_5
+axi_ethernetlite_v3_0_26=$RDI_DATADIR/xsim/ip/axi_ethernetlite_v3_0_26
+lib_bmg_v1_0_14=$RDI_DATADIR/xsim/ip/lib_bmg_v1_0_14
+audio_formatter_v1_0_9=$RDI_DATADIR/xsim/ip/audio_formatter_v1_0_9
+axi_epc_v2_0_30=$RDI_DATADIR/xsim/ip/axi_epc_v2_0_30
+xbip_counter_v3_0_6=$RDI_DATADIR/xsim/ip/xbip_counter_v3_0_6
+xfft_v9_1_8=$RDI_DATADIR/xsim/ip/xfft_v9_1_8
+microblaze_v9_5_4=$RDI_DATADIR/xsim/ip/microblaze_v9_5_4
+blk_mem_gen_v8_4_5=$RDI_DATADIR/xsim/ip/blk_mem_gen_v8_4_5
+sim_xdma_sc_v1=$RDI_DATADIR/xsim/ip/sim_xdma_sc_v1
+proc_sys_reset_v5_0_13=$RDI_DATADIR/xsim/ip/proc_sys_reset_v5_0_13
+v_tpg_v8_0_10=$RDI_DATADIR/xsim/ip/v_tpg_v8_0_10
+hdmi_acr_ctrl_v1_0_0=$RDI_DATADIR/xsim/ip/hdmi_acr_ctrl_v1_0_0
+v_mix_v5_2_4=$RDI_DATADIR/xsim/ip/v_mix_v5_2_4
+flexo_100g_rs_fec_v1_0_23=$RDI_DATADIR/xsim/ip/flexo_100g_rs_fec_v1_0_23
+amm_axi_bridge_v1_0_13=$RDI_DATADIR/xsim/ip/amm_axi_bridge_v1_0_13
+axi_uart16550_v2_0_29=$RDI_DATADIR/xsim/ip/axi_uart16550_v2_0_29
+hw_trace=$RDI_DATADIR/xsim/ip/hw_trace
+axis_clock_converter_v1_1_28=$RDI_DATADIR/xsim/ip/axis_clock_converter_v1_1_28
+xpm=$RDI_DATADIR/xsim/ip/xpm
+versal_cips_ps_vip_v1_0_5=$RDI_DATADIR/xsim/ip/versal_cips_ps_vip_v1_0_5
+noc_nmu_phydir_v1_0_0=$RDI_DATADIR/xsim/ip/noc_nmu_phydir_v1_0_0
+roe_framer_v3_0_4=$RDI_DATADIR/xsim/ip/roe_framer_v3_0_4
+soft_ecc_proxy_v1_0_1=$RDI_DATADIR/xsim/ip/soft_ecc_proxy_v1_0_1
+fifo_generator_v13_1_4=$RDI_DATADIR/xsim/ip/fifo_generator_v13_1_4
+axis_combiner_v1_1_25=$RDI_DATADIR/xsim/ip/axis_combiner_v1_1_25
+switch_core_top_v1_0_11=$RDI_DATADIR/xsim/ip/switch_core_top_v1_0_11
+noc_ncrb_v1_0_0=$RDI_DATADIR/xsim/ip/noc_ncrb_v1_0_0
+axis_ila_adv_trig_v1_0_0=$RDI_DATADIR/xsim/ip/axis_ila_adv_trig_v1_0_0
+axi_ahblite_bridge_v3_0_24=$RDI_DATADIR/xsim/ip/axi_ahblite_bridge_v3_0_24
+accelerator_monitor_v1_1_0=$RDI_DATADIR/xsim/ip/accelerator_monitor_v1_1_0
+cpm5n_v1_0_1=$RDI_DATADIR/xsim/ip/cpm5n_v1_0_1
+lte_fft_v2_1_6=$RDI_DATADIR/xsim/ip/lte_fft_v2_1_6
+axi_fifo_mm_s_v4_2_9=$RDI_DATADIR/xsim/ip/axi_fifo_mm_s_v4_2_9
+axi_intc_v4_1_17=$RDI_DATADIR/xsim/ip/axi_intc_v4_1_17
+xbip_bram18k_v3_0_6=$RDI_DATADIR/xsim/ip/xbip_bram18k_v3_0_6
+trace_s2mm_v2_0_0=$RDI_DATADIR/xsim/ip/trace_s2mm_v2_0_0
+vid_phy_controller_v2_1_14=$RDI_DATADIR/xsim/ip/vid_phy_controller_v2_1_14
+ats_switch_v1_0_6=$RDI_DATADIR/xsim/ip/ats_switch_v1_0_6
+ahblite_axi_bridge_v3_0_22=$RDI_DATADIR/xsim/ip/ahblite_axi_bridge_v3_0_22
+multi_channel_25g_rs_fec_v1_0_19=$RDI_DATADIR/xsim/ip/multi_channel_25g_rs_fec_v1_0_19
+xpm_cdc_gen_v1_0_2=$RDI_DATADIR/xsim/ip/xpm_cdc_gen_v1_0_2
+sim_xdma_cpp_v1=$RDI_DATADIR/xsim/ip/sim_xdma_cpp_v1
+dfx_axi_shutdown_manager_v1_0_0=$RDI_DATADIR/xsim/ip/dfx_axi_shutdown_manager_v1_0_0
+uhdsdi_gt_v2_0_9=$RDI_DATADIR/xsim/ip/uhdsdi_gt_v2_0_9
+noc_mc_ddr5_phy_v1_0_0=$RDI_DATADIR/xsim/ip/noc_mc_ddr5_phy_v1_0_0
+axi_jtag_v1_0_0=$RDI_DATADIR/xsim/ip/axi_jtag_v1_0_0
+oran_radio_if_v2_3_0=$RDI_DATADIR/xsim/ip/oran_radio_if_v2_3_0
+noc2_nps_v1_0_0=$RDI_DATADIR/xsim/ip/noc2_nps_v1_0_0
+fast_adapter_v1_0_4=$RDI_DATADIR/xsim/ip/fast_adapter_v1_0_4
+mdm_v3_2=$RDI_DATADIR/xsim/ip/mdm_v3_2
+v_deinterlacer_v5_1_0=$RDI_DATADIR/xsim/ip/v_deinterlacer_v5_1_0
+ta_dma_v1_0_11=$RDI_DATADIR/xsim/ip/ta_dma_v1_0_11
+xbip_dsp48_multacc_v3_0_6=$RDI_DATADIR/xsim/ip/xbip_dsp48_multacc_v3_0_6
+ll_compress_v2_1_1=$RDI_DATADIR/xsim/ip/ll_compress_v2_1_1
+l_ethernet_v3_3_1=$RDI_DATADIR/xsim/ip/l_ethernet_v3_3_1
+mipi_csi2_rx_ctrl_v1_0_8=$RDI_DATADIR/xsim/ip/mipi_csi2_rx_ctrl_v1_0_8
+v_axi4s_remap_v1_1_6=$RDI_DATADIR/xsim/ip/v_axi4s_remap_v1_1_6
+generic_baseblocks_v2_1_0=$RDI_DATADIR/xsim/ip/generic_baseblocks_v2_1_0
+v_mix_v5_1_6=$RDI_DATADIR/xsim/ip/v_mix_v5_1_6
+axi_remapper_rx_v1_0_0=$RDI_DATADIR/xsim/ip/axi_remapper_rx_v1_0_0
+axi_pcie_v2_9_8=$RDI_DATADIR/xsim/ip/axi_pcie_v2_9_8
+emu_perf_common_v1_0=$RDI_DATADIR/xsim/ip/emu_perf_common_v1_0
+v_hdmi_rx1_v1_0_4=$RDI_DATADIR/xsim/ip/v_hdmi_rx1_v1_0_4
+v_hdmi_tx1_v1_0_4=$RDI_DATADIR/xsim/ip/v_hdmi_tx1_v1_0_4
+lib_srl_fifo_v1_0_2=$RDI_DATADIR/xsim/ip/lib_srl_fifo_v1_0_2
+clk_gen_sim_v1_0_3=$RDI_DATADIR/xsim/ip/clk_gen_sim_v1_0_3
+dds_compiler_v6_0_22=$RDI_DATADIR/xsim/ip/dds_compiler_v6_0_22
+mem_tg_v1_0_9=$RDI_DATADIR/xsim/ip/mem_tg_v1_0_9
+axi_chip2chip_v5_0_16=$RDI_DATADIR/xsim/ip/axi_chip2chip_v5_0_16
+axis_ila_ct_v1_0_0=$RDI_DATADIR/xsim/ip/axis_ila_ct_v1_0_0
+v_hcresampler_v1_1_6=$RDI_DATADIR/xsim/ip/v_hcresampler_v1_1_6
+util_vector_logic_v2_0_2=$RDI_DATADIR/xsim/ip/util_vector_logic_v2_0_2
+axis_dbg_stub_v1_0_0=$RDI_DATADIR/xsim/ip/axis_dbg_stub_v1_0_0
+axi_amm_bridge_v1_0_17=$RDI_DATADIR/xsim/ip/axi_amm_bridge_v1_0_17
+cic_compiler_v4_0_16=$RDI_DATADIR/xsim/ip/cic_compiler_v4_0_16
+axi_interconnect_v1_7_20=$RDI_DATADIR/xsim/ip/axi_interconnect_v1_7_20
+axis_interconnect_v1_1_20=$RDI_DATADIR/xsim/ip/axis_interconnect_v1_1_20
+fir_compiler_v7_2_18=$RDI_DATADIR/xsim/ip/fir_compiler_v7_2_18
+iomodule_v3_0=$RDI_DATADIR/xsim/ip/iomodule_v3_0
+common_cpp_v1_0=$RDI_DATADIR/xsim/ip/common_cpp_v1_0
+pr_decoupler_v1_0_10=$RDI_DATADIR/xsim/ip/pr_decoupler_v1_0_10
+v_warp_filter_v1_1_1=$RDI_DATADIR/xsim/ip/v_warp_filter_v1_1_1
+xbip_pipe_v3_0_6=$RDI_DATADIR/xsim/ip/xbip_pipe_v3_0_6
+xdfe_nlf_v1_0_2=$RDI_DATADIR/xsim/ip/xdfe_nlf_v1_0_2
+mipi_dsi_tx_ctrl_v1_0_7=$RDI_DATADIR/xsim/ip/mipi_dsi_tx_ctrl_v1_0_7
+xilinx_vip=$RDI_DATADIR/xsim/ip/xilinx_vip
+axis_ila_intf_v1_0_0=$RDI_DATADIR/xsim/ip/axis_ila_intf_v1_0_0
+i2s_transmitter_v1_0_5=$RDI_DATADIR/xsim/ip/i2s_transmitter_v1_0_5
+axi_tg_sc_v1_0=$RDI_DATADIR/xsim/ip/axi_tg_sc_v1_0
+ll_compress_v1_0_0=$RDI_DATADIR/xsim/ip/ll_compress_v1_0_0
+trace_hub_v1_1_0=$RDI_DATADIR/xsim/ip/trace_hub_v1_1_0
+c_shift_ram_v12_0_14=$RDI_DATADIR/xsim/ip/c_shift_ram_v12_0_14
+axi_datamover_v5_1_29=$RDI_DATADIR/xsim/ip/axi_datamover_v5_1_29
+pcie_qdma_mailbox_v1_0_0=$RDI_DATADIR/xsim/ip/pcie_qdma_mailbox_v1_0_0
+ptp_1588_timer_syncer_v1_0_2=$RDI_DATADIR/xsim/ip/ptp_1588_timer_syncer_v1_0_2
+fc32_rs_fec_v1_0_22=$RDI_DATADIR/xsim/ip/fc32_rs_fec_v1_0_22
+axi_vfifo_ctrl_v2_0_29=$RDI_DATADIR/xsim/ip/axi_vfifo_ctrl_v2_0_29
+xtlm_ap_ctrl_v1_0=$RDI_DATADIR/xsim/ip/xtlm_ap_ctrl_v1_0
+icap_arb_v1_0_1=$RDI_DATADIR/xsim/ip/icap_arb_v1_0_1
+sim_rst_gen_v1_0_2=$RDI_DATADIR/xsim/ip/sim_rst_gen_v1_0_2
+tcc_encoder_3gpplte_v4_0_16=$RDI_DATADIR/xsim/ip/tcc_encoder_3gpplte_v4_0_16
+axis_mu_v1_0_0=$RDI_DATADIR/xsim/ip/axis_mu_v1_0_0
+bsip_v1_1_0=$RDI_DATADIR/xsim/ip/bsip_v1_1_0
+gtwizard_ultrascale_v1_6_14=$RDI_DATADIR/xsim/ip/gtwizard_ultrascale_v1_6_14
+lib_pkg_v1_0_2=$RDI_DATADIR/xsim/ip/lib_pkg_v1_0_2
+cpri_v8_11_13=$RDI_DATADIR/xsim/ip/cpri_v8_11_13
+interrupt_control_v3_1_4=$RDI_DATADIR/xsim/ip/interrupt_control_v3_1_4
+v_uhdsdi_audio_v2_0_6=$RDI_DATADIR/xsim/ip/v_uhdsdi_audio_v2_0_6
+dfx_decoupler_v1_0_5=$RDI_DATADIR/xsim/ip/dfx_decoupler_v1_0_5
+c_accum_v12_0_14=$RDI_DATADIR/xsim/ip/c_accum_v12_0_14
+axis_ila_pp_v1_0_0=$RDI_DATADIR/xsim/ip/axis_ila_pp_v1_0_0
+dcmac_v2_1_0=$RDI_DATADIR/xsim/ip/dcmac_v2_1_0
+dptx_v1_0_0=$RDI_DATADIR/xsim/ip/dptx_v1_0_0
+v_axi4s_vid_out_v4_0_15=$RDI_DATADIR/xsim/ip/v_axi4s_vid_out_v4_0_15
+lte_fft_v2_0_22=$RDI_DATADIR/xsim/ip/lte_fft_v2_0_22
+sd_fec_v1_1_10=$RDI_DATADIR/xsim/ip/sd_fec_v1_1_10
+axi_firewall_v1_2_2=$RDI_DATADIR/xsim/ip/axi_firewall_v1_2_2
+processing_system7_vip_v1_0_15=$RDI_DATADIR/xsim/ip/processing_system7_vip_v1_0_15
+axi4stream_vip_v1_1_13=$RDI_DATADIR/xsim/ip/axi4stream_vip_v1_1_13
+lut_buffer_v2_0_0=$RDI_DATADIR/xsim/ip/lut_buffer_v2_0_0
+timer_sync_1588_v1_2_4=$RDI_DATADIR/xsim/ip/timer_sync_1588_v1_2_4
+sim_ddr_v1_0=$RDI_DATADIR/xsim/ip/sim_ddr_v1_0
+v_smpte_uhdsdi_rx_v1_0_1=$RDI_DATADIR/xsim/ip/v_smpte_uhdsdi_rx_v1_0_1
+axi_intc_v4_1=$RDI_DATADIR/xsim/ip/axi_intc_v4_1
+axi_crossbar_v2_1_28=$RDI_DATADIR/xsim/ip/axi_crossbar_v2_1_28
+xbip_dsp48_multadd_v3_0_6=$RDI_DATADIR/xsim/ip/xbip_dsp48_multadd_v3_0_6
+axis_protocol_checker_v2_0_11=$RDI_DATADIR/xsim/ip/axis_protocol_checker_v2_0_11
+axi_interface_monitor_v1_1_0=$RDI_DATADIR/xsim/ip/axi_interface_monitor_v1_1_0
+v_uhdsdi_vidgen_v1_0_1=$RDI_DATADIR/xsim/ip/v_uhdsdi_vidgen_v1_0_1
+jesd204_v7_2_16=$RDI_DATADIR/xsim/ip/jesd204_v7_2_16
+dft_v4_2_3=$RDI_DATADIR/xsim/ip/dft_v4_2_3
+axi_dbg_hub=$RDI_DATADIR/xsim/ip/axi_dbg_hub
+v_vscaler_v1_1_6=$RDI_DATADIR/xsim/ip/v_vscaler_v1_1_6
+ddr4_pl_phy_v1_0_0=$RDI_DATADIR/xsim/ip/ddr4_pl_phy_v1_0_0
+av_pat_gen_v1_0_1=$RDI_DATADIR/xsim/ip/av_pat_gen_v1_0_1
+fifo_generator_v13_2_7=$RDI_DATADIR/xsim/ip/fifo_generator_v13_2_7
+srio_gen2_v4_1_15=$RDI_DATADIR/xsim/ip/srio_gen2_v4_1_15
+canfd_v3_0_6=$RDI_DATADIR/xsim/ip/canfd_v3_0_6
+tsn_temac_v1_0_7=$RDI_DATADIR/xsim/ip/tsn_temac_v1_0_7
+v_tc_v6_2_5=$RDI_DATADIR/xsim/ip/v_tc_v6_2_5
+v_dual_splitter_v1_0_9=$RDI_DATADIR/xsim/ip/v_dual_splitter_v1_0_9
+floating_point_v7_1_15=$RDI_DATADIR/xsim/ip/floating_point_v7_1_15
+xtlm_ipc_v1_0=$RDI_DATADIR/xsim/ip/xtlm_ipc_v1_0
+viterbi_v9_1_13=$RDI_DATADIR/xsim/ip/viterbi_v9_1_13
+axi_tlm_ext_v1_0=$RDI_DATADIR/xsim/ip/axi_tlm_ext_v1_0
+axi_lite_ipif_v3_0=$RDI_DATADIR/xsim/ip/axi_lite_ipif_v3_0
+xbip_accum_v3_0_6=$RDI_DATADIR/xsim/ip/xbip_accum_v3_0_6
+axis_itct_v1_0_0=$RDI_DATADIR/xsim/ip/axis_itct_v1_0_0
+rs_toolbox_v9_0_9=$RDI_DATADIR/xsim/ip/rs_toolbox_v9_0_9
+noc_nps6_v1_0_0=$RDI_DATADIR/xsim/ip/noc_nps6_v1_0_0
+ieee802d3_25g_rs_fec_v1_0_24=$RDI_DATADIR/xsim/ip/ieee802d3_25g_rs_fec_v1_0_24
+rld3_pl_v1_0_10=$RDI_DATADIR/xsim/ip/rld3_pl_v1_0_10
+gtwizard_ultrascale_v1_7_14=$RDI_DATADIR/xsim/ip/gtwizard_ultrascale_v1_7_14
+ai_pl=$RDI_DATADIR/xsim/ip/ai_pl
+v_vid_in_axi4s_v5_0_2=$RDI_DATADIR/xsim/ip/v_vid_in_axi4s_v5_0_2
+dp_videoaxi4s_bridge_v1_0_1=$RDI_DATADIR/xsim/ip/dp_videoaxi4s_bridge_v1_0_1
+qdma_v5_0_0=$RDI_DATADIR/xsim/ip/qdma_v5_0_0
+xbip_dsp48_mult_v3_0_6=$RDI_DATADIR/xsim/ip/xbip_dsp48_mult_v3_0_6
+axis_vio_v1_0_7=$RDI_DATADIR/xsim/ip/axis_vio_v1_0_7
+c_compare_v12_0_6=$RDI_DATADIR/xsim/ip/c_compare_v12_0_6
+spdif_v2_0_26=$RDI_DATADIR/xsim/ip/spdif_v2_0_26
+xdfe_common_v1_0_0=$RDI_DATADIR/xsim/ip/xdfe_common_v1_0_0
+tcc_decoder_3gppmm_v2_0_24=$RDI_DATADIR/xsim/ip/tcc_decoder_3gppmm_v2_0_24
+axi_timebase_wdt_v3_0_19=$RDI_DATADIR/xsim/ip/axi_timebase_wdt_v3_0_19
+pci32_v5_0_12=$RDI_DATADIR/xsim/ip/pci32_v5_0_12
+polar_v1_1_0=$RDI_DATADIR/xsim/ip/polar_v1_1_0
+fir_compiler_v5_2_6=$RDI_DATADIR/xsim/ip/fir_compiler_v5_2_6
+axis_data_fifo_v1_1_28=$RDI_DATADIR/xsim/ip/axis_data_fifo_v1_1_28
+hdmi_gt_controller_v1_0_8=$RDI_DATADIR/xsim/ip/hdmi_gt_controller_v1_0_8
+compact_gt_v1_0_13=$RDI_DATADIR/xsim/ip/compact_gt_v1_0_13
+axi_remapper_tx_v1_0_0=$RDI_DATADIR/xsim/ip/axi_remapper_tx_v1_0_0
+xbip_utils_v3_0_10=$RDI_DATADIR/xsim/ip/xbip_utils_v3_0_10
+anlt_subcore_ip_v1_0_0=$RDI_DATADIR/xsim/ip/anlt_subcore_ip_v1_0_0
+ieee802d3_50g_rs_fec_v1_0_20=$RDI_DATADIR/xsim/ip/ieee802d3_50g_rs_fec_v1_0_20
+tsn_endpoint_ethernet_mac_block_v1_0_12=$RDI_DATADIR/xsim/ip/tsn_endpoint_ethernet_mac_block_v1_0_12
+sim_clk_gen_v1_0_3=$RDI_DATADIR/xsim/ip/sim_clk_gen_v1_0_3
+can_v5_0_30=$RDI_DATADIR/xsim/ip/can_v5_0_30
+v_warp_init_v1_1_1=$RDI_DATADIR/xsim/ip/v_warp_init_v1_1_1
+perf_axi_tg_v1_0_9=$RDI_DATADIR/xsim/ip/perf_axi_tg_v1_0_9
+axi_epu_v1_0_0=$RDI_DATADIR/xsim/ip/axi_epu_v1_0_0
+gmii_to_rgmii_v4_1_5=$RDI_DATADIR/xsim/ip/gmii_to_rgmii_v4_1_5
+noc_nps_v1_0_0=$RDI_DATADIR/xsim/ip/noc_nps_v1_0_0
+advanced_io_wizard_v1_0_8=$RDI_DATADIR/xsim/ip/advanced_io_wizard_v1_0_8
+convolution_v9_0_16=$RDI_DATADIR/xsim/ip/convolution_v9_0_16
+axis_accelerator_adapter_v2_1_16=$RDI_DATADIR/xsim/ip/axis_accelerator_adapter_v2_1_16
+microblaze_mcs_v2_3_6=$RDI_DATADIR/xsim/ip/microblaze_mcs_v2_3_6
+axi_infrastructure_v1_1_0=$RDI_DATADIR/xsim/ip/axi_infrastructure_v1_1_0
+ai_pl_trig=$RDI_DATADIR/xsim/ip/ai_pl_trig
+axi_protocol_checker_v2_0_13=$RDI_DATADIR/xsim/ip/axi_protocol_checker_v2_0_13
+high_speed_selectio_wiz_v3_6_4=$RDI_DATADIR/xsim/ip/high_speed_selectio_wiz_v3_6_4
+xbip_dsp48_addsub_v3_0_6=$RDI_DATADIR/xsim/ip/xbip_dsp48_addsub_v3_0_6
+axi_traffic_gen_v3_0_13=$RDI_DATADIR/xsim/ip/axi_traffic_gen_v3_0_13
+ieee802d3_clause74_fec_v1_0_14=$RDI_DATADIR/xsim/ip/ieee802d3_clause74_fec_v1_0_14
+hdcp22_cipher_dp_v1_0_0=$RDI_DATADIR/xsim/ip/hdcp22_cipher_dp_v1_0_0
+axi_perf_mon_v5_0_29=$RDI_DATADIR/xsim/ip/axi_perf_mon_v5_0_29
+func_emu_util_v1_0=$RDI_DATADIR/xsim/ip/func_emu_util_v1_0
+clk_vip_v1_0_2=$RDI_DATADIR/xsim/ip/clk_vip_v1_0_2
+axis_infrastructure_v1_1_0=$RDI_DATADIR/xsim/ip/axis_infrastructure_v1_1_0
+c_mux_bit_v12_0_6=$RDI_DATADIR/xsim/ip/c_mux_bit_v12_0_6
+v_sdi_rx_vid_bridge_v2_0_0=$RDI_DATADIR/xsim/ip/v_sdi_rx_vid_bridge_v2_0_0
+sim_qdma_sc_v1_0=$RDI_DATADIR/xsim/ip/sim_qdma_sc_v1_0
+uhdsdi_gt_v2_1_0=$RDI_DATADIR/xsim/ip/uhdsdi_gt_v2_1_0
+util_reduced_logic_v2_0_4=$RDI_DATADIR/xsim/ip/util_reduced_logic_v2_0_4
+bscan_axi_v1_0_0=$RDI_DATADIR/xsim/ip/bscan_axi_v1_0_0
+v_hdmi_phy1_v1_0_7=$RDI_DATADIR/xsim/ip/v_hdmi_phy1_v1_0_7
+v_frmbuf_rd_v2_2_6=$RDI_DATADIR/xsim/ip/v_frmbuf_rd_v2_2_6
+noc_hbm_v1_0_0=$RDI_DATADIR/xsim/ip/noc_hbm_v1_0_0
+nvmeha_v1_0_8=$RDI_DATADIR/xsim/ip/nvmeha_v1_0_8
+pl_fileio_v1_0_0=$RDI_DATADIR/xsim/ip/pl_fileio_v1_0_0
+axi_apb_bridge_v3_0_17=$RDI_DATADIR/xsim/ip/axi_apb_bridge_v3_0_17
+tri_mode_ethernet_mac_v9_0_23=$RDI_DATADIR/xsim/ip/tri_mode_ethernet_mac_v9_0_23
+usxgmii_v1_2_8=$RDI_DATADIR/xsim/ip/usxgmii_v1_2_8
+axi_mcdma_v1_1_8=$RDI_DATADIR/xsim/ip/axi_mcdma_v1_1_8
+ibert_lib_v1_0_7=$RDI_DATADIR/xsim/ip/ibert_lib_v1_0_7
+axi_master_burst_v2_0_7=$RDI_DATADIR/xsim/ip/axi_master_burst_v2_0_7
+aie_xtlm_v1_0_0=$RDI_DATADIR/xsim/ip/aie_xtlm_v1_0_0
+tcc_encoder_3gpp_v5_0_18=$RDI_DATADIR/xsim/ip/tcc_encoder_3gpp_v5_0_18
+xdma_v4_1_20=$RDI_DATADIR/xsim/ip/xdma_v4_1_20
+xlslice_v1_0_2=$RDI_DATADIR/xsim/ip/xlslice_v1_0_2
+ddr4_pl_v1_0_9=$RDI_DATADIR/xsim/ip/ddr4_pl_v1_0_9
+g709_fec_v2_4_6=$RDI_DATADIR/xsim/ip/g709_fec_v2_4_6
+ai_noc=$RDI_DATADIR/xsim/ip/ai_noc
+fit_timer_v2_0_10=$RDI_DATADIR/xsim/ip/fit_timer_v2_0_10
+xdfe_nr_prach_v1_1_0=$RDI_DATADIR/xsim/ip/xdfe_nr_prach_v1_1_0
+noc2_xbr2x4_v1_0_0=$RDI_DATADIR/xsim/ip/noc2_xbr2x4_v1_0_0
+xtlm_trace_model_v1_0=$RDI_DATADIR/xsim/ip/xtlm_trace_model_v1_0
+v_hdmi_tx_v3_0_0=$RDI_DATADIR/xsim/ip/v_hdmi_tx_v3_0_0
+lib_cdc_v1_0_2=$RDI_DATADIR/xsim/ip/lib_cdc_v1_0_2
+gigantic_mux=$RDI_DATADIR/xsim/ip/gigantic_mux
+v_vid_sdi_tx_bridge_v2_0_0=$RDI_DATADIR/xsim/ip/v_vid_sdi_tx_bridge_v2_0_0
+dprx_v1_0_0=$RDI_DATADIR/xsim/ip/dprx_v1_0_0
+jesd204c_v4_2_9=$RDI_DATADIR/xsim/ip/jesd204c_v4_2_9
+etrnic_v1_1_5=$RDI_DATADIR/xsim/ip/etrnic_v1_1_5
+axi_dwidth_converter_v2_1_27=$RDI_DATADIR/xsim/ip/axi_dwidth_converter_v2_1_27
+v_frmbuf_wr_v2_2_6=$RDI_DATADIR/xsim/ip/v_frmbuf_wr_v2_2_6
+xsdbm_v3_0_0=$RDI_DATADIR/xsim/ip/xsdbm_v3_0_0
+rs_encoder_v9_0_17=$RDI_DATADIR/xsim/ip/rs_encoder_v9_0_17
+xdfe_resampler_v1_0_5=$RDI_DATADIR/xsim/ip/xdfe_resampler_v1_0_5
+xxv_ethernet_v4_1_1=$RDI_DATADIR/xsim/ip/xxv_ethernet_v4_1_1
+hdcp_v1_0_3=$RDI_DATADIR/xsim/ip/hdcp_v1_0_3
+vby1hs_v1_0_2=$RDI_DATADIR/xsim/ip/vby1hs_v1_0_2
+axi_mm2s_mapper_v1_1_26=$RDI_DATADIR/xsim/ip/axi_mm2s_mapper_v1_1_26
+v_smpte_sdi_v3_0_9=$RDI_DATADIR/xsim/ip/v_smpte_sdi_v3_0_9
+v_frmbuf_rd_v2_3_2=$RDI_DATADIR/xsim/ip/v_frmbuf_rd_v2_3_2
+emb_mem_gen_v1_0_6=$RDI_DATADIR/xsim/ip/emb_mem_gen_v1_0_6
+axi_protocol_converter_v2_1_27=$RDI_DATADIR/xsim/ip/axi_protocol_converter_v2_1_27
+div_gen_v5_1_19=$RDI_DATADIR/xsim/ip/div_gen_v5_1_19
+xdfe_fft_v1_0_4=$RDI_DATADIR/xsim/ip/xdfe_fft_v1_0_4
+hbm2e_pl_v1_0_0=$RDI_DATADIR/xsim/ip/hbm2e_pl_v1_0_0
+mammoth_transcode_v1_0_0=$RDI_DATADIR/xsim/ip/mammoth_transcode_v1_0_0
+v_letterbox_v1_1_6=$RDI_DATADIR/xsim/ip/v_letterbox_v1_1_6
+v_gamma_lut_v1_1_6=$RDI_DATADIR/xsim/ip/v_gamma_lut_v1_1_6
+tmr_voter_v1_0_4=$RDI_DATADIR/xsim/ip/tmr_voter_v1_0_4
+cpm4_v1_0_9=$RDI_DATADIR/xsim/ip/cpm4_v1_0_9
+vid_phy_controller_v2_2_14=$RDI_DATADIR/xsim/ip/vid_phy_controller_v2_2_14
+v_tpg_v8_2_2=$RDI_DATADIR/xsim/ip/v_tpg_v8_2_2
+xlconstant_v1_1_7=$RDI_DATADIR/xsim/ip/xlconstant_v1_1_7
+c_mux_bus_v12_0_6=$RDI_DATADIR/xsim/ip/c_mux_bus_v12_0_6
+g975_efec_i4_v1_0_19=$RDI_DATADIR/xsim/ip/g975_efec_i4_v1_0_19
+lmb_bram_if_cntlr_v4_0=$RDI_DATADIR/xsim/ip/lmb_bram_if_cntlr_v4_0
+v_warp_filter_v1_0_2=$RDI_DATADIR/xsim/ip/v_warp_filter_v1_0_2
+i2s_receiver_v1_0_5=$RDI_DATADIR/xsim/ip/i2s_receiver_v1_0_5
+zynq_ultra_ps_e_v3_3_8=$RDI_DATADIR/xsim/ip/zynq_ultra_ps_e_v3_3_8
+axis_cap_ctrl_v1_0_0=$RDI_DATADIR/xsim/ip/axis_cap_ctrl_v1_0_0
+pcie_jtag_v1_0_0=$RDI_DATADIR/xsim/ip/pcie_jtag_v1_0_0
+lmb_v10_v3_0=$RDI_DATADIR/xsim/ip/lmb_v10_v3_0
+dist_mem_gen_v8_0_13=$RDI_DATADIR/xsim/ip/dist_mem_gen_v8_0_13
+v_warp_init_v1_0_2=$RDI_DATADIR/xsim/ip/v_warp_init_v1_0_2
+displayport_v7_0_0=$RDI_DATADIR/xsim/ip/displayport_v7_0_0
+versal_cips_v3_2_2=$RDI_DATADIR/xsim/ip/versal_cips_v3_2_2
+lib_fifo_v1_0_16=$RDI_DATADIR/xsim/ip/lib_fifo_v1_0_16
+blk_mem_gen_v8_3_6=$RDI_DATADIR/xsim/ip/blk_mem_gen_v8_3_6
+emb_fifo_gen_v1_0_2=$RDI_DATADIR/xsim/ip/emb_fifo_gen_v1_0_2
+microblaze_v11_0_10=$RDI_DATADIR/xsim/ip/microblaze_v11_0_10
+dfx_bitstream_monitor_v1_0_2=$RDI_DATADIR/xsim/ip/dfx_bitstream_monitor_v1_0_2
+vfb_v1_0_21=$RDI_DATADIR/xsim/ip/vfb_v1_0_21
+ecc_v2_0_13=$RDI_DATADIR/xsim/ip/ecc_v2_0_13
+mrmac_v2_0_0=$RDI_DATADIR/xsim/ip/mrmac_v2_0_0
+rwd_tlmmodel_v1=$RDI_DATADIR/xsim/ip/rwd_tlmmodel_v1
+ernic_v4_0_0=$RDI_DATADIR/xsim/ip/ernic_v4_0_0
+mailbox_v2_1_15=$RDI_DATADIR/xsim/ip/mailbox_v2_1_15
+noc_nidb_v1_0_0=$RDI_DATADIR/xsim/ip/noc_nidb_v1_0_0
+displayport_v9_0_5=$RDI_DATADIR/xsim/ip/displayport_v9_0_5
+ll_compress_v2_0_1=$RDI_DATADIR/xsim/ip/ll_compress_v2_0_1
+cordic_v6_0_18=$RDI_DATADIR/xsim/ip/cordic_v6_0_18
+tmr_manager_v1_0_10=$RDI_DATADIR/xsim/ip/tmr_manager_v1_0_10
+axis_mem_v1_0_0=$RDI_DATADIR/xsim/ip/axis_mem_v1_0_0
+noc2_nmu_v1_0_0=$RDI_DATADIR/xsim/ip/noc2_nmu_v1_0_0
+aie_ps_v1_0=$RDI_DATADIR/xsim/ip/aie_ps_v1_0
+noc_sc_v1_0_0=$RDI_DATADIR/xsim/ip/noc_sc_v1_0_0
+rst_vip_v1_0_4=$RDI_DATADIR/xsim/ip/rst_vip_v1_0_4
+mult_gen_v12_0_18=$RDI_DATADIR/xsim/ip/mult_gen_v12_0_18
+qdriv_pl_phy_v1_0_0=$RDI_DATADIR/xsim/ip/qdriv_pl_phy_v1_0_0
+av_pat_gen_v2_0_0=$RDI_DATADIR/xsim/ip/av_pat_gen_v2_0_0
+xtlm_simple_interconnect_v1_0=$RDI_DATADIR/xsim/ip/xtlm_simple_interconnect_v1_0
+stm_v1_0_0=$RDI_DATADIR/xsim/ip/stm_v1_0_0
+zynq_ultra_ps_e_vip_v1_0_13=$RDI_DATADIR/xsim/ip/zynq_ultra_ps_e_vip_v1_0_13
+ieee802d3_50g_rs_fec_v2_0_12=$RDI_DATADIR/xsim/ip/ieee802d3_50g_rs_fec_v2_0_12
+axi_dma_v7_1_28=$RDI_DATADIR/xsim/ip/axi_dma_v7_1_28
+processing_system7_v5_5_6=$RDI_DATADIR/xsim/ip/processing_system7_v5_5_6
+v_hscaler_v1_1_6=$RDI_DATADIR/xsim/ip/v_hscaler_v1_1_6
+ldpc_v2_0_11=$RDI_DATADIR/xsim/ip/ldpc_v2_0_11
+axi_utils_v2_0_6=$RDI_DATADIR/xsim/ip/axi_utils_v2_0_6
+ieee802d3_rs_fec_v2_0_16=$RDI_DATADIR/xsim/ip/ieee802d3_rs_fec_v2_0_16
+advanced_io_wizard_phy_v1_0_0=$RDI_DATADIR/xsim/ip/advanced_io_wizard_phy_v1_0_0
+fifo_generator_v13_0_6=$RDI_DATADIR/xsim/ip/fifo_generator_v13_0_6
+v_vcresampler_v1_1_6=$RDI_DATADIR/xsim/ip/v_vcresampler_v1_1_6
+axi_emc_v3_0_27=$RDI_DATADIR/xsim/ip/axi_emc_v3_0_27
+axi_hbicap_v1_0_4=$RDI_DATADIR/xsim/ip/axi_hbicap_v1_0_4
+util_idelay_ctrl_v1_0_2=$RDI_DATADIR/xsim/ip/util_idelay_ctrl_v1_0_2
+xbip_dsp48_acc_v3_0_6=$RDI_DATADIR/xsim/ip/xbip_dsp48_acc_v3_0_6
+lmb_v10_v3_0_12=$RDI_DATADIR/xsim/ip/lmb_v10_v3_0_12
+axi_cdma_v4_1_27=$RDI_DATADIR/xsim/ip/axi_cdma_v4_1_27
+iomodule_v3_1_8=$RDI_DATADIR/xsim/ip/iomodule_v3_1_8
+tmr_sem_v1_0_23=$RDI_DATADIR/xsim/ip/tmr_sem_v1_0_23
+sem_v4_1_13=$RDI_DATADIR/xsim/ip/sem_v4_1_13
+video_frame_crc_v1_0_4=$RDI_DATADIR/xsim/ip/video_frame_crc_v1_0_4
+axi_lmb_bridge_v1_0_1=$RDI_DATADIR/xsim/ip/axi_lmb_bridge_v1_0_1
+ten_gig_eth_mac_v15_1_10=$RDI_DATADIR/xsim/ip/ten_gig_eth_mac_v15_1_10
+v_hdmi_rx_v3_0_0=$RDI_DATADIR/xsim/ip/v_hdmi_rx_v3_0_0
+rama_v1_1_13_lib=$RDI_DATADIR/xsim/ip/rama_v1_1_13_lib
+hdcp_keymngmt_blk_v1_0_0=$RDI_DATADIR/xsim/ip/hdcp_keymngmt_blk_v1_0_0
+v_vid_gt_bridge_v1_0_6=$RDI_DATADIR/xsim/ip/v_vid_gt_bridge_v1_0_6
+pc_cfr_v7_0_1=$RDI_DATADIR/xsim/ip/pc_cfr_v7_0_1
+mutex_v2_1_11=$RDI_DATADIR/xsim/ip/mutex_v2_1_11
+axis_dwidth_converter_sc_v1_1=$RDI_DATADIR/xsim/ip/axis_dwidth_converter_sc_v1_1
+shell_utils_addr_remap_v1_0_6=$RDI_DATADIR/xsim/ip/shell_utils_addr_remap_v1_0_6
+xfft_v7_2_13=$RDI_DATADIR/xsim/ip/xfft_v7_2_13
+v_demosaic_v1_1_6=$RDI_DATADIR/xsim/ip/v_demosaic_v1_1_6
+axi_lite_ipif_v3_0_4=$RDI_DATADIR/xsim/ip/axi_lite_ipif_v3_0_4
+c_addsub_v12_0_14=$RDI_DATADIR/xsim/ip/c_addsub_v12_0_14
diff --git a/game.sim/sim_1/behav/xsim/xsim.ini.bak b/game.sim/sim_1/behav/xsim/xsim.ini.bak
new file mode 100644
index 0000000000000000000000000000000000000000..b80378eeddd5196a846bc727f7a7cc03b1a637bc
--- /dev/null
+++ b/game.sim/sim_1/behav/xsim/xsim.ini.bak
@@ -0,0 +1,498 @@
+std=$RDI_DATADIR/xsim/vhdl/std
+ieee=$RDI_DATADIR/xsim/vhdl/ieee
+ieee_proposed=$RDI_DATADIR/xsim/vhdl/ieee_proposed
+vl=$RDI_DATADIR/xsim/vhdl/vl
+synopsys=$RDI_DATADIR/xsim/vhdl/synopsys
+uvm=$RDI_DATADIR/xsim/system_verilog/uvm
+secureip=$RDI_DATADIR/xsim/verilog/secureip
+unisim=$RDI_DATADIR/xsim/vhdl/unisim
+unimacro=$RDI_DATADIR/xsim/vhdl/unimacro
+unifast=$RDI_DATADIR/xsim/vhdl/unifast
+unisims_ver=$RDI_DATADIR/xsim/verilog/unisims_ver
+unimacro_ver=$RDI_DATADIR/xsim/verilog/unimacro_ver
+unifast_ver=$RDI_DATADIR/xsim/verilog/unifast_ver
+simprims_ver=$RDI_DATADIR/xsim/verilog/simprims_ver
+ilknf_v1_2_0=$RDI_DATADIR/xsim/ip/ilknf_v1_2_0
+pci64_v5_0_11=$RDI_DATADIR/xsim/ip/pci64_v5_0_11
+axis_ila_txns_cntr_v1_0_0=$RDI_DATADIR/xsim/ip/axis_ila_txns_cntr_v1_0_0
+qdriv_pl_v1_0_8=$RDI_DATADIR/xsim/ip/qdriv_pl_v1_0_8
+axis_switch_sc_v1_1=$RDI_DATADIR/xsim/ip/axis_switch_sc_v1_1
+uram_rd_back_v1_0_2=$RDI_DATADIR/xsim/ip/uram_rd_back_v1_0_2
+interlaken_v2_4_12=$RDI_DATADIR/xsim/ip/interlaken_v2_4_12
+axis_register_slice_v1_1_27=$RDI_DATADIR/xsim/ip/axis_register_slice_v1_1_27
+c_gate_bit_v12_0_6=$RDI_DATADIR/xsim/ip/c_gate_bit_v12_0_6
+cmac_v2_6_8=$RDI_DATADIR/xsim/ip/cmac_v2_6_8
+axi_bram_ctrl_v4_1_7=$RDI_DATADIR/xsim/ip/axi_bram_ctrl_v4_1_7
+tmr_inject_v1_0_4=$RDI_DATADIR/xsim/ip/tmr_inject_v1_0_4
+mdm_v3_2_23=$RDI_DATADIR/xsim/ip/mdm_v3_2_23
+axi_quad_spi_v3_2_26=$RDI_DATADIR/xsim/ip/axi_quad_spi_v3_2_26
+noc_npp_rptr_v1_0_0=$RDI_DATADIR/xsim/ip/noc_npp_rptr_v1_0_0
+xlconcat_v2_1_4=$RDI_DATADIR/xsim/ip/xlconcat_v2_1_4
+xbip_multadd_v3_0_17=$RDI_DATADIR/xsim/ip/xbip_multadd_v3_0_17
+c_counter_binary_v12_0_15=$RDI_DATADIR/xsim/ip/c_counter_binary_v12_0_15
+ieee802d3_200g_rs_fec_v2_0_6=$RDI_DATADIR/xsim/ip/ieee802d3_200g_rs_fec_v2_0_6
+dsp_macro_v1_0_2=$RDI_DATADIR/xsim/ip/dsp_macro_v1_0_2
+cmac_usplus_v3_1_10=$RDI_DATADIR/xsim/ip/cmac_usplus_v3_1_10
+noc2_nsu_v1_0_0=$RDI_DATADIR/xsim/ip/noc2_nsu_v1_0_0
+sid_v8_0_17=$RDI_DATADIR/xsim/ip/sid_v8_0_17
+v_frmbuf_wr_v2_4_0=$RDI_DATADIR/xsim/ip/v_frmbuf_wr_v2_4_0
+axi_pcie3_v3_0_23=$RDI_DATADIR/xsim/ip/axi_pcie3_v3_0_23
+axi_mmu_v2_1_25=$RDI_DATADIR/xsim/ip/axi_mmu_v2_1_25
+axis_data_fifo_v2_0_9=$RDI_DATADIR/xsim/ip/axis_data_fifo_v2_0_9
+jtag_axi=$RDI_DATADIR/xsim/ip/jtag_axi
+quadsgmii_v3_5_9=$RDI_DATADIR/xsim/ip/quadsgmii_v3_5_9
+g975_efec_i7_v2_0_19=$RDI_DATADIR/xsim/ip/g975_efec_i7_v2_0_19
+audio_tpg_v1_0_0=$RDI_DATADIR/xsim/ip/audio_tpg_v1_0_0
+axi_c2c_v1_0_4=$RDI_DATADIR/xsim/ip/axi_c2c_v1_0_4
+emc_common_v3_0_5=$RDI_DATADIR/xsim/ip/emc_common_v3_0_5
+ptp_1588_timer_syncer_v2_0_4=$RDI_DATADIR/xsim/ip/ptp_1588_timer_syncer_v2_0_4
+xdfe_cc_mixer_v2_0_0=$RDI_DATADIR/xsim/ip/xdfe_cc_mixer_v2_0_0
+xtlm=$RDI_DATADIR/xsim/ip/xtlm
+pcie_axi4lite_tap_v1_0_1=$RDI_DATADIR/xsim/ip/pcie_axi4lite_tap_v1_0_1
+hdcp22_rng_v1_0_1=$RDI_DATADIR/xsim/ip/hdcp22_rng_v1_0_1
+axi_ethernet_buffer_v2_0_24=$RDI_DATADIR/xsim/ip/axi_ethernet_buffer_v2_0_24
+v_vid_in_axi4s_v4_0_9=$RDI_DATADIR/xsim/ip/v_vid_in_axi4s_v4_0_9
+axi_firewall_v1_1_6=$RDI_DATADIR/xsim/ip/axi_firewall_v1_1_6
+sim_ipc_multi_intf_v1_0=$RDI_DATADIR/xsim/ip/sim_ipc_multi_intf_v1_0
+axis_subset_converter_v1_1_27=$RDI_DATADIR/xsim/ip/axis_subset_converter_v1_1_27
+videoaxi4s_bridge_v1_0_5=$RDI_DATADIR/xsim/ip/videoaxi4s_bridge_v1_0_5
+ieee802d3_400g_rs_fec_v2_0_9=$RDI_DATADIR/xsim/ip/ieee802d3_400g_rs_fec_v2_0_9
+axi_timer_v2_0_29=$RDI_DATADIR/xsim/ip/axi_timer_v2_0_29
+noc2_xbr4x2_v1_0_0=$RDI_DATADIR/xsim/ip/noc2_xbr4x2_v1_0_0
+remote_port_sc_v4=$RDI_DATADIR/xsim/ip/remote_port_sc_v4
+axi_tft_v2_0_25=$RDI_DATADIR/xsim/ip/axi_tft_v2_0_25
+v_smpte_uhdsdi_tx_v1_0_2=$RDI_DATADIR/xsim/ip/v_smpte_uhdsdi_tx_v1_0_2
+pc_cfr_v7_2_0=$RDI_DATADIR/xsim/ip/pc_cfr_v7_2_0
+v_frmbuf_rd_v2_4_0=$RDI_DATADIR/xsim/ip/v_frmbuf_rd_v2_4_0
+g709_rs_decoder_v2_2_10=$RDI_DATADIR/xsim/ip/g709_rs_decoder_v2_2_10
+axi_msg_v1_0_8=$RDI_DATADIR/xsim/ip/axi_msg_v1_0_8
+dprx_fec_8b10b_v1_0_1=$RDI_DATADIR/xsim/ip/dprx_fec_8b10b_v1_0_1
+v_dp_axi4s_vid_out_v1_0_5=$RDI_DATADIR/xsim/ip/v_dp_axi4s_vid_out_v1_0_5
+v_scenechange_v1_1_4=$RDI_DATADIR/xsim/ip/v_scenechange_v1_1_4
+versal_cips_v3_3_0=$RDI_DATADIR/xsim/ip/versal_cips_v3_3_0
+axi_register_slice_v2_1_27=$RDI_DATADIR/xsim/ip/axi_register_slice_v2_1_27
+axis_dwidth_converter_v1_1_26=$RDI_DATADIR/xsim/ip/axis_dwidth_converter_v1_1_26
+mipi_dphy_v4_3_5=$RDI_DATADIR/xsim/ip/mipi_dphy_v4_3_5
+system_cache_v5_0_8=$RDI_DATADIR/xsim/ip/system_cache_v5_0_8
+axi_pmon_v1_0_0=$RDI_DATADIR/xsim/ip/axi_pmon_v1_0_0
+oddr_v1_0_2=$RDI_DATADIR/xsim/ip/oddr_v1_0_2
+vitis_net_p4_v1_2_0=$RDI_DATADIR/xsim/ip/vitis_net_p4_v1_2_0
+smartconnect_v1_0=$RDI_DATADIR/xsim/ip/smartconnect_v1_0
+axis_switch_v1_1_27=$RDI_DATADIR/xsim/ip/axis_switch_v1_1_27
+v_frmbuf_wr_v2_3_2=$RDI_DATADIR/xsim/ip/v_frmbuf_wr_v2_3_2
+cmpy_v6_0_21=$RDI_DATADIR/xsim/ip/cmpy_v6_0_21
+common_rpc_v1=$RDI_DATADIR/xsim/ip/common_rpc_v1
+gtwizard_ultrascale_v1_5_4=$RDI_DATADIR/xsim/ip/gtwizard_ultrascale_v1_5_4
+debug_tcp_server_v1=$RDI_DATADIR/xsim/ip/debug_tcp_server_v1
+v_tpg_v8_1_6=$RDI_DATADIR/xsim/ip/v_tpg_v8_1_6
+mipi_csi2_tx_ctrl_v1_0_4=$RDI_DATADIR/xsim/ip/mipi_csi2_tx_ctrl_v1_0_4
+floating_point_v7_0_20=$RDI_DATADIR/xsim/ip/floating_point_v7_0_20
+mpegtsmux_v1_1_5=$RDI_DATADIR/xsim/ip/mpegtsmux_v1_1_5
+noc_nps4_v1_0_0=$RDI_DATADIR/xsim/ip/noc_nps4_v1_0_0
+an_lt_v1_0_7=$RDI_DATADIR/xsim/ip/an_lt_v1_0_7
+picxo=$RDI_DATADIR/xsim/ip/picxo
+axi_bram_ctrl_v4_0_14=$RDI_DATADIR/xsim/ip/axi_bram_ctrl_v4_0_14
+axi_vdma_v6_3_15=$RDI_DATADIR/xsim/ip/axi_vdma_v6_3_15
+dbg_intf=$RDI_DATADIR/xsim/ip/dbg_intf
+xsdbs_v1_0_2=$RDI_DATADIR/xsim/ip/xsdbs_v1_0_2
+v_axi4s_remap_v1_0_20=$RDI_DATADIR/xsim/ip/v_axi4s_remap_v1_0_20
+pc_cfr_v6_4_2=$RDI_DATADIR/xsim/ip/pc_cfr_v6_4_2
+v_csc_v1_1_6=$RDI_DATADIR/xsim/ip/v_csc_v1_1_6
+xbip_addsub_v3_0_6=$RDI_DATADIR/xsim/ip/xbip_addsub_v3_0_6
+vitis_deadlock_detector_v1_0_1=$RDI_DATADIR/xsim/ip/vitis_deadlock_detector_v1_0_1
+vid_edid_v1_0_0=$RDI_DATADIR/xsim/ip/vid_edid_v1_0_0
+axi4svideo_bridge_v1_0_15=$RDI_DATADIR/xsim/ip/axi4svideo_bridge_v1_0_15
+ethernet_1_10_25g_v2_7_6=$RDI_DATADIR/xsim/ip/ethernet_1_10_25g_v2_7_6
+xdfe_cc_filter_v1_1_0=$RDI_DATADIR/xsim/ip/xdfe_cc_filter_v1_1_0
+axi_clock_converter_v2_1_26=$RDI_DATADIR/xsim/ip/axi_clock_converter_v2_1_26
+axi_hwicap_v3_0_31=$RDI_DATADIR/xsim/ip/axi_hwicap_v3_0_31
+xscl=$RDI_DATADIR/xsim/ip/xscl
+noc_nsu_v1_0_0=$RDI_DATADIR/xsim/ip/noc_nsu_v1_0_0
+fec_5g_common_v1_1_1=$RDI_DATADIR/xsim/ip/fec_5g_common_v1_1_1
+in_system_ibert_v1_0_17=$RDI_DATADIR/xsim/ip/in_system_ibert_v1_0_17
+displayport_v8_1_5=$RDI_DATADIR/xsim/ip/displayport_v8_1_5
+bs_switch_v1_0_1=$RDI_DATADIR/xsim/ip/bs_switch_v1_0_1
+sim_cpu_v1_0=$RDI_DATADIR/xsim/ip/sim_cpu_v1_0
+dfx_controller_v1_0_3=$RDI_DATADIR/xsim/ip/dfx_controller_v1_0_3
+polar_v1_0_10=$RDI_DATADIR/xsim/ip/polar_v1_0_10
+axi_sideband_util_v1_0_11=$RDI_DATADIR/xsim/ip/axi_sideband_util_v1_0_11
+ltlib_v1_0_0=$RDI_DATADIR/xsim/ip/ltlib_v1_0_0
+shell_utils_msp432_bsl_crc_gen_v1_0_0=$RDI_DATADIR/xsim/ip/shell_utils_msp432_bsl_crc_gen_v1_0_0
+adc_dac_if_phy_v1_0_0=$RDI_DATADIR/xsim/ip/adc_dac_if_phy_v1_0_0
+hdcp22_cipher_v1_0_3=$RDI_DATADIR/xsim/ip/hdcp22_cipher_v1_0_3
+axi_uartlite_v2_0_31=$RDI_DATADIR/xsim/ip/axi_uartlite_v2_0_31
+audio_clock_recovery_unit_v1_0_2=$RDI_DATADIR/xsim/ip/audio_clock_recovery_unit_v1_0_2
+g709_rs_encoder_v2_2_8=$RDI_DATADIR/xsim/ip/g709_rs_encoder_v2_2_8
+v_smpte_uhdsdi_v1_0_9=$RDI_DATADIR/xsim/ip/v_smpte_uhdsdi_v1_0_9
+zynq_ultra_ps_e_v3_4_1=$RDI_DATADIR/xsim/ip/zynq_ultra_ps_e_v3_4_1
+v_multi_scaler_v1_2_3=$RDI_DATADIR/xsim/ip/v_multi_scaler_v1_2_3
+nvme_tc_v3_0_2=$RDI_DATADIR/xsim/ip/nvme_tc_v3_0_2
+axi_iic_v2_1_3=$RDI_DATADIR/xsim/ip/axi_iic_v2_1_3
+bs_mux_v1_0_0=$RDI_DATADIR/xsim/ip/bs_mux_v1_0_0
+sim_qdma_cpp_v1_0=$RDI_DATADIR/xsim/ip/sim_qdma_cpp_v1_0
+aurora_8b10b_versal_v1_0_1=$RDI_DATADIR/xsim/ip/aurora_8b10b_versal_v1_0_1
+rld3_pl_phy_v1_0_0=$RDI_DATADIR/xsim/ip/rld3_pl_phy_v1_0_0
+remote_port_c_v4=$RDI_DATADIR/xsim/ip/remote_port_c_v4
+util_ff_v1_0_1=$RDI_DATADIR/xsim/ip/util_ff_v1_0_1
+xbip_dsp48_wrapper_v3_0_4=$RDI_DATADIR/xsim/ip/xbip_dsp48_wrapper_v3_0_4
+mem_pl_v1_0_0=$RDI_DATADIR/xsim/ip/mem_pl_v1_0_0
+dft_v4_0_16=$RDI_DATADIR/xsim/ip/dft_v4_0_16
+axi_sg_v4_1_15=$RDI_DATADIR/xsim/ip/axi_sg_v4_1_15
+xdfe_equalizer_v1_0_5=$RDI_DATADIR/xsim/ip/xdfe_equalizer_v1_0_5
+v_vid_gt_bridge_v2_0_0=$RDI_DATADIR/xsim/ip/v_vid_gt_bridge_v2_0_0
+sim_trig_v1_0_8=$RDI_DATADIR/xsim/ip/sim_trig_v1_0_8
+axi_stream_monitor_v1_1_0=$RDI_DATADIR/xsim/ip/axi_stream_monitor_v1_1_0
+axi_gpio_v2_0_29=$RDI_DATADIR/xsim/ip/axi_gpio_v2_0_29
+axi_memory_init_v1_0_8=$RDI_DATADIR/xsim/ip/axi_memory_init_v1_0_8
+c_reg_fd_v12_0_6=$RDI_DATADIR/xsim/ip/c_reg_fd_v12_0_6
+stm_v1_0=$RDI_DATADIR/xsim/ip/stm_v1_0
+sem_ultra_v3_1_24=$RDI_DATADIR/xsim/ip/sem_ultra_v3_1_24
+axi_vip_v1_1_13=$RDI_DATADIR/xsim/ip/axi_vip_v1_1_13
+axis_broadcaster_v1_1_26=$RDI_DATADIR/xsim/ip/axis_broadcaster_v1_1_26
+gig_ethernet_pcs_pma_v16_2_9=$RDI_DATADIR/xsim/ip/gig_ethernet_pcs_pma_v16_2_9
+tcc_decoder_3gpplte_v3_0_6=$RDI_DATADIR/xsim/ip/tcc_decoder_3gpplte_v3_0_6
+axi_data_fifo_v2_1_26=$RDI_DATADIR/xsim/ip/axi_data_fifo_v2_1_26
+ernic_v3_1_2=$RDI_DATADIR/xsim/ip/ernic_v3_1_2
+axis_dbg_sync_v1_0_0=$RDI_DATADIR/xsim/ip/axis_dbg_sync_v1_0_0
+ten_gig_eth_pcs_pma_v6_0_23=$RDI_DATADIR/xsim/ip/ten_gig_eth_pcs_pma_v6_0_23
+lmb_bram_if_cntlr_v4_0_21=$RDI_DATADIR/xsim/ip/lmb_bram_if_cntlr_v4_0_21
+axi_usb2_device_v5_0_28=$RDI_DATADIR/xsim/ip/axi_usb2_device_v5_0_28
+pc_cfr_v7_1_0=$RDI_DATADIR/xsim/ip/pc_cfr_v7_1_0
+rs_decoder_v9_0_18=$RDI_DATADIR/xsim/ip/rs_decoder_v9_0_18
+cam_v2_4_0=$RDI_DATADIR/xsim/ip/cam_v2_4_0
+ll_compress_v1_1_0=$RDI_DATADIR/xsim/ip/ll_compress_v1_1_0
+v_tc_v6_1_13=$RDI_DATADIR/xsim/ip/v_tc_v6_1_13
+cpm5_v1_0_9=$RDI_DATADIR/xsim/ip/cpm5_v1_0_9
+hsdp_trace_v1_0_0=$RDI_DATADIR/xsim/ip/hsdp_trace_v1_0_0
+tmr_comparator_v1_0_5=$RDI_DATADIR/xsim/ip/tmr_comparator_v1_0_5
+axi_ethernetlite_v3_0_26=$RDI_DATADIR/xsim/ip/axi_ethernetlite_v3_0_26
+lib_bmg_v1_0_14=$RDI_DATADIR/xsim/ip/lib_bmg_v1_0_14
+audio_formatter_v1_0_9=$RDI_DATADIR/xsim/ip/audio_formatter_v1_0_9
+axi_epc_v2_0_30=$RDI_DATADIR/xsim/ip/axi_epc_v2_0_30
+xbip_counter_v3_0_6=$RDI_DATADIR/xsim/ip/xbip_counter_v3_0_6
+xfft_v9_1_8=$RDI_DATADIR/xsim/ip/xfft_v9_1_8
+microblaze_v9_5_4=$RDI_DATADIR/xsim/ip/microblaze_v9_5_4
+blk_mem_gen_v8_4_5=$RDI_DATADIR/xsim/ip/blk_mem_gen_v8_4_5
+sim_xdma_sc_v1=$RDI_DATADIR/xsim/ip/sim_xdma_sc_v1
+proc_sys_reset_v5_0_13=$RDI_DATADIR/xsim/ip/proc_sys_reset_v5_0_13
+v_tpg_v8_0_10=$RDI_DATADIR/xsim/ip/v_tpg_v8_0_10
+hdmi_acr_ctrl_v1_0_0=$RDI_DATADIR/xsim/ip/hdmi_acr_ctrl_v1_0_0
+v_mix_v5_2_4=$RDI_DATADIR/xsim/ip/v_mix_v5_2_4
+flexo_100g_rs_fec_v1_0_23=$RDI_DATADIR/xsim/ip/flexo_100g_rs_fec_v1_0_23
+amm_axi_bridge_v1_0_13=$RDI_DATADIR/xsim/ip/amm_axi_bridge_v1_0_13
+axi_uart16550_v2_0_29=$RDI_DATADIR/xsim/ip/axi_uart16550_v2_0_29
+hw_trace=$RDI_DATADIR/xsim/ip/hw_trace
+axis_clock_converter_v1_1_28=$RDI_DATADIR/xsim/ip/axis_clock_converter_v1_1_28
+xpm=$RDI_DATADIR/xsim/ip/xpm
+versal_cips_ps_vip_v1_0_5=$RDI_DATADIR/xsim/ip/versal_cips_ps_vip_v1_0_5
+noc_nmu_phydir_v1_0_0=$RDI_DATADIR/xsim/ip/noc_nmu_phydir_v1_0_0
+roe_framer_v3_0_4=$RDI_DATADIR/xsim/ip/roe_framer_v3_0_4
+soft_ecc_proxy_v1_0_1=$RDI_DATADIR/xsim/ip/soft_ecc_proxy_v1_0_1
+fifo_generator_v13_1_4=$RDI_DATADIR/xsim/ip/fifo_generator_v13_1_4
+axis_combiner_v1_1_25=$RDI_DATADIR/xsim/ip/axis_combiner_v1_1_25
+switch_core_top_v1_0_11=$RDI_DATADIR/xsim/ip/switch_core_top_v1_0_11
+noc_ncrb_v1_0_0=$RDI_DATADIR/xsim/ip/noc_ncrb_v1_0_0
+axis_ila_adv_trig_v1_0_0=$RDI_DATADIR/xsim/ip/axis_ila_adv_trig_v1_0_0
+axi_ahblite_bridge_v3_0_24=$RDI_DATADIR/xsim/ip/axi_ahblite_bridge_v3_0_24
+accelerator_monitor_v1_1_0=$RDI_DATADIR/xsim/ip/accelerator_monitor_v1_1_0
+cpm5n_v1_0_1=$RDI_DATADIR/xsim/ip/cpm5n_v1_0_1
+lte_fft_v2_1_6=$RDI_DATADIR/xsim/ip/lte_fft_v2_1_6
+axi_fifo_mm_s_v4_2_9=$RDI_DATADIR/xsim/ip/axi_fifo_mm_s_v4_2_9
+axi_intc_v4_1_17=$RDI_DATADIR/xsim/ip/axi_intc_v4_1_17
+xbip_bram18k_v3_0_6=$RDI_DATADIR/xsim/ip/xbip_bram18k_v3_0_6
+trace_s2mm_v2_0_0=$RDI_DATADIR/xsim/ip/trace_s2mm_v2_0_0
+vid_phy_controller_v2_1_14=$RDI_DATADIR/xsim/ip/vid_phy_controller_v2_1_14
+ats_switch_v1_0_6=$RDI_DATADIR/xsim/ip/ats_switch_v1_0_6
+ahblite_axi_bridge_v3_0_22=$RDI_DATADIR/xsim/ip/ahblite_axi_bridge_v3_0_22
+multi_channel_25g_rs_fec_v1_0_19=$RDI_DATADIR/xsim/ip/multi_channel_25g_rs_fec_v1_0_19
+xpm_cdc_gen_v1_0_2=$RDI_DATADIR/xsim/ip/xpm_cdc_gen_v1_0_2
+sim_xdma_cpp_v1=$RDI_DATADIR/xsim/ip/sim_xdma_cpp_v1
+dfx_axi_shutdown_manager_v1_0_0=$RDI_DATADIR/xsim/ip/dfx_axi_shutdown_manager_v1_0_0
+uhdsdi_gt_v2_0_9=$RDI_DATADIR/xsim/ip/uhdsdi_gt_v2_0_9
+noc_mc_ddr5_phy_v1_0_0=$RDI_DATADIR/xsim/ip/noc_mc_ddr5_phy_v1_0_0
+axi_jtag_v1_0_0=$RDI_DATADIR/xsim/ip/axi_jtag_v1_0_0
+oran_radio_if_v2_3_0=$RDI_DATADIR/xsim/ip/oran_radio_if_v2_3_0
+noc2_nps_v1_0_0=$RDI_DATADIR/xsim/ip/noc2_nps_v1_0_0
+fast_adapter_v1_0_4=$RDI_DATADIR/xsim/ip/fast_adapter_v1_0_4
+mdm_v3_2=$RDI_DATADIR/xsim/ip/mdm_v3_2
+v_deinterlacer_v5_1_0=$RDI_DATADIR/xsim/ip/v_deinterlacer_v5_1_0
+ta_dma_v1_0_11=$RDI_DATADIR/xsim/ip/ta_dma_v1_0_11
+xbip_dsp48_multacc_v3_0_6=$RDI_DATADIR/xsim/ip/xbip_dsp48_multacc_v3_0_6
+ll_compress_v2_1_1=$RDI_DATADIR/xsim/ip/ll_compress_v2_1_1
+l_ethernet_v3_3_1=$RDI_DATADIR/xsim/ip/l_ethernet_v3_3_1
+mipi_csi2_rx_ctrl_v1_0_8=$RDI_DATADIR/xsim/ip/mipi_csi2_rx_ctrl_v1_0_8
+v_axi4s_remap_v1_1_6=$RDI_DATADIR/xsim/ip/v_axi4s_remap_v1_1_6
+generic_baseblocks_v2_1_0=$RDI_DATADIR/xsim/ip/generic_baseblocks_v2_1_0
+v_mix_v5_1_6=$RDI_DATADIR/xsim/ip/v_mix_v5_1_6
+axi_remapper_rx_v1_0_0=$RDI_DATADIR/xsim/ip/axi_remapper_rx_v1_0_0
+axi_pcie_v2_9_8=$RDI_DATADIR/xsim/ip/axi_pcie_v2_9_8
+emu_perf_common_v1_0=$RDI_DATADIR/xsim/ip/emu_perf_common_v1_0
+v_hdmi_rx1_v1_0_4=$RDI_DATADIR/xsim/ip/v_hdmi_rx1_v1_0_4
+v_hdmi_tx1_v1_0_4=$RDI_DATADIR/xsim/ip/v_hdmi_tx1_v1_0_4
+lib_srl_fifo_v1_0_2=$RDI_DATADIR/xsim/ip/lib_srl_fifo_v1_0_2
+clk_gen_sim_v1_0_3=$RDI_DATADIR/xsim/ip/clk_gen_sim_v1_0_3
+dds_compiler_v6_0_22=$RDI_DATADIR/xsim/ip/dds_compiler_v6_0_22
+mem_tg_v1_0_9=$RDI_DATADIR/xsim/ip/mem_tg_v1_0_9
+axi_chip2chip_v5_0_16=$RDI_DATADIR/xsim/ip/axi_chip2chip_v5_0_16
+axis_ila_ct_v1_0_0=$RDI_DATADIR/xsim/ip/axis_ila_ct_v1_0_0
+v_hcresampler_v1_1_6=$RDI_DATADIR/xsim/ip/v_hcresampler_v1_1_6
+util_vector_logic_v2_0_2=$RDI_DATADIR/xsim/ip/util_vector_logic_v2_0_2
+axis_dbg_stub_v1_0_0=$RDI_DATADIR/xsim/ip/axis_dbg_stub_v1_0_0
+axi_amm_bridge_v1_0_17=$RDI_DATADIR/xsim/ip/axi_amm_bridge_v1_0_17
+cic_compiler_v4_0_16=$RDI_DATADIR/xsim/ip/cic_compiler_v4_0_16
+axi_interconnect_v1_7_20=$RDI_DATADIR/xsim/ip/axi_interconnect_v1_7_20
+axis_interconnect_v1_1_20=$RDI_DATADIR/xsim/ip/axis_interconnect_v1_1_20
+fir_compiler_v7_2_18=$RDI_DATADIR/xsim/ip/fir_compiler_v7_2_18
+iomodule_v3_0=$RDI_DATADIR/xsim/ip/iomodule_v3_0
+common_cpp_v1_0=$RDI_DATADIR/xsim/ip/common_cpp_v1_0
+pr_decoupler_v1_0_10=$RDI_DATADIR/xsim/ip/pr_decoupler_v1_0_10
+v_warp_filter_v1_1_1=$RDI_DATADIR/xsim/ip/v_warp_filter_v1_1_1
+xbip_pipe_v3_0_6=$RDI_DATADIR/xsim/ip/xbip_pipe_v3_0_6
+xdfe_nlf_v1_0_2=$RDI_DATADIR/xsim/ip/xdfe_nlf_v1_0_2
+mipi_dsi_tx_ctrl_v1_0_7=$RDI_DATADIR/xsim/ip/mipi_dsi_tx_ctrl_v1_0_7
+xilinx_vip=$RDI_DATADIR/xsim/ip/xilinx_vip
+axis_ila_intf_v1_0_0=$RDI_DATADIR/xsim/ip/axis_ila_intf_v1_0_0
+i2s_transmitter_v1_0_5=$RDI_DATADIR/xsim/ip/i2s_transmitter_v1_0_5
+axi_tg_sc_v1_0=$RDI_DATADIR/xsim/ip/axi_tg_sc_v1_0
+ll_compress_v1_0_0=$RDI_DATADIR/xsim/ip/ll_compress_v1_0_0
+trace_hub_v1_1_0=$RDI_DATADIR/xsim/ip/trace_hub_v1_1_0
+c_shift_ram_v12_0_14=$RDI_DATADIR/xsim/ip/c_shift_ram_v12_0_14
+axi_datamover_v5_1_29=$RDI_DATADIR/xsim/ip/axi_datamover_v5_1_29
+pcie_qdma_mailbox_v1_0_0=$RDI_DATADIR/xsim/ip/pcie_qdma_mailbox_v1_0_0
+ptp_1588_timer_syncer_v1_0_2=$RDI_DATADIR/xsim/ip/ptp_1588_timer_syncer_v1_0_2
+fc32_rs_fec_v1_0_22=$RDI_DATADIR/xsim/ip/fc32_rs_fec_v1_0_22
+axi_vfifo_ctrl_v2_0_29=$RDI_DATADIR/xsim/ip/axi_vfifo_ctrl_v2_0_29
+xtlm_ap_ctrl_v1_0=$RDI_DATADIR/xsim/ip/xtlm_ap_ctrl_v1_0
+icap_arb_v1_0_1=$RDI_DATADIR/xsim/ip/icap_arb_v1_0_1
+sim_rst_gen_v1_0_2=$RDI_DATADIR/xsim/ip/sim_rst_gen_v1_0_2
+tcc_encoder_3gpplte_v4_0_16=$RDI_DATADIR/xsim/ip/tcc_encoder_3gpplte_v4_0_16
+axis_mu_v1_0_0=$RDI_DATADIR/xsim/ip/axis_mu_v1_0_0
+bsip_v1_1_0=$RDI_DATADIR/xsim/ip/bsip_v1_1_0
+gtwizard_ultrascale_v1_6_14=$RDI_DATADIR/xsim/ip/gtwizard_ultrascale_v1_6_14
+lib_pkg_v1_0_2=$RDI_DATADIR/xsim/ip/lib_pkg_v1_0_2
+cpri_v8_11_13=$RDI_DATADIR/xsim/ip/cpri_v8_11_13
+interrupt_control_v3_1_4=$RDI_DATADIR/xsim/ip/interrupt_control_v3_1_4
+v_uhdsdi_audio_v2_0_6=$RDI_DATADIR/xsim/ip/v_uhdsdi_audio_v2_0_6
+dfx_decoupler_v1_0_5=$RDI_DATADIR/xsim/ip/dfx_decoupler_v1_0_5
+c_accum_v12_0_14=$RDI_DATADIR/xsim/ip/c_accum_v12_0_14
+axis_ila_pp_v1_0_0=$RDI_DATADIR/xsim/ip/axis_ila_pp_v1_0_0
+dcmac_v2_1_0=$RDI_DATADIR/xsim/ip/dcmac_v2_1_0
+dptx_v1_0_0=$RDI_DATADIR/xsim/ip/dptx_v1_0_0
+v_axi4s_vid_out_v4_0_15=$RDI_DATADIR/xsim/ip/v_axi4s_vid_out_v4_0_15
+lte_fft_v2_0_22=$RDI_DATADIR/xsim/ip/lte_fft_v2_0_22
+sd_fec_v1_1_10=$RDI_DATADIR/xsim/ip/sd_fec_v1_1_10
+axi_firewall_v1_2_2=$RDI_DATADIR/xsim/ip/axi_firewall_v1_2_2
+processing_system7_vip_v1_0_15=$RDI_DATADIR/xsim/ip/processing_system7_vip_v1_0_15
+axi4stream_vip_v1_1_13=$RDI_DATADIR/xsim/ip/axi4stream_vip_v1_1_13
+lut_buffer_v2_0_0=$RDI_DATADIR/xsim/ip/lut_buffer_v2_0_0
+timer_sync_1588_v1_2_4=$RDI_DATADIR/xsim/ip/timer_sync_1588_v1_2_4
+sim_ddr_v1_0=$RDI_DATADIR/xsim/ip/sim_ddr_v1_0
+v_smpte_uhdsdi_rx_v1_0_1=$RDI_DATADIR/xsim/ip/v_smpte_uhdsdi_rx_v1_0_1
+axi_intc_v4_1=$RDI_DATADIR/xsim/ip/axi_intc_v4_1
+axi_crossbar_v2_1_28=$RDI_DATADIR/xsim/ip/axi_crossbar_v2_1_28
+xbip_dsp48_multadd_v3_0_6=$RDI_DATADIR/xsim/ip/xbip_dsp48_multadd_v3_0_6
+axis_protocol_checker_v2_0_11=$RDI_DATADIR/xsim/ip/axis_protocol_checker_v2_0_11
+axi_interface_monitor_v1_1_0=$RDI_DATADIR/xsim/ip/axi_interface_monitor_v1_1_0
+v_uhdsdi_vidgen_v1_0_1=$RDI_DATADIR/xsim/ip/v_uhdsdi_vidgen_v1_0_1
+jesd204_v7_2_16=$RDI_DATADIR/xsim/ip/jesd204_v7_2_16
+dft_v4_2_3=$RDI_DATADIR/xsim/ip/dft_v4_2_3
+axi_dbg_hub=$RDI_DATADIR/xsim/ip/axi_dbg_hub
+v_vscaler_v1_1_6=$RDI_DATADIR/xsim/ip/v_vscaler_v1_1_6
+ddr4_pl_phy_v1_0_0=$RDI_DATADIR/xsim/ip/ddr4_pl_phy_v1_0_0
+av_pat_gen_v1_0_1=$RDI_DATADIR/xsim/ip/av_pat_gen_v1_0_1
+fifo_generator_v13_2_7=$RDI_DATADIR/xsim/ip/fifo_generator_v13_2_7
+srio_gen2_v4_1_15=$RDI_DATADIR/xsim/ip/srio_gen2_v4_1_15
+canfd_v3_0_6=$RDI_DATADIR/xsim/ip/canfd_v3_0_6
+tsn_temac_v1_0_7=$RDI_DATADIR/xsim/ip/tsn_temac_v1_0_7
+v_tc_v6_2_5=$RDI_DATADIR/xsim/ip/v_tc_v6_2_5
+v_dual_splitter_v1_0_9=$RDI_DATADIR/xsim/ip/v_dual_splitter_v1_0_9
+floating_point_v7_1_15=$RDI_DATADIR/xsim/ip/floating_point_v7_1_15
+xtlm_ipc_v1_0=$RDI_DATADIR/xsim/ip/xtlm_ipc_v1_0
+viterbi_v9_1_13=$RDI_DATADIR/xsim/ip/viterbi_v9_1_13
+axi_tlm_ext_v1_0=$RDI_DATADIR/xsim/ip/axi_tlm_ext_v1_0
+axi_lite_ipif_v3_0=$RDI_DATADIR/xsim/ip/axi_lite_ipif_v3_0
+xbip_accum_v3_0_6=$RDI_DATADIR/xsim/ip/xbip_accum_v3_0_6
+axis_itct_v1_0_0=$RDI_DATADIR/xsim/ip/axis_itct_v1_0_0
+rs_toolbox_v9_0_9=$RDI_DATADIR/xsim/ip/rs_toolbox_v9_0_9
+noc_nps6_v1_0_0=$RDI_DATADIR/xsim/ip/noc_nps6_v1_0_0
+ieee802d3_25g_rs_fec_v1_0_24=$RDI_DATADIR/xsim/ip/ieee802d3_25g_rs_fec_v1_0_24
+rld3_pl_v1_0_10=$RDI_DATADIR/xsim/ip/rld3_pl_v1_0_10
+gtwizard_ultrascale_v1_7_14=$RDI_DATADIR/xsim/ip/gtwizard_ultrascale_v1_7_14
+ai_pl=$RDI_DATADIR/xsim/ip/ai_pl
+v_vid_in_axi4s_v5_0_2=$RDI_DATADIR/xsim/ip/v_vid_in_axi4s_v5_0_2
+dp_videoaxi4s_bridge_v1_0_1=$RDI_DATADIR/xsim/ip/dp_videoaxi4s_bridge_v1_0_1
+qdma_v5_0_0=$RDI_DATADIR/xsim/ip/qdma_v5_0_0
+xbip_dsp48_mult_v3_0_6=$RDI_DATADIR/xsim/ip/xbip_dsp48_mult_v3_0_6
+axis_vio_v1_0_7=$RDI_DATADIR/xsim/ip/axis_vio_v1_0_7
+c_compare_v12_0_6=$RDI_DATADIR/xsim/ip/c_compare_v12_0_6
+spdif_v2_0_26=$RDI_DATADIR/xsim/ip/spdif_v2_0_26
+xdfe_common_v1_0_0=$RDI_DATADIR/xsim/ip/xdfe_common_v1_0_0
+tcc_decoder_3gppmm_v2_0_24=$RDI_DATADIR/xsim/ip/tcc_decoder_3gppmm_v2_0_24
+axi_timebase_wdt_v3_0_19=$RDI_DATADIR/xsim/ip/axi_timebase_wdt_v3_0_19
+pci32_v5_0_12=$RDI_DATADIR/xsim/ip/pci32_v5_0_12
+polar_v1_1_0=$RDI_DATADIR/xsim/ip/polar_v1_1_0
+fir_compiler_v5_2_6=$RDI_DATADIR/xsim/ip/fir_compiler_v5_2_6
+axis_data_fifo_v1_1_28=$RDI_DATADIR/xsim/ip/axis_data_fifo_v1_1_28
+hdmi_gt_controller_v1_0_8=$RDI_DATADIR/xsim/ip/hdmi_gt_controller_v1_0_8
+compact_gt_v1_0_13=$RDI_DATADIR/xsim/ip/compact_gt_v1_0_13
+axi_remapper_tx_v1_0_0=$RDI_DATADIR/xsim/ip/axi_remapper_tx_v1_0_0
+xbip_utils_v3_0_10=$RDI_DATADIR/xsim/ip/xbip_utils_v3_0_10
+anlt_subcore_ip_v1_0_0=$RDI_DATADIR/xsim/ip/anlt_subcore_ip_v1_0_0
+ieee802d3_50g_rs_fec_v1_0_20=$RDI_DATADIR/xsim/ip/ieee802d3_50g_rs_fec_v1_0_20
+tsn_endpoint_ethernet_mac_block_v1_0_12=$RDI_DATADIR/xsim/ip/tsn_endpoint_ethernet_mac_block_v1_0_12
+sim_clk_gen_v1_0_3=$RDI_DATADIR/xsim/ip/sim_clk_gen_v1_0_3
+can_v5_0_30=$RDI_DATADIR/xsim/ip/can_v5_0_30
+v_warp_init_v1_1_1=$RDI_DATADIR/xsim/ip/v_warp_init_v1_1_1
+perf_axi_tg_v1_0_9=$RDI_DATADIR/xsim/ip/perf_axi_tg_v1_0_9
+axi_epu_v1_0_0=$RDI_DATADIR/xsim/ip/axi_epu_v1_0_0
+gmii_to_rgmii_v4_1_5=$RDI_DATADIR/xsim/ip/gmii_to_rgmii_v4_1_5
+noc_nps_v1_0_0=$RDI_DATADIR/xsim/ip/noc_nps_v1_0_0
+advanced_io_wizard_v1_0_8=$RDI_DATADIR/xsim/ip/advanced_io_wizard_v1_0_8
+convolution_v9_0_16=$RDI_DATADIR/xsim/ip/convolution_v9_0_16
+axis_accelerator_adapter_v2_1_16=$RDI_DATADIR/xsim/ip/axis_accelerator_adapter_v2_1_16
+microblaze_mcs_v2_3_6=$RDI_DATADIR/xsim/ip/microblaze_mcs_v2_3_6
+axi_infrastructure_v1_1_0=$RDI_DATADIR/xsim/ip/axi_infrastructure_v1_1_0
+ai_pl_trig=$RDI_DATADIR/xsim/ip/ai_pl_trig
+axi_protocol_checker_v2_0_13=$RDI_DATADIR/xsim/ip/axi_protocol_checker_v2_0_13
+high_speed_selectio_wiz_v3_6_4=$RDI_DATADIR/xsim/ip/high_speed_selectio_wiz_v3_6_4
+xbip_dsp48_addsub_v3_0_6=$RDI_DATADIR/xsim/ip/xbip_dsp48_addsub_v3_0_6
+axi_traffic_gen_v3_0_13=$RDI_DATADIR/xsim/ip/axi_traffic_gen_v3_0_13
+ieee802d3_clause74_fec_v1_0_14=$RDI_DATADIR/xsim/ip/ieee802d3_clause74_fec_v1_0_14
+hdcp22_cipher_dp_v1_0_0=$RDI_DATADIR/xsim/ip/hdcp22_cipher_dp_v1_0_0
+axi_perf_mon_v5_0_29=$RDI_DATADIR/xsim/ip/axi_perf_mon_v5_0_29
+func_emu_util_v1_0=$RDI_DATADIR/xsim/ip/func_emu_util_v1_0
+clk_vip_v1_0_2=$RDI_DATADIR/xsim/ip/clk_vip_v1_0_2
+axis_infrastructure_v1_1_0=$RDI_DATADIR/xsim/ip/axis_infrastructure_v1_1_0
+c_mux_bit_v12_0_6=$RDI_DATADIR/xsim/ip/c_mux_bit_v12_0_6
+v_sdi_rx_vid_bridge_v2_0_0=$RDI_DATADIR/xsim/ip/v_sdi_rx_vid_bridge_v2_0_0
+sim_qdma_sc_v1_0=$RDI_DATADIR/xsim/ip/sim_qdma_sc_v1_0
+uhdsdi_gt_v2_1_0=$RDI_DATADIR/xsim/ip/uhdsdi_gt_v2_1_0
+util_reduced_logic_v2_0_4=$RDI_DATADIR/xsim/ip/util_reduced_logic_v2_0_4
+bscan_axi_v1_0_0=$RDI_DATADIR/xsim/ip/bscan_axi_v1_0_0
+v_hdmi_phy1_v1_0_7=$RDI_DATADIR/xsim/ip/v_hdmi_phy1_v1_0_7
+v_frmbuf_rd_v2_2_6=$RDI_DATADIR/xsim/ip/v_frmbuf_rd_v2_2_6
+noc_hbm_v1_0_0=$RDI_DATADIR/xsim/ip/noc_hbm_v1_0_0
+nvmeha_v1_0_8=$RDI_DATADIR/xsim/ip/nvmeha_v1_0_8
+pl_fileio_v1_0_0=$RDI_DATADIR/xsim/ip/pl_fileio_v1_0_0
+axi_apb_bridge_v3_0_17=$RDI_DATADIR/xsim/ip/axi_apb_bridge_v3_0_17
+tri_mode_ethernet_mac_v9_0_23=$RDI_DATADIR/xsim/ip/tri_mode_ethernet_mac_v9_0_23
+usxgmii_v1_2_8=$RDI_DATADIR/xsim/ip/usxgmii_v1_2_8
+axi_mcdma_v1_1_8=$RDI_DATADIR/xsim/ip/axi_mcdma_v1_1_8
+ibert_lib_v1_0_7=$RDI_DATADIR/xsim/ip/ibert_lib_v1_0_7
+axi_master_burst_v2_0_7=$RDI_DATADIR/xsim/ip/axi_master_burst_v2_0_7
+aie_xtlm_v1_0_0=$RDI_DATADIR/xsim/ip/aie_xtlm_v1_0_0
+tcc_encoder_3gpp_v5_0_18=$RDI_DATADIR/xsim/ip/tcc_encoder_3gpp_v5_0_18
+xdma_v4_1_20=$RDI_DATADIR/xsim/ip/xdma_v4_1_20
+xlslice_v1_0_2=$RDI_DATADIR/xsim/ip/xlslice_v1_0_2
+ddr4_pl_v1_0_9=$RDI_DATADIR/xsim/ip/ddr4_pl_v1_0_9
+g709_fec_v2_4_6=$RDI_DATADIR/xsim/ip/g709_fec_v2_4_6
+ai_noc=$RDI_DATADIR/xsim/ip/ai_noc
+fit_timer_v2_0_10=$RDI_DATADIR/xsim/ip/fit_timer_v2_0_10
+xdfe_nr_prach_v1_1_0=$RDI_DATADIR/xsim/ip/xdfe_nr_prach_v1_1_0
+noc2_xbr2x4_v1_0_0=$RDI_DATADIR/xsim/ip/noc2_xbr2x4_v1_0_0
+xtlm_trace_model_v1_0=$RDI_DATADIR/xsim/ip/xtlm_trace_model_v1_0
+v_hdmi_tx_v3_0_0=$RDI_DATADIR/xsim/ip/v_hdmi_tx_v3_0_0
+lib_cdc_v1_0_2=$RDI_DATADIR/xsim/ip/lib_cdc_v1_0_2
+gigantic_mux=$RDI_DATADIR/xsim/ip/gigantic_mux
+v_vid_sdi_tx_bridge_v2_0_0=$RDI_DATADIR/xsim/ip/v_vid_sdi_tx_bridge_v2_0_0
+dprx_v1_0_0=$RDI_DATADIR/xsim/ip/dprx_v1_0_0
+jesd204c_v4_2_9=$RDI_DATADIR/xsim/ip/jesd204c_v4_2_9
+etrnic_v1_1_5=$RDI_DATADIR/xsim/ip/etrnic_v1_1_5
+axi_dwidth_converter_v2_1_27=$RDI_DATADIR/xsim/ip/axi_dwidth_converter_v2_1_27
+v_frmbuf_wr_v2_2_6=$RDI_DATADIR/xsim/ip/v_frmbuf_wr_v2_2_6
+xsdbm_v3_0_0=$RDI_DATADIR/xsim/ip/xsdbm_v3_0_0
+rs_encoder_v9_0_17=$RDI_DATADIR/xsim/ip/rs_encoder_v9_0_17
+xdfe_resampler_v1_0_5=$RDI_DATADIR/xsim/ip/xdfe_resampler_v1_0_5
+xxv_ethernet_v4_1_1=$RDI_DATADIR/xsim/ip/xxv_ethernet_v4_1_1
+hdcp_v1_0_3=$RDI_DATADIR/xsim/ip/hdcp_v1_0_3
+vby1hs_v1_0_2=$RDI_DATADIR/xsim/ip/vby1hs_v1_0_2
+axi_mm2s_mapper_v1_1_26=$RDI_DATADIR/xsim/ip/axi_mm2s_mapper_v1_1_26
+v_smpte_sdi_v3_0_9=$RDI_DATADIR/xsim/ip/v_smpte_sdi_v3_0_9
+v_frmbuf_rd_v2_3_2=$RDI_DATADIR/xsim/ip/v_frmbuf_rd_v2_3_2
+emb_mem_gen_v1_0_6=$RDI_DATADIR/xsim/ip/emb_mem_gen_v1_0_6
+axi_protocol_converter_v2_1_27=$RDI_DATADIR/xsim/ip/axi_protocol_converter_v2_1_27
+div_gen_v5_1_19=$RDI_DATADIR/xsim/ip/div_gen_v5_1_19
+xdfe_fft_v1_0_4=$RDI_DATADIR/xsim/ip/xdfe_fft_v1_0_4
+hbm2e_pl_v1_0_0=$RDI_DATADIR/xsim/ip/hbm2e_pl_v1_0_0
+mammoth_transcode_v1_0_0=$RDI_DATADIR/xsim/ip/mammoth_transcode_v1_0_0
+v_letterbox_v1_1_6=$RDI_DATADIR/xsim/ip/v_letterbox_v1_1_6
+v_gamma_lut_v1_1_6=$RDI_DATADIR/xsim/ip/v_gamma_lut_v1_1_6
+tmr_voter_v1_0_4=$RDI_DATADIR/xsim/ip/tmr_voter_v1_0_4
+cpm4_v1_0_9=$RDI_DATADIR/xsim/ip/cpm4_v1_0_9
+vid_phy_controller_v2_2_14=$RDI_DATADIR/xsim/ip/vid_phy_controller_v2_2_14
+v_tpg_v8_2_2=$RDI_DATADIR/xsim/ip/v_tpg_v8_2_2
+xlconstant_v1_1_7=$RDI_DATADIR/xsim/ip/xlconstant_v1_1_7
+c_mux_bus_v12_0_6=$RDI_DATADIR/xsim/ip/c_mux_bus_v12_0_6
+g975_efec_i4_v1_0_19=$RDI_DATADIR/xsim/ip/g975_efec_i4_v1_0_19
+lmb_bram_if_cntlr_v4_0=$RDI_DATADIR/xsim/ip/lmb_bram_if_cntlr_v4_0
+v_warp_filter_v1_0_2=$RDI_DATADIR/xsim/ip/v_warp_filter_v1_0_2
+i2s_receiver_v1_0_5=$RDI_DATADIR/xsim/ip/i2s_receiver_v1_0_5
+zynq_ultra_ps_e_v3_3_8=$RDI_DATADIR/xsim/ip/zynq_ultra_ps_e_v3_3_8
+axis_cap_ctrl_v1_0_0=$RDI_DATADIR/xsim/ip/axis_cap_ctrl_v1_0_0
+pcie_jtag_v1_0_0=$RDI_DATADIR/xsim/ip/pcie_jtag_v1_0_0
+lmb_v10_v3_0=$RDI_DATADIR/xsim/ip/lmb_v10_v3_0
+dist_mem_gen_v8_0_13=$RDI_DATADIR/xsim/ip/dist_mem_gen_v8_0_13
+v_warp_init_v1_0_2=$RDI_DATADIR/xsim/ip/v_warp_init_v1_0_2
+displayport_v7_0_0=$RDI_DATADIR/xsim/ip/displayport_v7_0_0
+versal_cips_v3_2_2=$RDI_DATADIR/xsim/ip/versal_cips_v3_2_2
+lib_fifo_v1_0_16=$RDI_DATADIR/xsim/ip/lib_fifo_v1_0_16
+blk_mem_gen_v8_3_6=$RDI_DATADIR/xsim/ip/blk_mem_gen_v8_3_6
+emb_fifo_gen_v1_0_2=$RDI_DATADIR/xsim/ip/emb_fifo_gen_v1_0_2
+microblaze_v11_0_10=$RDI_DATADIR/xsim/ip/microblaze_v11_0_10
+dfx_bitstream_monitor_v1_0_2=$RDI_DATADIR/xsim/ip/dfx_bitstream_monitor_v1_0_2
+vfb_v1_0_21=$RDI_DATADIR/xsim/ip/vfb_v1_0_21
+ecc_v2_0_13=$RDI_DATADIR/xsim/ip/ecc_v2_0_13
+mrmac_v2_0_0=$RDI_DATADIR/xsim/ip/mrmac_v2_0_0
+rwd_tlmmodel_v1=$RDI_DATADIR/xsim/ip/rwd_tlmmodel_v1
+ernic_v4_0_0=$RDI_DATADIR/xsim/ip/ernic_v4_0_0
+mailbox_v2_1_15=$RDI_DATADIR/xsim/ip/mailbox_v2_1_15
+noc_nidb_v1_0_0=$RDI_DATADIR/xsim/ip/noc_nidb_v1_0_0
+displayport_v9_0_5=$RDI_DATADIR/xsim/ip/displayport_v9_0_5
+ll_compress_v2_0_1=$RDI_DATADIR/xsim/ip/ll_compress_v2_0_1
+cordic_v6_0_18=$RDI_DATADIR/xsim/ip/cordic_v6_0_18
+tmr_manager_v1_0_10=$RDI_DATADIR/xsim/ip/tmr_manager_v1_0_10
+axis_mem_v1_0_0=$RDI_DATADIR/xsim/ip/axis_mem_v1_0_0
+noc2_nmu_v1_0_0=$RDI_DATADIR/xsim/ip/noc2_nmu_v1_0_0
+aie_ps_v1_0=$RDI_DATADIR/xsim/ip/aie_ps_v1_0
+noc_sc_v1_0_0=$RDI_DATADIR/xsim/ip/noc_sc_v1_0_0
+rst_vip_v1_0_4=$RDI_DATADIR/xsim/ip/rst_vip_v1_0_4
+mult_gen_v12_0_18=$RDI_DATADIR/xsim/ip/mult_gen_v12_0_18
+qdriv_pl_phy_v1_0_0=$RDI_DATADIR/xsim/ip/qdriv_pl_phy_v1_0_0
+av_pat_gen_v2_0_0=$RDI_DATADIR/xsim/ip/av_pat_gen_v2_0_0
+xtlm_simple_interconnect_v1_0=$RDI_DATADIR/xsim/ip/xtlm_simple_interconnect_v1_0
+stm_v1_0_0=$RDI_DATADIR/xsim/ip/stm_v1_0_0
+zynq_ultra_ps_e_vip_v1_0_13=$RDI_DATADIR/xsim/ip/zynq_ultra_ps_e_vip_v1_0_13
+ieee802d3_50g_rs_fec_v2_0_12=$RDI_DATADIR/xsim/ip/ieee802d3_50g_rs_fec_v2_0_12
+axi_dma_v7_1_28=$RDI_DATADIR/xsim/ip/axi_dma_v7_1_28
+processing_system7_v5_5_6=$RDI_DATADIR/xsim/ip/processing_system7_v5_5_6
+v_hscaler_v1_1_6=$RDI_DATADIR/xsim/ip/v_hscaler_v1_1_6
+ldpc_v2_0_11=$RDI_DATADIR/xsim/ip/ldpc_v2_0_11
+axi_utils_v2_0_6=$RDI_DATADIR/xsim/ip/axi_utils_v2_0_6
+ieee802d3_rs_fec_v2_0_16=$RDI_DATADIR/xsim/ip/ieee802d3_rs_fec_v2_0_16
+advanced_io_wizard_phy_v1_0_0=$RDI_DATADIR/xsim/ip/advanced_io_wizard_phy_v1_0_0
+fifo_generator_v13_0_6=$RDI_DATADIR/xsim/ip/fifo_generator_v13_0_6
+v_vcresampler_v1_1_6=$RDI_DATADIR/xsim/ip/v_vcresampler_v1_1_6
+axi_emc_v3_0_27=$RDI_DATADIR/xsim/ip/axi_emc_v3_0_27
+axi_hbicap_v1_0_4=$RDI_DATADIR/xsim/ip/axi_hbicap_v1_0_4
+util_idelay_ctrl_v1_0_2=$RDI_DATADIR/xsim/ip/util_idelay_ctrl_v1_0_2
+xbip_dsp48_acc_v3_0_6=$RDI_DATADIR/xsim/ip/xbip_dsp48_acc_v3_0_6
+lmb_v10_v3_0_12=$RDI_DATADIR/xsim/ip/lmb_v10_v3_0_12
+axi_cdma_v4_1_27=$RDI_DATADIR/xsim/ip/axi_cdma_v4_1_27
+iomodule_v3_1_8=$RDI_DATADIR/xsim/ip/iomodule_v3_1_8
+tmr_sem_v1_0_23=$RDI_DATADIR/xsim/ip/tmr_sem_v1_0_23
+sem_v4_1_13=$RDI_DATADIR/xsim/ip/sem_v4_1_13
+video_frame_crc_v1_0_4=$RDI_DATADIR/xsim/ip/video_frame_crc_v1_0_4
+axi_lmb_bridge_v1_0_1=$RDI_DATADIR/xsim/ip/axi_lmb_bridge_v1_0_1
+ten_gig_eth_mac_v15_1_10=$RDI_DATADIR/xsim/ip/ten_gig_eth_mac_v15_1_10
+v_hdmi_rx_v3_0_0=$RDI_DATADIR/xsim/ip/v_hdmi_rx_v3_0_0
+rama_v1_1_13_lib=$RDI_DATADIR/xsim/ip/rama_v1_1_13_lib
+hdcp_keymngmt_blk_v1_0_0=$RDI_DATADIR/xsim/ip/hdcp_keymngmt_blk_v1_0_0
+v_vid_gt_bridge_v1_0_6=$RDI_DATADIR/xsim/ip/v_vid_gt_bridge_v1_0_6
+pc_cfr_v7_0_1=$RDI_DATADIR/xsim/ip/pc_cfr_v7_0_1
+mutex_v2_1_11=$RDI_DATADIR/xsim/ip/mutex_v2_1_11
+axis_dwidth_converter_sc_v1_1=$RDI_DATADIR/xsim/ip/axis_dwidth_converter_sc_v1_1
+shell_utils_addr_remap_v1_0_6=$RDI_DATADIR/xsim/ip/shell_utils_addr_remap_v1_0_6
+xfft_v7_2_13=$RDI_DATADIR/xsim/ip/xfft_v7_2_13
+v_demosaic_v1_1_6=$RDI_DATADIR/xsim/ip/v_demosaic_v1_1_6
+axi_lite_ipif_v3_0_4=$RDI_DATADIR/xsim/ip/axi_lite_ipif_v3_0_4
+c_addsub_v12_0_14=$RDI_DATADIR/xsim/ip/c_addsub_v12_0_14
diff --git a/game.sim/sim_1/behav/xsim/xvhdl.log b/game.sim/sim_1/behav/xsim/xvhdl.log
new file mode 100644
index 0000000000000000000000000000000000000000..1b4ecdab156140987e6dbd0399e74d458aeff7ef
--- /dev/null
+++ b/game.sim/sim_1/behav/xsim/xvhdl.log
@@ -0,0 +1,2 @@
+INFO: [VRFC 10-163] Analyzing VHDL file "/home/prasic/game/game.srcs/sources_1/new/runner.vhd" into library xil_defaultlib
+INFO: [VRFC 10-3107] analyzing entity 'runner'
diff --git a/game.sim/sim_1/behav/xsim/xvhdl.pb b/game.sim/sim_1/behav/xsim/xvhdl.pb
new file mode 100644
index 0000000000000000000000000000000000000000..13950188e823ee75dbac81a9d013d1018914193e
Binary files /dev/null and b/game.sim/sim_1/behav/xsim/xvhdl.pb differ
diff --git a/game.sim/sim_1/behav/xsim/xvlog.log b/game.sim/sim_1/behav/xsim/xvlog.log
new file mode 100644
index 0000000000000000000000000000000000000000..e69de29bb2d1d6434b8b29ae775ad8c2e48c5391
diff --git a/game.sim/sim_1/behav/xsim/xvlog.pb b/game.sim/sim_1/behav/xsim/xvlog.pb
new file mode 100644
index 0000000000000000000000000000000000000000..b155e40f06a230303a04d2a77f07560e35c5dc93
--- /dev/null
+++ b/game.sim/sim_1/behav/xsim/xvlog.pb
@@ -0,0 +1,4 @@
+
+
+
+End Record
\ No newline at end of file
diff --git a/game.srcs/constrs_1/imports/PrASIC_Data/Nexys4_Master.xdc b/game.srcs/constrs_1/imports/PrASIC_Data/Nexys4_Master.xdc
new file mode 100644
index 0000000000000000000000000000000000000000..c87008cabfccc328d49e028e3a9280b575a4f9b9
--- /dev/null
+++ b/game.srcs/constrs_1/imports/PrASIC_Data/Nexys4_Master.xdc
@@ -0,0 +1,722 @@
+## This file is a general .xdc for the Nexys4 rev B board
+## To use it in a project:
+## - uncomment the lines corresponding to used pins
+## - rename the used ports (in each line, after get_ports) according to the top level signal names in the project
+
+## Clock signal
+#Bank = 35, Pin name = IO_L12P_T1_MRCC_35, Sch name = CLK100MHZ
+set_property PACKAGE_PIN E3 [get_ports clk]
+ set_property IOSTANDARD LVCMOS33 [get_ports clk]
+ create_clock -add -name sys_clk_pin -period 10.00 -waveform {0 5} [get_ports clk]
+
+## Switches
+##Bank = 34, Pin name = IO_L21P_T3_DQS_34, Sch name = SW0
+#set_property PACKAGE_PIN U9 [get_ports {sw[0]}]
+ #set_property IOSTANDARD LVCMOS33 [get_ports {sw[0]}]
+##Bank = 34, Pin name = IO_25_34, Sch name = SW1
+#set_property PACKAGE_PIN U8 [get_ports {sw[1]}]
+ #set_property IOSTANDARD LVCMOS33 [get_ports {sw[1]}]
+##Bank = 34, Pin name = IO_L23P_T3_34, Sch name = SW2
+#set_property PACKAGE_PIN R7 [get_ports {sw[2]}]
+ #set_property IOSTANDARD LVCMOS33 [get_ports {sw[2]}]
+##Bank = 34, Pin name = IO_L19P_T3_34, Sch name = SW3
+#set_property PACKAGE_PIN R6 [get_ports {sw[3]}]
+ #set_property IOSTANDARD LVCMOS33 [get_ports {sw[3]}]
+##Bank = 34, Pin name = IO_L19N_T3_VREF_34, Sch name = SW4
+#set_property PACKAGE_PIN R5 [get_ports {sw[4]}]
+ #set_property IOSTANDARD LVCMOS33 [get_ports {sw[4]}]
+##Bank = 34, Pin name = IO_L20P_T3_34, Sch name = SW5
+#set_property PACKAGE_PIN V7 [get_ports {sw[5]}]
+ #set_property IOSTANDARD LVCMOS33 [get_ports {sw[5]}]
+##Bank = 34, Pin name = IO_L20N_T3_34, Sch name = SW6
+#set_property PACKAGE_PIN V6 [get_ports {sw[6]}]
+ #set_property IOSTANDARD LVCMOS33 [get_ports {sw[6]}]
+##Bank = 34, Pin name = IO_L10P_T1_34, Sch name = SW7
+#set_property PACKAGE_PIN V5 [get_ports {sw[7]}]
+ #set_property IOSTANDARD LVCMOS33 [get_ports {sw[7]}]
+##Bank = 34, Pin name = IO_L8P_T1-34, Sch name = SW8
+#set_property PACKAGE_PIN U4 [get_ports {sw[8]}]
+ #set_property IOSTANDARD LVCMOS33 [get_ports {sw[8]}]
+##Bank = 34, Pin name = IO_L9N_T1_DQS_34, Sch name = SW9
+#set_property PACKAGE_PIN V2 [get_ports {sw[9]}]
+ #set_property IOSTANDARD LVCMOS33 [get_ports {sw[9]}]
+##Bank = 34, Pin name = IO_L9P_T1_DQS_34, Sch name = SW10
+#set_property PACKAGE_PIN U2 [get_ports {sw[10]}]
+ #set_property IOSTANDARD LVCMOS33 [get_ports {sw[10]}]
+##Bank = 34, Pin name = IO_L11N_T1_MRCC_34, Sch name = SW11
+#set_property PACKAGE_PIN T3 [get_ports {sw[11]}]
+ #set_property IOSTANDARD LVCMOS33 [get_ports {sw[11]}]
+##Bank = 34, Pin name = IO_L17N_T2_34, Sch name = SW12
+#set_property PACKAGE_PIN T1 [get_ports {sw[12]}]
+ #set_property IOSTANDARD LVCMOS33 [get_ports {sw[12]}]
+##Bank = 34, Pin name = IO_L11P_T1_SRCC_34, Sch name = SW13
+#set_property PACKAGE_PIN R3 [get_ports {sw[13]}]
+ #set_property IOSTANDARD LVCMOS33 [get_ports {sw[13]}]
+##Bank = 34, Pin name = IO_L14N_T2_SRCC_34, Sch name = SW14
+#set_property PACKAGE_PIN P3 [get_ports {sw[14]}]
+ #set_property IOSTANDARD LVCMOS33 [get_ports {sw[14]}]
+##Bank = 34, Pin name = IO_L14P_T2_SRCC_34, Sch name = SW15
+#set_property PACKAGE_PIN P4 [get_ports {sw[15]}]
+ #set_property IOSTANDARD LVCMOS33 [get_ports {sw[15]}]
+
+
+
+# LEDs
+#Bank = 34, Pin name = IO_L24N_T3_34, Sch name = LED0
+set_property PACKAGE_PIN T8 [get_ports {led[0]}]
+ set_property IOSTANDARD LVCMOS33 [get_ports {led[0]}]
+#Bank = 34, Pin name = IO_L21N_T3_DQS_34, Sch name = LED1
+set_property PACKAGE_PIN V9 [get_ports {led[1]}]
+ set_property IOSTANDARD LVCMOS33 [get_ports {led[1]}]
+#Bank = 34, Pin name = IO_L24P_T3_34, Sch name = LED2
+set_property PACKAGE_PIN R8 [get_ports {led[2]}]
+ set_property IOSTANDARD LVCMOS33 [get_ports {led[2]}]
+#Bank = 34, Pin name = IO_L23N_T3_34, Sch name = LED3
+set_property PACKAGE_PIN T6 [get_ports {led[3]}]
+ set_property IOSTANDARD LVCMOS33 [get_ports {led[3]}]
+#Bank = 34, Pin name = IO_L12P_T1_MRCC_34, Sch name = LED4
+set_property PACKAGE_PIN T5 [get_ports {led[4]}]
+ set_property IOSTANDARD LVCMOS33 [get_ports {led[4]}]
+#Bank = 34, Pin name = IO_L12N_T1_MRCC_34, Sch name = LED5
+set_property PACKAGE_PIN T4 [get_ports {led[5]}]
+ set_property IOSTANDARD LVCMOS33 [get_ports {led[5]}]
+#Bank = 34, Pin name = IO_L22P_T3_34, Sch name = LED6
+set_property PACKAGE_PIN U7 [get_ports {led[6]}]
+ set_property IOSTANDARD LVCMOS33 [get_ports {led[6]}]
+#Bank = 34, Pin name = IO_L22N_T3_34, Sch name = LED7
+set_property PACKAGE_PIN U6 [get_ports {led[7]}]
+ set_property IOSTANDARD LVCMOS33 [get_ports {led[7]}]
+#Bank = 34, Pin name = IO_L10N_T1_34, Sch name = LED8
+set_property PACKAGE_PIN V4 [get_ports {led[8]}]
+ set_property IOSTANDARD LVCMOS33 [get_ports {led[8]}]
+#Bank = 34, Pin name = IO_L8N_T1_34, Sch name = LED9
+set_property PACKAGE_PIN U3 [get_ports {led[9]}]
+ set_property IOSTANDARD LVCMOS33 [get_ports {led[9]}]
+#Bank = 34, Pin name = IO_L7N_T1_34, Sch name = LED10
+set_property PACKAGE_PIN V1 [get_ports {led[10]}]
+ set_property IOSTANDARD LVCMOS33 [get_ports {led[10]}]
+#Bank = 34, Pin name = IO_L17P_T2_34, Sch name = LED11
+set_property PACKAGE_PIN R1 [get_ports {led[11]}]
+ set_property IOSTANDARD LVCMOS33 [get_ports {led[11]}]
+#Bank = 34, Pin name = IO_L13N_T2_MRCC_34, Sch name = LED12
+set_property PACKAGE_PIN P5 [get_ports {led[12]}]
+ set_property IOSTANDARD LVCMOS33 [get_ports {led[12]}]
+#Bank = 34, Pin name = IO_L7P_T1_34, Sch name = LED13
+set_property PACKAGE_PIN U1 [get_ports {led[13]}]
+ set_property IOSTANDARD LVCMOS33 [get_ports {led[13]}]
+#Bank = 34, Pin name = IO_L15N_T2_DQS_34, Sch name = LED14
+set_property PACKAGE_PIN R2 [get_ports {led[14]}]
+ set_property IOSTANDARD LVCMOS33 [get_ports {led[14]}]
+#Bank = 34, Pin name = IO_L15P_T2_DQS_34, Sch name = LED15
+set_property PACKAGE_PIN P2 [get_ports {led[15]}]
+ set_property IOSTANDARD LVCMOS33 [get_ports {led[15]}]
+
+##Bank = 34, Pin name = IO_L5P_T0_34, Sch name = LED16_R
+#set_property PACKAGE_PIN K5 [get_ports RGB1_Red]
+ #set_property IOSTANDARD LVCMOS33 [get_ports RGB1_Red]
+##Bank = 15, Pin name = IO_L5P_T0_AD9P_15, Sch name = LED16_G
+#set_property PACKAGE_PIN F13 [get_ports RGB1_Green]
+ #set_property IOSTANDARD LVCMOS33 [get_ports RGB1_Green]
+##Bank = 35, Pin name = IO_L19N_T3_VREF_35, Sch name = LED16_B
+#set_property PACKAGE_PIN F6 [get_ports RGB1_Blue]
+ #set_property IOSTANDARD LVCMOS33 [get_ports RGB1_Blue]
+##Bank = 34, Pin name = IO_0_34, Sch name = LED17_R
+#set_property PACKAGE_PIN K6 [get_ports RGB2_Red]
+ #set_property IOSTANDARD LVCMOS33 [get_ports RGB2_Red]
+##Bank = 35, Pin name = IO_24P_T3_35, Sch name = LED17_G
+#set_property PACKAGE_PIN H6 [get_ports RGB2_Green]
+ #set_property IOSTANDARD LVCMOS33 [get_ports RGB2_Green]
+##Bank = CONFIG, Pin name = IO_L3N_T0_DQS_EMCCLK_14, Sch name = LED17_B
+#set_property PACKAGE_PIN L16 [get_ports RGB2_Blue]
+ #set_property IOSTANDARD LVCMOS33 [get_ports RGB2_Blue]
+
+
+
+##7 segment display
+##Bank = 34, Pin name = IO_L2N_T0_34, Sch name = CA
+#set_property PACKAGE_PIN L3 [get_ports {seg[0]}]
+ #set_property IOSTANDARD LVCMOS33 [get_ports {seg[0]}]
+##Bank = 34, Pin name = IO_L3N_T0_DQS_34, Sch name = CB
+#set_property PACKAGE_PIN N1 [get_ports {seg[1]}]
+ #set_property IOSTANDARD LVCMOS33 [get_ports {seg[1]}]
+##Bank = 34, Pin name = IO_L6N_T0_VREF_34, Sch name = CC
+#set_property PACKAGE_PIN L5 [get_ports {seg[2]}]
+ #set_property IOSTANDARD LVCMOS33 [get_ports {seg[2]}]
+##Bank = 34, Pin name = IO_L5N_T0_34, Sch name = CD
+#set_property PACKAGE_PIN L4 [get_ports {seg[3]}]
+ #set_property IOSTANDARD LVCMOS33 [get_ports {seg[3]}]
+##Bank = 34, Pin name = IO_L2P_T0_34, Sch name = CE
+#set_property PACKAGE_PIN K3 [get_ports {seg[4]}]
+ #set_property IOSTANDARD LVCMOS33 [get_ports {seg[4]}]
+##Bank = 34, Pin name = IO_L4N_T0_34, Sch name = CF
+#set_property PACKAGE_PIN M2 [get_ports {seg[5]}]
+ #set_property IOSTANDARD LVCMOS33 [get_ports {seg[5]}]
+##Bank = 34, Pin name = IO_L6P_T0_34, Sch name = CG
+#set_property PACKAGE_PIN L6 [get_ports {seg[6]}]
+ #set_property IOSTANDARD LVCMOS33 [get_ports {seg[6]}]
+
+##Bank = 34, Pin name = IO_L16P_T2_34, Sch name = DP
+#set_property PACKAGE_PIN M4 [get_ports dp]
+ #set_property IOSTANDARD LVCMOS33 [get_ports dp]
+
+##Bank = 34, Pin name = IO_L18N_T2_34, Sch name = AN0
+#set_property PACKAGE_PIN N6 [get_ports {an[0]}]
+ #set_property IOSTANDARD LVCMOS33 [get_ports {an[0]}]
+##Bank = 34, Pin name = IO_L18P_T2_34, Sch name = AN1
+#set_property PACKAGE_PIN M6 [get_ports {an[1]}]
+ #set_property IOSTANDARD LVCMOS33 [get_ports {an[1]}]
+##Bank = 34, Pin name = IO_L4P_T0_34, Sch name = AN2
+#set_property PACKAGE_PIN M3 [get_ports {an[2]}]
+ #set_property IOSTANDARD LVCMOS33 [get_ports {an[2]}]
+##Bank = 34, Pin name = IO_L13_T2_MRCC_34, Sch name = AN3
+#set_property PACKAGE_PIN N5 [get_ports {an[3]}]
+ #set_property IOSTANDARD LVCMOS33 [get_ports {an[3]}]
+##Bank = 34, Pin name = IO_L3P_T0_DQS_34, Sch name = AN4
+#set_property PACKAGE_PIN N2 [get_ports {an[4]}]
+ #set_property IOSTANDARD LVCMOS33 [get_ports {an[4]}]
+##Bank = 34, Pin name = IO_L16N_T2_34, Sch name = AN5
+#set_property PACKAGE_PIN N4 [get_ports {an[5]}]
+ #set_property IOSTANDARD LVCMOS33 [get_ports {an[5]}]
+##Bank = 34, Pin name = IO_L1P_T0_34, Sch name = AN6
+#set_property PACKAGE_PIN L1 [get_ports {an[6]}]
+ #set_property IOSTANDARD LVCMOS33 [get_ports {an[6]}]
+##Bank = 34, Pin name = IO_L1N_T034, Sch name = AN7
+#set_property PACKAGE_PIN M1 [get_ports {an[7]}]
+ #set_property IOSTANDARD LVCMOS33 [get_ports {an[7]}]
+
+
+
+##Buttons
+##Bank = 15, Pin name = IO_L3P_T0_DQS_AD1P_15, Sch name = CPU_RESET
+set_property PACKAGE_PIN C12 [get_ports btnCpuReset]
+ set_property IOSTANDARD LVCMOS33 [get_ports btnCpuReset]
+##Bank = 15, Pin name = IO_L11N_T1_SRCC_15, Sch name = BTNC
+#set_property PACKAGE_PIN E16 [get_ports btnC]
+ #set_property IOSTANDARD LVCMOS33 [get_ports btnC]
+##Bank = 15, Pin name = IO_L14P_T2_SRCC_15, Sch name = BTNU
+set_property PACKAGE_PIN F15 [get_ports btnU]
+ set_property IOSTANDARD LVCMOS33 [get_ports btnU]
+##Bank = CONFIG, Pin name = IO_L15N_T2_DQS_DOUT_CSO_B_14, Sch name = BTNL
+#set_property PACKAGE_PIN T16 [get_ports btnL]
+ #set_property IOSTANDARD LVCMOS33 [get_ports btnL]
+##Bank = 14, Pin name = IO_25_14, Sch name = BTNR
+#set_property PACKAGE_PIN R10 [get_ports btnR]
+ #set_property IOSTANDARD LVCMOS33 [get_ports btnR]
+##Bank = 14, Pin name = IO_L21P_T3_DQS_14, Sch name = BTND
+#set_property PACKAGE_PIN V10 [get_ports btnD]
+ #set_property IOSTANDARD LVCMOS33 [get_ports btnD]
+
+
+
+##Pmod Header JA
+##Bank = 15, Pin name = IO_L1N_T0_AD0N_15, Sch name = JA1
+#set_property PACKAGE_PIN B13 [get_ports {JA[0]}]
+ #set_property IOSTANDARD LVCMOS33 [get_ports {JA[0]}]
+##Bank = 15, Pin name = IO_L5N_T0_AD9N_15, Sch name = JA2
+#set_property PACKAGE_PIN F14 [get_ports {JA[1]}]
+ #set_property IOSTANDARD LVCMOS33 [get_ports {JA[1]}]
+##Bank = 15, Pin name = IO_L16N_T2_A27_15, Sch name = JA3
+#set_property PACKAGE_PIN D17 [get_ports {JA[2]}]
+ #set_property IOSTANDARD LVCMOS33 [get_ports {JA[2]}]
+##Bank = 15, Pin name = IO_L16P_T2_A28_15, Sch name = JA4
+#set_property PACKAGE_PIN E17 [get_ports {JA[3]}]
+ #set_property IOSTANDARD LVCMOS33 [get_ports {JA[3]}]
+##Bank = 15, Pin name = IO_0_15, Sch name = JA7
+#set_property PACKAGE_PIN G13 [get_ports {JA[4]}]
+ #set_property IOSTANDARD LVCMOS33 [get_ports {JA[4]}]
+##Bank = 15, Pin name = IO_L20N_T3_A19_15, Sch name = JA8
+#set_property PACKAGE_PIN C17 [get_ports {JA[5]}]
+ #set_property IOSTANDARD LVCMOS33 [get_ports {JA[5]}]
+##Bank = 15, Pin name = IO_L21N_T3_A17_15, Sch name = JA9
+#set_property PACKAGE_PIN D18 [get_ports {JA[6]}]
+ #set_property IOSTANDARD LVCMOS33 [get_ports {JA[6]}]
+##Bank = 15, Pin name = IO_L21P_T3_DQS_15, Sch name = JA10
+#set_property PACKAGE_PIN E18 [get_ports {JA[7]}]
+ #set_property IOSTANDARD LVCMOS33 [get_ports {JA[7]}]
+
+
+
+##Pmod Header JB
+##Bank = 15, Pin name = IO_L15N_T2_DQS_ADV_B_15, Sch name = JB1
+#set_property PACKAGE_PIN G14 [get_ports {JB[0]}]
+ #set_property IOSTANDARD LVCMOS33 [get_ports {JB[0]}]
+##Bank = 14, Pin name = IO_L13P_T2_MRCC_14, Sch name = JB2
+#set_property PACKAGE_PIN P15 [get_ports {JB[1]}]
+ #set_property IOSTANDARD LVCMOS33 [get_ports {JB[1]}]
+##Bank = 14, Pin name = IO_L21N_T3_DQS_A06_D22_14, Sch name = JB3
+#set_property PACKAGE_PIN V11 [get_ports {JB[2]}]
+ #set_property IOSTANDARD LVCMOS33 [get_ports {JB[2]}]
+##Bank = CONFIG, Pin name = IO_L16P_T2_CSI_B_14, Sch name = JB4
+#set_property PACKAGE_PIN V15 [get_ports {JB[3]}]
+ #set_property IOSTANDARD LVCMOS33 [get_ports {JB[3]}]
+##Bank = 15, Pin name = IO_25_15, Sch name = JB7
+#set_property PACKAGE_PIN K16 [get_ports {JB[4]}]
+ #set_property IOSTANDARD LVCMOS33 [get_ports {JB[4]}]
+##Bank = CONFIG, Pin name = IO_L15P_T2_DQS_RWR_B_14, Sch name = JB8
+#set_property PACKAGE_PIN R16 [get_ports {JB[5]}]
+ #set_property IOSTANDARD LVCMOS33 [get_ports {JB[5]}]
+##Bank = 14, Pin name = IO_L24P_T3_A01_D17_14, Sch name = JB9
+#set_property PACKAGE_PIN T9 [get_ports {JB[6]}]
+ #set_property IOSTANDARD LVCMOS33 [get_ports {JB[6]}]
+##Bank = 14, Pin name = IO_L19N_T3_A09_D25_VREF_14, Sch name = JB10
+#set_property PACKAGE_PIN U11 [get_ports {JB[7]}]
+ #set_property IOSTANDARD LVCMOS33 [get_ports {JB[7]}]
+
+
+
+##Pmod Header JC
+##Bank = 35, Pin name = IO_L23P_T3_35, Sch name = JC1
+#set_property PACKAGE_PIN K2 [get_ports {JC[0]}]
+ #set_property IOSTANDARD LVCMOS33 [get_ports {JC[0]}]
+##Bank = 35, Pin name = IO_L6P_T0_35, Sch name = JC2
+#set_property PACKAGE_PIN E7 [get_ports {JC[1]}]
+ #set_property IOSTANDARD LVCMOS33 [get_ports {JC[1]}]
+##Bank = 35, Pin name = IO_L22P_T3_35, Sch name = JC3
+#set_property PACKAGE_PIN J3 [get_ports {JC[2]}]
+ #set_property IOSTANDARD LVCMOS33 [get_ports {JC[2]}]
+##Bank = 35, Pin name = IO_L21P_T3_DQS_35, Sch name = JC4
+#set_property PACKAGE_PIN J4 [get_ports {JC[3]}]
+ #set_property IOSTANDARD LVCMOS33 [get_ports {JC[3]}]
+##Bank = 35, Pin name = IO_L23N_T3_35, Sch name = JC7
+#set_property PACKAGE_PIN K1 [get_ports {JC[4]}]
+ #set_property IOSTANDARD LVCMOS33 [get_ports {JC[4]}]
+##Bank = 35, Pin name = IO_L5P_T0_AD13P_35, Sch name = JC8
+#set_property PACKAGE_PIN E6 [get_ports {JC[5]}]
+ #set_property IOSTANDARD LVCMOS33 [get_ports {JC[5]}]
+##Bank = 35, Pin name = IO_L22N_T3_35, Sch name = JC9
+#set_property PACKAGE_PIN J2 [get_ports {JC[6]}]
+ #set_property IOSTANDARD LVCMOS33 [get_ports {JC[6]}]
+##Bank = 35, Pin name = IO_L19P_T3_35, Sch name = JC10
+#set_property PACKAGE_PIN G6 [get_ports {JC[7]}]
+ #set_property IOSTANDARD LVCMOS33 [get_ports {JC[7]}]
+
+
+
+##Pmod Header JD
+##Bank = 35, Pin name = IO_L21N_T2_DQS_35, Sch name = JD1
+#set_property PACKAGE_PIN H4 [get_ports {JD[0]}]
+ #set_property IOSTANDARD LVCMOS33 [get_ports {JD[0]}]
+##Bank = 35, Pin name = IO_L17P_T2_35, Sch name = JD2
+#set_property PACKAGE_PIN H1 [get_ports {JD[1]}]
+ #set_property IOSTANDARD LVCMOS33 [get_ports {JD[1]}]
+##Bank = 35, Pin name = IO_L17N_T2_35, Sch name = JD3
+#set_property PACKAGE_PIN G1 [get_ports {JD[2]}]
+ #set_property IOSTANDARD LVCMOS33 [get_ports {JD[2]}]
+##Bank = 35, Pin name = IO_L20N_T3_35, Sch name = JD4
+#set_property PACKAGE_PIN G3 [get_ports {JD[3]}]
+ #set_property IOSTANDARD LVCMOS33 [get_ports {JD[3]}]
+##Bank = 35, Pin name = IO_L15P_T2_DQS_35, Sch name = JD7
+#set_property PACKAGE_PIN H2 [get_ports {JD[4]}]
+ #set_property IOSTANDARD LVCMOS33 [get_ports {JD[4]}]
+##Bank = 35, Pin name = IO_L20P_T3_35, Sch name = JD8
+#set_property PACKAGE_PIN G4 [get_ports {JD[5]}]
+ #set_property IOSTANDARD LVCMOS33 [get_ports {JD[5]}]
+##Bank = 35, Pin name = IO_L15N_T2_DQS_35, Sch name = JD9
+#set_property PACKAGE_PIN G2 [get_ports {JD[6]}]
+ #set_property IOSTANDARD LVCMOS33 [get_ports {JD[6]}]
+##Bank = 35, Pin name = IO_L13N_T2_MRCC_35, Sch name = JD10
+#set_property PACKAGE_PIN F3 [get_ports {JD[7]}]
+ #set_property IOSTANDARD LVCMOS33 [get_ports {JD[7]}]
+
+
+
+##Pmod Header JXADC
+##Bank = 15, Pin name = IO_L9P_T1_DQS_AD3P_15, Sch name = XADC1_P -> XA1_P
+#set_property PACKAGE_PIN A13 [get_ports {JXADC[0]}]
+ #set_property IOSTANDARD LVCMOS33 [get_ports {JXADC[0]}]
+##Bank = 15, Pin name = IO_L8P_T1_AD10P_15, Sch name = XADC2_P -> XA2_P
+#set_property PACKAGE_PIN A15 [get_ports {JXADC[1]}]
+ #set_property IOSTANDARD LVCMOS33 [get_ports {JXADC[1]}]
+##Bank = 15, Pin name = IO_L7P_T1_AD2P_15, Sch name = XADC3_P -> XA3_P
+#set_property PACKAGE_PIN B16 [get_ports {JXADC[2]}]
+ #set_property IOSTANDARD LVCMOS33 [get_ports {JXADC[2]}]
+##Bank = 15, Pin name = IO_L10P_T1_AD11P_15, Sch name = XADC4_P -> XA4_P
+#set_property PACKAGE_PIN B18 [get_ports {JXADC[3]}]
+ #set_property IOSTANDARD LVCMOS33 [get_ports {JXADC[3]}]
+##Bank = 15, Pin name = IO_L9N_T1_DQS_AD3N_15, Sch name = XADC1_N -> XA1_N
+#set_property PACKAGE_PIN A14 [get_ports {JXADC[4]}]
+ #set_property IOSTANDARD LVCMOS33 [get_ports {JXADC[4]}]
+##Bank = 15, Pin name = IO_L8N_T1_AD10N_15, Sch name = XADC2_N -> XA2_N
+#set_property PACKAGE_PIN A16 [get_ports {JXADC[5]}]
+ #set_property IOSTANDARD LVCMOS33 [get_ports {JXADC[5]}]
+##Bank = 15, Pin name = IO_L7N_T1_AD2N_15, Sch name = XADC3_N -> XA3_N
+#set_property PACKAGE_PIN B17 [get_ports {JXADC[6]}]
+ #set_property IOSTANDARD LVCMOS33 [get_ports {JXADC[6]}]
+##Bank = 15, Pin name = IO_L10N_T1_AD11N_15, Sch name = XADC4_N -> XA4_N
+#set_property PACKAGE_PIN A18 [get_ports {JXADC[7]}]
+ #set_property IOSTANDARD LVCMOS33 [get_ports {JXADC[7]}]
+
+
+
+##VGA Connector
+#Bank = 35, Pin name = IO_L8N_T1_AD14N_35, Sch name = VGA_R0
+set_property PACKAGE_PIN A3 [get_ports {vgaRed[0]}]
+ set_property IOSTANDARD LVCMOS33 [get_ports {vgaRed[0]}]
+#Bank = 35, Pin name = IO_L7N_T1_AD6N_35, Sch name = VGA_R1
+set_property PACKAGE_PIN B4 [get_ports {vgaRed[1]}]
+ set_property IOSTANDARD LVCMOS33 [get_ports {vgaRed[1]}]
+#Bank = 35, Pin name = IO_L1N_T0_AD4N_35, Sch name = VGA_R2
+set_property PACKAGE_PIN C5 [get_ports {vgaRed[2]}]
+ set_property IOSTANDARD LVCMOS33 [get_ports {vgaRed[2]}]
+#Bank = 35, Pin name = IO_L8P_T1_AD14P_35, Sch name = VGA_R3
+set_property PACKAGE_PIN A4 [get_ports {vgaRed[3]}]
+ set_property IOSTANDARD LVCMOS33 [get_ports {vgaRed[3]}]
+#Bank = 35, Pin name = IO_L2P_T0_AD12P_35, Sch name = VGA_B0
+set_property PACKAGE_PIN B7 [get_ports {vgaBlue[0]}]
+ set_property IOSTANDARD LVCMOS33 [get_ports {vgaBlue[0]}]
+#Bank = 35, Pin name = IO_L4N_T0_35, Sch name = VGA_B1
+set_property PACKAGE_PIN C7 [get_ports {vgaBlue[1]}]
+ set_property IOSTANDARD LVCMOS33 [get_ports {vgaBlue[1]}]
+#Bank = 35, Pin name = IO_L6N_T0_VREF_35, Sch name = VGA_B2
+set_property PACKAGE_PIN D7 [get_ports {vgaBlue[2]}]
+ set_property IOSTANDARD LVCMOS33 [get_ports {vgaBlue[2]}]
+#Bank = 35, Pin name = IO_L4P_T0_35, Sch name = VGA_B3
+set_property PACKAGE_PIN D8 [get_ports {vgaBlue[3]}]
+ set_property IOSTANDARD LVCMOS33 [get_ports {vgaBlue[3]}]
+#Bank = 35, Pin name = IO_L1P_T0_AD4P_35, Sch name = VGA_G0
+set_property PACKAGE_PIN C6 [get_ports {vgaGreen[0]}]
+ set_property IOSTANDARD LVCMOS33 [get_ports {vgaGreen[0]}]
+#Bank = 35, Pin name = IO_L3N_T0_DQS_AD5N_35, Sch name = VGA_G1
+set_property PACKAGE_PIN A5 [get_ports {vgaGreen[1]}]
+ set_property IOSTANDARD LVCMOS33 [get_ports {vgaGreen[1]}]
+#Bank = 35, Pin name = IO_L2N_T0_AD12N_35, Sch name = VGA_G2
+set_property PACKAGE_PIN B6 [get_ports {vgaGreen[2]}]
+ set_property IOSTANDARD LVCMOS33 [get_ports {vgaGreen[2]}]
+#Bank = 35, Pin name = IO_L3P_T0_DQS_AD5P_35, Sch name = VGA_G3
+set_property PACKAGE_PIN A6 [get_ports {vgaGreen[3]}]
+ set_property IOSTANDARD LVCMOS33 [get_ports {vgaGreen[3]}]
+#Bank = 15, Pin name = IO_L4P_T0_15, Sch name = VGA_HS
+set_property PACKAGE_PIN B11 [get_ports Hsync]
+ set_property IOSTANDARD LVCMOS33 [get_ports Hsync]
+#Bank = 15, Pin name = IO_L3N_T0_DQS_AD1N_15, Sch name = VGA_VS
+set_property PACKAGE_PIN B12 [get_ports Vsync]
+ set_property IOSTANDARD LVCMOS33 [get_ports Vsync]
+
+
+
+##Micro SD Connector
+##Bank = 35, Pin name = IO_L14P_T2_SRCC_35, Sch name = SD_RESET
+#set_property PACKAGE_PIN E2 [get_ports sdReset]
+ #set_property IOSTANDARD LVCMOS33 [get_ports sdReset]
+##Bank = 35, Pin name = IO_L9N_T1_DQS_AD7N_35, Sch name = SD_CD
+#set_property PACKAGE_PIN A1 [get_ports sdCD]
+ #set_property IOSTANDARD LVCMOS33 [get_ports sdCD]
+##Bank = 35, Pin name = IO_L9P_T1_DQS_AD7P_35, Sch name = SD_SCK
+#set_property PACKAGE_PIN B1 [get_ports sdSCK]
+ #set_property IOSTANDARD LVCMOS33 [get_ports sdSCK]
+##Bank = 35, Pin name = IO_L16N_T2_35, Sch name = SD_CMD
+#set_property PACKAGE_PIN C1 [get_ports sdCmd]
+ #set_property IOSTANDARD LVCMOS33 [get_ports sdCmd]
+##Bank = 35, Pin name = IO_L16P_T2_35, Sch name = SD_DAT0
+#set_property PACKAGE_PIN C2 [get_ports {sdData[0]}]
+ #set_property IOSTANDARD LVCMOS33 [get_ports {sdData[0]}]
+##Bank = 35, Pin name = IO_L18N_T2_35, Sch name = SD_DAT1
+#set_property PACKAGE_PIN E1 [get_ports {sdData[1]}]
+ #set_property IOSTANDARD LVCMOS33 [get_ports {sdData[1]}]
+##Bank = 35, Pin name = IO_L18P_T2_35, Sch name = SD_DAT2
+#set_property PACKAGE_PIN F1 [get_ports {sdData[2]}]
+ #set_property IOSTANDARD LVCMOS33 [get_ports {sdData[2]}]
+##Bank = 35, Pin name = IO_L14N_T2_SRCC_35, Sch name = SD_DAT3
+#set_property PACKAGE_PIN D2 [get_ports {sdData[3]}]
+ #set_property IOSTANDARD LVCMOS33 [get_ports {sdData[3]}]
+
+
+
+##Accelerometer
+##Bank = 15, Pin name = IO_L6N_T0_VREF_15, Sch name = ACL_MISO
+#set_property PACKAGE_PIN D13 [get_ports aclMISO]
+ #set_property IOSTANDARD LVCMOS33 [get_ports aclMISO]
+##Bank = 15, Pin name = IO_L2N_T0_AD8N_15, Sch name = ACL_MOSI
+#set_property PACKAGE_PIN B14 [get_ports aclMOSI]
+ #set_property IOSTANDARD LVCMOS33 [get_ports aclMOSI]
+##Bank = 15, Pin name = IO_L12P_T1_MRCC_15, Sch name = ACL_SCLK
+#set_property PACKAGE_PIN D15 [get_ports aclSCK]
+ #set_property IOSTANDARD LVCMOS33 [get_ports aclSCK]
+##Bank = 15, Pin name = IO_L12N_T1_MRCC_15, Sch name = ACL_CSN
+#set_property PACKAGE_PIN C15 [get_ports aclSS]
+ #set_property IOSTANDARD LVCMOS33 [get_ports aclSS]
+##Bank = 15, Pin name = IO_L20P_T3_A20_15, Sch name = ACL_INT1
+#set_property PACKAGE_PIN C16 [get_ports aclInt1]
+ #set_property IOSTANDARD LVCMOS33 [get_ports aclInt1]
+##Bank = 15, Pin name = IO_L11P_T1_SRCC_15, Sch name = ACL_INT2
+#set_property PACKAGE_PIN E15 [get_ports aclInt2]
+ #set_property IOSTANDARD LVCMOS33 [get_ports aclInt2]
+
+
+
+##Temperature Sensor
+##Bank = 15, Pin name = IO_L14N_T2_SRCC_15, Sch name = TMP_SCL
+#set_property PACKAGE_PIN F16 [get_ports tmpSCL]
+ #set_property IOSTANDARD LVCMOS33 [get_ports tmpSCL]
+##Bank = 15, Pin name = IO_L13N_T2_MRCC_15, Sch name = TMP_SDA
+#set_property PACKAGE_PIN G16 [get_ports tmpSDA]
+ #set_property IOSTANDARD LVCMOS33 [get_ports tmpSDA]
+##Bank = 15, Pin name = IO_L1P_T0_AD0P_15, Sch name = TMP_INT
+#set_property PACKAGE_PIN D14 [get_ports tmpInt]
+ #set_property IOSTANDARD LVCMOS33 [get_ports tmpInt]
+##Bank = 15, Pin name = IO_L1N_T0_AD0N_15, Sch name = TMP_CT
+#set_property PACKAGE_PIN C14 [get_ports tmpCT]
+ #set_property IOSTANDARD LVCMOS33 [get_ports tmpCT]
+
+
+
+##Omnidirectional Microphone
+##Bank = 35, Pin name = IO_25_35, Sch name = M_CLK
+#set_property PACKAGE_PIN J5 [get_ports micClk]
+ #set_property IOSTANDARD LVCMOS33 [get_ports micClk]
+##Bank = 35, Pin name = IO_L24N_T3_35, Sch name = M_DATA
+#set_property PACKAGE_PIN H5 [get_ports micData]
+ #set_property IOSTANDARD LVCMOS33 [get_ports micData]
+##Bank = 35, Pin name = IO_0_35, Sch name = M_LRSEL
+#set_property PACKAGE_PIN F5 [get_ports micLRSel]
+ #set_property IOSTANDARD LVCMOS33 [get_ports micLRSel]
+
+
+
+##PWM Audio Amplifier
+##Bank = 15, Pin name = IO_L4N_T0_15, Sch name = AUD_PWM
+#set_property PACKAGE_PIN A11 [get_ports ampPWM]
+ #set_property IOSTANDARD LVCMOS33 [get_ports ampPWM]
+##Bank = 15, Pin name = IO_L6P_T0_15, Sch name = AUD_SD
+#set_property PACKAGE_PIN D12 [get_ports ampSD]
+ #set_property IOSTANDARD LVCMOS33 [get_ports ampSD]
+
+
+##USB-RS232 Interface
+##Bank = 35, Pin name = IO_L7P_T1_AD6P_35, Sch name = UART_TXD_IN
+#set_property PACKAGE_PIN C4 [get_ports RsRx]
+ #set_property IOSTANDARD LVCMOS33 [get_ports RsRx]
+##Bank = 35, Pin name = IO_L11N_T1_SRCC_35, Sch name = UART_RXD_OUT
+#set_property PACKAGE_PIN D4 [get_ports RsTx]
+ #set_property IOSTANDARD LVCMOS33 [get_ports RsTx]
+##Bank = 35, Pin name = IO_L12N_T1_MRCC_35, Sch name = UART_CTS
+#set_property PACKAGE_PIN D3 [get_ports RsCts]
+ #set_property IOSTANDARD LVCMOS33 [get_ports RsCts]
+##Bank = 35, Pin name = IO_L5N_T0_AD13N_35, Sch name = UART_RTS
+#set_property PACKAGE_PIN E5 [get_ports RsRts]
+ #set_property IOSTANDARD LVCMOS33 [get_ports RsRts]
+
+
+
+##USB HID (PS/2)
+##Bank = 35, Pin name = IO_L13P_T2_MRCC_35, Sch name = PS2_CLK
+#set_property PACKAGE_PIN F4 [get_ports PS2Clk]
+ #set_property IOSTANDARD LVCMOS33 [get_ports PS2Clk]
+ #set_property PULLUP true [get_ports PS2Clk]
+##Bank = 35, Pin name = IO_L10N_T1_AD15N_35, Sch name = PS2_DATA
+#set_property PACKAGE_PIN B2 [get_ports PS2Data]
+ #set_property IOSTANDARD LVCMOS33 [get_ports PS2Data]
+ #set_property PULLUP true [get_ports PS2Data]
+
+
+
+##SMSC Ethernet PHY
+##Bank = 16, Pin name = IO_L11P_T1_SRCC_16, Sch name = ETH_MDC
+#set_property PACKAGE_PIN C9 [get_ports PhyMdc]
+ #set_property IOSTANDARD LVCMOS33 [get_ports PhyMdc]
+##Bank = 16, Pin name = IO_L14N_T2_SRCC_16, Sch name = ETH_MDIO
+#set_property PACKAGE_PIN A9 [get_ports PhyMdio]
+ #set_property IOSTANDARD LVCMOS33 [get_ports PhyMdio]
+##Bank = 35, Pin name = IO_L10P_T1_AD15P_35, Sch name = ETH_RSTN
+#set_property PACKAGE_PIN B3 [get_ports PhyRstn]
+ #set_property IOSTANDARD LVCMOS33 [get_ports PhyRstn]
+##Bank = 16, Pin name = IO_L6N_T0_VREF_16, Sch name = ETH_CRSDV
+#set_property PACKAGE_PIN D9 [get_ports PhyCrs]
+ #set_property IOSTANDARD LVCMOS33 [get_ports PhyCrs]
+##Bank = 16, Pin name = IO_L13N_T2_MRCC_16, Sch name = ETH_RXERR
+#set_property PACKAGE_PIN C10 [get_ports PhyRxErr]
+ #set_property IOSTANDARD LVCMOS33 [get_ports PhyRxErr]
+##Bank = 16, Pin name = IO_L19N_T3_VREF_16, Sch name = ETH_RXD0
+#set_property PACKAGE_PIN D10 [get_ports {PhyRxd[0]}]
+ #set_property IOSTANDARD LVCMOS33 [get_ports {PhyRxd[0]}]
+##Bank = 16, Pin name = IO_L13P_T2_MRCC_16, Sch name = ETH_RXD1
+#set_property PACKAGE_PIN C11 [get_ports {PhyRxd[1]}]
+ #set_property IOSTANDARD LVCMOS33 [get_ports {PhyRxd[1]}]
+##Bank = 16, Pin name = IO_L11N_T1_SRCC_16, Sch name = ETH_TXEN
+#set_property PACKAGE_PIN B9 [get_ports PhyTxEn]
+ #set_property IOSTANDARD LVCMOS33 [get_ports PhyTxEn]
+##Bank = 16, Pin name = IO_L14P_T2_SRCC_16, Sch name = ETH_TXD0
+#set_property PACKAGE_PIN A10 [get_ports {PhyTxd[0]}]
+ #set_property IOSTANDARD LVCMOS33 [get_ports {PhyTxd[0]}]
+##Bank = 16, Pin name = IO_L12N_T1_MRCC_16, Sch name = ETH_TXD1
+#set_property PACKAGE_PIN A8 [get_ports {PhyTxd[1]}]
+ #set_property IOSTANDARD LVCMOS33 [get_ports {PhyTxd[1]}]
+##Bank = 35, Pin name = IO_L11P_T1_SRCC_35, Sch name = ETH_REFCLK
+#set_property PACKAGE_PIN D5 [get_ports PhyClk50Mhz]
+ #set_property IOSTANDARD LVCMOS33 [get_ports PhyClk50Mhz]
+##Bank = 16, Pin name = IO_L12P_T1_MRCC_16, Sch name = ETH_INTN
+#set_property PACKAGE_PIN B8 [get_ports PhyIntn]
+ #set_property IOSTANDARD LVCMOS33 [get_ports PhyIntn]
+
+
+
+##Quad SPI Flash
+##Bank = CONFIG, Pin name = CCLK_0, Sch name = QSPI_SCK
+#set_property PACKAGE_PIN E9 [get_ports {QspiSCK}]
+ #set_property IOSTANDARD LVCMOS33 [get_ports {QspiSCK}]
+##Bank = CONFIG, Pin name = IO_L1P_T0_D00_MOSI_14, Sch name = QSPI_DQ0
+#set_property PACKAGE_PIN K17 [get_ports {QspiDB[0]}]
+ #set_property IOSTANDARD LVCMOS33 [get_ports {QspiDB[0]}]
+##Bank = CONFIG, Pin name = IO_L1N_T0_D01_DIN_14, Sch name = QSPI_DQ1
+#set_property PACKAGE_PIN K18 [get_ports {QspiDB[1]}]
+ #set_property IOSTANDARD LVCMOS33 [get_ports {QspiDB[1]}]
+##Bank = CONFIG, Pin name = IO_L20_T0_D02_14, Sch name = QSPI_DQ2
+#set_property PACKAGE_PIN L14 [get_ports {QspiDB[2]}]
+ #set_property IOSTANDARD LVCMOS33 [get_ports {QspiDB[2]}]
+##Bank = CONFIG, Pin name = IO_L2P_T0_D03_14, Sch name = QSPI_DQ3
+#set_property PACKAGE_PIN M14 [get_ports {QspiDB[3]}]
+ #set_property IOSTANDARD LVCMOS33 [get_ports {QspiDB[3]}]
+##Bank = CONFIG, Pin name = IO_L15N_T2_DQS_DOUT_CSO_B_14, Sch name = QSPI_CSN
+#set_property PACKAGE_PIN L13 [get_ports QspiCSn]
+ #set_property IOSTANDARD LVCMOS33 [get_ports QspiCSn]
+
+
+
+##Cellular RAM
+##Bank = 14, Pin name = IO_L14N_T2_SRCC_14, Sch name = CRAM_CLK
+#set_property PACKAGE_PIN T15 [get_ports RamCLK]
+ #set_property IOSTANDARD LVCMOS33 [get_ports RamCLK]
+##Bank = 14, Pin name = IO_L23P_T3_A03_D19_14, Sch name = CRAM_ADVN
+#set_property PACKAGE_PIN T13 [get_ports RamADVn]
+ #set_property IOSTANDARD LVCMOS33 [get_ports RamADVn]
+##Bank = 14, Pin name = IO_L4P_T0_D04_14, Sch name = CRAM_CEN
+#set_property PACKAGE_PIN L18 [get_ports RamCEn]
+ #set_property IOSTANDARD LVCMOS33 [get_ports RamCEn]
+##Bank = 15, Pin name = IO_L19P_T3_A22_15, Sch name = CRAM_CRE
+#set_property PACKAGE_PIN J14 [get_ports RamCRE]
+ #set_property IOSTANDARD LVCMOS33 [get_ports RamCRE]
+##Bank = 15, Pin name = IO_L15P_T2_DQS_15, Sch name = CRAM_OEN
+#set_property PACKAGE_PIN H14 [get_ports RamOEn]
+ #set_property IOSTANDARD LVCMOS33 [get_ports RamOEn]
+##Bank = 14, Pin name = IO_0_14, Sch name = CRAM_WEN
+#set_property PACKAGE_PIN R11 [get_ports RamWEn]
+ #set_property IOSTANDARD LVCMOS33 [get_ports RamWEn]
+##Bank = 15, Pin name = IO_L24N_T3_RS0_15, Sch name = CRAM_LBN
+#set_property PACKAGE_PIN J15 [get_ports RamLBn]
+ #set_property IOSTANDARD LVCMOS33 [get_ports RamLBn]
+##Bank = 15, Pin name = IO_L17N_T2_A25_15, Sch name = CRAM_UBN
+#set_property PACKAGE_PIN J13 [get_ports RamUBn]
+ #set_property IOSTANDARD LVCMOS33 [get_ports RamUBn]
+##Bank = 14, Pin name = IO_L14P_T2_SRCC_14, Sch name = CRAM_WAIT
+#set_property PACKAGE_PIN T14 [get_ports RamWait]
+ #set_property IOSTANDARD LVCMOS33 [get_ports RamWait]
+
+##Bank = 14, Pin name = IO_L5P_T0_DQ06_14, Sch name = CRAM_DQ0
+#set_property PACKAGE_PIN R12 [get_ports {MemDB[0]}]
+ #set_property IOSTANDARD LVCMOS33 [get_ports {MemDB[0]}]
+##Bank = 14, Pin name = IO_L19P_T3_A10_D26_14, Sch name = CRAM_DQ1
+#set_property PACKAGE_PIN T11 [get_ports {MemDB[1]}]
+ #set_property IOSTANDARD LVCMOS33 [get_ports {MemDB[1]}]
+##Bank = 14, Pin name = IO_L20P_T3_A08)D24_14, Sch name = CRAM_DQ2
+#set_property PACKAGE_PIN U12 [get_ports {MemDB[2]}]
+ #set_property IOSTANDARD LVCMOS33 [get_ports {MemDB[2]}]
+##Bank = 14, Pin name = IO_L5N_T0_D07_14, Sch name = CRAM_DQ3
+#set_property PACKAGE_PIN R13 [get_ports {MemDB[3]}]
+ #set_property IOSTANDARD LVCMOS33 [get_ports {MemDB[3]}]
+##Bank = 14, Pin name = IO_L17N_T2_A13_D29_14, Sch name = CRAM_DQ4
+#set_property PACKAGE_PIN U18 [get_ports {MemDB[4]}]
+ #set_property IOSTANDARD LVCMOS33 [get_ports {MemDB[4]}]
+##Bank = 14, Pin name = IO_L12N_T1_MRCC_14, Sch name = CRAM_DQ5
+#set_property PACKAGE_PIN R17 [get_ports {MemDB[5]}]
+ #set_property IOSTANDARD LVCMOS33 [get_ports {MemDB[5]}]
+##Bank = 14, Pin name = IO_L7N_T1_D10_14, Sch name = CRAM_DQ6
+#set_property PACKAGE_PIN T18 [get_ports {MemDB[6]}]
+ #set_property IOSTANDARD LVCMOS33 [get_ports {MemDB[6]}]
+##Bank = 14, Pin name = IO_L7P_T1_D09_14, Sch name = CRAM_DQ7
+#set_property PACKAGE_PIN R18 [get_ports {MemDB[7]}]
+ #set_property IOSTANDARD LVCMOS33 [get_ports {MemDB[7]}]
+##Bank = 15, Pin name = IO_L22N_T3_A16_15, Sch name = CRAM_DQ8
+#set_property PACKAGE_PIN F18 [get_ports {MemDB[8]}]
+ #set_property IOSTANDARD LVCMOS33 [get_ports {MemDB[8]}]
+##Bank = 15, Pin name = IO_L22P_T3_A17_15, Sch name = CRAM_DQ9
+#set_property PACKAGE_PIN G18 [get_ports {MemDB[9]}]
+ #set_property IOSTANDARD LVCMOS33 [get_ports {MemDB[9]}]
+##Bank = 15, Pin name = IO_IO_L18N_T2_A23_15, Sch name = CRAM_DQ10
+#set_property PACKAGE_PIN G17 [get_ports {MemDB[10]}]
+ #set_property IOSTANDARD LVCMOS33 [get_ports {MemDB[10]}]
+##Bank = 14, Pin name = IO_L4N_T0_D05_14, Sch name = CRAM_DQ11
+#set_property PACKAGE_PIN M18 [get_ports {MemDB[11]}]
+ #set_property IOSTANDARD LVCMOS33 [get_ports {MemDB[11]}]
+##Bank = 14, Pin name = IO_L10N_T1_D15_14, Sch name = CRAM_DQ12
+#set_property PACKAGE_PIN M17 [get_ports {MemDB[12]}]
+ #set_property IOSTANDARD LVCMOS33 [get_ports {MemDB[12]}]
+##Bank = 14, Pin name = IO_L9N_T1_DQS_D13_14, Sch name = CRAM_DQ13
+#set_property PACKAGE_PIN P18 [get_ports {MemDB[13]}]
+ #set_property IOSTANDARD LVCMOS33 [get_ports {MemDB[13]}]
+##Bank = 14, Pin name = IO_L9P_T1_DQS_14, Sch name = CRAM_DQ14
+#set_property PACKAGE_PIN N17 [get_ports {MemDB[14]}]
+ #set_property IOSTANDARD LVCMOS33 [get_ports {MemDB[14]}]
+##Bank = 14, Pin name = IO_L12P_T1_MRCC_14, Sch name = CRAM_DQ15
+#set_property PACKAGE_PIN P17 [get_ports {MemDB[15]}]
+ #set_property IOSTANDARD LVCMOS33 [get_ports {MemDB[15]}]
+
+##Bank = 15, Pin name = IO_L23N_T3_FWE_B_15, Sch name = CRAM_A0
+#set_property PACKAGE_PIN J18 [get_ports {MemAdr[0]}]
+ #set_property IOSTANDARD LVCMOS33 [get_ports {MemAdr[0]}]
+##Bank = 15, Pin name = IO_L18P_T2_A24_15, Sch name = CRAM_A1
+#set_property PACKAGE_PIN H17 [get_ports {MemAdr[1]}]
+ #set_property IOSTANDARD LVCMOS33 [get_ports {MemAdr[1]}]
+##Bank = 15, Pin name = IO_L19N_T3_A21_VREF_15, Sch name = CRAM_A2
+#set_property PACKAGE_PIN H15 [get_ports {MemAdr[2]}]
+ #set_property IOSTANDARD LVCMOS33 [get_ports {MemAdr[2]}]
+##Bank = 15, Pin name = IO_L23P_T3_FOE_B_15, Sch name = CRAM_A3
+#set_property PACKAGE_PIN J17 [get_ports {MemAdr[3]}]
+ #set_property IOSTANDARD LVCMOS33 [get_ports {MemAdr[3]}]
+##Bank = 15, Pin name = IO_L13P_T2_MRCC_15, Sch name = CRAM_A4
+#set_property PACKAGE_PIN H16 [get_ports {MemAdr[4]}]
+ #set_property IOSTANDARD LVCMOS33 [get_ports {MemAdr[4]}]
+##Bank = 15, Pin name = IO_L24P_T3_RS1_15, Sch name = CRAM_A5
+#set_property PACKAGE_PIN K15 [get_ports {MemAdr[5]}]
+ #set_property IOSTANDARD LVCMOS33 [get_ports {MemAdr[5]}]
+##Bank = 15, Pin name = IO_L17P_T2_A26_15, Sch name = CRAM_A6
+#set_property PACKAGE_PIN K13 [get_ports {MemAdr[6]}]
+ #set_property IOSTANDARD LVCMOS33 [get_ports {MemAdr[6]}]
+##Bank = 14, Pin name = IO_L11P_T1_SRCC_14, Sch name = CRAM_A7
+#set_property PACKAGE_PIN N15 [get_ports {MemAdr[7]}]
+ #set_property IOSTANDARD LVCMOS33 [get_ports {MemAdr[7]}]
+##Bank = 14, Pin name = IO_L16N_T2_SRCC-14, Sch name = CRAM_A8
+#set_property PACKAGE_PIN V16 [get_ports {MemAdr[8]}]
+ #set_property IOSTANDARD LVCMOS33 [get_ports {MemAdr[8]}]
+##Bank = 14, Pin name = IO_L22P_T3_A05_D21_14, Sch name = CRAM_A9
+#set_property PACKAGE_PIN U14 [get_ports {MemAdr[9]}]
+ #set_property IOSTANDARD LVCMOS33 [get_ports {MemAdr[9]}]
+##Bank = 14, Pin name = IO_L22N_T3_A04_D20_14, Sch name = CRAM_A10
+#set_property PACKAGE_PIN V14 [get_ports {MemAdr[10]}]
+ #set_property IOSTANDARD LVCMOS33 [get_ports {MemAdr[10]}]
+##Bank = 14, Pin name = IO_L20N_T3_A07_D23_14, Sch name = CRAM_A11
+#set_property PACKAGE_PIN V12 [get_ports {MemAdr[11]}]
+ #set_property IOSTANDARD LVCMOS33 [get_ports {MemAdr[11]}]
+##Bank = 14, Pin name = IO_L8N_T1_D12_14, Sch name = CRAM_A12
+#set_property PACKAGE_PIN P14 [get_ports {MemAdr[12]}]
+ #set_property IOSTANDARD LVCMOS33 [get_ports {MemAdr[12]}]
+##Bank = 14, Pin name = IO_L18P_T2_A12_D28_14, Sch name = CRAM_A13
+#set_property PACKAGE_PIN U16 [get_ports {MemAdr[13]}]
+ #set_property IOSTANDARD LVCMOS33 [get_ports {MemAdr[13]}]
+##Bank = 14, Pin name = IO_L13N_T2_MRCC_14, Sch name = CRAM_A14
+#set_property PACKAGE_PIN R15 [get_ports {MemAdr[14]}]
+ #set_property IOSTANDARD LVCMOS33 [get_ports {MemAdr[14]}]
+##Bank = 14, Pin name = IO_L8P_T1_D11_14, Sch name = CRAM_A15
+#set_property PACKAGE_PIN N14 [get_ports {MemAdr[15]}]
+ #set_property IOSTANDARD LVCMOS33 [get_ports {MemAdr[15]}]
+##Bank = 14, Pin name = IO_L11N_T1_SRCC_14, Sch name = CRAM_A16
+#set_property PACKAGE_PIN N16 [get_ports {MemAdr[16]}]
+ #set_property IOSTANDARD LVCMOS33 [get_ports {MemAdr[16]}]
+##Bank = 14, Pin name = IO_L6N_T0_D08_VREF_14, Sch name = CRAM_A17
+#set_property PACKAGE_PIN M13 [get_ports {MemAdr[17]}]
+ #set_property IOSTANDARD LVCMOS33 [get_ports {MemAdr[17]}]
+##Bank = 14, Pin name = IO_L18N_T2_A11_D27_14, Sch name = CRAM_A18
+#set_property PACKAGE_PIN V17 [get_ports {MemAdr[18]}]
+ #set_property IOSTANDARD LVCMOS33 [get_ports {MemAdr[18]}]
+##Bank = 14, Pin name = IO_L17P_T2_A14_D30_14, Sch name = CRAM_A19
+#set_property PACKAGE_PIN U17 [get_ports {MemAdr[19]}]
+ #set_property IOSTANDARD LVCMOS33 [get_ports {MemAdr[19]}]
+##Bank = 14, Pin name = IO_L24N_T3_A00_D16_14, Sch name = CRAM_A20
+#set_property PACKAGE_PIN T10 [get_ports {MemAdr[20]}]
+ #set_property IOSTANDARD LVCMOS33 [get_ports {MemAdr[20]}]
+##Bank = 14, Pin name = IO_L10P_T1_D14_14, Sch name = CRAM_A21
+#set_property PACKAGE_PIN M16 [get_ports {MemAdr[21]}]
+ #set_property IOSTANDARD LVCMOS33 [get_ports {MemAdr[21]}]
+##Bank = 14, Pin name = IO_L23N_T3_A02_D18_14, Sch name = CRAM_A22
+#set_property PACKAGE_PIN U13 [get_ports {MemAdr[22]}]
+ #set_property IOSTANDARD LVCMOS33 [get_ports {MemAdr[22]}]
+
diff --git a/game.srcs/sim_1/new/TopModule_tb.vhd b/game.srcs/sim_1/new/TopModule_tb.vhd
new file mode 100644
index 0000000000000000000000000000000000000000..2f95d9b3e5f218a9ac52df788568a96883b280ff
--- /dev/null
+++ b/game.srcs/sim_1/new/TopModule_tb.vhd
@@ -0,0 +1,91 @@
+----------------------------------------------------------------------------------
+-- Company:
+-- Engineer:
+--
+-- Create Date: 02/27/2023 11:10:14 AM
+-- Design Name:
+-- Module Name: TopModule_tb - Behavioral
+-- Project Name:
+-- Target Devices:
+-- Tool Versions:
+-- Description:
+--
+-- Dependencies:
+--
+-- Revision:
+-- Revision 0.01 - File Created
+-- Additional Comments:
+--
+----------------------------------------------------------------------------------
+
+
+library IEEE;
+use IEEE.STD_LOGIC_1164.ALL;
+
+-- Uncomment the following library declaration if using
+-- arithmetic functions with Signed or Unsigned values
+--use IEEE.NUMERIC_STD.ALL;
+
+-- Uncomment the following library declaration if instantiating
+-- any Xilinx leaf cells in this code.
+--library UNISIM;
+--use UNISIM.VComponents.all;
+
+entity TopModule_tb is
+-- Port ( );
+end TopModule_tb;
+
+architecture Test of TopModule_tb is
+
+component TopModule
+ port( clk, btnCpuReset : in std_logic;
+ btnU: in std_logic;
+ vgaRed : out std_logic_vector(3 downto 0);
+ vgaBlue : out std_logic_vector(3 downto 0);
+ vgaGreen : out std_logic_vector(3 downto 0);
+ Hsync, Vsync : out std_logic
+ );
+end component;
+
+signal btnCpuReset_i, Hsync_i, Vsync_i, btnU_i : std_logic;
+signal clk_i : std_logic := '0';
+signal vgaRed_i : std_logic_vector(3 downto 0);
+signal vgaBlue_i : std_logic_vector(3 downto 0);
+signal vgaGreen_i : std_logic_vector(3 downto 0);
+constant period: time:= 10ns;
+
+begin
+
+DUT: TopModule port map(
+ clk => clk_i,
+ btnCpuReset => btnCpuReset_i,
+ btnU => btnU_i,
+ Hsync => Hsync_i,
+ Vsync => Vsync_i,
+ vgaRed => vgaRed_i,
+ vgaBlue => vgaBlue_i,
+ vgaGreen => vgaGreen_i
+ );
+
+ clk_i <= not clk_i after period/2;
+
+Stimulus : process
+
+ begin
+
+ btnCpuReset_i <= '1';
+ btnU_i <= '0';
+ wait for 10* period;
+ btnCpuReset_i <= '0';
+ wait for 10* period;
+ btnCpuReset_i <= '1';
+ wait for 100* period;
+ btnU_i <= '1';
+ wait for 100* period;
+ btnU_i <= '0';
+ wait;
+
+end process Stimulus;
+
+
+end Test;
diff --git a/game.srcs/sim_1/new/vga_tb.vhd b/game.srcs/sim_1/new/vga_tb.vhd
new file mode 100644
index 0000000000000000000000000000000000000000..8cad940d03ab599632d0bed8627e351bb624f7c0
--- /dev/null
+++ b/game.srcs/sim_1/new/vga_tb.vhd
@@ -0,0 +1,72 @@
+----------------------------------------------------------------------------------
+-- Company:
+-- Engineer:
+--
+-- Create Date: 02/27/2023 11:51:05 AM
+-- Design Name:
+-- Module Name: vga_tb - Behavioral
+-- Project Name:
+-- Target Devices:
+-- Tool Versions:
+-- Description:
+--
+-- Dependencies:
+--
+-- Revision:
+-- Revision 0.01 - File Created
+-- Additional Comments:
+--
+----------------------------------------------------------------------------------
+
+
+library IEEE;
+use IEEE.STD_LOGIC_1164.ALL;
+
+-- Uncomment the following library declaration if using
+-- arithmetic functions with Signed or Unsigned values
+--use IEEE.NUMERIC_STD.ALL;
+
+-- Uncomment the following library declaration if instantiating
+-- any Xilinx leaf cells in this code.
+--library UNISIM;
+--use UNISIM.VComponents.all;
+
+entity vga_tb is
+-- Port ( );
+end vga_tb;
+
+architecture Test of vga_tb is
+
+component vga is
+Port ( clk_pixel, btnCpuReset_v : in std_logic;
+ color : in std_logic_vector (11 downto 0);
+ vgaRed_v : out std_logic_vector(3 downto 0);
+ vgaBlue_v : out std_logic_vector(3 downto 0);
+ vgaGreen_v : out std_logic_vector(3 downto 0);
+ Hsync_v, Vsync_v : out std_logic;
+ HCounter : out integer range 1 to 800;
+ VCounter : out integer range 1 to 525;
+ FCounter : out integer range 0 to 4095;
+ FStrobe : out std_logic
+ );
+ end component;
+
+signal btnCpuReset_i, Hsync_i, Vsync_i : std_logic;
+signal clk_pixel_i : std_logic := '0';
+signal color_i : std_logic_vector(11 downto 0);
+
+begin
+DUT: vga port map(
+ clk_pixel => clk_pixel_i,
+ color => color_i,
+ btnCpuReset_v => btnCpuReset_i,
+ Hsync_v => Hsync_i,
+ Vsync_v => Vsync_i
+ );
+
+
+
+
+
+
+end Test;
diff --git a/game.srcs/sources_1/bd/design_1/design_1.bd b/game.srcs/sources_1/bd/design_1/design_1.bd
new file mode 100644
index 0000000000000000000000000000000000000000..b5a37ec677b6d390b907c4234ea7e858eb39b128
--- /dev/null
+++ b/game.srcs/sources_1/bd/design_1/design_1.bd
@@ -0,0 +1,13 @@
+{
+ "design": {
+ "design_info": {
+ "boundary_crc": "0x0",
+ "gen_directory": "../../../../game.gen/sources_1/bd/design_1",
+ "name": "design_1",
+ "rev_ctrl_bd_flag": "RevCtrlBdOff",
+ "synth_flow_mode": "Hierarchical",
+ "tool_version": "2022.2"
+ },
+ "design_tree": {}
+ }
+}
\ No newline at end of file
diff --git a/game.srcs/sources_1/bd/design_1/ui/bd_1f5defd0.ui b/game.srcs/sources_1/bd/design_1/ui/bd_1f5defd0.ui
new file mode 100644
index 0000000000000000000000000000000000000000..aeea98b9debc75ff62fb1198920449dbe531c722
--- /dev/null
+++ b/game.srcs/sources_1/bd/design_1/ui/bd_1f5defd0.ui
@@ -0,0 +1,12 @@
+{
+ "ActiveEmotionalView":"Default View",
+ "Default View_ScaleFactor":"1.0",
+ "Default View_TopLeft":"-904,-419",
+ "ExpandedHierarchyInLayout":"",
+ "guistr":"# # String gsaved with Nlview 7.0r4 2019-12-20 bk=1.5203 VDI=41 GEI=36 GUI=JA:10.0 TLS
+# -string -flagsOSRD
+levelinfo -pg 1 0 10
+pagesize -pg 1 -db -bbox -sgen 0 0 10 10
+"
+}
+
diff --git a/game.srcs/sources_1/ip/clk_wiz_0/clk_wiz_0.xci b/game.srcs/sources_1/ip/clk_wiz_0/clk_wiz_0.xci
new file mode 100644
index 0000000000000000000000000000000000000000..b3602039688147e373099ce018cbd497e90a7595
--- /dev/null
+++ b/game.srcs/sources_1/ip/clk_wiz_0/clk_wiz_0.xci
@@ -0,0 +1,671 @@
+{
+ "schema": "xilinx.com:schema:json_instance:1.0",
+ "ip_inst": {
+ "xci_name": "clk_wiz_0",
+ "component_reference": "xilinx.com:ip:clk_wiz:6.0",
+ "ip_revision": "11",
+ "gen_directory": "../../../../game.gen/sources_1/ip/clk_wiz_0",
+ "parameters": {
+ "component_parameters": {
+ "Component_Name": [ { "value": "clk_wiz_0", "resolve_type": "user", "usage": "all" } ],
+ "USER_CLK_FREQ0": [ { "value": "100.0", "resolve_type": "user", "format": "float", "usage": "all" } ],
+ "USER_CLK_FREQ1": [ { "value": "100.0", "resolve_type": "user", "format": "float", "usage": "all" } ],
+ "USER_CLK_FREQ2": [ { "value": "100.0", "resolve_type": "user", "format": "float", "usage": "all" } ],
+ "USER_CLK_FREQ3": [ { "value": "100.0", "resolve_type": "user", "format": "float", "usage": "all" } ],
+ "ENABLE_CLOCK_MONITOR": [ { "value": "false", "resolve_type": "user", "format": "bool", "usage": "all" } ],
+ "OPTIMIZE_CLOCKING_STRUCTURE_EN": [ { "value": "false", "resolve_type": "user", "format": "bool", "usage": "all" } ],
+ "ENABLE_USER_CLOCK0": [ { "value": "false", "resolve_type": "user", "format": "bool", "usage": "all" } ],
+ "ENABLE_USER_CLOCK1": [ { "value": "false", "resolve_type": "user", "format": "bool", "usage": "all" } ],
+ "ENABLE_USER_CLOCK2": [ { "value": "false", "resolve_type": "user", "format": "bool", "usage": "all" } ],
+ "ENABLE_USER_CLOCK3": [ { "value": "false", "resolve_type": "user", "format": "bool", "usage": "all" } ],
+ "Enable_PLL0": [ { "value": "false", "resolve_type": "user", "format": "bool", "usage": "all" } ],
+ "Enable_PLL1": [ { "value": "false", "resolve_type": "user", "format": "bool", "usage": "all" } ],
+ "REF_CLK_FREQ": [ { "value": "100.0", "resolve_type": "user", "format": "float", "usage": "all" } ],
+ "PRECISION": [ { "value": "1", "resolve_type": "user", "format": "float", "usage": "all" } ],
+ "PRIMITIVE": [ { "value": "MMCM", "resolve_type": "user", "usage": "all" } ],
+ "PRIMTYPE_SEL": [ { "value": "mmcm_adv", "resolve_type": "user", "usage": "all" } ],
+ "CLOCK_MGR_TYPE": [ { "value": "auto", "resolve_type": "user", "usage": "all" } ],
+ "USE_FREQ_SYNTH": [ { "value": "true", "resolve_type": "user", "format": "bool", "usage": "all" } ],
+ "USE_SPREAD_SPECTRUM": [ { "value": "false", "resolve_type": "user", "format": "bool", "usage": "all" } ],
+ "USE_PHASE_ALIGNMENT": [ { "value": "true", "resolve_type": "user", "format": "bool", "usage": "all" } ],
+ "USE_MIN_POWER": [ { "value": "false", "resolve_type": "user", "format": "bool", "usage": "all" } ],
+ "USE_DYN_PHASE_SHIFT": [ { "value": "false", "resolve_type": "user", "format": "bool", "usage": "all" } ],
+ "USE_DYN_RECONFIG": [ { "value": "false", "resolve_type": "user", "format": "bool", "usage": "all" } ],
+ "JITTER_SEL": [ { "value": "No_Jitter", "resolve_type": "user", "usage": "all" } ],
+ "PRIM_IN_FREQ": [ { "value": "100.000", "resolve_type": "user", "format": "float", "usage": "all" } ],
+ "PRIM_IN_TIMEPERIOD": [ { "value": "10.000", "resolve_type": "user", "format": "float", "usage": "all" } ],
+ "IN_FREQ_UNITS": [ { "value": "Units_MHz", "resolve_type": "user", "usage": "all" } ],
+ "PHASESHIFT_MODE": [ { "value": "WAVEFORM", "resolve_type": "user", "usage": "all" } ],
+ "IN_JITTER_UNITS": [ { "value": "Units_UI", "resolve_type": "user", "usage": "all" } ],
+ "RELATIVE_INCLK": [ { "value": "REL_PRIMARY", "resolve_type": "user", "usage": "all" } ],
+ "USE_INCLK_SWITCHOVER": [ { "value": "false", "resolve_type": "user", "format": "bool", "usage": "all" } ],
+ "SECONDARY_IN_FREQ": [ { "value": "100.000", "resolve_type": "user", "format": "float", "usage": "all" } ],
+ "SECONDARY_IN_TIMEPERIOD": [ { "value": "10.000", "resolve_type": "user", "format": "float", "usage": "all" } ],
+ "SECONDARY_PORT": [ { "value": "clk_in2", "resolve_type": "user", "usage": "all" } ],
+ "SECONDARY_SOURCE": [ { "value": "Single_ended_clock_capable_pin", "resolve_type": "user", "usage": "all" } ],
+ "JITTER_OPTIONS": [ { "value": "UI", "resolve_type": "user", "usage": "all" } ],
+ "CLKIN1_UI_JITTER": [ { "value": "0.010", "resolve_type": "user", "format": "float", "usage": "all" } ],
+ "CLKIN2_UI_JITTER": [ { "value": "0.010", "resolve_type": "user", "format": "float", "usage": "all" } ],
+ "PRIM_IN_JITTER": [ { "value": "0.010", "resolve_type": "user", "format": "float", "usage": "all" } ],
+ "SECONDARY_IN_JITTER": [ { "value": "0.010", "resolve_type": "user", "format": "float", "usage": "all" } ],
+ "CLKIN1_JITTER_PS": [ { "value": "100.0", "resolve_type": "user", "format": "float", "usage": "all" } ],
+ "CLKIN2_JITTER_PS": [ { "value": "100.0", "resolve_type": "user", "format": "float", "usage": "all" } ],
+ "CLKOUT1_USED": [ { "value": "true", "resolve_type": "user", "format": "bool", "usage": "all" } ],
+ "CLKOUT2_USED": [ { "value": "false", "resolve_type": "user", "format": "bool", "usage": "all" } ],
+ "CLKOUT3_USED": [ { "value": "false", "resolve_type": "user", "format": "bool", "usage": "all" } ],
+ "CLKOUT4_USED": [ { "value": "false", "resolve_type": "user", "format": "bool", "usage": "all" } ],
+ "CLKOUT5_USED": [ { "value": "false", "resolve_type": "user", "format": "bool", "usage": "all" } ],
+ "CLKOUT6_USED": [ { "value": "false", "resolve_type": "user", "format": "bool", "usage": "all" } ],
+ "CLKOUT7_USED": [ { "value": "false", "resolve_type": "user", "format": "bool", "usage": "all" } ],
+ "NUM_OUT_CLKS": [ { "value": "1", "resolve_type": "user", "format": "long", "usage": "all" } ],
+ "CLK_OUT1_USE_FINE_PS_GUI": [ { "value": "false", "resolve_type": "user", "format": "bool", "usage": "all" } ],
+ "CLK_OUT2_USE_FINE_PS_GUI": [ { "value": "false", "resolve_type": "user", "format": "bool", "usage": "all" } ],
+ "CLK_OUT3_USE_FINE_PS_GUI": [ { "value": "false", "resolve_type": "user", "format": "bool", "usage": "all" } ],
+ "CLK_OUT4_USE_FINE_PS_GUI": [ { "value": "false", "resolve_type": "user", "format": "bool", "usage": "all" } ],
+ "CLK_OUT5_USE_FINE_PS_GUI": [ { "value": "false", "resolve_type": "user", "format": "bool", "usage": "all" } ],
+ "CLK_OUT6_USE_FINE_PS_GUI": [ { "value": "false", "resolve_type": "user", "format": "bool", "usage": "all" } ],
+ "CLK_OUT7_USE_FINE_PS_GUI": [ { "value": "false", "resolve_type": "user", "format": "bool", "usage": "all" } ],
+ "PRIMARY_PORT": [ { "value": "clk_in1", "resolve_type": "user", "usage": "all" } ],
+ "CLK_OUT1_PORT": [ { "value": "clk_out1", "resolve_type": "user", "usage": "all" } ],
+ "CLK_OUT2_PORT": [ { "value": "clk_out2", "resolve_type": "user", "usage": "all" } ],
+ "CLK_OUT3_PORT": [ { "value": "clk_out3", "resolve_type": "user", "usage": "all" } ],
+ "CLK_OUT4_PORT": [ { "value": "clk_out4", "resolve_type": "user", "usage": "all" } ],
+ "CLK_OUT5_PORT": [ { "value": "clk_out5", "resolve_type": "user", "usage": "all" } ],
+ "CLK_OUT6_PORT": [ { "value": "clk_out6", "resolve_type": "user", "usage": "all" } ],
+ "CLK_OUT7_PORT": [ { "value": "clk_out7", "resolve_type": "user", "usage": "all" } ],
+ "DADDR_PORT": [ { "value": "daddr", "resolve_type": "user", "usage": "all" } ],
+ "DCLK_PORT": [ { "value": "dclk", "resolve_type": "user", "usage": "all" } ],
+ "DRDY_PORT": [ { "value": "drdy", "resolve_type": "user", "usage": "all" } ],
+ "DWE_PORT": [ { "value": "dwe", "resolve_type": "user", "usage": "all" } ],
+ "DIN_PORT": [ { "value": "din", "resolve_type": "user", "usage": "all" } ],
+ "DOUT_PORT": [ { "value": "dout", "resolve_type": "user", "usage": "all" } ],
+ "DEN_PORT": [ { "value": "den", "resolve_type": "user", "usage": "all" } ],
+ "PSCLK_PORT": [ { "value": "psclk", "resolve_type": "user", "usage": "all" } ],
+ "PSEN_PORT": [ { "value": "psen", "resolve_type": "user", "usage": "all" } ],
+ "PSINCDEC_PORT": [ { "value": "psincdec", "resolve_type": "user", "usage": "all" } ],
+ "PSDONE_PORT": [ { "value": "psdone", "resolve_type": "user", "usage": "all" } ],
+ "CLKOUT1_REQUESTED_OUT_FREQ": [ { "value": "25", "value_src": "user", "resolve_type": "user", "format": "float", "usage": "all" } ],
+ "CLKOUT1_REQUESTED_PHASE": [ { "value": "0.000", "resolve_type": "user", "format": "float", "usage": "all" } ],
+ "CLKOUT1_REQUESTED_DUTY_CYCLE": [ { "value": "50.000", "resolve_type": "user", "format": "float", "usage": "all" } ],
+ "CLKOUT2_REQUESTED_OUT_FREQ": [ { "value": "100.000", "resolve_type": "user", "format": "float", "usage": "all" } ],
+ "CLKOUT2_REQUESTED_PHASE": [ { "value": "0.000", "resolve_type": "user", "format": "float", "usage": "all" } ],
+ "CLKOUT2_REQUESTED_DUTY_CYCLE": [ { "value": "50.000", "resolve_type": "user", "format": "float", "usage": "all" } ],
+ "CLKOUT3_REQUESTED_OUT_FREQ": [ { "value": "100.000", "resolve_type": "user", "format": "float", "usage": "all" } ],
+ "CLKOUT3_REQUESTED_PHASE": [ { "value": "0.000", "resolve_type": "user", "format": "float", "usage": "all" } ],
+ "CLKOUT3_REQUESTED_DUTY_CYCLE": [ { "value": "50.000", "resolve_type": "user", "format": "float", "usage": "all" } ],
+ "CLKOUT4_REQUESTED_OUT_FREQ": [ { "value": "100.000", "resolve_type": "user", "format": "float", "usage": "all" } ],
+ "CLKOUT4_REQUESTED_PHASE": [ { "value": "0.000", "resolve_type": "user", "format": "float", "usage": "all" } ],
+ "CLKOUT4_REQUESTED_DUTY_CYCLE": [ { "value": "50.000", "resolve_type": "user", "format": "float", "usage": "all" } ],
+ "CLKOUT5_REQUESTED_OUT_FREQ": [ { "value": "100.000", "resolve_type": "user", "format": "float", "usage": "all" } ],
+ "CLKOUT5_REQUESTED_PHASE": [ { "value": "0.000", "resolve_type": "user", "format": "float", "usage": "all" } ],
+ "CLKOUT5_REQUESTED_DUTY_CYCLE": [ { "value": "50.000", "resolve_type": "user", "format": "float", "usage": "all" } ],
+ "CLKOUT6_REQUESTED_OUT_FREQ": [ { "value": "100.000", "resolve_type": "user", "format": "float", "usage": "all" } ],
+ "CLKOUT6_REQUESTED_PHASE": [ { "value": "0.000", "resolve_type": "user", "format": "float", "usage": "all" } ],
+ "CLKOUT6_REQUESTED_DUTY_CYCLE": [ { "value": "50.000", "resolve_type": "user", "format": "float", "usage": "all" } ],
+ "CLKOUT7_REQUESTED_OUT_FREQ": [ { "value": "100.000", "resolve_type": "user", "format": "float", "usage": "all" } ],
+ "CLKOUT7_REQUESTED_PHASE": [ { "value": "0.000", "resolve_type": "user", "format": "float", "usage": "all" } ],
+ "CLKOUT7_REQUESTED_DUTY_CYCLE": [ { "value": "50.000", "resolve_type": "user", "format": "float", "usage": "all" } ],
+ "USE_MAX_I_JITTER": [ { "value": "false", "resolve_type": "user", "format": "bool", "usage": "all" } ],
+ "USE_MIN_O_JITTER": [ { "value": "false", "resolve_type": "user", "format": "bool", "usage": "all" } ],
+ "CLKOUT1_MATCHED_ROUTING": [ { "value": "false", "resolve_type": "user", "format": "bool", "usage": "all" } ],
+ "CLKOUT2_MATCHED_ROUTING": [ { "value": "false", "resolve_type": "user", "format": "bool", "usage": "all" } ],
+ "CLKOUT3_MATCHED_ROUTING": [ { "value": "false", "resolve_type": "user", "format": "bool", "usage": "all" } ],
+ "CLKOUT4_MATCHED_ROUTING": [ { "value": "false", "resolve_type": "user", "format": "bool", "usage": "all" } ],
+ "CLKOUT5_MATCHED_ROUTING": [ { "value": "false", "resolve_type": "user", "format": "bool", "usage": "all" } ],
+ "CLKOUT6_MATCHED_ROUTING": [ { "value": "false", "resolve_type": "user", "format": "bool", "usage": "all" } ],
+ "CLKOUT7_MATCHED_ROUTING": [ { "value": "false", "resolve_type": "user", "format": "bool", "usage": "all" } ],
+ "PRIM_SOURCE": [ { "value": "Single_ended_clock_capable_pin", "resolve_type": "user", "usage": "all" } ],
+ "CLKOUT1_DRIVES": [ { "value": "BUFG", "resolve_type": "user", "usage": "all" } ],
+ "CLKOUT2_DRIVES": [ { "value": "BUFG", "resolve_type": "user", "usage": "all" } ],
+ "CLKOUT3_DRIVES": [ { "value": "BUFG", "resolve_type": "user", "usage": "all" } ],
+ "CLKOUT4_DRIVES": [ { "value": "BUFG", "resolve_type": "user", "usage": "all" } ],
+ "CLKOUT5_DRIVES": [ { "value": "BUFG", "resolve_type": "user", "usage": "all" } ],
+ "CLKOUT6_DRIVES": [ { "value": "BUFG", "resolve_type": "user", "usage": "all" } ],
+ "CLKOUT7_DRIVES": [ { "value": "BUFG", "resolve_type": "user", "usage": "all" } ],
+ "FEEDBACK_SOURCE": [ { "value": "FDBK_AUTO", "resolve_type": "user", "usage": "all" } ],
+ "CLKFB_IN_SIGNALING": [ { "value": "SINGLE", "resolve_type": "user", "usage": "all" } ],
+ "CLKFB_IN_PORT": [ { "value": "clkfb_in", "resolve_type": "user", "usage": "all" } ],
+ "CLKFB_IN_P_PORT": [ { "value": "clkfb_in_p", "resolve_type": "user", "usage": "all" } ],
+ "CLKFB_IN_N_PORT": [ { "value": "clkfb_in_n", "resolve_type": "user", "usage": "all" } ],
+ "CLKFB_OUT_PORT": [ { "value": "clkfb_out", "resolve_type": "user", "usage": "all" } ],
+ "CLKFB_OUT_P_PORT": [ { "value": "clkfb_out_p", "resolve_type": "user", "usage": "all" } ],
+ "CLKFB_OUT_N_PORT": [ { "value": "clkfb_out_n", "resolve_type": "user", "usage": "all" } ],
+ "PLATFORM": [ { "value": "UNKNOWN", "resolve_type": "user", "usage": "all" } ],
+ "SUMMARY_STRINGS": [ { "value": "empty", "resolve_type": "user", "usage": "all" } ],
+ "USE_LOCKED": [ { "value": "false", "value_src": "user", "resolve_type": "user", "format": "bool", "usage": "all" } ],
+ "CALC_DONE": [ { "value": "empty", "resolve_type": "user", "usage": "all" } ],
+ "USE_RESET": [ { "value": "true", "resolve_type": "user", "format": "bool", "usage": "all" } ],
+ "USE_POWER_DOWN": [ { "value": "false", "resolve_type": "user", "format": "bool", "usage": "all" } ],
+ "USE_STATUS": [ { "value": "false", "resolve_type": "user", "format": "bool", "usage": "all" } ],
+ "USE_FREEZE": [ { "value": "false", "resolve_type": "user", "format": "bool", "usage": "all" } ],
+ "USE_CLK_VALID": [ { "value": "false", "resolve_type": "user", "format": "bool", "usage": "all" } ],
+ "USE_INCLK_STOPPED": [ { "value": "false", "resolve_type": "user", "format": "bool", "usage": "all" } ],
+ "USE_CLKFB_STOPPED": [ { "value": "false", "resolve_type": "user", "format": "bool", "usage": "all" } ],
+ "RESET_PORT": [ { "value": "resetn", "value_src": "user", "resolve_type": "user", "usage": "all" } ],
+ "LOCKED_PORT": [ { "value": "locked", "resolve_type": "user", "usage": "all" } ],
+ "POWER_DOWN_PORT": [ { "value": "power_down", "resolve_type": "user", "usage": "all" } ],
+ "CLK_VALID_PORT": [ { "value": "CLK_VALID", "resolve_type": "user", "usage": "all" } ],
+ "STATUS_PORT": [ { "value": "STATUS", "resolve_type": "user", "usage": "all" } ],
+ "CLK_IN_SEL_PORT": [ { "value": "clk_in_sel", "resolve_type": "user", "usage": "all" } ],
+ "INPUT_CLK_STOPPED_PORT": [ { "value": "input_clk_stopped", "resolve_type": "user", "usage": "all" } ],
+ "CLKFB_STOPPED_PORT": [ { "value": "clkfb_stopped", "resolve_type": "user", "usage": "all" } ],
+ "SS_MODE": [ { "value": "CENTER_HIGH", "resolve_type": "user", "usage": "all" } ],
+ "SS_MOD_FREQ": [ { "value": "250", "resolve_type": "user", "format": "float", "usage": "all" } ],
+ "SS_MOD_TIME": [ { "value": "0.004", "resolve_type": "user", "format": "float", "usage": "all" } ],
+ "OVERRIDE_MMCM": [ { "value": "false", "resolve_type": "user", "format": "bool", "usage": "all" } ],
+ "MMCM_NOTES": [ { "value": "None", "resolve_type": "user", "usage": "all" } ],
+ "MMCM_DIVCLK_DIVIDE": [ { "value": "1", "resolve_type": "user", "format": "long", "usage": "all" } ],
+ "MMCM_BANDWIDTH": [ { "value": "OPTIMIZED", "resolve_type": "user", "usage": "all" } ],
+ "MMCM_CLKFBOUT_MULT_F": [ { "value": "9.125", "value_src": "user", "resolve_type": "user", "format": "float", "usage": "all" } ],
+ "MMCM_CLKFBOUT_PHASE": [ { "value": "0.000", "resolve_type": "user", "format": "float", "usage": "all" } ],
+ "MMCM_CLKFBOUT_USE_FINE_PS": [ { "value": "false", "resolve_type": "user", "format": "bool", "usage": "all" } ],
+ "MMCM_CLKIN1_PERIOD": [ { "value": "10.000", "resolve_type": "user", "format": "float", "usage": "all" } ],
+ "MMCM_CLKIN2_PERIOD": [ { "value": "10.000", "resolve_type": "user", "format": "float", "usage": "all" } ],
+ "MMCM_CLKOUT4_CASCADE": [ { "value": "false", "resolve_type": "user", "format": "bool", "usage": "all" } ],
+ "MMCM_CLOCK_HOLD": [ { "value": "false", "resolve_type": "user", "format": "bool", "usage": "all" } ],
+ "MMCM_COMPENSATION": [ { "value": "ZHOLD", "resolve_type": "user", "usage": "all" } ],
+ "MMCM_REF_JITTER1": [ { "value": "0.010", "resolve_type": "user", "format": "float", "usage": "all" } ],
+ "MMCM_REF_JITTER2": [ { "value": "0.010", "resolve_type": "user", "format": "float", "usage": "all" } ],
+ "MMCM_STARTUP_WAIT": [ { "value": "false", "resolve_type": "user", "format": "bool", "usage": "all" } ],
+ "MMCM_CLKOUT0_DIVIDE_F": [ { "value": "36.500", "value_src": "user", "resolve_type": "user", "format": "float", "usage": "all" } ],
+ "MMCM_CLKOUT0_DUTY_CYCLE": [ { "value": "0.500", "resolve_type": "user", "format": "float", "usage": "all" } ],
+ "MMCM_CLKOUT0_PHASE": [ { "value": "0.000", "resolve_type": "user", "format": "float", "usage": "all" } ],
+ "MMCM_CLKOUT0_USE_FINE_PS": [ { "value": "false", "resolve_type": "user", "format": "bool", "usage": "all" } ],
+ "MMCM_CLKOUT1_DIVIDE": [ { "value": "1", "resolve_type": "user", "format": "long", "usage": "all" } ],
+ "MMCM_CLKOUT1_DUTY_CYCLE": [ { "value": "0.500", "resolve_type": "user", "format": "float", "usage": "all" } ],
+ "MMCM_CLKOUT1_PHASE": [ { "value": "0.000", "resolve_type": "user", "format": "float", "usage": "all" } ],
+ "MMCM_CLKOUT1_USE_FINE_PS": [ { "value": "false", "resolve_type": "user", "format": "bool", "usage": "all" } ],
+ "MMCM_CLKOUT2_DIVIDE": [ { "value": "1", "resolve_type": "user", "format": "long", "usage": "all" } ],
+ "MMCM_CLKOUT2_DUTY_CYCLE": [ { "value": "0.500", "resolve_type": "user", "format": "float", "usage": "all" } ],
+ "MMCM_CLKOUT2_PHASE": [ { "value": "0.000", "resolve_type": "user", "format": "float", "usage": "all" } ],
+ "MMCM_CLKOUT2_USE_FINE_PS": [ { "value": "false", "resolve_type": "user", "format": "bool", "usage": "all" } ],
+ "MMCM_CLKOUT3_DIVIDE": [ { "value": "1", "resolve_type": "user", "format": "long", "usage": "all" } ],
+ "MMCM_CLKOUT3_DUTY_CYCLE": [ { "value": "0.500", "resolve_type": "user", "format": "float", "usage": "all" } ],
+ "MMCM_CLKOUT3_PHASE": [ { "value": "0.000", "resolve_type": "user", "format": "float", "usage": "all" } ],
+ "MMCM_CLKOUT3_USE_FINE_PS": [ { "value": "false", "resolve_type": "user", "format": "bool", "usage": "all" } ],
+ "MMCM_CLKOUT4_DIVIDE": [ { "value": "1", "resolve_type": "user", "format": "long", "usage": "all" } ],
+ "MMCM_CLKOUT4_DUTY_CYCLE": [ { "value": "0.500", "resolve_type": "user", "format": "float", "usage": "all" } ],
+ "MMCM_CLKOUT4_PHASE": [ { "value": "0.000", "resolve_type": "user", "format": "float", "usage": "all" } ],
+ "MMCM_CLKOUT4_USE_FINE_PS": [ { "value": "false", "resolve_type": "user", "format": "bool", "usage": "all" } ],
+ "MMCM_CLKOUT5_DIVIDE": [ { "value": "1", "resolve_type": "user", "format": "long", "usage": "all" } ],
+ "MMCM_CLKOUT5_DUTY_CYCLE": [ { "value": "0.500", "resolve_type": "user", "format": "float", "usage": "all" } ],
+ "MMCM_CLKOUT5_PHASE": [ { "value": "0.000", "resolve_type": "user", "format": "float", "usage": "all" } ],
+ "MMCM_CLKOUT5_USE_FINE_PS": [ { "value": "false", "resolve_type": "user", "format": "bool", "usage": "all" } ],
+ "MMCM_CLKOUT6_DIVIDE": [ { "value": "1", "resolve_type": "user", "format": "long", "usage": "all" } ],
+ "MMCM_CLKOUT6_DUTY_CYCLE": [ { "value": "0.500", "resolve_type": "user", "format": "float", "usage": "all" } ],
+ "MMCM_CLKOUT6_PHASE": [ { "value": "0.000", "resolve_type": "user", "format": "float", "usage": "all" } ],
+ "MMCM_CLKOUT6_USE_FINE_PS": [ { "value": "false", "resolve_type": "user", "format": "bool", "usage": "all" } ],
+ "OVERRIDE_PLL": [ { "value": "false", "resolve_type": "user", "format": "bool", "usage": "all" } ],
+ "PLL_NOTES": [ { "value": "None", "resolve_type": "user", "usage": "all" } ],
+ "PLL_BANDWIDTH": [ { "value": "OPTIMIZED", "resolve_type": "user", "usage": "all" } ],
+ "PLL_CLKFBOUT_MULT": [ { "value": "4", "resolve_type": "user", "format": "long", "usage": "all" } ],
+ "PLL_CLKFBOUT_PHASE": [ { "value": "0.000", "resolve_type": "user", "format": "float", "usage": "all" } ],
+ "PLL_CLK_FEEDBACK": [ { "value": "CLKFBOUT", "resolve_type": "user", "usage": "all" } ],
+ "PLL_DIVCLK_DIVIDE": [ { "value": "1", "resolve_type": "user", "format": "long", "usage": "all" } ],
+ "PLL_CLKIN_PERIOD": [ { "value": "10.000", "resolve_type": "user", "format": "float", "usage": "all" } ],
+ "PLL_COMPENSATION": [ { "value": "SYSTEM_SYNCHRONOUS", "resolve_type": "user", "usage": "all" } ],
+ "PLL_REF_JITTER": [ { "value": "0.010", "resolve_type": "user", "format": "float", "usage": "all" } ],
+ "PLL_CLKOUT0_DIVIDE": [ { "value": "1", "resolve_type": "user", "format": "long", "usage": "all" } ],
+ "PLL_CLKOUT0_DUTY_CYCLE": [ { "value": "0.500", "resolve_type": "user", "format": "float", "usage": "all" } ],
+ "PLL_CLKOUT0_PHASE": [ { "value": "0.000", "resolve_type": "user", "format": "float", "usage": "all" } ],
+ "PLL_CLKOUT1_DIVIDE": [ { "value": "1", "resolve_type": "user", "format": "long", "usage": "all" } ],
+ "PLL_CLKOUT1_DUTY_CYCLE": [ { "value": "0.500", "resolve_type": "user", "format": "float", "usage": "all" } ],
+ "PLL_CLKOUT1_PHASE": [ { "value": "0.000", "resolve_type": "user", "format": "float", "usage": "all" } ],
+ "PLL_CLKOUT2_DIVIDE": [ { "value": "1", "resolve_type": "user", "format": "long", "usage": "all" } ],
+ "PLL_CLKOUT2_DUTY_CYCLE": [ { "value": "0.500", "resolve_type": "user", "format": "float", "usage": "all" } ],
+ "PLL_CLKOUT2_PHASE": [ { "value": "0.000", "resolve_type": "user", "format": "float", "usage": "all" } ],
+ "PLL_CLKOUT3_DIVIDE": [ { "value": "1", "resolve_type": "user", "format": "long", "usage": "all" } ],
+ "PLL_CLKOUT3_DUTY_CYCLE": [ { "value": "0.500", "resolve_type": "user", "format": "float", "usage": "all" } ],
+ "PLL_CLKOUT3_PHASE": [ { "value": "0.000", "resolve_type": "user", "format": "float", "usage": "all" } ],
+ "PLL_CLKOUT4_DIVIDE": [ { "value": "1", "resolve_type": "user", "format": "long", "usage": "all" } ],
+ "PLL_CLKOUT4_DUTY_CYCLE": [ { "value": "0.500", "resolve_type": "user", "format": "float", "usage": "all" } ],
+ "PLL_CLKOUT4_PHASE": [ { "value": "0.000", "resolve_type": "user", "format": "float", "usage": "all" } ],
+ "PLL_CLKOUT5_DIVIDE": [ { "value": "1", "resolve_type": "user", "format": "long", "usage": "all" } ],
+ "PLL_CLKOUT5_DUTY_CYCLE": [ { "value": "0.500", "resolve_type": "user", "format": "float", "usage": "all" } ],
+ "PLL_CLKOUT5_PHASE": [ { "value": "0.000", "resolve_type": "user", "format": "float", "usage": "all" } ],
+ "RESET_TYPE": [ { "value": "ACTIVE_LOW", "value_src": "user", "resolve_type": "user", "usage": "all" } ],
+ "USE_SAFE_CLOCK_STARTUP": [ { "value": "false", "resolve_type": "user", "format": "bool", "usage": "all" } ],
+ "USE_CLOCK_SEQUENCING": [ { "value": "false", "resolve_type": "user", "format": "bool", "usage": "all" } ],
+ "CLKOUT1_SEQUENCE_NUMBER": [ { "value": "1", "resolve_type": "user", "format": "long", "usage": "all" } ],
+ "CLKOUT2_SEQUENCE_NUMBER": [ { "value": "1", "resolve_type": "user", "format": "long", "usage": "all" } ],
+ "CLKOUT3_SEQUENCE_NUMBER": [ { "value": "1", "resolve_type": "user", "format": "long", "usage": "all" } ],
+ "CLKOUT4_SEQUENCE_NUMBER": [ { "value": "1", "resolve_type": "user", "format": "long", "usage": "all" } ],
+ "CLKOUT5_SEQUENCE_NUMBER": [ { "value": "1", "resolve_type": "user", "format": "long", "usage": "all" } ],
+ "CLKOUT6_SEQUENCE_NUMBER": [ { "value": "1", "resolve_type": "user", "format": "long", "usage": "all" } ],
+ "CLKOUT7_SEQUENCE_NUMBER": [ { "value": "1", "resolve_type": "user", "format": "long", "usage": "all" } ],
+ "USE_BOARD_FLOW": [ { "value": "false", "resolve_type": "user", "format": "bool", "usage": "all" } ],
+ "CLK_IN1_BOARD_INTERFACE": [ { "value": "Custom", "resolve_type": "user", "usage": "all" } ],
+ "CLK_IN2_BOARD_INTERFACE": [ { "value": "Custom", "resolve_type": "user", "usage": "all" } ],
+ "DIFF_CLK_IN1_BOARD_INTERFACE": [ { "value": "Custom", "resolve_type": "user", "usage": "all" } ],
+ "DIFF_CLK_IN2_BOARD_INTERFACE": [ { "value": "Custom", "resolve_type": "user", "usage": "all" } ],
+ "AUTO_PRIMITIVE": [ { "value": "MMCM", "resolve_type": "user", "usage": "all" } ],
+ "RESET_BOARD_INTERFACE": [ { "value": "Custom", "resolve_type": "user", "usage": "all" } ],
+ "ENABLE_CDDC": [ { "value": "false", "resolve_type": "user", "format": "bool", "usage": "all" } ],
+ "CDDCDONE_PORT": [ { "value": "cddcdone", "resolve_type": "user", "usage": "all" } ],
+ "CDDCREQ_PORT": [ { "value": "cddcreq", "resolve_type": "user", "usage": "all" } ],
+ "ENABLE_CLKOUTPHY": [ { "value": "false", "resolve_type": "user", "format": "bool", "usage": "all" } ],
+ "CLKOUTPHY_REQUESTED_FREQ": [ { "value": "600.000", "resolve_type": "user", "format": "float", "usage": "all" } ],
+ "CLKOUT1_JITTER": [ { "value": "181.828", "value_src": "user", "resolve_type": "user", "format": "float", "usage": "all" } ],
+ "CLKOUT1_PHASE_ERROR": [ { "value": "104.359", "value_src": "user", "resolve_type": "user", "format": "float", "usage": "all" } ],
+ "CLKOUT2_JITTER": [ { "value": "0.0", "resolve_type": "user", "format": "float", "usage": "all" } ],
+ "CLKOUT2_PHASE_ERROR": [ { "value": "0.0", "resolve_type": "user", "format": "float", "usage": "all" } ],
+ "CLKOUT3_JITTER": [ { "value": "0.0", "resolve_type": "user", "format": "float", "usage": "all" } ],
+ "CLKOUT3_PHASE_ERROR": [ { "value": "0.0", "resolve_type": "user", "format": "float", "usage": "all" } ],
+ "CLKOUT4_JITTER": [ { "value": "0.0", "resolve_type": "user", "format": "float", "usage": "all" } ],
+ "CLKOUT4_PHASE_ERROR": [ { "value": "0.0", "resolve_type": "user", "format": "float", "usage": "all" } ],
+ "CLKOUT5_JITTER": [ { "value": "0.0", "resolve_type": "user", "format": "float", "usage": "all" } ],
+ "CLKOUT5_PHASE_ERROR": [ { "value": "0.0", "resolve_type": "user", "format": "float", "usage": "all" } ],
+ "CLKOUT6_JITTER": [ { "value": "0.0", "resolve_type": "user", "format": "float", "usage": "all" } ],
+ "CLKOUT6_PHASE_ERROR": [ { "value": "0.0", "resolve_type": "user", "format": "float", "usage": "all" } ],
+ "CLKOUT7_JITTER": [ { "value": "0.0", "resolve_type": "user", "format": "float", "usage": "all" } ],
+ "CLKOUT7_PHASE_ERROR": [ { "value": "0.0", "resolve_type": "user", "format": "float", "usage": "all" } ],
+ "INPUT_MODE": [ { "value": "frequency", "resolve_type": "user", "usage": "all" } ],
+ "INTERFACE_SELECTION": [ { "value": "Enable_AXI", "resolve_type": "user", "usage": "all" } ],
+ "AXI_DRP": [ { "value": "false", "resolve_type": "user", "format": "bool", "usage": "all" } ],
+ "PHASE_DUTY_CONFIG": [ { "value": "false", "resolve_type": "user", "format": "bool", "usage": "all" } ]
+ },
+ "model_parameters": {
+ "C_CLKOUT2_USED": [ { "value": "0", "resolve_type": "generated", "format": "long", "usage": "all" } ],
+ "C_USER_CLK_FREQ0": [ { "value": "100.0", "resolve_type": "generated", "format": "float", "usage": "all" } ],
+ "C_AUTO_PRIMITIVE": [ { "value": "MMCM", "resolve_type": "generated", "usage": "all" } ],
+ "C_USER_CLK_FREQ1": [ { "value": "100.0", "resolve_type": "generated", "format": "float", "usage": "all" } ],
+ "C_USER_CLK_FREQ2": [ { "value": "100.0", "resolve_type": "generated", "format": "float", "usage": "all" } ],
+ "C_USER_CLK_FREQ3": [ { "value": "100.0", "resolve_type": "generated", "format": "float", "usage": "all" } ],
+ "C_ENABLE_CLOCK_MONITOR": [ { "value": "0", "resolve_type": "generated", "format": "long", "usage": "all" } ],
+ "C_ENABLE_USER_CLOCK0": [ { "value": "0", "resolve_type": "generated", "format": "long", "usage": "all" } ],
+ "C_ENABLE_USER_CLOCK1": [ { "value": "0", "resolve_type": "generated", "format": "long", "usage": "all" } ],
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+ "C_Enable_PLL0": [ { "value": "0", "resolve_type": "generated", "format": "long", "usage": "all" } ],
+ "C_Enable_PLL1": [ { "value": "0", "resolve_type": "generated", "format": "long", "usage": "all" } ],
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+ "C_USE_CLKOUT1_BAR": [ { "value": "0", "resolve_type": "generated", "format": "long", "usage": "all" } ],
+ "C_USE_CLKOUT2_BAR": [ { "value": "0", "resolve_type": "generated", "format": "long", "usage": "all" } ],
+ "C_USE_CLKOUT3_BAR": [ { "value": "0", "resolve_type": "generated", "format": "long", "usage": "all" } ],
+ "C_USE_CLKOUT4_BAR": [ { "value": "0", "resolve_type": "generated", "format": "long", "usage": "all" } ],
+ "c_component_name": [ { "value": "clk_wiz_0", "resolve_type": "generated", "usage": "all" } ],
+ "C_PLATFORM": [ { "value": "UNKNOWN", "resolve_type": "generated", "usage": "all" } ],
+ "C_USE_FREQ_SYNTH": [ { "value": "1", "resolve_type": "generated", "format": "long", "usage": "all" } ],
+ "C_USE_PHASE_ALIGNMENT": [ { "value": "1", "resolve_type": "generated", "format": "long", "usage": "all" } ],
+ "C_PRIM_IN_JITTER": [ { "value": "0.010", "resolve_type": "generated", "format": "float", "usage": "all" } ],
+ "C_SECONDARY_IN_JITTER": [ { "value": "0.010", "resolve_type": "generated", "format": "float", "usage": "all" } ],
+ "C_JITTER_SEL": [ { "value": "No_Jitter", "resolve_type": "generated", "usage": "all" } ],
+ "C_USE_MIN_POWER": [ { "value": "0", "resolve_type": "generated", "format": "long", "usage": "all" } ],
+ "C_USE_MIN_O_JITTER": [ { "value": "0", "resolve_type": "generated", "format": "long", "usage": "all" } ],
+ "C_USE_MAX_I_JITTER": [ { "value": "0", "resolve_type": "generated", "format": "long", "usage": "all" } ],
+ "C_USE_DYN_PHASE_SHIFT": [ { "value": "0", "resolve_type": "generated", "format": "long", "usage": "all" } ],
+ "C_OPTIMIZE_CLOCKING_STRUCTURE_EN": [ { "value": "0", "resolve_type": "generated", "format": "long", "usage": "all" } ],
+ "C_USE_INCLK_SWITCHOVER": [ { "value": "0", "resolve_type": "generated", "format": "long", "usage": "all" } ],
+ "C_USE_DYN_RECONFIG": [ { "value": "0", "resolve_type": "generated", "format": "long", "usage": "all" } ],
+ "C_USE_SPREAD_SPECTRUM": [ { "value": "0", "resolve_type": "generated", "format": "long", "usage": "all" } ],
+ "C_USE_FAST_SIMULATION": [ { "value": "0", "resolve_type": "generated", "format": "long", "usage": "all" } ],
+ "C_PRIMTYPE_SEL": [ { "value": "AUTO", "resolve_type": "generated", "usage": "all" } ],
+ "C_USE_CLK_VALID": [ { "value": "0", "resolve_type": "generated", "format": "long", "usage": "all" } ],
+ "C_PRIM_IN_FREQ": [ { "value": "100.000", "resolve_type": "generated", "format": "float", "usage": "all" } ],
+ "C_PRIM_IN_TIMEPERIOD": [ { "value": "10.000", "resolve_type": "generated", "format": "float", "usage": "all" } ],
+ "C_IN_FREQ_UNITS": [ { "value": "Units_MHz", "resolve_type": "generated", "usage": "all" } ],
+ "C_SECONDARY_IN_FREQ": [ { "value": "100.000", "resolve_type": "generated", "format": "float", "usage": "all" } ],
+ "C_SECONDARY_IN_TIMEPERIOD": [ { "value": "10.000", "resolve_type": "generated", "format": "float", "usage": "all" } ],
+ "C_FEEDBACK_SOURCE": [ { "value": "FDBK_AUTO", "resolve_type": "generated", "usage": "all" } ],
+ "C_PRIM_SOURCE": [ { "value": "Single_ended_clock_capable_pin", "resolve_type": "generated", "usage": "all" } ],
+ "C_PHASESHIFT_MODE": [ { "value": "WAVEFORM", "resolve_type": "generated", "usage": "all" } ],
+ "C_SECONDARY_SOURCE": [ { "value": "Single_ended_clock_capable_pin", "resolve_type": "generated", "usage": "all" } ],
+ "C_CLKFB_IN_SIGNALING": [ { "value": "SINGLE", "resolve_type": "generated", "usage": "all" } ],
+ "C_USE_RESET": [ { "value": "1", "resolve_type": "generated", "format": "long", "usage": "all" } ],
+ "C_RESET_LOW": [ { "value": "1", "resolve_type": "generated", "format": "long", "usage": "all" } ],
+ "C_USE_LOCKED": [ { "value": "0", "resolve_type": "generated", "format": "long", "usage": "all" } ],
+ "C_USE_INCLK_STOPPED": [ { "value": "0", "resolve_type": "generated", "format": "long", "usage": "all" } ],
+ "C_USE_CLKFB_STOPPED": [ { "value": "0", "resolve_type": "generated", "format": "long", "usage": "all" } ],
+ "C_USE_POWER_DOWN": [ { "value": "0", "resolve_type": "generated", "format": "long", "usage": "all" } ],
+ "C_USE_STATUS": [ { "value": "0", "resolve_type": "generated", "format": "long", "usage": "all" } ],
+ "C_USE_FREEZE": [ { "value": "0", "resolve_type": "generated", "format": "long", "usage": "all" } ],
+ "C_NUM_OUT_CLKS": [ { "value": "1", "resolve_type": "generated", "format": "long", "usage": "all" } ],
+ "C_CLKOUT1_DRIVES": [ { "value": "BUFG", "resolve_type": "generated", "usage": "all" } ],
+ "C_CLKOUT2_DRIVES": [ { "value": "BUFG", "resolve_type": "generated", "usage": "all" } ],
+ "C_CLKOUT3_DRIVES": [ { "value": "BUFG", "resolve_type": "generated", "usage": "all" } ],
+ "C_CLKOUT4_DRIVES": [ { "value": "BUFG", "resolve_type": "generated", "usage": "all" } ],
+ "C_CLKOUT5_DRIVES": [ { "value": "BUFG", "resolve_type": "generated", "usage": "all" } ],
+ "C_CLKOUT6_DRIVES": [ { "value": "BUFG", "resolve_type": "generated", "usage": "all" } ],
+ "C_CLKOUT7_DRIVES": [ { "value": "BUFG", "resolve_type": "generated", "usage": "all" } ],
+ "C_INCLK_SUM_ROW0": [ { "value": "Input Clock Freq (MHz) Input Jitter (UI)", "resolve_type": "generated", "usage": "all" } ],
+ "C_INCLK_SUM_ROW1": [ { "value": "__primary_________100.000____________0.010", "resolve_type": "generated", "usage": "all" } ],
+ "C_INCLK_SUM_ROW2": [ { "value": "no_secondary_input_clock ", "resolve_type": "generated", "usage": "all" } ],
+ "C_OUTCLK_SUM_ROW0A": [ { "value": " Output Output Phase Duty Cycle Pk-to-Pk Phase", "resolve_type": "generated", "usage": "all" } ],
+ "C_OUTCLK_SUM_ROW0B": [ { "value": " Clock Freq (MHz) (degrees) (%) Jitter (ps) Error (ps)", "resolve_type": "generated", "usage": "all" } ],
+ "C_OUTCLK_SUM_ROW1": [ { "value": "clk_out1__25.00000______0.000______50.0______181.828____104.359", "resolve_type": "generated", "usage": "all" } ],
+ "C_OUTCLK_SUM_ROW2": [ { "value": "no_CLK_OUT2_output", "resolve_type": "generated", "usage": "all" } ],
+ "C_OUTCLK_SUM_ROW3": [ { "value": "no_CLK_OUT3_output", "resolve_type": "generated", "usage": "all" } ],
+ "C_OUTCLK_SUM_ROW4": [ { "value": "no_CLK_OUT4_output", "resolve_type": "generated", "usage": "all" } ],
+ "C_OUTCLK_SUM_ROW5": [ { "value": "no_CLK_OUT5_output", "resolve_type": "generated", "usage": "all" } ],
+ "C_OUTCLK_SUM_ROW6": [ { "value": "no_CLK_OUT6_output", "resolve_type": "generated", "usage": "all" } ],
+ "C_OUTCLK_SUM_ROW7": [ { "value": "no_CLK_OUT7_output", "resolve_type": "generated", "usage": "all" } ],
+ "C_CLKOUT1_REQUESTED_OUT_FREQ": [ { "value": "25", "resolve_type": "generated", "format": "float", "usage": "all" } ],
+ "C_CLKOUT2_REQUESTED_OUT_FREQ": [ { "value": "100.000", "resolve_type": "generated", "format": "float", "usage": "all" } ],
+ "C_CLKOUT3_REQUESTED_OUT_FREQ": [ { "value": "100.000", "resolve_type": "generated", "format": "float", "usage": "all" } ],
+ "C_CLKOUT4_REQUESTED_OUT_FREQ": [ { "value": "100.000", "resolve_type": "generated", "format": "float", "usage": "all" } ],
+ "C_CLKOUT5_REQUESTED_OUT_FREQ": [ { "value": "100.000", "resolve_type": "generated", "format": "float", "usage": "all" } ],
+ "C_CLKOUT6_REQUESTED_OUT_FREQ": [ { "value": "100.000", "resolve_type": "generated", "format": "float", "usage": "all" } ],
+ "C_CLKOUT7_REQUESTED_OUT_FREQ": [ { "value": "100.000", "resolve_type": "generated", "format": "float", "usage": "all" } ],
+ "C_CLKOUT1_REQUESTED_PHASE": [ { "value": "0.000", "resolve_type": "generated", "format": "float", "usage": "all" } ],
+ "C_CLKOUT2_REQUESTED_PHASE": [ { "value": "0.000", "resolve_type": "generated", "format": "float", "usage": "all" } ],
+ "C_CLKOUT3_REQUESTED_PHASE": [ { "value": "0.000", "resolve_type": "generated", "format": "float", "usage": "all" } ],
+ "C_CLKOUT4_REQUESTED_PHASE": [ { "value": "0.000", "resolve_type": "generated", "format": "float", "usage": "all" } ],
+ "C_CLKOUT5_REQUESTED_PHASE": [ { "value": "0.000", "resolve_type": "generated", "format": "float", "usage": "all" } ],
+ "C_CLKOUT6_REQUESTED_PHASE": [ { "value": "0.000", "resolve_type": "generated", "format": "float", "usage": "all" } ],
+ "C_CLKOUT7_REQUESTED_PHASE": [ { "value": "0.000", "resolve_type": "generated", "format": "float", "usage": "all" } ],
+ "C_CLKOUT1_REQUESTED_DUTY_CYCLE": [ { "value": "50.000", "resolve_type": "generated", "format": "float", "usage": "all" } ],
+ "C_CLKOUT2_REQUESTED_DUTY_CYCLE": [ { "value": "50.000", "resolve_type": "generated", "format": "float", "usage": "all" } ],
+ "C_CLKOUT3_REQUESTED_DUTY_CYCLE": [ { "value": "50.000", "resolve_type": "generated", "format": "float", "usage": "all" } ],
+ "C_CLKOUT4_REQUESTED_DUTY_CYCLE": [ { "value": "50.000", "resolve_type": "generated", "format": "float", "usage": "all" } ],
+ "C_CLKOUT5_REQUESTED_DUTY_CYCLE": [ { "value": "50.000", "resolve_type": "generated", "format": "float", "usage": "all" } ],
+ "C_CLKOUT6_REQUESTED_DUTY_CYCLE": [ { "value": "50.000", "resolve_type": "generated", "format": "float", "usage": "all" } ],
+ "C_CLKOUT7_REQUESTED_DUTY_CYCLE": [ { "value": "50.000", "resolve_type": "generated", "format": "float", "usage": "all" } ],
+ "C_CLKOUT1_OUT_FREQ": [ { "value": "25.00000", "resolve_type": "generated", "format": "float", "usage": "all" } ],
+ "C_CLKOUT2_OUT_FREQ": [ { "value": "100.000", "resolve_type": "generated", "format": "float", "usage": "all" } ],
+ "C_CLKOUT3_OUT_FREQ": [ { "value": "100.000", "resolve_type": "generated", "format": "float", "usage": "all" } ],
+ "C_CLKOUT4_OUT_FREQ": [ { "value": "100.000", "resolve_type": "generated", "format": "float", "usage": "all" } ],
+ "C_CLKOUT5_OUT_FREQ": [ { "value": "100.000", "resolve_type": "generated", "format": "float", "usage": "all" } ],
+ "C_CLKOUT6_OUT_FREQ": [ { "value": "100.000", "resolve_type": "generated", "format": "float", "usage": "all" } ],
+ "C_CLKOUT7_OUT_FREQ": [ { "value": "100.000", "resolve_type": "generated", "format": "float", "usage": "all" } ],
+ "C_CLKOUT1_PHASE": [ { "value": "0.000", "resolve_type": "generated", "format": "float", "usage": "all" } ],
+ "C_CLKOUT2_PHASE": [ { "value": "0.000", "resolve_type": "generated", "format": "float", "usage": "all" } ],
+ "C_CLKOUT3_PHASE": [ { "value": "0.000", "resolve_type": "generated", "format": "float", "usage": "all" } ],
+ "C_CLKOUT4_PHASE": [ { "value": "0.000", "resolve_type": "generated", "format": "float", "usage": "all" } ],
+ "C_CLKOUT5_PHASE": [ { "value": "0.000", "resolve_type": "generated", "format": "float", "usage": "all" } ],
+ "C_CLKOUT6_PHASE": [ { "value": "0.000", "resolve_type": "generated", "format": "float", "usage": "all" } ],
+ "C_CLKOUT7_PHASE": [ { "value": "0.000", "resolve_type": "generated", "format": "float", "usage": "all" } ],
+ "C_CLKOUT1_DUTY_CYCLE": [ { "value": "50.0", "resolve_type": "generated", "format": "float", "usage": "all" } ],
+ "C_CLKOUT2_DUTY_CYCLE": [ { "value": "50.000", "resolve_type": "generated", "format": "float", "usage": "all" } ],
+ "C_CLKOUT3_DUTY_CYCLE": [ { "value": "50.000", "resolve_type": "generated", "format": "float", "usage": "all" } ],
+ "C_CLKOUT4_DUTY_CYCLE": [ { "value": "50.000", "resolve_type": "generated", "format": "float", "usage": "all" } ],
+ "C_CLKOUT5_DUTY_CYCLE": [ { "value": "50.000", "resolve_type": "generated", "format": "float", "usage": "all" } ],
+ "C_CLKOUT6_DUTY_CYCLE": [ { "value": "50.000", "resolve_type": "generated", "format": "float", "usage": "all" } ],
+ "C_CLKOUT7_DUTY_CYCLE": [ { "value": "50.000", "resolve_type": "generated", "format": "float", "usage": "all" } ],
+ "C_USE_SAFE_CLOCK_STARTUP": [ { "value": "0", "resolve_type": "generated", "format": "long", "usage": "all" } ],
+ "C_USE_CLOCK_SEQUENCING": [ { "value": "0", "resolve_type": "generated", "format": "long", "usage": "all" } ],
+ "C_CLKOUT1_SEQUENCE_NUMBER": [ { "value": "1", "resolve_type": "generated", "format": "long", "usage": "all" } ],
+ "C_CLKOUT2_SEQUENCE_NUMBER": [ { "value": "1", "resolve_type": "generated", "format": "long", "usage": "all" } ],
+ "C_CLKOUT3_SEQUENCE_NUMBER": [ { "value": "1", "resolve_type": "generated", "format": "long", "usage": "all" } ],
+ "C_CLKOUT4_SEQUENCE_NUMBER": [ { "value": "1", "resolve_type": "generated", "format": "long", "usage": "all" } ],
+ "C_CLKOUT5_SEQUENCE_NUMBER": [ { "value": "1", "resolve_type": "generated", "format": "long", "usage": "all" } ],
+ "C_CLKOUT6_SEQUENCE_NUMBER": [ { "value": "1", "resolve_type": "generated", "format": "long", "usage": "all" } ],
+ "C_CLKOUT7_SEQUENCE_NUMBER": [ { "value": "1", "resolve_type": "generated", "format": "long", "usage": "all" } ],
+ "C_MMCM_NOTES": [ { "value": "None", "resolve_type": "generated", "usage": "all" } ],
+ "C_MMCM_BANDWIDTH": [ { "value": "OPTIMIZED", "resolve_type": "generated", "usage": "all" } ],
+ "C_MMCM_CLKFBOUT_MULT_F": [ { "value": "9.125", "resolve_type": "generated", "format": "float", "usage": "all" } ],
+ "C_MMCM_CLKIN1_PERIOD": [ { "value": "10.000", "resolve_type": "generated", "format": "float", "usage": "all" } ],
+ "C_MMCM_CLKIN2_PERIOD": [ { "value": "10.000", "resolve_type": "generated", "format": "float", "usage": "all" } ],
+ "C_MMCM_CLKOUT4_CASCADE": [ { "value": "FALSE", "resolve_type": "generated", "format": "bool", "usage": "all" } ],
+ "C_MMCM_CLOCK_HOLD": [ { "value": "FALSE", "resolve_type": "generated", "format": "bool", "usage": "all" } ],
+ "C_MMCM_COMPENSATION": [ { "value": "ZHOLD", "resolve_type": "generated", "usage": "all" } ],
+ "C_MMCM_DIVCLK_DIVIDE": [ { "value": "1", "resolve_type": "generated", "format": "long", "usage": "all" } ],
+ "C_MMCM_REF_JITTER1": [ { "value": "0.010", "resolve_type": "generated", "format": "float", "usage": "all" } ],
+ "C_MMCM_REF_JITTER2": [ { "value": "0.010", "resolve_type": "generated", "format": "float", "usage": "all" } ],
+ "C_MMCM_STARTUP_WAIT": [ { "value": "FALSE", "resolve_type": "generated", "usage": "all" } ],
+ "C_MMCM_CLKOUT0_DIVIDE_F": [ { "value": "36.500", "resolve_type": "generated", "format": "float", "usage": "all" } ],
+ "C_MMCM_CLKOUT1_DIVIDE": [ { "value": "1", "resolve_type": "generated", "format": "long", "usage": "all" } ],
+ "C_MMCM_CLKOUT2_DIVIDE": [ { "value": "1", "resolve_type": "generated", "format": "long", "usage": "all" } ],
+ "C_MMCM_CLKOUT3_DIVIDE": [ { "value": "1", "resolve_type": "generated", "format": "long", "usage": "all" } ],
+ "C_MMCM_CLKOUT4_DIVIDE": [ { "value": "1", "resolve_type": "generated", "format": "long", "usage": "all" } ],
+ "C_MMCM_CLKOUT5_DIVIDE": [ { "value": "1", "resolve_type": "generated", "format": "long", "usage": "all" } ],
+ "C_MMCM_CLKOUT6_DIVIDE": [ { "value": "1", "resolve_type": "generated", "format": "long", "usage": "all" } ],
+ "C_MMCM_CLKOUT0_DUTY_CYCLE": [ { "value": "0.500", "resolve_type": "generated", "format": "float", "usage": "all" } ],
+ "C_MMCM_CLKOUT1_DUTY_CYCLE": [ { "value": "0.500", "resolve_type": "generated", "format": "float", "usage": "all" } ],
+ "C_MMCM_CLKOUT2_DUTY_CYCLE": [ { "value": "0.500", "resolve_type": "generated", "format": "float", "usage": "all" } ],
+ "C_MMCM_CLKOUT3_DUTY_CYCLE": [ { "value": "0.500", "resolve_type": "generated", "format": "float", "usage": "all" } ],
+ "C_MMCM_CLKOUT4_DUTY_CYCLE": [ { "value": "0.500", "resolve_type": "generated", "format": "float", "usage": "all" } ],
+ "C_MMCM_CLKOUT5_DUTY_CYCLE": [ { "value": "0.500", "resolve_type": "generated", "format": "float", "usage": "all" } ],
+ "C_MMCM_CLKOUT6_DUTY_CYCLE": [ { "value": "0.500", "resolve_type": "generated", "format": "float", "usage": "all" } ],
+ "C_MMCM_CLKFBOUT_PHASE": [ { "value": "0.000", "resolve_type": "generated", "format": "float", "usage": "all" } ],
+ "C_MMCM_CLKOUT0_PHASE": [ { "value": "0.000", "resolve_type": "generated", "format": "float", "usage": "all" } ],
+ "C_MMCM_CLKOUT1_PHASE": [ { "value": "0.000", "resolve_type": "generated", "format": "float", "usage": "all" } ],
+ "C_MMCM_CLKOUT2_PHASE": [ { "value": "0.000", "resolve_type": "generated", "format": "float", "usage": "all" } ],
+ "C_MMCM_CLKOUT3_PHASE": [ { "value": "0.000", "resolve_type": "generated", "format": "float", "usage": "all" } ],
+ "C_MMCM_CLKOUT4_PHASE": [ { "value": "0.000", "resolve_type": "generated", "format": "float", "usage": "all" } ],
+ "C_MMCM_CLKOUT5_PHASE": [ { "value": "0.000", "resolve_type": "generated", "format": "float", "usage": "all" } ],
+ "C_MMCM_CLKOUT6_PHASE": [ { "value": "0.000", "resolve_type": "generated", "format": "float", "usage": "all" } ],
+ "C_MMCM_CLKFBOUT_USE_FINE_PS": [ { "value": "FALSE", "resolve_type": "generated", "usage": "all" } ],
+ "C_MMCM_CLKOUT0_USE_FINE_PS": [ { "value": "FALSE", "resolve_type": "generated", "usage": "all" } ],
+ "C_MMCM_CLKOUT1_USE_FINE_PS": [ { "value": "FALSE", "resolve_type": "generated", "usage": "all" } ],
+ "C_MMCM_CLKOUT2_USE_FINE_PS": [ { "value": "FALSE", "resolve_type": "generated", "usage": "all" } ],
+ "C_MMCM_CLKOUT3_USE_FINE_PS": [ { "value": "FALSE", "resolve_type": "generated", "usage": "all" } ],
+ "C_MMCM_CLKOUT4_USE_FINE_PS": [ { "value": "FALSE", "resolve_type": "generated", "usage": "all" } ],
+ "C_MMCM_CLKOUT5_USE_FINE_PS": [ { "value": "FALSE", "resolve_type": "generated", "usage": "all" } ],
+ "C_MMCM_CLKOUT6_USE_FINE_PS": [ { "value": "FALSE", "resolve_type": "generated", "usage": "all" } ],
+ "C_PLL_NOTES": [ { "value": "No notes", "resolve_type": "generated", "usage": "all" } ],
+ "C_PLL_BANDWIDTH": [ { "value": "OPTIMIZED", "resolve_type": "generated", "usage": "all" } ],
+ "C_PLL_CLK_FEEDBACK": [ { "value": "CLKFBOUT", "resolve_type": "generated", "usage": "all" } ],
+ "C_PLL_CLKFBOUT_MULT": [ { "value": "1", "resolve_type": "generated", "format": "long", "usage": "all" } ],
+ "C_PLL_CLKIN_PERIOD": [ { "value": "1.000", "resolve_type": "generated", "format": "float", "usage": "all" } ],
+ "C_PLL_COMPENSATION": [ { "value": "SYSTEM_SYNCHRONOUS", "resolve_type": "generated", "usage": "all" } ],
+ "C_PLL_DIVCLK_DIVIDE": [ { "value": "1", "resolve_type": "generated", "format": "long", "usage": "all" } ],
+ "C_PLL_REF_JITTER": [ { "value": "0.010", "resolve_type": "generated", "format": "float", "usage": "all" } ],
+ "C_PLL_CLKOUT0_DIVIDE": [ { "value": "1", "resolve_type": "generated", "format": "long", "usage": "all" } ],
+ "C_PLL_CLKOUT1_DIVIDE": [ { "value": "1", "resolve_type": "generated", "format": "long", "usage": "all" } ],
+ "C_PLL_CLKOUT2_DIVIDE": [ { "value": "1", "resolve_type": "generated", "format": "long", "usage": "all" } ],
+ "C_PLL_CLKOUT3_DIVIDE": [ { "value": "1", "resolve_type": "generated", "format": "long", "usage": "all" } ],
+ "C_PLL_CLKOUT4_DIVIDE": [ { "value": "1", "resolve_type": "generated", "format": "long", "usage": "all" } ],
+ "C_PLL_CLKOUT5_DIVIDE": [ { "value": "1", "resolve_type": "generated", "format": "long", "usage": "all" } ],
+ "C_PLL_CLKOUT0_DUTY_CYCLE": [ { "value": "0.500", "resolve_type": "generated", "format": "float", "usage": "all" } ],
+ "C_PLL_CLKOUT1_DUTY_CYCLE": [ { "value": "0.500", "resolve_type": "generated", "format": "float", "usage": "all" } ],
+ "C_PLL_CLKOUT2_DUTY_CYCLE": [ { "value": "0.500", "resolve_type": "generated", "format": "float", "usage": "all" } ],
+ "C_PLL_CLKOUT3_DUTY_CYCLE": [ { "value": "0.500", "resolve_type": "generated", "format": "float", "usage": "all" } ],
+ "C_PLL_CLKOUT4_DUTY_CYCLE": [ { "value": "0.500", "resolve_type": "generated", "format": "float", "usage": "all" } ],
+ "C_PLL_CLKOUT5_DUTY_CYCLE": [ { "value": "0.500", "resolve_type": "generated", "format": "float", "usage": "all" } ],
+ "C_PLL_CLKFBOUT_PHASE": [ { "value": "0.000", "resolve_type": "generated", "format": "float", "usage": "all" } ],
+ "C_PLL_CLKOUT0_PHASE": [ { "value": "0.000", "resolve_type": "generated", "format": "float", "usage": "all" } ],
+ "C_PLL_CLKOUT1_PHASE": [ { "value": "0.000", "resolve_type": "generated", "format": "float", "usage": "all" } ],
+ "C_PLL_CLKOUT2_PHASE": [ { "value": "0.000", "resolve_type": "generated", "format": "float", "usage": "all" } ],
+ "C_PLL_CLKOUT3_PHASE": [ { "value": "0.000", "resolve_type": "generated", "format": "float", "usage": "all" } ],
+ "C_PLL_CLKOUT4_PHASE": [ { "value": "0.000", "resolve_type": "generated", "format": "float", "usage": "all" } ],
+ "C_PLL_CLKOUT5_PHASE": [ { "value": "0.000", "resolve_type": "generated", "format": "float", "usage": "all" } ],
+ "C_CLOCK_MGR_TYPE": [ { "value": "NA", "resolve_type": "generated", "usage": "all" } ],
+ "C_OVERRIDE_MMCM": [ { "value": "0", "resolve_type": "generated", "format": "long", "usage": "all" } ],
+ "C_OVERRIDE_PLL": [ { "value": "0", "resolve_type": "generated", "format": "long", "usage": "all" } ],
+ "C_PRIMARY_PORT": [ { "value": "clk_in1", "resolve_type": "generated", "usage": "all" } ],
+ "C_SECONDARY_PORT": [ { "value": "clk_in2", "resolve_type": "generated", "usage": "all" } ],
+ "C_CLK_OUT1_PORT": [ { "value": "clk_out1", "resolve_type": "generated", "usage": "all" } ],
+ "C_CLK_OUT2_PORT": [ { "value": "clk_out2", "resolve_type": "generated", "usage": "all" } ],
+ "C_CLK_OUT3_PORT": [ { "value": "clk_out3", "resolve_type": "generated", "usage": "all" } ],
+ "C_CLK_OUT4_PORT": [ { "value": "clk_out4", "resolve_type": "generated", "usage": "all" } ],
+ "C_CLK_OUT5_PORT": [ { "value": "clk_out5", "resolve_type": "generated", "usage": "all" } ],
+ "C_CLK_OUT6_PORT": [ { "value": "clk_out6", "resolve_type": "generated", "usage": "all" } ],
+ "C_CLK_OUT7_PORT": [ { "value": "clk_out7", "resolve_type": "generated", "usage": "all" } ],
+ "C_RESET_PORT": [ { "value": "resetn", "resolve_type": "generated", "usage": "all" } ],
+ "C_LOCKED_PORT": [ { "value": "locked", "resolve_type": "generated", "usage": "all" } ],
+ "C_CLKFB_IN_PORT": [ { "value": "clkfb_in", "resolve_type": "generated", "usage": "all" } ],
+ "C_CLKFB_IN_P_PORT": [ { "value": "clkfb_in_p", "resolve_type": "generated", "usage": "all" } ],
+ "C_CLKFB_IN_N_PORT": [ { "value": "clkfb_in_n", "resolve_type": "generated", "usage": "all" } ],
+ "C_CLKFB_OUT_PORT": [ { "value": "clkfb_out", "resolve_type": "generated", "usage": "all" } ],
+ "C_CLKFB_OUT_P_PORT": [ { "value": "clkfb_out_p", "resolve_type": "generated", "usage": "all" } ],
+ "C_CLKFB_OUT_N_PORT": [ { "value": "clkfb_out_n", "resolve_type": "generated", "usage": "all" } ],
+ "C_POWER_DOWN_PORT": [ { "value": "power_down", "resolve_type": "generated", "usage": "all" } ],
+ "C_DADDR_PORT": [ { "value": "daddr", "resolve_type": "generated", "usage": "all" } ],
+ "C_DCLK_PORT": [ { "value": "dclk", "resolve_type": "generated", "usage": "all" } ],
+ "C_DRDY_PORT": [ { "value": "drdy", "resolve_type": "generated", "usage": "all" } ],
+ "C_DWE_PORT": [ { "value": "dwe", "resolve_type": "generated", "usage": "all" } ],
+ "C_DIN_PORT": [ { "value": "din", "resolve_type": "generated", "usage": "all" } ],
+ "C_DOUT_PORT": [ { "value": "dout", "resolve_type": "generated", "usage": "all" } ],
+ "C_DEN_PORT": [ { "value": "den", "resolve_type": "generated", "usage": "all" } ],
+ "C_PSCLK_PORT": [ { "value": "psclk", "resolve_type": "generated", "usage": "all" } ],
+ "C_PSEN_PORT": [ { "value": "psen", "resolve_type": "generated", "usage": "all" } ],
+ "C_PSINCDEC_PORT": [ { "value": "psincdec", "resolve_type": "generated", "usage": "all" } ],
+ "C_PSDONE_PORT": [ { "value": "psdone", "resolve_type": "generated", "usage": "all" } ],
+ "C_CLK_VALID_PORT": [ { "value": "CLK_VALID", "resolve_type": "generated", "usage": "all" } ],
+ "C_STATUS_PORT": [ { "value": "STATUS", "resolve_type": "generated", "usage": "all" } ],
+ "C_CLK_IN_SEL_PORT": [ { "value": "clk_in_sel", "resolve_type": "generated", "usage": "all" } ],
+ "C_INPUT_CLK_STOPPED_PORT": [ { "value": "input_clk_stopped", "resolve_type": "generated", "usage": "all" } ],
+ "C_CLKFB_STOPPED_PORT": [ { "value": "clkfb_stopped", "resolve_type": "generated", "usage": "all" } ],
+ "C_CLKIN1_JITTER_PS": [ { "value": "100.0", "resolve_type": "generated", "format": "float", "usage": "all" } ],
+ "C_CLKIN2_JITTER_PS": [ { "value": "100.0", "resolve_type": "generated", "format": "float", "usage": "all" } ],
+ "C_PRIMITIVE": [ { "value": "MMCM", "resolve_type": "generated", "usage": "all" } ],
+ "C_SS_MODE": [ { "value": "CENTER_HIGH", "resolve_type": "generated", "usage": "all" } ],
+ "C_SS_MOD_PERIOD": [ { "value": "4000", "resolve_type": "generated", "format": "long", "usage": "all" } ],
+ "C_SS_MOD_TIME": [ { "value": "0.004", "resolve_type": "generated", "format": "float", "usage": "all" } ],
+ "C_HAS_CDDC": [ { "value": "0", "resolve_type": "generated", "format": "long", "usage": "all" } ],
+ "C_CDDCDONE_PORT": [ { "value": "cddcdone", "resolve_type": "generated", "usage": "all" } ],
+ "C_CDDCREQ_PORT": [ { "value": "cddcreq", "resolve_type": "generated", "usage": "all" } ],
+ "C_CLKOUTPHY_MODE": [ { "value": "VCO", "resolve_type": "generated", "usage": "all" } ],
+ "C_ENABLE_CLKOUTPHY": [ { "value": "0", "resolve_type": "generated", "format": "long", "usage": "all" } ],
+ "C_INTERFACE_SELECTION": [ { "value": "0", "resolve_type": "generated", "format": "long", "usage": "all" } ],
+ "C_S_AXI_ADDR_WIDTH": [ { "value": "11", "resolve_type": "generated", "format": "long", "usage": "all" } ],
+ "C_S_AXI_DATA_WIDTH": [ { "value": "32", "resolve_type": "generated", "format": "long", "usage": "all" } ],
+ "C_POWER_REG": [ { "value": "0000", "resolve_type": "generated", "usage": "all" } ],
+ "C_CLKOUT0_1": [ { "value": "0000", "resolve_type": "generated", "usage": "all" } ],
+ "C_CLKOUT0_2": [ { "value": "0000", "resolve_type": "generated", "usage": "all" } ],
+ "C_CLKOUT1_1": [ { "value": "0000", "resolve_type": "generated", "usage": "all" } ],
+ "C_CLKOUT1_2": [ { "value": "0000", "resolve_type": "generated", "usage": "all" } ],
+ "C_CLKOUT2_1": [ { "value": "0000", "resolve_type": "generated", "usage": "all" } ],
+ "C_CLKOUT2_2": [ { "value": "0000", "resolve_type": "generated", "usage": "all" } ],
+ "C_CLKOUT3_1": [ { "value": "0000", "resolve_type": "generated", "usage": "all" } ],
+ "C_CLKOUT3_2": [ { "value": "0000", "resolve_type": "generated", "usage": "all" } ],
+ "C_CLKOUT4_1": [ { "value": "0000", "resolve_type": "generated", "usage": "all" } ],
+ "C_CLKOUT4_2": [ { "value": "0000", "resolve_type": "generated", "usage": "all" } ],
+ "C_CLKOUT5_1": [ { "value": "0000", "resolve_type": "generated", "usage": "all" } ],
+ "C_CLKOUT5_2": [ { "value": "0000", "resolve_type": "generated", "usage": "all" } ],
+ "C_CLKOUT6_1": [ { "value": "0000", "resolve_type": "generated", "usage": "all" } ],
+ "C_CLKOUT6_2": [ { "value": "0000", "resolve_type": "generated", "usage": "all" } ],
+ "C_CLKFBOUT_1": [ { "value": "0000", "resolve_type": "generated", "usage": "all" } ],
+ "C_CLKFBOUT_2": [ { "value": "0000", "resolve_type": "generated", "usage": "all" } ],
+ "C_DIVCLK": [ { "value": "0000", "resolve_type": "generated", "usage": "all" } ],
+ "C_LOCK_1": [ { "value": "0000", "resolve_type": "generated", "usage": "all" } ],
+ "C_LOCK_2": [ { "value": "0000", "resolve_type": "generated", "usage": "all" } ],
+ "C_LOCK_3": [ { "value": "0000", "resolve_type": "generated", "usage": "all" } ],
+ "C_FILTER_1": [ { "value": "0000", "resolve_type": "generated", "usage": "all" } ],
+ "C_FILTER_2": [ { "value": "0000", "resolve_type": "generated", "usage": "all" } ],
+ "C_DIVIDE1_AUTO": [ { "value": "1", "resolve_type": "generated", "usage": "all" } ],
+ "C_DIVIDE2_AUTO": [ { "value": "0.0273972602739726", "resolve_type": "generated", "usage": "all" } ],
+ "C_DIVIDE3_AUTO": [ { "value": "0.0273972602739726", "resolve_type": "generated", "usage": "all" } ],
+ "C_DIVIDE4_AUTO": [ { "value": "0.0273972602739726", "resolve_type": "generated", "usage": "all" } ],
+ "C_DIVIDE5_AUTO": [ { "value": "0.0273972602739726", "resolve_type": "generated", "usage": "all" } ],
+ "C_DIVIDE6_AUTO": [ { "value": "0.0273972602739726", "resolve_type": "generated", "usage": "all" } ],
+ "C_DIVIDE7_AUTO": [ { "value": "0.0273972602739726", "resolve_type": "generated", "usage": "all" } ],
+ "C_PLLBUFGCEDIV": [ { "value": "false", "resolve_type": "generated", "usage": "all" } ],
+ "C_MMCMBUFGCEDIV": [ { "value": "false", "resolve_type": "generated", "usage": "all" } ],
+ "C_PLLBUFGCEDIV1": [ { "value": "false", "resolve_type": "generated", "usage": "all" } ],
+ "C_PLLBUFGCEDIV2": [ { "value": "false", "resolve_type": "generated", "usage": "all" } ],
+ "C_PLLBUFGCEDIV3": [ { "value": "false", "resolve_type": "generated", "usage": "all" } ],
+ "C_PLLBUFGCEDIV4": [ { "value": "false", "resolve_type": "generated", "usage": "all" } ],
+ "C_MMCMBUFGCEDIV1": [ { "value": "false", "resolve_type": "generated", "usage": "all" } ],
+ "C_MMCMBUFGCEDIV2": [ { "value": "false", "resolve_type": "generated", "usage": "all" } ],
+ "C_MMCMBUFGCEDIV3": [ { "value": "false", "resolve_type": "generated", "usage": "all" } ],
+ "C_MMCMBUFGCEDIV4": [ { "value": "false", "resolve_type": "generated", "usage": "all" } ],
+ "C_MMCMBUFGCEDIV5": [ { "value": "false", "resolve_type": "generated", "usage": "all" } ],
+ "C_MMCMBUFGCEDIV6": [ { "value": "false", "resolve_type": "generated", "usage": "all" } ],
+ "C_MMCMBUFGCEDIV7": [ { "value": "false", "resolve_type": "generated", "usage": "all" } ],
+ "C_CLKOUT1_MATCHED_ROUTING": [ { "value": "false", "resolve_type": "generated", "usage": "all" } ],
+ "C_CLKOUT2_MATCHED_ROUTING": [ { "value": "false", "resolve_type": "generated", "usage": "all" } ],
+ "C_CLKOUT3_MATCHED_ROUTING": [ { "value": "false", "resolve_type": "generated", "usage": "all" } ],
+ "C_CLKOUT4_MATCHED_ROUTING": [ { "value": "false", "resolve_type": "generated", "usage": "all" } ],
+ "C_CLKOUT5_MATCHED_ROUTING": [ { "value": "false", "resolve_type": "generated", "usage": "all" } ],
+ "C_CLKOUT6_MATCHED_ROUTING": [ { "value": "false", "resolve_type": "generated", "usage": "all" } ],
+ "C_CLKOUT7_MATCHED_ROUTING": [ { "value": "false", "resolve_type": "generated", "usage": "all" } ],
+ "C_CLKOUT0_ACTUAL_FREQ": [ { "value": "25.00000", "resolve_type": "generated", "usage": "all" } ],
+ "C_CLKOUT1_ACTUAL_FREQ": [ { "value": "100.000", "resolve_type": "generated", "usage": "all" } ],
+ "C_CLKOUT2_ACTUAL_FREQ": [ { "value": "100.000", "resolve_type": "generated", "usage": "all" } ],
+ "C_CLKOUT3_ACTUAL_FREQ": [ { "value": "100.000", "resolve_type": "generated", "usage": "all" } ],
+ "C_CLKOUT4_ACTUAL_FREQ": [ { "value": "100.000", "resolve_type": "generated", "usage": "all" } ],
+ "C_CLKOUT5_ACTUAL_FREQ": [ { "value": "100.000", "resolve_type": "generated", "usage": "all" } ],
+ "C_CLKOUT6_ACTUAL_FREQ": [ { "value": "100.000", "resolve_type": "generated", "usage": "all" } ],
+ "C_M_MAX": [ { "value": "64.000", "resolve_type": "generated", "format": "float", "usage": "all" } ],
+ "C_M_MIN": [ { "value": "2.000", "resolve_type": "generated", "format": "float", "usage": "all" } ],
+ "C_D_MAX": [ { "value": "80.000", "resolve_type": "generated", "format": "float", "usage": "all" } ],
+ "C_D_MIN": [ { "value": "1.000", "resolve_type": "generated", "format": "float", "usage": "all" } ],
+ "C_O_MAX": [ { "value": "128.000", "resolve_type": "generated", "format": "float", "usage": "all" } ],
+ "C_O_MIN": [ { "value": "1.000", "resolve_type": "generated", "format": "float", "usage": "all" } ],
+ "C_VCO_MIN": [ { "value": "600.000", "resolve_type": "generated", "format": "float", "usage": "all" } ],
+ "C_VCO_MAX": [ { "value": "1200.000", "resolve_type": "generated", "format": "float", "usage": "all" } ]
+ },
+ "project_parameters": {
+ "ARCHITECTURE": [ { "value": "artix7" } ],
+ "BASE_BOARD_PART": [ { "value": "" } ],
+ "BOARD_CONNECTIONS": [ { "value": "" } ],
+ "DEVICE": [ { "value": "xc7a100t" } ],
+ "PACKAGE": [ { "value": "csg324" } ],
+ "PREFHDL": [ { "value": "VHDL" } ],
+ "SILICON_REVISION": [ { "value": "" } ],
+ "SIMULATOR_LANGUAGE": [ { "value": "VHDL" } ],
+ "SPEEDGRADE": [ { "value": "-1" } ],
+ "STATIC_POWER": [ { "value": "" } ],
+ "TEMPERATURE_GRADE": [ { "value": "" } ],
+ "USE_RDI_CUSTOMIZATION": [ { "value": "TRUE" } ],
+ "USE_RDI_GENERATION": [ { "value": "TRUE" } ]
+ },
+ "runtime_parameters": {
+ "IPCONTEXT": [ { "value": "IP_Flow" } ],
+ "IPREVISION": [ { "value": "11" } ],
+ "MANAGED": [ { "value": "TRUE" } ],
+ "OUTPUTDIR": [ { "value": "../../../../game.gen/sources_1/ip/clk_wiz_0" } ],
+ "SELECTEDSIMMODEL": [ { "value": "" } ],
+ "SHAREDDIR": [ { "value": "." } ],
+ "SWVERSION": [ { "value": "2022.2" } ],
+ "SYNTHESISFLOW": [ { "value": "OUT_OF_CONTEXT" } ]
+ }
+ },
+ "boundary": {
+ "ports": {
+ "resetn": [ { "direction": "in", "driver_value": "0" } ],
+ "clk_in1": [ { "direction": "in" } ],
+ "clk_out1": [ { "direction": "out" } ]
+ },
+ "interfaces": {
+ "resetn": {
+ "vlnv": "xilinx.com:signal:reset:1.0",
+ "abstraction_type": "xilinx.com:signal:reset_rtl:1.0",
+ "mode": "slave",
+ "parameters": {
+ "POLARITY": [ { "value": "ACTIVE_LOW", "value_src": "constant", "usage": "all" } ],
+ "BOARD.ASSOCIATED_PARAM": [ { "value": "RESET_BOARD_INTERFACE", "value_src": "constant", "usage": "all" } ],
+ "INSERT_VIP": [ { "value": "0", "resolve_type": "user", "format": "long", "usage": "simulation.rtl", "is_ips_inferred": true, "is_static_object": false } ]
+ },
+ "port_maps": {
+ "RST": [ { "physical_name": "resetn" } ]
+ }
+ },
+ "clock_CLK_IN1": {
+ "vlnv": "xilinx.com:signal:clock:1.0",
+ "abstraction_type": "xilinx.com:signal:clock_rtl:1.0",
+ "mode": "slave",
+ "parameters": {
+ "FREQ_HZ": [ { "value": "100000000", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
+ "FREQ_TOLERANCE_HZ": [ { "value": "0", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
+ "PHASE": [ { "value": "0.0", "resolve_type": "generated", "format": "float", "is_ips_inferred": true, "is_static_object": false } ],
+ "CLK_DOMAIN": [ { "value": "", "resolve_type": "generated", "is_ips_inferred": true, "is_static_object": false } ],
+ "ASSOCIATED_BUSIF": [ { "value": "", "resolve_type": "generated", "is_ips_inferred": true, "is_static_object": false } ],
+ "ASSOCIATED_PORT": [ { "value": "", "resolve_type": "generated", "is_ips_inferred": true, "is_static_object": false } ],
+ "ASSOCIATED_RESET": [ { "value": "", "resolve_type": "generated", "is_ips_inferred": true, "is_static_object": false } ],
+ "INSERT_VIP": [ { "value": "0", "resolve_type": "user", "format": "long", "usage": "simulation.rtl", "is_ips_inferred": true, "is_static_object": false } ],
+ "BOARD.ASSOCIATED_PARAM": [ { "value": "CLK_IN1_BOARD_INTERFACE", "usage": "all", "is_static_object": false } ]
+ },
+ "port_maps": {
+ "CLK_IN1": [ { "physical_name": "clk_in1" } ]
+ }
+ },
+ "clock_CLK_OUT1": {
+ "vlnv": "xilinx.com:signal:clock:1.0",
+ "abstraction_type": "xilinx.com:signal:clock_rtl:1.0",
+ "mode": "master",
+ "parameters": {
+ "FREQ_HZ": [ { "value": "100000000", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
+ "FREQ_TOLERANCE_HZ": [ { "value": "0", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
+ "PHASE": [ { "value": "0.0", "resolve_type": "generated", "format": "float", "is_ips_inferred": true, "is_static_object": false } ],
+ "CLK_DOMAIN": [ { "value": "", "resolve_type": "generated", "is_ips_inferred": true, "is_static_object": false } ],
+ "ASSOCIATED_BUSIF": [ { "value": "", "resolve_type": "generated", "is_ips_inferred": true, "is_static_object": false } ],
+ "ASSOCIATED_PORT": [ { "value": "", "resolve_type": "generated", "is_ips_inferred": true, "is_static_object": false } ],
+ "ASSOCIATED_RESET": [ { "value": "", "resolve_type": "generated", "is_ips_inferred": true, "is_static_object": false } ],
+ "INSERT_VIP": [ { "value": "0", "resolve_type": "user", "format": "long", "usage": "simulation.rtl", "is_ips_inferred": true, "is_static_object": false } ]
+ },
+ "port_maps": {
+ "CLK_OUT1": [ { "physical_name": "clk_out1" } ]
+ }
+ }
+ }
+ }
+ }
+}
\ No newline at end of file
diff --git a/game.srcs/sources_1/ip/clk_wiz_1/clk_wiz_1.xci b/game.srcs/sources_1/ip/clk_wiz_1/clk_wiz_1.xci
new file mode 100644
index 0000000000000000000000000000000000000000..09d70b9a325dcef773c6ed84d60e44f3cd1fefd5
--- /dev/null
+++ b/game.srcs/sources_1/ip/clk_wiz_1/clk_wiz_1.xci
@@ -0,0 +1,671 @@
+{
+ "schema": "xilinx.com:schema:json_instance:1.0",
+ "ip_inst": {
+ "xci_name": "clk_wiz_1",
+ "component_reference": "xilinx.com:ip:clk_wiz:6.0",
+ "ip_revision": "11",
+ "gen_directory": "../../../../game.gen/sources_1/ip/clk_wiz_1",
+ "parameters": {
+ "component_parameters": {
+ "Component_Name": [ { "value": "clk_wiz_1", "resolve_type": "user", "usage": "all" } ],
+ "USER_CLK_FREQ0": [ { "value": "100.0", "resolve_type": "user", "format": "float", "usage": "all" } ],
+ "USER_CLK_FREQ1": [ { "value": "100.0", "resolve_type": "user", "format": "float", "usage": "all" } ],
+ "USER_CLK_FREQ2": [ { "value": "100.0", "resolve_type": "user", "format": "float", "usage": "all" } ],
+ "USER_CLK_FREQ3": [ { "value": "100.0", "resolve_type": "user", "format": "float", "usage": "all" } ],
+ "ENABLE_CLOCK_MONITOR": [ { "value": "false", "resolve_type": "user", "format": "bool", "usage": "all" } ],
+ "OPTIMIZE_CLOCKING_STRUCTURE_EN": [ { "value": "false", "resolve_type": "user", "format": "bool", "usage": "all" } ],
+ "ENABLE_USER_CLOCK0": [ { "value": "false", "resolve_type": "user", "format": "bool", "usage": "all" } ],
+ "ENABLE_USER_CLOCK1": [ { "value": "false", "resolve_type": "user", "format": "bool", "usage": "all" } ],
+ "ENABLE_USER_CLOCK2": [ { "value": "false", "resolve_type": "user", "format": "bool", "usage": "all" } ],
+ "ENABLE_USER_CLOCK3": [ { "value": "false", "resolve_type": "user", "format": "bool", "usage": "all" } ],
+ "Enable_PLL0": [ { "value": "false", "resolve_type": "user", "format": "bool", "usage": "all" } ],
+ "Enable_PLL1": [ { "value": "false", "resolve_type": "user", "format": "bool", "usage": "all" } ],
+ "REF_CLK_FREQ": [ { "value": "100.0", "resolve_type": "user", "format": "float", "usage": "all" } ],
+ "PRECISION": [ { "value": "1", "resolve_type": "user", "format": "float", "usage": "all" } ],
+ "PRIMITIVE": [ { "value": "MMCM", "resolve_type": "user", "usage": "all" } ],
+ "PRIMTYPE_SEL": [ { "value": "mmcm_adv", "resolve_type": "user", "usage": "all" } ],
+ "CLOCK_MGR_TYPE": [ { "value": "auto", "resolve_type": "user", "usage": "all" } ],
+ "USE_FREQ_SYNTH": [ { "value": "true", "resolve_type": "user", "format": "bool", "usage": "all" } ],
+ "USE_SPREAD_SPECTRUM": [ { "value": "false", "resolve_type": "user", "format": "bool", "usage": "all" } ],
+ "USE_PHASE_ALIGNMENT": [ { "value": "true", "resolve_type": "user", "format": "bool", "usage": "all" } ],
+ "USE_MIN_POWER": [ { "value": "false", "resolve_type": "user", "format": "bool", "usage": "all" } ],
+ "USE_DYN_PHASE_SHIFT": [ { "value": "false", "resolve_type": "user", "format": "bool", "usage": "all" } ],
+ "USE_DYN_RECONFIG": [ { "value": "false", "resolve_type": "user", "format": "bool", "usage": "all" } ],
+ "JITTER_SEL": [ { "value": "No_Jitter", "resolve_type": "user", "usage": "all" } ],
+ "PRIM_IN_FREQ": [ { "value": "100.000", "resolve_type": "user", "format": "float", "usage": "all" } ],
+ "PRIM_IN_TIMEPERIOD": [ { "value": "10.000", "resolve_type": "user", "format": "float", "usage": "all" } ],
+ "IN_FREQ_UNITS": [ { "value": "Units_MHz", "resolve_type": "user", "usage": "all" } ],
+ "PHASESHIFT_MODE": [ { "value": "WAVEFORM", "resolve_type": "user", "usage": "all" } ],
+ "IN_JITTER_UNITS": [ { "value": "Units_UI", "resolve_type": "user", "usage": "all" } ],
+ "RELATIVE_INCLK": [ { "value": "REL_PRIMARY", "resolve_type": "user", "usage": "all" } ],
+ "USE_INCLK_SWITCHOVER": [ { "value": "false", "resolve_type": "user", "format": "bool", "usage": "all" } ],
+ "SECONDARY_IN_FREQ": [ { "value": "100.000", "resolve_type": "user", "format": "float", "usage": "all" } ],
+ "SECONDARY_IN_TIMEPERIOD": [ { "value": "10.000", "resolve_type": "user", "format": "float", "usage": "all" } ],
+ "SECONDARY_PORT": [ { "value": "clk_in2", "resolve_type": "user", "usage": "all" } ],
+ "SECONDARY_SOURCE": [ { "value": "Single_ended_clock_capable_pin", "resolve_type": "user", "usage": "all" } ],
+ "JITTER_OPTIONS": [ { "value": "UI", "resolve_type": "user", "usage": "all" } ],
+ "CLKIN1_UI_JITTER": [ { "value": "0.010", "resolve_type": "user", "format": "float", "usage": "all" } ],
+ "CLKIN2_UI_JITTER": [ { "value": "0.010", "resolve_type": "user", "format": "float", "usage": "all" } ],
+ "PRIM_IN_JITTER": [ { "value": "0.010", "resolve_type": "user", "format": "float", "usage": "all" } ],
+ "SECONDARY_IN_JITTER": [ { "value": "0.010", "resolve_type": "user", "format": "float", "usage": "all" } ],
+ "CLKIN1_JITTER_PS": [ { "value": "100.0", "resolve_type": "user", "format": "float", "usage": "all" } ],
+ "CLKIN2_JITTER_PS": [ { "value": "100.0", "resolve_type": "user", "format": "float", "usage": "all" } ],
+ "CLKOUT1_USED": [ { "value": "true", "resolve_type": "user", "format": "bool", "usage": "all" } ],
+ "CLKOUT2_USED": [ { "value": "false", "resolve_type": "user", "format": "bool", "usage": "all" } ],
+ "CLKOUT3_USED": [ { "value": "false", "resolve_type": "user", "format": "bool", "usage": "all" } ],
+ "CLKOUT4_USED": [ { "value": "false", "resolve_type": "user", "format": "bool", "usage": "all" } ],
+ "CLKOUT5_USED": [ { "value": "false", "resolve_type": "user", "format": "bool", "usage": "all" } ],
+ "CLKOUT6_USED": [ { "value": "false", "resolve_type": "user", "format": "bool", "usage": "all" } ],
+ "CLKOUT7_USED": [ { "value": "false", "resolve_type": "user", "format": "bool", "usage": "all" } ],
+ "NUM_OUT_CLKS": [ { "value": "1", "resolve_type": "user", "format": "long", "usage": "all" } ],
+ "CLK_OUT1_USE_FINE_PS_GUI": [ { "value": "false", "resolve_type": "user", "format": "bool", "usage": "all" } ],
+ "CLK_OUT2_USE_FINE_PS_GUI": [ { "value": "false", "resolve_type": "user", "format": "bool", "usage": "all" } ],
+ "CLK_OUT3_USE_FINE_PS_GUI": [ { "value": "false", "resolve_type": "user", "format": "bool", "usage": "all" } ],
+ "CLK_OUT4_USE_FINE_PS_GUI": [ { "value": "false", "resolve_type": "user", "format": "bool", "usage": "all" } ],
+ "CLK_OUT5_USE_FINE_PS_GUI": [ { "value": "false", "resolve_type": "user", "format": "bool", "usage": "all" } ],
+ "CLK_OUT6_USE_FINE_PS_GUI": [ { "value": "false", "resolve_type": "user", "format": "bool", "usage": "all" } ],
+ "CLK_OUT7_USE_FINE_PS_GUI": [ { "value": "false", "resolve_type": "user", "format": "bool", "usage": "all" } ],
+ "PRIMARY_PORT": [ { "value": "clk_in1", "resolve_type": "user", "usage": "all" } ],
+ "CLK_OUT1_PORT": [ { "value": "clk_out1", "resolve_type": "user", "usage": "all" } ],
+ "CLK_OUT2_PORT": [ { "value": "clk_out2", "resolve_type": "user", "usage": "all" } ],
+ "CLK_OUT3_PORT": [ { "value": "clk_out3", "resolve_type": "user", "usage": "all" } ],
+ "CLK_OUT4_PORT": [ { "value": "clk_out4", "resolve_type": "user", "usage": "all" } ],
+ "CLK_OUT5_PORT": [ { "value": "clk_out5", "resolve_type": "user", "usage": "all" } ],
+ "CLK_OUT6_PORT": [ { "value": "clk_out6", "resolve_type": "user", "usage": "all" } ],
+ "CLK_OUT7_PORT": [ { "value": "clk_out7", "resolve_type": "user", "usage": "all" } ],
+ "DADDR_PORT": [ { "value": "daddr", "resolve_type": "user", "usage": "all" } ],
+ "DCLK_PORT": [ { "value": "dclk", "resolve_type": "user", "usage": "all" } ],
+ "DRDY_PORT": [ { "value": "drdy", "resolve_type": "user", "usage": "all" } ],
+ "DWE_PORT": [ { "value": "dwe", "resolve_type": "user", "usage": "all" } ],
+ "DIN_PORT": [ { "value": "din", "resolve_type": "user", "usage": "all" } ],
+ "DOUT_PORT": [ { "value": "dout", "resolve_type": "user", "usage": "all" } ],
+ "DEN_PORT": [ { "value": "den", "resolve_type": "user", "usage": "all" } ],
+ "PSCLK_PORT": [ { "value": "psclk", "resolve_type": "user", "usage": "all" } ],
+ "PSEN_PORT": [ { "value": "psen", "resolve_type": "user", "usage": "all" } ],
+ "PSINCDEC_PORT": [ { "value": "psincdec", "resolve_type": "user", "usage": "all" } ],
+ "PSDONE_PORT": [ { "value": "psdone", "resolve_type": "user", "usage": "all" } ],
+ "CLKOUT1_REQUESTED_OUT_FREQ": [ { "value": "25.000", "value_src": "user", "resolve_type": "user", "format": "float", "usage": "all" } ],
+ "CLKOUT1_REQUESTED_PHASE": [ { "value": "0.000", "resolve_type": "user", "format": "float", "usage": "all" } ],
+ "CLKOUT1_REQUESTED_DUTY_CYCLE": [ { "value": "50.000", "resolve_type": "user", "format": "float", "usage": "all" } ],
+ "CLKOUT2_REQUESTED_OUT_FREQ": [ { "value": "100.000", "resolve_type": "user", "format": "float", "usage": "all" } ],
+ "CLKOUT2_REQUESTED_PHASE": [ { "value": "0.000", "resolve_type": "user", "format": "float", "usage": "all" } ],
+ "CLKOUT2_REQUESTED_DUTY_CYCLE": [ { "value": "50.000", "resolve_type": "user", "format": "float", "usage": "all" } ],
+ "CLKOUT3_REQUESTED_OUT_FREQ": [ { "value": "100.000", "resolve_type": "user", "format": "float", "usage": "all" } ],
+ "CLKOUT3_REQUESTED_PHASE": [ { "value": "0.000", "resolve_type": "user", "format": "float", "usage": "all" } ],
+ "CLKOUT3_REQUESTED_DUTY_CYCLE": [ { "value": "50.000", "resolve_type": "user", "format": "float", "usage": "all" } ],
+ "CLKOUT4_REQUESTED_OUT_FREQ": [ { "value": "100.000", "resolve_type": "user", "format": "float", "usage": "all" } ],
+ "CLKOUT4_REQUESTED_PHASE": [ { "value": "0.000", "resolve_type": "user", "format": "float", "usage": "all" } ],
+ "CLKOUT4_REQUESTED_DUTY_CYCLE": [ { "value": "50.000", "resolve_type": "user", "format": "float", "usage": "all" } ],
+ "CLKOUT5_REQUESTED_OUT_FREQ": [ { "value": "100.000", "resolve_type": "user", "format": "float", "usage": "all" } ],
+ "CLKOUT5_REQUESTED_PHASE": [ { "value": "0.000", "resolve_type": "user", "format": "float", "usage": "all" } ],
+ "CLKOUT5_REQUESTED_DUTY_CYCLE": [ { "value": "50.000", "resolve_type": "user", "format": "float", "usage": "all" } ],
+ "CLKOUT6_REQUESTED_OUT_FREQ": [ { "value": "100.000", "resolve_type": "user", "format": "float", "usage": "all" } ],
+ "CLKOUT6_REQUESTED_PHASE": [ { "value": "0.000", "resolve_type": "user", "format": "float", "usage": "all" } ],
+ "CLKOUT6_REQUESTED_DUTY_CYCLE": [ { "value": "50.000", "resolve_type": "user", "format": "float", "usage": "all" } ],
+ "CLKOUT7_REQUESTED_OUT_FREQ": [ { "value": "100.000", "resolve_type": "user", "format": "float", "usage": "all" } ],
+ "CLKOUT7_REQUESTED_PHASE": [ { "value": "0.000", "resolve_type": "user", "format": "float", "usage": "all" } ],
+ "CLKOUT7_REQUESTED_DUTY_CYCLE": [ { "value": "50.000", "resolve_type": "user", "format": "float", "usage": "all" } ],
+ "USE_MAX_I_JITTER": [ { "value": "false", "resolve_type": "user", "format": "bool", "usage": "all" } ],
+ "USE_MIN_O_JITTER": [ { "value": "false", "resolve_type": "user", "format": "bool", "usage": "all" } ],
+ "CLKOUT1_MATCHED_ROUTING": [ { "value": "false", "resolve_type": "user", "format": "bool", "usage": "all" } ],
+ "CLKOUT2_MATCHED_ROUTING": [ { "value": "false", "resolve_type": "user", "format": "bool", "usage": "all" } ],
+ "CLKOUT3_MATCHED_ROUTING": [ { "value": "false", "resolve_type": "user", "format": "bool", "usage": "all" } ],
+ "CLKOUT4_MATCHED_ROUTING": [ { "value": "false", "resolve_type": "user", "format": "bool", "usage": "all" } ],
+ "CLKOUT5_MATCHED_ROUTING": [ { "value": "false", "resolve_type": "user", "format": "bool", "usage": "all" } ],
+ "CLKOUT6_MATCHED_ROUTING": [ { "value": "false", "resolve_type": "user", "format": "bool", "usage": "all" } ],
+ "CLKOUT7_MATCHED_ROUTING": [ { "value": "false", "resolve_type": "user", "format": "bool", "usage": "all" } ],
+ "PRIM_SOURCE": [ { "value": "Single_ended_clock_capable_pin", "resolve_type": "user", "usage": "all" } ],
+ "CLKOUT1_DRIVES": [ { "value": "BUFG", "resolve_type": "user", "usage": "all" } ],
+ "CLKOUT2_DRIVES": [ { "value": "BUFG", "resolve_type": "user", "usage": "all" } ],
+ "CLKOUT3_DRIVES": [ { "value": "BUFG", "resolve_type": "user", "usage": "all" } ],
+ "CLKOUT4_DRIVES": [ { "value": "BUFG", "resolve_type": "user", "usage": "all" } ],
+ "CLKOUT5_DRIVES": [ { "value": "BUFG", "resolve_type": "user", "usage": "all" } ],
+ "CLKOUT6_DRIVES": [ { "value": "BUFG", "resolve_type": "user", "usage": "all" } ],
+ "CLKOUT7_DRIVES": [ { "value": "BUFG", "resolve_type": "user", "usage": "all" } ],
+ "FEEDBACK_SOURCE": [ { "value": "FDBK_AUTO", "resolve_type": "user", "usage": "all" } ],
+ "CLKFB_IN_SIGNALING": [ { "value": "SINGLE", "resolve_type": "user", "usage": "all" } ],
+ "CLKFB_IN_PORT": [ { "value": "clkfb_in", "resolve_type": "user", "usage": "all" } ],
+ "CLKFB_IN_P_PORT": [ { "value": "clkfb_in_p", "resolve_type": "user", "usage": "all" } ],
+ "CLKFB_IN_N_PORT": [ { "value": "clkfb_in_n", "resolve_type": "user", "usage": "all" } ],
+ "CLKFB_OUT_PORT": [ { "value": "clkfb_out", "resolve_type": "user", "usage": "all" } ],
+ "CLKFB_OUT_P_PORT": [ { "value": "clkfb_out_p", "resolve_type": "user", "usage": "all" } ],
+ "CLKFB_OUT_N_PORT": [ { "value": "clkfb_out_n", "resolve_type": "user", "usage": "all" } ],
+ "PLATFORM": [ { "value": "UNKNOWN", "resolve_type": "user", "usage": "all" } ],
+ "SUMMARY_STRINGS": [ { "value": "empty", "resolve_type": "user", "usage": "all" } ],
+ "USE_LOCKED": [ { "value": "false", "value_src": "user", "resolve_type": "user", "format": "bool", "usage": "all" } ],
+ "CALC_DONE": [ { "value": "empty", "resolve_type": "user", "usage": "all" } ],
+ "USE_RESET": [ { "value": "true", "resolve_type": "user", "format": "bool", "usage": "all" } ],
+ "USE_POWER_DOWN": [ { "value": "false", "resolve_type": "user", "format": "bool", "usage": "all" } ],
+ "USE_STATUS": [ { "value": "false", "resolve_type": "user", "format": "bool", "usage": "all" } ],
+ "USE_FREEZE": [ { "value": "false", "resolve_type": "user", "format": "bool", "usage": "all" } ],
+ "USE_CLK_VALID": [ { "value": "false", "resolve_type": "user", "format": "bool", "usage": "all" } ],
+ "USE_INCLK_STOPPED": [ { "value": "false", "resolve_type": "user", "format": "bool", "usage": "all" } ],
+ "USE_CLKFB_STOPPED": [ { "value": "false", "resolve_type": "user", "format": "bool", "usage": "all" } ],
+ "RESET_PORT": [ { "value": "resetn", "value_src": "user", "resolve_type": "user", "usage": "all" } ],
+ "LOCKED_PORT": [ { "value": "locked", "resolve_type": "user", "usage": "all" } ],
+ "POWER_DOWN_PORT": [ { "value": "power_down", "resolve_type": "user", "usage": "all" } ],
+ "CLK_VALID_PORT": [ { "value": "CLK_VALID", "resolve_type": "user", "usage": "all" } ],
+ "STATUS_PORT": [ { "value": "STATUS", "resolve_type": "user", "usage": "all" } ],
+ "CLK_IN_SEL_PORT": [ { "value": "clk_in_sel", "resolve_type": "user", "usage": "all" } ],
+ "INPUT_CLK_STOPPED_PORT": [ { "value": "input_clk_stopped", "resolve_type": "user", "usage": "all" } ],
+ "CLKFB_STOPPED_PORT": [ { "value": "clkfb_stopped", "resolve_type": "user", "usage": "all" } ],
+ "SS_MODE": [ { "value": "CENTER_HIGH", "resolve_type": "user", "usage": "all" } ],
+ "SS_MOD_FREQ": [ { "value": "250", "resolve_type": "user", "format": "float", "usage": "all" } ],
+ "SS_MOD_TIME": [ { "value": "0.004", "resolve_type": "user", "format": "float", "usage": "all" } ],
+ "OVERRIDE_MMCM": [ { "value": "false", "resolve_type": "user", "format": "bool", "usage": "all" } ],
+ "MMCM_NOTES": [ { "value": "None", "resolve_type": "user", "usage": "all" } ],
+ "MMCM_DIVCLK_DIVIDE": [ { "value": "1", "resolve_type": "user", "format": "long", "usage": "all" } ],
+ "MMCM_BANDWIDTH": [ { "value": "OPTIMIZED", "resolve_type": "user", "usage": "all" } ],
+ "MMCM_CLKFBOUT_MULT_F": [ { "value": "9.125", "value_src": "user", "resolve_type": "user", "format": "float", "usage": "all" } ],
+ "MMCM_CLKFBOUT_PHASE": [ { "value": "0.000", "resolve_type": "user", "format": "float", "usage": "all" } ],
+ "MMCM_CLKFBOUT_USE_FINE_PS": [ { "value": "false", "resolve_type": "user", "format": "bool", "usage": "all" } ],
+ "MMCM_CLKIN1_PERIOD": [ { "value": "10.000", "resolve_type": "user", "format": "float", "usage": "all" } ],
+ "MMCM_CLKIN2_PERIOD": [ { "value": "10.000", "resolve_type": "user", "format": "float", "usage": "all" } ],
+ "MMCM_CLKOUT4_CASCADE": [ { "value": "false", "resolve_type": "user", "format": "bool", "usage": "all" } ],
+ "MMCM_CLOCK_HOLD": [ { "value": "false", "resolve_type": "user", "format": "bool", "usage": "all" } ],
+ "MMCM_COMPENSATION": [ { "value": "ZHOLD", "resolve_type": "user", "usage": "all" } ],
+ "MMCM_REF_JITTER1": [ { "value": "0.010", "resolve_type": "user", "format": "float", "usage": "all" } ],
+ "MMCM_REF_JITTER2": [ { "value": "0.010", "resolve_type": "user", "format": "float", "usage": "all" } ],
+ "MMCM_STARTUP_WAIT": [ { "value": "false", "resolve_type": "user", "format": "bool", "usage": "all" } ],
+ "MMCM_CLKOUT0_DIVIDE_F": [ { "value": "36.500", "value_src": "user", "resolve_type": "user", "format": "float", "usage": "all" } ],
+ "MMCM_CLKOUT0_DUTY_CYCLE": [ { "value": "0.500", "resolve_type": "user", "format": "float", "usage": "all" } ],
+ "MMCM_CLKOUT0_PHASE": [ { "value": "0.000", "resolve_type": "user", "format": "float", "usage": "all" } ],
+ "MMCM_CLKOUT0_USE_FINE_PS": [ { "value": "false", "resolve_type": "user", "format": "bool", "usage": "all" } ],
+ "MMCM_CLKOUT1_DIVIDE": [ { "value": "1", "resolve_type": "user", "format": "long", "usage": "all" } ],
+ "MMCM_CLKOUT1_DUTY_CYCLE": [ { "value": "0.500", "resolve_type": "user", "format": "float", "usage": "all" } ],
+ "MMCM_CLKOUT1_PHASE": [ { "value": "0.000", "resolve_type": "user", "format": "float", "usage": "all" } ],
+ "MMCM_CLKOUT1_USE_FINE_PS": [ { "value": "false", "resolve_type": "user", "format": "bool", "usage": "all" } ],
+ "MMCM_CLKOUT2_DIVIDE": [ { "value": "1", "resolve_type": "user", "format": "long", "usage": "all" } ],
+ "MMCM_CLKOUT2_DUTY_CYCLE": [ { "value": "0.500", "resolve_type": "user", "format": "float", "usage": "all" } ],
+ "MMCM_CLKOUT2_PHASE": [ { "value": "0.000", "resolve_type": "user", "format": "float", "usage": "all" } ],
+ "MMCM_CLKOUT2_USE_FINE_PS": [ { "value": "false", "resolve_type": "user", "format": "bool", "usage": "all" } ],
+ "MMCM_CLKOUT3_DIVIDE": [ { "value": "1", "resolve_type": "user", "format": "long", "usage": "all" } ],
+ "MMCM_CLKOUT3_DUTY_CYCLE": [ { "value": "0.500", "resolve_type": "user", "format": "float", "usage": "all" } ],
+ "MMCM_CLKOUT3_PHASE": [ { "value": "0.000", "resolve_type": "user", "format": "float", "usage": "all" } ],
+ "MMCM_CLKOUT3_USE_FINE_PS": [ { "value": "false", "resolve_type": "user", "format": "bool", "usage": "all" } ],
+ "MMCM_CLKOUT4_DIVIDE": [ { "value": "1", "resolve_type": "user", "format": "long", "usage": "all" } ],
+ "MMCM_CLKOUT4_DUTY_CYCLE": [ { "value": "0.500", "resolve_type": "user", "format": "float", "usage": "all" } ],
+ "MMCM_CLKOUT4_PHASE": [ { "value": "0.000", "resolve_type": "user", "format": "float", "usage": "all" } ],
+ "MMCM_CLKOUT4_USE_FINE_PS": [ { "value": "false", "resolve_type": "user", "format": "bool", "usage": "all" } ],
+ "MMCM_CLKOUT5_DIVIDE": [ { "value": "1", "resolve_type": "user", "format": "long", "usage": "all" } ],
+ "MMCM_CLKOUT5_DUTY_CYCLE": [ { "value": "0.500", "resolve_type": "user", "format": "float", "usage": "all" } ],
+ "MMCM_CLKOUT5_PHASE": [ { "value": "0.000", "resolve_type": "user", "format": "float", "usage": "all" } ],
+ "MMCM_CLKOUT5_USE_FINE_PS": [ { "value": "false", "resolve_type": "user", "format": "bool", "usage": "all" } ],
+ "MMCM_CLKOUT6_DIVIDE": [ { "value": "1", "resolve_type": "user", "format": "long", "usage": "all" } ],
+ "MMCM_CLKOUT6_DUTY_CYCLE": [ { "value": "0.500", "resolve_type": "user", "format": "float", "usage": "all" } ],
+ "MMCM_CLKOUT6_PHASE": [ { "value": "0.000", "resolve_type": "user", "format": "float", "usage": "all" } ],
+ "MMCM_CLKOUT6_USE_FINE_PS": [ { "value": "false", "resolve_type": "user", "format": "bool", "usage": "all" } ],
+ "OVERRIDE_PLL": [ { "value": "false", "resolve_type": "user", "format": "bool", "usage": "all" } ],
+ "PLL_NOTES": [ { "value": "None", "resolve_type": "user", "usage": "all" } ],
+ "PLL_BANDWIDTH": [ { "value": "OPTIMIZED", "resolve_type": "user", "usage": "all" } ],
+ "PLL_CLKFBOUT_MULT": [ { "value": "4", "resolve_type": "user", "format": "long", "usage": "all" } ],
+ "PLL_CLKFBOUT_PHASE": [ { "value": "0.000", "resolve_type": "user", "format": "float", "usage": "all" } ],
+ "PLL_CLK_FEEDBACK": [ { "value": "CLKFBOUT", "resolve_type": "user", "usage": "all" } ],
+ "PLL_DIVCLK_DIVIDE": [ { "value": "1", "resolve_type": "user", "format": "long", "usage": "all" } ],
+ "PLL_CLKIN_PERIOD": [ { "value": "10.000", "resolve_type": "user", "format": "float", "usage": "all" } ],
+ "PLL_COMPENSATION": [ { "value": "SYSTEM_SYNCHRONOUS", "resolve_type": "user", "usage": "all" } ],
+ "PLL_REF_JITTER": [ { "value": "0.010", "resolve_type": "user", "format": "float", "usage": "all" } ],
+ "PLL_CLKOUT0_DIVIDE": [ { "value": "1", "resolve_type": "user", "format": "long", "usage": "all" } ],
+ "PLL_CLKOUT0_DUTY_CYCLE": [ { "value": "0.500", "resolve_type": "user", "format": "float", "usage": "all" } ],
+ "PLL_CLKOUT0_PHASE": [ { "value": "0.000", "resolve_type": "user", "format": "float", "usage": "all" } ],
+ "PLL_CLKOUT1_DIVIDE": [ { "value": "1", "resolve_type": "user", "format": "long", "usage": "all" } ],
+ "PLL_CLKOUT1_DUTY_CYCLE": [ { "value": "0.500", "resolve_type": "user", "format": "float", "usage": "all" } ],
+ "PLL_CLKOUT1_PHASE": [ { "value": "0.000", "resolve_type": "user", "format": "float", "usage": "all" } ],
+ "PLL_CLKOUT2_DIVIDE": [ { "value": "1", "resolve_type": "user", "format": "long", "usage": "all" } ],
+ "PLL_CLKOUT2_DUTY_CYCLE": [ { "value": "0.500", "resolve_type": "user", "format": "float", "usage": "all" } ],
+ "PLL_CLKOUT2_PHASE": [ { "value": "0.000", "resolve_type": "user", "format": "float", "usage": "all" } ],
+ "PLL_CLKOUT3_DIVIDE": [ { "value": "1", "resolve_type": "user", "format": "long", "usage": "all" } ],
+ "PLL_CLKOUT3_DUTY_CYCLE": [ { "value": "0.500", "resolve_type": "user", "format": "float", "usage": "all" } ],
+ "PLL_CLKOUT3_PHASE": [ { "value": "0.000", "resolve_type": "user", "format": "float", "usage": "all" } ],
+ "PLL_CLKOUT4_DIVIDE": [ { "value": "1", "resolve_type": "user", "format": "long", "usage": "all" } ],
+ "PLL_CLKOUT4_DUTY_CYCLE": [ { "value": "0.500", "resolve_type": "user", "format": "float", "usage": "all" } ],
+ "PLL_CLKOUT4_PHASE": [ { "value": "0.000", "resolve_type": "user", "format": "float", "usage": "all" } ],
+ "PLL_CLKOUT5_DIVIDE": [ { "value": "1", "resolve_type": "user", "format": "long", "usage": "all" } ],
+ "PLL_CLKOUT5_DUTY_CYCLE": [ { "value": "0.500", "resolve_type": "user", "format": "float", "usage": "all" } ],
+ "PLL_CLKOUT5_PHASE": [ { "value": "0.000", "resolve_type": "user", "format": "float", "usage": "all" } ],
+ "RESET_TYPE": [ { "value": "ACTIVE_LOW", "value_src": "user", "resolve_type": "user", "usage": "all" } ],
+ "USE_SAFE_CLOCK_STARTUP": [ { "value": "false", "resolve_type": "user", "format": "bool", "usage": "all" } ],
+ "USE_CLOCK_SEQUENCING": [ { "value": "false", "resolve_type": "user", "format": "bool", "usage": "all" } ],
+ "CLKOUT1_SEQUENCE_NUMBER": [ { "value": "1", "resolve_type": "user", "format": "long", "usage": "all" } ],
+ "CLKOUT2_SEQUENCE_NUMBER": [ { "value": "1", "resolve_type": "user", "format": "long", "usage": "all" } ],
+ "CLKOUT3_SEQUENCE_NUMBER": [ { "value": "1", "resolve_type": "user", "format": "long", "usage": "all" } ],
+ "CLKOUT4_SEQUENCE_NUMBER": [ { "value": "1", "resolve_type": "user", "format": "long", "usage": "all" } ],
+ "CLKOUT5_SEQUENCE_NUMBER": [ { "value": "1", "resolve_type": "user", "format": "long", "usage": "all" } ],
+ "CLKOUT6_SEQUENCE_NUMBER": [ { "value": "1", "resolve_type": "user", "format": "long", "usage": "all" } ],
+ "CLKOUT7_SEQUENCE_NUMBER": [ { "value": "1", "resolve_type": "user", "format": "long", "usage": "all" } ],
+ "USE_BOARD_FLOW": [ { "value": "false", "resolve_type": "user", "format": "bool", "usage": "all" } ],
+ "CLK_IN1_BOARD_INTERFACE": [ { "value": "Custom", "resolve_type": "user", "usage": "all" } ],
+ "CLK_IN2_BOARD_INTERFACE": [ { "value": "Custom", "resolve_type": "user", "usage": "all" } ],
+ "DIFF_CLK_IN1_BOARD_INTERFACE": [ { "value": "Custom", "resolve_type": "user", "usage": "all" } ],
+ "DIFF_CLK_IN2_BOARD_INTERFACE": [ { "value": "Custom", "resolve_type": "user", "usage": "all" } ],
+ "AUTO_PRIMITIVE": [ { "value": "MMCM", "resolve_type": "user", "usage": "all" } ],
+ "RESET_BOARD_INTERFACE": [ { "value": "Custom", "resolve_type": "user", "usage": "all" } ],
+ "ENABLE_CDDC": [ { "value": "false", "resolve_type": "user", "format": "bool", "usage": "all" } ],
+ "CDDCDONE_PORT": [ { "value": "cddcdone", "resolve_type": "user", "usage": "all" } ],
+ "CDDCREQ_PORT": [ { "value": "cddcreq", "resolve_type": "user", "usage": "all" } ],
+ "ENABLE_CLKOUTPHY": [ { "value": "false", "resolve_type": "user", "format": "bool", "usage": "all" } ],
+ "CLKOUTPHY_REQUESTED_FREQ": [ { "value": "600.000", "resolve_type": "user", "format": "float", "usage": "all" } ],
+ "CLKOUT1_JITTER": [ { "value": "181.828", "value_src": "user", "resolve_type": "user", "format": "float", "usage": "all" } ],
+ "CLKOUT1_PHASE_ERROR": [ { "value": "104.359", "value_src": "user", "resolve_type": "user", "format": "float", "usage": "all" } ],
+ "CLKOUT2_JITTER": [ { "value": "0.0", "resolve_type": "user", "format": "float", "usage": "all" } ],
+ "CLKOUT2_PHASE_ERROR": [ { "value": "0.0", "resolve_type": "user", "format": "float", "usage": "all" } ],
+ "CLKOUT3_JITTER": [ { "value": "0.0", "resolve_type": "user", "format": "float", "usage": "all" } ],
+ "CLKOUT3_PHASE_ERROR": [ { "value": "0.0", "resolve_type": "user", "format": "float", "usage": "all" } ],
+ "CLKOUT4_JITTER": [ { "value": "0.0", "resolve_type": "user", "format": "float", "usage": "all" } ],
+ "CLKOUT4_PHASE_ERROR": [ { "value": "0.0", "resolve_type": "user", "format": "float", "usage": "all" } ],
+ "CLKOUT5_JITTER": [ { "value": "0.0", "resolve_type": "user", "format": "float", "usage": "all" } ],
+ "CLKOUT5_PHASE_ERROR": [ { "value": "0.0", "resolve_type": "user", "format": "float", "usage": "all" } ],
+ "CLKOUT6_JITTER": [ { "value": "0.0", "resolve_type": "user", "format": "float", "usage": "all" } ],
+ "CLKOUT6_PHASE_ERROR": [ { "value": "0.0", "resolve_type": "user", "format": "float", "usage": "all" } ],
+ "CLKOUT7_JITTER": [ { "value": "0.0", "resolve_type": "user", "format": "float", "usage": "all" } ],
+ "CLKOUT7_PHASE_ERROR": [ { "value": "0.0", "resolve_type": "user", "format": "float", "usage": "all" } ],
+ "INPUT_MODE": [ { "value": "frequency", "resolve_type": "user", "usage": "all" } ],
+ "INTERFACE_SELECTION": [ { "value": "Enable_AXI", "resolve_type": "user", "usage": "all" } ],
+ "AXI_DRP": [ { "value": "false", "resolve_type": "user", "format": "bool", "usage": "all" } ],
+ "PHASE_DUTY_CONFIG": [ { "value": "false", "resolve_type": "user", "format": "bool", "usage": "all" } ]
+ },
+ "model_parameters": {
+ "C_CLKOUT2_USED": [ { "value": "0", "resolve_type": "generated", "format": "long", "usage": "all" } ],
+ "C_USER_CLK_FREQ0": [ { "value": "100.0", "resolve_type": "generated", "format": "float", "usage": "all" } ],
+ "C_AUTO_PRIMITIVE": [ { "value": "MMCM", "resolve_type": "generated", "usage": "all" } ],
+ "C_USER_CLK_FREQ1": [ { "value": "100.0", "resolve_type": "generated", "format": "float", "usage": "all" } ],
+ "C_USER_CLK_FREQ2": [ { "value": "100.0", "resolve_type": "generated", "format": "float", "usage": "all" } ],
+ "C_USER_CLK_FREQ3": [ { "value": "100.0", "resolve_type": "generated", "format": "float", "usage": "all" } ],
+ "C_ENABLE_CLOCK_MONITOR": [ { "value": "0", "resolve_type": "generated", "format": "long", "usage": "all" } ],
+ "C_ENABLE_USER_CLOCK0": [ { "value": "0", "resolve_type": "generated", "format": "long", "usage": "all" } ],
+ "C_ENABLE_USER_CLOCK1": [ { "value": "0", "resolve_type": "generated", "format": "long", "usage": "all" } ],
+ "C_ENABLE_USER_CLOCK2": [ { "value": "0", "resolve_type": "generated", "format": "long", "usage": "all" } ],
+ "C_ENABLE_USER_CLOCK3": [ { "value": "0", "resolve_type": "generated", "format": "long", "usage": "all" } ],
+ "C_Enable_PLL0": [ { "value": "0", "resolve_type": "generated", "format": "long", "usage": "all" } ],
+ "C_Enable_PLL1": [ { "value": "0", "resolve_type": "generated", "format": "long", "usage": "all" } ],
+ "C_REF_CLK_FREQ": [ { "value": "100.0", "resolve_type": "generated", "format": "float", "usage": "all" } ],
+ "C_PRECISION": [ { "value": "1", "resolve_type": "generated", "format": "float", "usage": "all" } ],
+ "C_CLKOUT3_USED": [ { "value": "0", "resolve_type": "generated", "format": "long", "usage": "all" } ],
+ "C_CLKOUT4_USED": [ { "value": "0", "resolve_type": "generated", "format": "long", "usage": "all" } ],
+ "C_CLKOUT5_USED": [ { "value": "0", "resolve_type": "generated", "format": "long", "usage": "all" } ],
+ "C_CLKOUT6_USED": [ { "value": "0", "resolve_type": "generated", "format": "long", "usage": "all" } ],
+ "C_CLKOUT7_USED": [ { "value": "0", "resolve_type": "generated", "format": "long", "usage": "all" } ],
+ "C_USE_CLKOUT1_BAR": [ { "value": "0", "resolve_type": "generated", "format": "long", "usage": "all" } ],
+ "C_USE_CLKOUT2_BAR": [ { "value": "0", "resolve_type": "generated", "format": "long", "usage": "all" } ],
+ "C_USE_CLKOUT3_BAR": [ { "value": "0", "resolve_type": "generated", "format": "long", "usage": "all" } ],
+ "C_USE_CLKOUT4_BAR": [ { "value": "0", "resolve_type": "generated", "format": "long", "usage": "all" } ],
+ "c_component_name": [ { "value": "clk_wiz_1", "resolve_type": "generated", "usage": "all" } ],
+ "C_PLATFORM": [ { "value": "UNKNOWN", "resolve_type": "generated", "usage": "all" } ],
+ "C_USE_FREQ_SYNTH": [ { "value": "1", "resolve_type": "generated", "format": "long", "usage": "all" } ],
+ "C_USE_PHASE_ALIGNMENT": [ { "value": "1", "resolve_type": "generated", "format": "long", "usage": "all" } ],
+ "C_PRIM_IN_JITTER": [ { "value": "0.010", "resolve_type": "generated", "format": "float", "usage": "all" } ],
+ "C_SECONDARY_IN_JITTER": [ { "value": "0.010", "resolve_type": "generated", "format": "float", "usage": "all" } ],
+ "C_JITTER_SEL": [ { "value": "No_Jitter", "resolve_type": "generated", "usage": "all" } ],
+ "C_USE_MIN_POWER": [ { "value": "0", "resolve_type": "generated", "format": "long", "usage": "all" } ],
+ "C_USE_MIN_O_JITTER": [ { "value": "0", "resolve_type": "generated", "format": "long", "usage": "all" } ],
+ "C_USE_MAX_I_JITTER": [ { "value": "0", "resolve_type": "generated", "format": "long", "usage": "all" } ],
+ "C_USE_DYN_PHASE_SHIFT": [ { "value": "0", "resolve_type": "generated", "format": "long", "usage": "all" } ],
+ "C_OPTIMIZE_CLOCKING_STRUCTURE_EN": [ { "value": "0", "resolve_type": "generated", "format": "long", "usage": "all" } ],
+ "C_USE_INCLK_SWITCHOVER": [ { "value": "0", "resolve_type": "generated", "format": "long", "usage": "all" } ],
+ "C_USE_DYN_RECONFIG": [ { "value": "0", "resolve_type": "generated", "format": "long", "usage": "all" } ],
+ "C_USE_SPREAD_SPECTRUM": [ { "value": "0", "resolve_type": "generated", "format": "long", "usage": "all" } ],
+ "C_USE_FAST_SIMULATION": [ { "value": "0", "resolve_type": "generated", "format": "long", "usage": "all" } ],
+ "C_PRIMTYPE_SEL": [ { "value": "AUTO", "resolve_type": "generated", "usage": "all" } ],
+ "C_USE_CLK_VALID": [ { "value": "0", "resolve_type": "generated", "format": "long", "usage": "all" } ],
+ "C_PRIM_IN_FREQ": [ { "value": "100.000", "resolve_type": "generated", "format": "float", "usage": "all" } ],
+ "C_PRIM_IN_TIMEPERIOD": [ { "value": "10.000", "resolve_type": "generated", "format": "float", "usage": "all" } ],
+ "C_IN_FREQ_UNITS": [ { "value": "Units_MHz", "resolve_type": "generated", "usage": "all" } ],
+ "C_SECONDARY_IN_FREQ": [ { "value": "100.000", "resolve_type": "generated", "format": "float", "usage": "all" } ],
+ "C_SECONDARY_IN_TIMEPERIOD": [ { "value": "10.000", "resolve_type": "generated", "format": "float", "usage": "all" } ],
+ "C_FEEDBACK_SOURCE": [ { "value": "FDBK_AUTO", "resolve_type": "generated", "usage": "all" } ],
+ "C_PRIM_SOURCE": [ { "value": "Single_ended_clock_capable_pin", "resolve_type": "generated", "usage": "all" } ],
+ "C_PHASESHIFT_MODE": [ { "value": "WAVEFORM", "resolve_type": "generated", "usage": "all" } ],
+ "C_SECONDARY_SOURCE": [ { "value": "Single_ended_clock_capable_pin", "resolve_type": "generated", "usage": "all" } ],
+ "C_CLKFB_IN_SIGNALING": [ { "value": "SINGLE", "resolve_type": "generated", "usage": "all" } ],
+ "C_USE_RESET": [ { "value": "1", "resolve_type": "generated", "format": "long", "usage": "all" } ],
+ "C_RESET_LOW": [ { "value": "1", "resolve_type": "generated", "format": "long", "usage": "all" } ],
+ "C_USE_LOCKED": [ { "value": "0", "resolve_type": "generated", "format": "long", "usage": "all" } ],
+ "C_USE_INCLK_STOPPED": [ { "value": "0", "resolve_type": "generated", "format": "long", "usage": "all" } ],
+ "C_USE_CLKFB_STOPPED": [ { "value": "0", "resolve_type": "generated", "format": "long", "usage": "all" } ],
+ "C_USE_POWER_DOWN": [ { "value": "0", "resolve_type": "generated", "format": "long", "usage": "all" } ],
+ "C_USE_STATUS": [ { "value": "0", "resolve_type": "generated", "format": "long", "usage": "all" } ],
+ "C_USE_FREEZE": [ { "value": "0", "resolve_type": "generated", "format": "long", "usage": "all" } ],
+ "C_NUM_OUT_CLKS": [ { "value": "1", "resolve_type": "generated", "format": "long", "usage": "all" } ],
+ "C_CLKOUT1_DRIVES": [ { "value": "BUFG", "resolve_type": "generated", "usage": "all" } ],
+ "C_CLKOUT2_DRIVES": [ { "value": "BUFG", "resolve_type": "generated", "usage": "all" } ],
+ "C_CLKOUT3_DRIVES": [ { "value": "BUFG", "resolve_type": "generated", "usage": "all" } ],
+ "C_CLKOUT4_DRIVES": [ { "value": "BUFG", "resolve_type": "generated", "usage": "all" } ],
+ "C_CLKOUT5_DRIVES": [ { "value": "BUFG", "resolve_type": "generated", "usage": "all" } ],
+ "C_CLKOUT6_DRIVES": [ { "value": "BUFG", "resolve_type": "generated", "usage": "all" } ],
+ "C_CLKOUT7_DRIVES": [ { "value": "BUFG", "resolve_type": "generated", "usage": "all" } ],
+ "C_INCLK_SUM_ROW0": [ { "value": "Input Clock Freq (MHz) Input Jitter (UI)", "resolve_type": "generated", "usage": "all" } ],
+ "C_INCLK_SUM_ROW1": [ { "value": "__primary_________100.000____________0.010", "resolve_type": "generated", "usage": "all" } ],
+ "C_INCLK_SUM_ROW2": [ { "value": "no_secondary_input_clock ", "resolve_type": "generated", "usage": "all" } ],
+ "C_OUTCLK_SUM_ROW0A": [ { "value": " Output Output Phase Duty Cycle Pk-to-Pk Phase", "resolve_type": "generated", "usage": "all" } ],
+ "C_OUTCLK_SUM_ROW0B": [ { "value": " Clock Freq (MHz) (degrees) (%) Jitter (ps) Error (ps)", "resolve_type": "generated", "usage": "all" } ],
+ "C_OUTCLK_SUM_ROW1": [ { "value": "clk_out1__25.00000______0.000______50.0______181.828____104.359", "resolve_type": "generated", "usage": "all" } ],
+ "C_OUTCLK_SUM_ROW2": [ { "value": "no_CLK_OUT2_output", "resolve_type": "generated", "usage": "all" } ],
+ "C_OUTCLK_SUM_ROW3": [ { "value": "no_CLK_OUT3_output", "resolve_type": "generated", "usage": "all" } ],
+ "C_OUTCLK_SUM_ROW4": [ { "value": "no_CLK_OUT4_output", "resolve_type": "generated", "usage": "all" } ],
+ "C_OUTCLK_SUM_ROW5": [ { "value": "no_CLK_OUT5_output", "resolve_type": "generated", "usage": "all" } ],
+ "C_OUTCLK_SUM_ROW6": [ { "value": "no_CLK_OUT6_output", "resolve_type": "generated", "usage": "all" } ],
+ "C_OUTCLK_SUM_ROW7": [ { "value": "no_CLK_OUT7_output", "resolve_type": "generated", "usage": "all" } ],
+ "C_CLKOUT1_REQUESTED_OUT_FREQ": [ { "value": "25.000", "resolve_type": "generated", "format": "float", "usage": "all" } ],
+ "C_CLKOUT2_REQUESTED_OUT_FREQ": [ { "value": "100.000", "resolve_type": "generated", "format": "float", "usage": "all" } ],
+ "C_CLKOUT3_REQUESTED_OUT_FREQ": [ { "value": "100.000", "resolve_type": "generated", "format": "float", "usage": "all" } ],
+ "C_CLKOUT4_REQUESTED_OUT_FREQ": [ { "value": "100.000", "resolve_type": "generated", "format": "float", "usage": "all" } ],
+ "C_CLKOUT5_REQUESTED_OUT_FREQ": [ { "value": "100.000", "resolve_type": "generated", "format": "float", "usage": "all" } ],
+ "C_CLKOUT6_REQUESTED_OUT_FREQ": [ { "value": "100.000", "resolve_type": "generated", "format": "float", "usage": "all" } ],
+ "C_CLKOUT7_REQUESTED_OUT_FREQ": [ { "value": "100.000", "resolve_type": "generated", "format": "float", "usage": "all" } ],
+ "C_CLKOUT1_REQUESTED_PHASE": [ { "value": "0.000", "resolve_type": "generated", "format": "float", "usage": "all" } ],
+ "C_CLKOUT2_REQUESTED_PHASE": [ { "value": "0.000", "resolve_type": "generated", "format": "float", "usage": "all" } ],
+ "C_CLKOUT3_REQUESTED_PHASE": [ { "value": "0.000", "resolve_type": "generated", "format": "float", "usage": "all" } ],
+ "C_CLKOUT4_REQUESTED_PHASE": [ { "value": "0.000", "resolve_type": "generated", "format": "float", "usage": "all" } ],
+ "C_CLKOUT5_REQUESTED_PHASE": [ { "value": "0.000", "resolve_type": "generated", "format": "float", "usage": "all" } ],
+ "C_CLKOUT6_REQUESTED_PHASE": [ { "value": "0.000", "resolve_type": "generated", "format": "float", "usage": "all" } ],
+ "C_CLKOUT7_REQUESTED_PHASE": [ { "value": "0.000", "resolve_type": "generated", "format": "float", "usage": "all" } ],
+ "C_CLKOUT1_REQUESTED_DUTY_CYCLE": [ { "value": "50.000", "resolve_type": "generated", "format": "float", "usage": "all" } ],
+ "C_CLKOUT2_REQUESTED_DUTY_CYCLE": [ { "value": "50.000", "resolve_type": "generated", "format": "float", "usage": "all" } ],
+ "C_CLKOUT3_REQUESTED_DUTY_CYCLE": [ { "value": "50.000", "resolve_type": "generated", "format": "float", "usage": "all" } ],
+ "C_CLKOUT4_REQUESTED_DUTY_CYCLE": [ { "value": "50.000", "resolve_type": "generated", "format": "float", "usage": "all" } ],
+ "C_CLKOUT5_REQUESTED_DUTY_CYCLE": [ { "value": "50.000", "resolve_type": "generated", "format": "float", "usage": "all" } ],
+ "C_CLKOUT6_REQUESTED_DUTY_CYCLE": [ { "value": "50.000", "resolve_type": "generated", "format": "float", "usage": "all" } ],
+ "C_CLKOUT7_REQUESTED_DUTY_CYCLE": [ { "value": "50.000", "resolve_type": "generated", "format": "float", "usage": "all" } ],
+ "C_CLKOUT1_OUT_FREQ": [ { "value": "25.00000", "resolve_type": "generated", "format": "float", "usage": "all" } ],
+ "C_CLKOUT2_OUT_FREQ": [ { "value": "100.000", "resolve_type": "generated", "format": "float", "usage": "all" } ],
+ "C_CLKOUT3_OUT_FREQ": [ { "value": "100.000", "resolve_type": "generated", "format": "float", "usage": "all" } ],
+ "C_CLKOUT4_OUT_FREQ": [ { "value": "100.000", "resolve_type": "generated", "format": "float", "usage": "all" } ],
+ "C_CLKOUT5_OUT_FREQ": [ { "value": "100.000", "resolve_type": "generated", "format": "float", "usage": "all" } ],
+ "C_CLKOUT6_OUT_FREQ": [ { "value": "100.000", "resolve_type": "generated", "format": "float", "usage": "all" } ],
+ "C_CLKOUT7_OUT_FREQ": [ { "value": "100.000", "resolve_type": "generated", "format": "float", "usage": "all" } ],
+ "C_CLKOUT1_PHASE": [ { "value": "0.000", "resolve_type": "generated", "format": "float", "usage": "all" } ],
+ "C_CLKOUT2_PHASE": [ { "value": "0.000", "resolve_type": "generated", "format": "float", "usage": "all" } ],
+ "C_CLKOUT3_PHASE": [ { "value": "0.000", "resolve_type": "generated", "format": "float", "usage": "all" } ],
+ "C_CLKOUT4_PHASE": [ { "value": "0.000", "resolve_type": "generated", "format": "float", "usage": "all" } ],
+ "C_CLKOUT5_PHASE": [ { "value": "0.000", "resolve_type": "generated", "format": "float", "usage": "all" } ],
+ "C_CLKOUT6_PHASE": [ { "value": "0.000", "resolve_type": "generated", "format": "float", "usage": "all" } ],
+ "C_CLKOUT7_PHASE": [ { "value": "0.000", "resolve_type": "generated", "format": "float", "usage": "all" } ],
+ "C_CLKOUT1_DUTY_CYCLE": [ { "value": "50.0", "resolve_type": "generated", "format": "float", "usage": "all" } ],
+ "C_CLKOUT2_DUTY_CYCLE": [ { "value": "50.000", "resolve_type": "generated", "format": "float", "usage": "all" } ],
+ "C_CLKOUT3_DUTY_CYCLE": [ { "value": "50.000", "resolve_type": "generated", "format": "float", "usage": "all" } ],
+ "C_CLKOUT4_DUTY_CYCLE": [ { "value": "50.000", "resolve_type": "generated", "format": "float", "usage": "all" } ],
+ "C_CLKOUT5_DUTY_CYCLE": [ { "value": "50.000", "resolve_type": "generated", "format": "float", "usage": "all" } ],
+ "C_CLKOUT6_DUTY_CYCLE": [ { "value": "50.000", "resolve_type": "generated", "format": "float", "usage": "all" } ],
+ "C_CLKOUT7_DUTY_CYCLE": [ { "value": "50.000", "resolve_type": "generated", "format": "float", "usage": "all" } ],
+ "C_USE_SAFE_CLOCK_STARTUP": [ { "value": "0", "resolve_type": "generated", "format": "long", "usage": "all" } ],
+ "C_USE_CLOCK_SEQUENCING": [ { "value": "0", "resolve_type": "generated", "format": "long", "usage": "all" } ],
+ "C_CLKOUT1_SEQUENCE_NUMBER": [ { "value": "1", "resolve_type": "generated", "format": "long", "usage": "all" } ],
+ "C_CLKOUT2_SEQUENCE_NUMBER": [ { "value": "1", "resolve_type": "generated", "format": "long", "usage": "all" } ],
+ "C_CLKOUT3_SEQUENCE_NUMBER": [ { "value": "1", "resolve_type": "generated", "format": "long", "usage": "all" } ],
+ "C_CLKOUT4_SEQUENCE_NUMBER": [ { "value": "1", "resolve_type": "generated", "format": "long", "usage": "all" } ],
+ "C_CLKOUT5_SEQUENCE_NUMBER": [ { "value": "1", "resolve_type": "generated", "format": "long", "usage": "all" } ],
+ "C_CLKOUT6_SEQUENCE_NUMBER": [ { "value": "1", "resolve_type": "generated", "format": "long", "usage": "all" } ],
+ "C_CLKOUT7_SEQUENCE_NUMBER": [ { "value": "1", "resolve_type": "generated", "format": "long", "usage": "all" } ],
+ "C_MMCM_NOTES": [ { "value": "None", "resolve_type": "generated", "usage": "all" } ],
+ "C_MMCM_BANDWIDTH": [ { "value": "OPTIMIZED", "resolve_type": "generated", "usage": "all" } ],
+ "C_MMCM_CLKFBOUT_MULT_F": [ { "value": "9.125", "resolve_type": "generated", "format": "float", "usage": "all" } ],
+ "C_MMCM_CLKIN1_PERIOD": [ { "value": "10.000", "resolve_type": "generated", "format": "float", "usage": "all" } ],
+ "C_MMCM_CLKIN2_PERIOD": [ { "value": "10.000", "resolve_type": "generated", "format": "float", "usage": "all" } ],
+ "C_MMCM_CLKOUT4_CASCADE": [ { "value": "FALSE", "resolve_type": "generated", "format": "bool", "usage": "all" } ],
+ "C_MMCM_CLOCK_HOLD": [ { "value": "FALSE", "resolve_type": "generated", "format": "bool", "usage": "all" } ],
+ "C_MMCM_COMPENSATION": [ { "value": "ZHOLD", "resolve_type": "generated", "usage": "all" } ],
+ "C_MMCM_DIVCLK_DIVIDE": [ { "value": "1", "resolve_type": "generated", "format": "long", "usage": "all" } ],
+ "C_MMCM_REF_JITTER1": [ { "value": "0.010", "resolve_type": "generated", "format": "float", "usage": "all" } ],
+ "C_MMCM_REF_JITTER2": [ { "value": "0.010", "resolve_type": "generated", "format": "float", "usage": "all" } ],
+ "C_MMCM_STARTUP_WAIT": [ { "value": "FALSE", "resolve_type": "generated", "usage": "all" } ],
+ "C_MMCM_CLKOUT0_DIVIDE_F": [ { "value": "36.500", "resolve_type": "generated", "format": "float", "usage": "all" } ],
+ "C_MMCM_CLKOUT1_DIVIDE": [ { "value": "1", "resolve_type": "generated", "format": "long", "usage": "all" } ],
+ "C_MMCM_CLKOUT2_DIVIDE": [ { "value": "1", "resolve_type": "generated", "format": "long", "usage": "all" } ],
+ "C_MMCM_CLKOUT3_DIVIDE": [ { "value": "1", "resolve_type": "generated", "format": "long", "usage": "all" } ],
+ "C_MMCM_CLKOUT4_DIVIDE": [ { "value": "1", "resolve_type": "generated", "format": "long", "usage": "all" } ],
+ "C_MMCM_CLKOUT5_DIVIDE": [ { "value": "1", "resolve_type": "generated", "format": "long", "usage": "all" } ],
+ "C_MMCM_CLKOUT6_DIVIDE": [ { "value": "1", "resolve_type": "generated", "format": "long", "usage": "all" } ],
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+ "C_MMCM_CLKOUT1_DUTY_CYCLE": [ { "value": "0.500", "resolve_type": "generated", "format": "float", "usage": "all" } ],
+ "C_MMCM_CLKOUT2_DUTY_CYCLE": [ { "value": "0.500", "resolve_type": "generated", "format": "float", "usage": "all" } ],
+ "C_MMCM_CLKOUT3_DUTY_CYCLE": [ { "value": "0.500", "resolve_type": "generated", "format": "float", "usage": "all" } ],
+ "C_MMCM_CLKOUT4_DUTY_CYCLE": [ { "value": "0.500", "resolve_type": "generated", "format": "float", "usage": "all" } ],
+ "C_MMCM_CLKOUT5_DUTY_CYCLE": [ { "value": "0.500", "resolve_type": "generated", "format": "float", "usage": "all" } ],
+ "C_MMCM_CLKOUT6_DUTY_CYCLE": [ { "value": "0.500", "resolve_type": "generated", "format": "float", "usage": "all" } ],
+ "C_MMCM_CLKFBOUT_PHASE": [ { "value": "0.000", "resolve_type": "generated", "format": "float", "usage": "all" } ],
+ "C_MMCM_CLKOUT0_PHASE": [ { "value": "0.000", "resolve_type": "generated", "format": "float", "usage": "all" } ],
+ "C_MMCM_CLKOUT1_PHASE": [ { "value": "0.000", "resolve_type": "generated", "format": "float", "usage": "all" } ],
+ "C_MMCM_CLKOUT2_PHASE": [ { "value": "0.000", "resolve_type": "generated", "format": "float", "usage": "all" } ],
+ "C_MMCM_CLKOUT3_PHASE": [ { "value": "0.000", "resolve_type": "generated", "format": "float", "usage": "all" } ],
+ "C_MMCM_CLKOUT4_PHASE": [ { "value": "0.000", "resolve_type": "generated", "format": "float", "usage": "all" } ],
+ "C_MMCM_CLKOUT5_PHASE": [ { "value": "0.000", "resolve_type": "generated", "format": "float", "usage": "all" } ],
+ "C_MMCM_CLKOUT6_PHASE": [ { "value": "0.000", "resolve_type": "generated", "format": "float", "usage": "all" } ],
+ "C_MMCM_CLKFBOUT_USE_FINE_PS": [ { "value": "FALSE", "resolve_type": "generated", "usage": "all" } ],
+ "C_MMCM_CLKOUT0_USE_FINE_PS": [ { "value": "FALSE", "resolve_type": "generated", "usage": "all" } ],
+ "C_MMCM_CLKOUT1_USE_FINE_PS": [ { "value": "FALSE", "resolve_type": "generated", "usage": "all" } ],
+ "C_MMCM_CLKOUT2_USE_FINE_PS": [ { "value": "FALSE", "resolve_type": "generated", "usage": "all" } ],
+ "C_MMCM_CLKOUT3_USE_FINE_PS": [ { "value": "FALSE", "resolve_type": "generated", "usage": "all" } ],
+ "C_MMCM_CLKOUT4_USE_FINE_PS": [ { "value": "FALSE", "resolve_type": "generated", "usage": "all" } ],
+ "C_MMCM_CLKOUT5_USE_FINE_PS": [ { "value": "FALSE", "resolve_type": "generated", "usage": "all" } ],
+ "C_MMCM_CLKOUT6_USE_FINE_PS": [ { "value": "FALSE", "resolve_type": "generated", "usage": "all" } ],
+ "C_PLL_NOTES": [ { "value": "No notes", "resolve_type": "generated", "usage": "all" } ],
+ "C_PLL_BANDWIDTH": [ { "value": "OPTIMIZED", "resolve_type": "generated", "usage": "all" } ],
+ "C_PLL_CLK_FEEDBACK": [ { "value": "CLKFBOUT", "resolve_type": "generated", "usage": "all" } ],
+ "C_PLL_CLKFBOUT_MULT": [ { "value": "1", "resolve_type": "generated", "format": "long", "usage": "all" } ],
+ "C_PLL_CLKIN_PERIOD": [ { "value": "1.000", "resolve_type": "generated", "format": "float", "usage": "all" } ],
+ "C_PLL_COMPENSATION": [ { "value": "SYSTEM_SYNCHRONOUS", "resolve_type": "generated", "usage": "all" } ],
+ "C_PLL_DIVCLK_DIVIDE": [ { "value": "1", "resolve_type": "generated", "format": "long", "usage": "all" } ],
+ "C_PLL_REF_JITTER": [ { "value": "0.010", "resolve_type": "generated", "format": "float", "usage": "all" } ],
+ "C_PLL_CLKOUT0_DIVIDE": [ { "value": "1", "resolve_type": "generated", "format": "long", "usage": "all" } ],
+ "C_PLL_CLKOUT1_DIVIDE": [ { "value": "1", "resolve_type": "generated", "format": "long", "usage": "all" } ],
+ "C_PLL_CLKOUT2_DIVIDE": [ { "value": "1", "resolve_type": "generated", "format": "long", "usage": "all" } ],
+ "C_PLL_CLKOUT3_DIVIDE": [ { "value": "1", "resolve_type": "generated", "format": "long", "usage": "all" } ],
+ "C_PLL_CLKOUT4_DIVIDE": [ { "value": "1", "resolve_type": "generated", "format": "long", "usage": "all" } ],
+ "C_PLL_CLKOUT5_DIVIDE": [ { "value": "1", "resolve_type": "generated", "format": "long", "usage": "all" } ],
+ "C_PLL_CLKOUT0_DUTY_CYCLE": [ { "value": "0.500", "resolve_type": "generated", "format": "float", "usage": "all" } ],
+ "C_PLL_CLKOUT1_DUTY_CYCLE": [ { "value": "0.500", "resolve_type": "generated", "format": "float", "usage": "all" } ],
+ "C_PLL_CLKOUT2_DUTY_CYCLE": [ { "value": "0.500", "resolve_type": "generated", "format": "float", "usage": "all" } ],
+ "C_PLL_CLKOUT3_DUTY_CYCLE": [ { "value": "0.500", "resolve_type": "generated", "format": "float", "usage": "all" } ],
+ "C_PLL_CLKOUT4_DUTY_CYCLE": [ { "value": "0.500", "resolve_type": "generated", "format": "float", "usage": "all" } ],
+ "C_PLL_CLKOUT5_DUTY_CYCLE": [ { "value": "0.500", "resolve_type": "generated", "format": "float", "usage": "all" } ],
+ "C_PLL_CLKFBOUT_PHASE": [ { "value": "0.000", "resolve_type": "generated", "format": "float", "usage": "all" } ],
+ "C_PLL_CLKOUT0_PHASE": [ { "value": "0.000", "resolve_type": "generated", "format": "float", "usage": "all" } ],
+ "C_PLL_CLKOUT1_PHASE": [ { "value": "0.000", "resolve_type": "generated", "format": "float", "usage": "all" } ],
+ "C_PLL_CLKOUT2_PHASE": [ { "value": "0.000", "resolve_type": "generated", "format": "float", "usage": "all" } ],
+ "C_PLL_CLKOUT3_PHASE": [ { "value": "0.000", "resolve_type": "generated", "format": "float", "usage": "all" } ],
+ "C_PLL_CLKOUT4_PHASE": [ { "value": "0.000", "resolve_type": "generated", "format": "float", "usage": "all" } ],
+ "C_PLL_CLKOUT5_PHASE": [ { "value": "0.000", "resolve_type": "generated", "format": "float", "usage": "all" } ],
+ "C_CLOCK_MGR_TYPE": [ { "value": "NA", "resolve_type": "generated", "usage": "all" } ],
+ "C_OVERRIDE_MMCM": [ { "value": "0", "resolve_type": "generated", "format": "long", "usage": "all" } ],
+ "C_OVERRIDE_PLL": [ { "value": "0", "resolve_type": "generated", "format": "long", "usage": "all" } ],
+ "C_PRIMARY_PORT": [ { "value": "clk_in1", "resolve_type": "generated", "usage": "all" } ],
+ "C_SECONDARY_PORT": [ { "value": "clk_in2", "resolve_type": "generated", "usage": "all" } ],
+ "C_CLK_OUT1_PORT": [ { "value": "clk_out1", "resolve_type": "generated", "usage": "all" } ],
+ "C_CLK_OUT2_PORT": [ { "value": "clk_out2", "resolve_type": "generated", "usage": "all" } ],
+ "C_CLK_OUT3_PORT": [ { "value": "clk_out3", "resolve_type": "generated", "usage": "all" } ],
+ "C_CLK_OUT4_PORT": [ { "value": "clk_out4", "resolve_type": "generated", "usage": "all" } ],
+ "C_CLK_OUT5_PORT": [ { "value": "clk_out5", "resolve_type": "generated", "usage": "all" } ],
+ "C_CLK_OUT6_PORT": [ { "value": "clk_out6", "resolve_type": "generated", "usage": "all" } ],
+ "C_CLK_OUT7_PORT": [ { "value": "clk_out7", "resolve_type": "generated", "usage": "all" } ],
+ "C_RESET_PORT": [ { "value": "resetn", "resolve_type": "generated", "usage": "all" } ],
+ "C_LOCKED_PORT": [ { "value": "locked", "resolve_type": "generated", "usage": "all" } ],
+ "C_CLKFB_IN_PORT": [ { "value": "clkfb_in", "resolve_type": "generated", "usage": "all" } ],
+ "C_CLKFB_IN_P_PORT": [ { "value": "clkfb_in_p", "resolve_type": "generated", "usage": "all" } ],
+ "C_CLKFB_IN_N_PORT": [ { "value": "clkfb_in_n", "resolve_type": "generated", "usage": "all" } ],
+ "C_CLKFB_OUT_PORT": [ { "value": "clkfb_out", "resolve_type": "generated", "usage": "all" } ],
+ "C_CLKFB_OUT_P_PORT": [ { "value": "clkfb_out_p", "resolve_type": "generated", "usage": "all" } ],
+ "C_CLKFB_OUT_N_PORT": [ { "value": "clkfb_out_n", "resolve_type": "generated", "usage": "all" } ],
+ "C_POWER_DOWN_PORT": [ { "value": "power_down", "resolve_type": "generated", "usage": "all" } ],
+ "C_DADDR_PORT": [ { "value": "daddr", "resolve_type": "generated", "usage": "all" } ],
+ "C_DCLK_PORT": [ { "value": "dclk", "resolve_type": "generated", "usage": "all" } ],
+ "C_DRDY_PORT": [ { "value": "drdy", "resolve_type": "generated", "usage": "all" } ],
+ "C_DWE_PORT": [ { "value": "dwe", "resolve_type": "generated", "usage": "all" } ],
+ "C_DIN_PORT": [ { "value": "din", "resolve_type": "generated", "usage": "all" } ],
+ "C_DOUT_PORT": [ { "value": "dout", "resolve_type": "generated", "usage": "all" } ],
+ "C_DEN_PORT": [ { "value": "den", "resolve_type": "generated", "usage": "all" } ],
+ "C_PSCLK_PORT": [ { "value": "psclk", "resolve_type": "generated", "usage": "all" } ],
+ "C_PSEN_PORT": [ { "value": "psen", "resolve_type": "generated", "usage": "all" } ],
+ "C_PSINCDEC_PORT": [ { "value": "psincdec", "resolve_type": "generated", "usage": "all" } ],
+ "C_PSDONE_PORT": [ { "value": "psdone", "resolve_type": "generated", "usage": "all" } ],
+ "C_CLK_VALID_PORT": [ { "value": "CLK_VALID", "resolve_type": "generated", "usage": "all" } ],
+ "C_STATUS_PORT": [ { "value": "STATUS", "resolve_type": "generated", "usage": "all" } ],
+ "C_CLK_IN_SEL_PORT": [ { "value": "clk_in_sel", "resolve_type": "generated", "usage": "all" } ],
+ "C_INPUT_CLK_STOPPED_PORT": [ { "value": "input_clk_stopped", "resolve_type": "generated", "usage": "all" } ],
+ "C_CLKFB_STOPPED_PORT": [ { "value": "clkfb_stopped", "resolve_type": "generated", "usage": "all" } ],
+ "C_CLKIN1_JITTER_PS": [ { "value": "100.0", "resolve_type": "generated", "format": "float", "usage": "all" } ],
+ "C_CLKIN2_JITTER_PS": [ { "value": "100.0", "resolve_type": "generated", "format": "float", "usage": "all" } ],
+ "C_PRIMITIVE": [ { "value": "MMCM", "resolve_type": "generated", "usage": "all" } ],
+ "C_SS_MODE": [ { "value": "CENTER_HIGH", "resolve_type": "generated", "usage": "all" } ],
+ "C_SS_MOD_PERIOD": [ { "value": "4000", "resolve_type": "generated", "format": "long", "usage": "all" } ],
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+ "C_HAS_CDDC": [ { "value": "0", "resolve_type": "generated", "format": "long", "usage": "all" } ],
+ "C_CDDCDONE_PORT": [ { "value": "cddcdone", "resolve_type": "generated", "usage": "all" } ],
+ "C_CDDCREQ_PORT": [ { "value": "cddcreq", "resolve_type": "generated", "usage": "all" } ],
+ "C_CLKOUTPHY_MODE": [ { "value": "VCO", "resolve_type": "generated", "usage": "all" } ],
+ "C_ENABLE_CLKOUTPHY": [ { "value": "0", "resolve_type": "generated", "format": "long", "usage": "all" } ],
+ "C_INTERFACE_SELECTION": [ { "value": "0", "resolve_type": "generated", "format": "long", "usage": "all" } ],
+ "C_S_AXI_ADDR_WIDTH": [ { "value": "11", "resolve_type": "generated", "format": "long", "usage": "all" } ],
+ "C_S_AXI_DATA_WIDTH": [ { "value": "32", "resolve_type": "generated", "format": "long", "usage": "all" } ],
+ "C_POWER_REG": [ { "value": "0000", "resolve_type": "generated", "usage": "all" } ],
+ "C_CLKOUT0_1": [ { "value": "0000", "resolve_type": "generated", "usage": "all" } ],
+ "C_CLKOUT0_2": [ { "value": "0000", "resolve_type": "generated", "usage": "all" } ],
+ "C_CLKOUT1_1": [ { "value": "0000", "resolve_type": "generated", "usage": "all" } ],
+ "C_CLKOUT1_2": [ { "value": "0000", "resolve_type": "generated", "usage": "all" } ],
+ "C_CLKOUT2_1": [ { "value": "0000", "resolve_type": "generated", "usage": "all" } ],
+ "C_CLKOUT2_2": [ { "value": "0000", "resolve_type": "generated", "usage": "all" } ],
+ "C_CLKOUT3_1": [ { "value": "0000", "resolve_type": "generated", "usage": "all" } ],
+ "C_CLKOUT3_2": [ { "value": "0000", "resolve_type": "generated", "usage": "all" } ],
+ "C_CLKOUT4_1": [ { "value": "0000", "resolve_type": "generated", "usage": "all" } ],
+ "C_CLKOUT4_2": [ { "value": "0000", "resolve_type": "generated", "usage": "all" } ],
+ "C_CLKOUT5_1": [ { "value": "0000", "resolve_type": "generated", "usage": "all" } ],
+ "C_CLKOUT5_2": [ { "value": "0000", "resolve_type": "generated", "usage": "all" } ],
+ "C_CLKOUT6_1": [ { "value": "0000", "resolve_type": "generated", "usage": "all" } ],
+ "C_CLKOUT6_2": [ { "value": "0000", "resolve_type": "generated", "usage": "all" } ],
+ "C_CLKFBOUT_1": [ { "value": "0000", "resolve_type": "generated", "usage": "all" } ],
+ "C_CLKFBOUT_2": [ { "value": "0000", "resolve_type": "generated", "usage": "all" } ],
+ "C_DIVCLK": [ { "value": "0000", "resolve_type": "generated", "usage": "all" } ],
+ "C_LOCK_1": [ { "value": "0000", "resolve_type": "generated", "usage": "all" } ],
+ "C_LOCK_2": [ { "value": "0000", "resolve_type": "generated", "usage": "all" } ],
+ "C_LOCK_3": [ { "value": "0000", "resolve_type": "generated", "usage": "all" } ],
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+ "C_FILTER_2": [ { "value": "0000", "resolve_type": "generated", "usage": "all" } ],
+ "C_DIVIDE1_AUTO": [ { "value": "1", "resolve_type": "generated", "usage": "all" } ],
+ "C_DIVIDE2_AUTO": [ { "value": "0.0273972602739726", "resolve_type": "generated", "usage": "all" } ],
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+ "C_DIVIDE7_AUTO": [ { "value": "0.0273972602739726", "resolve_type": "generated", "usage": "all" } ],
+ "C_PLLBUFGCEDIV": [ { "value": "false", "resolve_type": "generated", "usage": "all" } ],
+ "C_MMCMBUFGCEDIV": [ { "value": "false", "resolve_type": "generated", "usage": "all" } ],
+ "C_PLLBUFGCEDIV1": [ { "value": "false", "resolve_type": "generated", "usage": "all" } ],
+ "C_PLLBUFGCEDIV2": [ { "value": "false", "resolve_type": "generated", "usage": "all" } ],
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+ "C_MMCMBUFGCEDIV7": [ { "value": "false", "resolve_type": "generated", "usage": "all" } ],
+ "C_CLKOUT1_MATCHED_ROUTING": [ { "value": "false", "resolve_type": "generated", "usage": "all" } ],
+ "C_CLKOUT2_MATCHED_ROUTING": [ { "value": "false", "resolve_type": "generated", "usage": "all" } ],
+ "C_CLKOUT3_MATCHED_ROUTING": [ { "value": "false", "resolve_type": "generated", "usage": "all" } ],
+ "C_CLKOUT4_MATCHED_ROUTING": [ { "value": "false", "resolve_type": "generated", "usage": "all" } ],
+ "C_CLKOUT5_MATCHED_ROUTING": [ { "value": "false", "resolve_type": "generated", "usage": "all" } ],
+ "C_CLKOUT6_MATCHED_ROUTING": [ { "value": "false", "resolve_type": "generated", "usage": "all" } ],
+ "C_CLKOUT7_MATCHED_ROUTING": [ { "value": "false", "resolve_type": "generated", "usage": "all" } ],
+ "C_CLKOUT0_ACTUAL_FREQ": [ { "value": "25.00000", "resolve_type": "generated", "usage": "all" } ],
+ "C_CLKOUT1_ACTUAL_FREQ": [ { "value": "100.000", "resolve_type": "generated", "usage": "all" } ],
+ "C_CLKOUT2_ACTUAL_FREQ": [ { "value": "100.000", "resolve_type": "generated", "usage": "all" } ],
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+ "C_CLKOUT4_ACTUAL_FREQ": [ { "value": "100.000", "resolve_type": "generated", "usage": "all" } ],
+ "C_CLKOUT5_ACTUAL_FREQ": [ { "value": "100.000", "resolve_type": "generated", "usage": "all" } ],
+ "C_CLKOUT6_ACTUAL_FREQ": [ { "value": "100.000", "resolve_type": "generated", "usage": "all" } ],
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+ "C_M_MIN": [ { "value": "2.000", "resolve_type": "generated", "format": "float", "usage": "all" } ],
+ "C_D_MAX": [ { "value": "80.000", "resolve_type": "generated", "format": "float", "usage": "all" } ],
+ "C_D_MIN": [ { "value": "1.000", "resolve_type": "generated", "format": "float", "usage": "all" } ],
+ "C_O_MAX": [ { "value": "128.000", "resolve_type": "generated", "format": "float", "usage": "all" } ],
+ "C_O_MIN": [ { "value": "1.000", "resolve_type": "generated", "format": "float", "usage": "all" } ],
+ "C_VCO_MIN": [ { "value": "600.000", "resolve_type": "generated", "format": "float", "usage": "all" } ],
+ "C_VCO_MAX": [ { "value": "1200.000", "resolve_type": "generated", "format": "float", "usage": "all" } ]
+ },
+ "project_parameters": {
+ "ARCHITECTURE": [ { "value": "artix7" } ],
+ "BASE_BOARD_PART": [ { "value": "" } ],
+ "BOARD_CONNECTIONS": [ { "value": "" } ],
+ "DEVICE": [ { "value": "xc7a100t" } ],
+ "PACKAGE": [ { "value": "csg324" } ],
+ "PREFHDL": [ { "value": "VHDL" } ],
+ "SILICON_REVISION": [ { "value": "" } ],
+ "SIMULATOR_LANGUAGE": [ { "value": "VHDL" } ],
+ "SPEEDGRADE": [ { "value": "-1" } ],
+ "STATIC_POWER": [ { "value": "" } ],
+ "TEMPERATURE_GRADE": [ { "value": "" } ],
+ "USE_RDI_CUSTOMIZATION": [ { "value": "TRUE" } ],
+ "USE_RDI_GENERATION": [ { "value": "TRUE" } ]
+ },
+ "runtime_parameters": {
+ "IPCONTEXT": [ { "value": "IP_Flow" } ],
+ "IPREVISION": [ { "value": "11" } ],
+ "MANAGED": [ { "value": "TRUE" } ],
+ "OUTPUTDIR": [ { "value": "../../../../game.gen/sources_1/ip/clk_wiz_1" } ],
+ "SELECTEDSIMMODEL": [ { "value": "" } ],
+ "SHAREDDIR": [ { "value": "." } ],
+ "SWVERSION": [ { "value": "2022.2" } ],
+ "SYNTHESISFLOW": [ { "value": "GLOBAL" } ]
+ }
+ },
+ "boundary": {
+ "ports": {
+ "resetn": [ { "direction": "in", "driver_value": "0" } ],
+ "clk_in1": [ { "direction": "in" } ],
+ "clk_out1": [ { "direction": "out" } ]
+ },
+ "interfaces": {
+ "resetn": {
+ "vlnv": "xilinx.com:signal:reset:1.0",
+ "abstraction_type": "xilinx.com:signal:reset_rtl:1.0",
+ "mode": "slave",
+ "parameters": {
+ "POLARITY": [ { "value": "ACTIVE_LOW", "value_src": "constant", "usage": "all" } ],
+ "BOARD.ASSOCIATED_PARAM": [ { "value": "RESET_BOARD_INTERFACE", "value_src": "constant", "usage": "all" } ],
+ "INSERT_VIP": [ { "value": "0", "resolve_type": "user", "format": "long", "usage": "simulation.rtl", "is_ips_inferred": true, "is_static_object": false } ]
+ },
+ "port_maps": {
+ "RST": [ { "physical_name": "resetn" } ]
+ }
+ },
+ "clock_CLK_IN1": {
+ "vlnv": "xilinx.com:signal:clock:1.0",
+ "abstraction_type": "xilinx.com:signal:clock_rtl:1.0",
+ "mode": "slave",
+ "parameters": {
+ "FREQ_HZ": [ { "value": "100000000", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
+ "FREQ_TOLERANCE_HZ": [ { "value": "0", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
+ "PHASE": [ { "value": "0.0", "resolve_type": "generated", "format": "float", "is_ips_inferred": true, "is_static_object": false } ],
+ "CLK_DOMAIN": [ { "value": "", "resolve_type": "generated", "is_ips_inferred": true, "is_static_object": false } ],
+ "ASSOCIATED_BUSIF": [ { "value": "", "resolve_type": "generated", "is_ips_inferred": true, "is_static_object": false } ],
+ "ASSOCIATED_PORT": [ { "value": "", "resolve_type": "generated", "is_ips_inferred": true, "is_static_object": false } ],
+ "ASSOCIATED_RESET": [ { "value": "", "resolve_type": "generated", "is_ips_inferred": true, "is_static_object": false } ],
+ "INSERT_VIP": [ { "value": "0", "resolve_type": "user", "format": "long", "usage": "simulation.rtl", "is_ips_inferred": true, "is_static_object": false } ],
+ "BOARD.ASSOCIATED_PARAM": [ { "value": "CLK_IN1_BOARD_INTERFACE", "usage": "all", "is_static_object": false } ]
+ },
+ "port_maps": {
+ "CLK_IN1": [ { "physical_name": "clk_in1" } ]
+ }
+ },
+ "clock_CLK_OUT1": {
+ "vlnv": "xilinx.com:signal:clock:1.0",
+ "abstraction_type": "xilinx.com:signal:clock_rtl:1.0",
+ "mode": "master",
+ "parameters": {
+ "FREQ_HZ": [ { "value": "100000000", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
+ "FREQ_TOLERANCE_HZ": [ { "value": "0", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
+ "PHASE": [ { "value": "0.0", "resolve_type": "generated", "format": "float", "is_ips_inferred": true, "is_static_object": false } ],
+ "CLK_DOMAIN": [ { "value": "", "resolve_type": "generated", "is_ips_inferred": true, "is_static_object": false } ],
+ "ASSOCIATED_BUSIF": [ { "value": "", "resolve_type": "generated", "is_ips_inferred": true, "is_static_object": false } ],
+ "ASSOCIATED_PORT": [ { "value": "", "resolve_type": "generated", "is_ips_inferred": true, "is_static_object": false } ],
+ "ASSOCIATED_RESET": [ { "value": "", "resolve_type": "generated", "is_ips_inferred": true, "is_static_object": false } ],
+ "INSERT_VIP": [ { "value": "0", "resolve_type": "user", "format": "long", "usage": "simulation.rtl", "is_ips_inferred": true, "is_static_object": false } ]
+ },
+ "port_maps": {
+ "CLK_OUT1": [ { "physical_name": "clk_out1" } ]
+ }
+ }
+ }
+ }
+ }
+}
\ No newline at end of file
diff --git a/game.srcs/sources_1/new/TopModule.vhd b/game.srcs/sources_1/new/TopModule.vhd
new file mode 100644
index 0000000000000000000000000000000000000000..a75750384a62173fd02cf137828959aacfb212be
--- /dev/null
+++ b/game.srcs/sources_1/new/TopModule.vhd
@@ -0,0 +1,256 @@
+----------------------------------------------------------------------------------
+-- Company:
+-- Engineer:
+--
+-- Create Date: 02/27/2023 10:26:07 AM
+-- Design Name:
+-- Module Name: TopModule - Behavioral
+-- Project Name:
+-- Target Devices:
+-- Tool Versions:
+-- Description:
+--
+-- Dependencies:
+--
+-- Revision:
+-- Revision 0.01 - File Created
+-- Additional Comments:
+--
+----------------------------------------------------------------------------------
+
+
+library IEEE;
+use IEEE.STD_LOGIC_1164.ALL;
+use work.jumpnrun_sizes.all;
+
+-- Uncomment the following library declaration if using
+-- arithmetic functions with Signed or Unsigned values
+--use IEEE.NUMERIC_STD.ALL;
+
+-- Uncomment the following library declaration if instantiating
+-- any Xilinx leaf cells in this code.
+--library UNISIM;
+--use UNISIM.VComponents.all;
+
+entity TopModule is
+ port( clk, btnCpuReset : in std_logic;
+ btnU : in std_logic;
+ vgaRed : out std_logic_vector(3 downto 0);
+ vgaBlue : out std_logic_vector(3 downto 0);
+ vgaGreen : out std_logic_vector(3 downto 0);
+ Hsync, Vsync : out std_logic;
+ led : out std_logic_vector (15 downto 0)
+ );
+end TopModule;
+
+architecture Behavioral of TopModule is
+
+component clk_wiz_0
+ port ( clk_out1 : out std_logic;
+ resetn : in std_logic;
+ clk_in1 : in std_logic
+ );
+end component clk_wiz_0;
+
+component vga
+ port (
+ clk_pixel, btnCpuReset_v : in std_logic;
+ color : in std_logic_vector (11 downto 0);
+ vgaRed_v : out std_logic_vector(3 downto 0);
+ vgaBlue_v : out std_logic_vector(3 downto 0);
+ vgaGreen_v : out std_logic_vector(3 downto 0);
+ Hsync_v, Vsync_v : out std_logic;
+ HCounter : out integer range 1 to 800;
+ VCounter : out integer range 1 to 525;
+ FCounter : out integer range 0 to MAX_FCOUNNT-1;
+ FStrobe : out std_logic
+ );
+end component vga;
+
+component priority
+ Port (
+ color_prio : out std_logic_vector(11 downto 0);
+ en_runner : in boolean;
+ en_back : in boolean;
+ en_obstacleS: in boolean;
+ en_obstacleL: in boolean;
+ color_runner : in std_logic_vector(11 downto 0);
+ color_back : in std_logic_vector(11 downto 0);
+ color_obstacleS: in std_logic_vector(11 downto 0);
+ color_obstacleL: in std_logic_vector(11 downto 0)
+ );
+end component priority;
+
+component runner
+ Port (clk_pixel: in std_logic;
+ btnU_r : in std_logic;
+ btnCpuReset_r : in std_logic;
+ HCounter_r : in integer range 1 to 800;
+ VCounter_r : in integer range 1 to 525;
+ FCounter_r : in integer range 0 to MAX_FCOUNNT-1;
+ FStrobe_r : in std_logic;
+ color_runner : out std_logic_vector (11 downto 0);
+ exists_runner : out boolean
+ );
+end component runner;
+
+component background is
+ Port (clk_pixel, btnCpuReset_b : in std_logic;
+ HCounter_b : in integer range 1 to 800;
+ VCounter_b : in integer range 1 to 525;
+ FCounter_b : in integer range 0 to MAX_FCOUNNT-1;
+ FStrobe_b : in std_logic;
+ color_back: out std_logic_vector (11 downto 0);
+ exists_back : out boolean
+ );
+end component background;
+
+component obstacle_S is
+ Port (clk_pixel: in std_logic;
+ btnCpuReset_o : in std_logic;
+ HCounter_o : in integer range 1 to 800;
+ VCounter_o : in integer range 1 to 525;
+ FCounter_o : in integer range 0 to MAX_FCOUNNT-1;
+ FStrobe_o : in std_logic;
+ color_obstacle : out std_logic_vector (11 downto 0);
+ exists_obstacle : out boolean
+ );
+ end component obstacle_S;
+
+component obstacle_L is
+ Port (clk_pixel: in std_logic;
+ btnCpuReset_o : in std_logic;
+ HCounter_o : in integer range 1 to 800;
+ VCounter_o : in integer range 1 to 525;
+ FCounter_o : in integer range 0 to MAX_FCOUNNT-1;
+ FStrobe_o : in std_logic;
+ color_obstacle : out std_logic_vector (11 downto 0);
+ exists_obstacle : out boolean
+ );
+end component obstacle_L;
+
+component collision is
+ Port (
+ clk_pixel: in std_logic;
+ btnCpuReset_c : in std_logic;
+ en_runner : in boolean;
+ en_obstacleS : in boolean;
+ en_obstacleL: in boolean;
+ led : out std_logic_vector(15 downto 0)
+ );
+end component collision;
+
+
+
+-- Signals
+signal clk25 : std_logic;
+
+signal color_sig : std_logic_vector (11 downto 0);
+signal color_runner_sig : std_logic_vector (11 downto 0);
+signal color_background_sig : std_logic_vector (11 downto 0);
+signal color_obstacleS_sig : std_logic_vector (11 downto 0);
+signal color_obstacleL_sig : std_logic_vector (11 downto 0);
+
+
+signal hcounter_sig : integer range 1 to 800;
+signal vcounter_sig : integer range 1 to 525;
+signal fcounter_sig : integer range 0 to MAX_FCOUNNT-1;
+signal fstrobe_sig : std_logic;
+
+signal exist_runner_sig : boolean;
+signal exist_background_sig : boolean;
+signal exists_obstacleS_sig : boolean;
+signal exists_obstacleL_sig : boolean;
+
+begin
+
+pixelClk : clk_wiz_0
+ port map( clk_in1 => clk,
+ resetn => btnCpuReset,
+ clk_out1 => clk25);
+
+vgaInterface : vga
+ port map(
+ clk_pixel => clk25,
+ btnCpuReset_v => btnCpuReset,
+ color => color_sig,
+ vgaRed_v => vgaRed,
+ vgaBlue_v => vgaBlue,
+ vgaGreen_v => vgaGreen,
+ Hsync_v => Hsync,
+ Vsync_v => Vsync,
+ HCounter => hcounter_sig,
+ VCounter => vcounter_sig,
+ FCounter => fcounter_sig,
+ FStrobe => fstrobe_sig
+ );
+
+priorityLogic : priority
+ port map (
+ color_prio => color_sig,
+ en_runner => exist_runner_sig,
+ en_back => exist_background_sig,
+ color_runner => color_runner_sig,
+ color_back => color_background_sig,
+ color_obstacleS => color_obstacleS_sig,
+ en_obstacleS => exists_obstacleS_sig,
+ color_obstacleL => color_obstacleL_sig,
+ en_obstacleL => exists_obstacleL_sig
+ );
+
+runnerObject : runner
+ port map (
+ clk_pixel => clk25,
+ btnU_r => btnU,
+ btnCpuReset_r => btnCpuReset,
+ HCounter_r => hcounter_sig,
+ VCounter_r => vcounter_sig,
+ FCounter_r => fcounter_sig,
+ FStrobe_r => fstrobe_sig,
+ color_runner => color_runner_sig,
+ exists_runner => exist_runner_sig
+ );
+
+backgroundObject : background
+ port map (
+ clk_pixel => clk25,
+ btnCpuReset_b => btnCpuReset,
+ HCounter_b => hcounter_sig,
+ VCounter_b => vcounter_sig,
+ FCounter_b => fcounter_sig,
+ FStrobe_b => fstrobe_sig,
+ color_back => color_background_sig,
+ exists_back => exist_background_sig
+ );
+smallObstacle : obstacle_S
+ port map (clk_pixel => clk25,
+ btnCpuReset_o=> btnCpuReset,
+ HCounter_o => hcounter_sig,
+ VCounter_o => vcounter_sig,
+ FCounter_o => fcounter_sig,
+ FStrobe_o => fstrobe_sig,
+ color_obstacle => color_obstacleS_sig,
+ exists_obstacle => exists_obstacleS_sig
+ );
+largeObstacle : obstacle_L
+ Port map(clk_pixel => clk25,
+ btnCpuReset_o => btnCpuReset,
+ HCounter_o => hcounter_sig,
+ VCounter_o => vcounter_sig,
+ FCounter_o => fcounter_sig,
+ FStrobe_o => fstrobe_sig,
+ color_obstacle => color_obstacleL_sig,
+ exists_obstacle => exists_obstacleL_sig
+ );
+
+
+ collisionDetection : collision
+ port map(
+ clk_pixel => clk25,
+ btnCpuReset_c => btnCpuReset,
+ en_runner => exist_runner_sig,
+ en_obstacleS => exists_obstacleS_sig,
+ en_obstacleL => exists_obstacleL_sig,
+ led => led
+ );
+end Behavioral;
diff --git a/game.srcs/sources_1/new/background.vhd b/game.srcs/sources_1/new/background.vhd
new file mode 100644
index 0000000000000000000000000000000000000000..0e5416cecac23db508a37262d61c8f95d7c911b1
--- /dev/null
+++ b/game.srcs/sources_1/new/background.vhd
@@ -0,0 +1,61 @@
+----------------------------------------------------------------------------------
+-- Company:
+-- Engineer:
+--
+-- Create Date: 02/27/2023 03:21:55 PM
+-- Design Name:
+-- Module Name: background - Behavioral
+-- Project Name:
+-- Target Devices:
+-- Tool Versions:
+-- Description:
+--
+-- Dependencies:
+--
+-- Revision:
+-- Revision 0.01 - File Created
+-- Additional Comments:
+--
+----------------------------------------------------------------------------------
+
+
+library IEEE;
+use IEEE.STD_LOGIC_1164.ALL;
+use work.jumpnrun_sizes.all;
+
+-- Uncomment the following library declaration if using
+-- arithmetic functions with Signed or Unsigned values
+--use IEEE.NUMERIC_STD.ALL;
+
+-- Uncomment the following library declaration if instantiating
+-- any Xilinx leaf cells in this code.
+--library UNISIM;
+--use UNISIM.VComponents.all;
+
+entity background is
+ Port (clk_pixel, btnCpuReset_b : in std_logic;
+ HCounter_b : in integer range 1 to 800;
+ VCounter_b : in integer range 1 to 525;
+ FCounter_b : in integer range 0 to 4095;
+ FStrobe_b : in std_logic;
+ color_back: out std_logic_vector (11 downto 0);
+ exists_back : out boolean
+ );end background;
+
+architecture Behavioral of background is
+
+begin
+exists_back <= true;
+
+-- Draw background
+process(VCounter_b)
+begin
+if (VCounter_b > GROUND_LEVEL) then
+ color_back <= x"4F5";
+ else
+ color_back <= x"49F";
+ end if;
+end process;
+
+
+end Behavioral;
diff --git a/game.srcs/sources_1/new/collision.vhd b/game.srcs/sources_1/new/collision.vhd
new file mode 100644
index 0000000000000000000000000000000000000000..756c1c890f1fa99c9ac52cbf571dd6e619d84ec1
--- /dev/null
+++ b/game.srcs/sources_1/new/collision.vhd
@@ -0,0 +1,68 @@
+----------------------------------------------------------------------------------
+-- Company:
+-- Engineer:
+--
+-- Create Date: 02/28/2023 03:34:56 PM
+-- Design Name:
+-- Module Name: collision - Behavioral
+-- Project Name:
+-- Target Devices:
+-- Tool Versions:
+-- Description:
+--
+-- Dependencies:
+--
+-- Revision:
+-- Revision 0.01 - File Created
+-- Additional Comments:
+--
+----------------------------------------------------------------------------------
+
+
+library IEEE;
+use IEEE.STD_LOGIC_1164.ALL;
+
+-- Uncomment the following library declaration if using
+-- arithmetic functions with Signed or Unsigned values
+--use IEEE.NUMERIC_STD.ALL;
+
+-- Uncomment the following library declaration if instantiating
+-- any Xilinx leaf cells in this code.
+--library UNISIM;
+--use UNISIM.VComponents.all;
+
+entity collision is
+ Port (
+ clk_pixel: in std_logic;
+ btnCpuReset_c : in std_logic;
+ en_runner : in boolean;
+ en_obstacleS : in boolean;
+ en_obstacleL: in boolean;
+ led : out std_logic_vector(15 downto 0)
+ );
+end collision;
+
+architecture Behavioral of collision is
+signal collision_cnt : std_logic_vector(15 downto 0);
+
+begin
+led <= collision_cnt;
+
+process(clk_pixel)
+ begin
+ if btnCpuReset_c = '0' then
+ collision_cnt <= x"0000";
+ elsif rising_edge(clk_pixel) then
+ if en_runner = true and (en_obstacleS = true or en_obstacleL = true) then
+ -- collision
+ if collision_cnt = x"FFFF" then --overflow
+ collision_cnt <= x"0000";
+ else
+ collision_cnt <= '1' & collision_cnt(15 downto 1);
+ end if;
+ else
+ collision_cnt <= collision_cnt;
+ end if;
+ end if;
+end process;
+end Behavioral;
diff --git a/game.srcs/sources_1/new/header.vhd b/game.srcs/sources_1/new/header.vhd
new file mode 100644
index 0000000000000000000000000000000000000000..ee61bd7c65ed672e20a4eb59feb576b0625fae92
--- /dev/null
+++ b/game.srcs/sources_1/new/header.vhd
@@ -0,0 +1,62 @@
+----------------------------------------------------------------------------------
+-- Company:
+-- Engineer:
+--
+-- Create Date: 02/28/2023 01:53:05 PM
+-- Design Name:
+-- Module Name: header - Behavioral
+-- Project Name:
+-- Target Devices:
+-- Tool Versions:
+-- Description:
+--
+-- Dependencies:
+--
+-- Revision:
+-- Revision 0.01 - File Created
+-- Additional Comments:
+--
+----------------------------------------------------------------------------------
+
+
+library IEEE;
+use IEEE.STD_LOGIC_1164.ALL;
+
+-- Uncomment the following library declaration if using
+-- arithmetic functions with Signed or Unsigned values
+--use IEEE.NUMERIC_STD.ALL;
+
+-- Uncomment the following library declaration if instantiating
+-- any Xilinx leaf cells in this code.
+--library UNISIM;
+--use UNISIM.VComponents.all;
+
+package jumpnrun_sizes is
+-- Framecounter
+constant MAX_FCOUNNT : integer := 65536;
+
+-- Obstacles
+constant LENGTH_SMALL_OBSTACLE: integer:= 15; --px
+constant HEIGTH_SMALL_OBSTACLE: integer:= 25; --px
+
+constant LENGTH_BIG_OBSTACLE: integer:= 15; --px
+constant HEIGTH_BIG_OBSTACLE: integer:= 50; --px
+
+constant GROUND_LEVEL : integer range 1 to 480 := 350;
+constant MOVE_INCREMENT : integer := 2; --px per frame
+
+constant VIRTUAL_SCREEN_LENGTH : integer := 1500; --px per frame
+
+constant OBST_L_START : integer := 1000; --px per frame
+
+-- Runner
+constant POS_X_RUNNER : integer := 100;
+constant LENGTH_RUNNER: integer:= 30; --px
+constant HEIGTH_RUNNER: integer:= 50; --px
+constant JUMP_HEIGTH : integer := 200; --px
+constant JUMP_INCREMENT : integer := 3; --px per frame
+-- 1 sec = 30 px jump incl. landing
+
+
+
+end package jumpnrun_sizes;
diff --git a/game.srcs/sources_1/new/obstacle.vhd b/game.srcs/sources_1/new/obstacle.vhd
new file mode 100644
index 0000000000000000000000000000000000000000..0aa211dc7c113171562f8be2a18460531c32554c
--- /dev/null
+++ b/game.srcs/sources_1/new/obstacle.vhd
@@ -0,0 +1,110 @@
+----------------------------------------------------------------------------------
+-- Company:
+-- Engineer:
+--
+-- Create Date: 02/28/2023 01:35:16 PM
+-- Design Name:
+-- Module Name: obstacle - Behavioral
+-- Project Name:
+-- Target Devices:
+-- Tool Versions:
+-- Description:
+--
+-- Dependencies:
+--
+-- Revision:
+-- Revision 0.01 - File Created
+-- Additional Comments:
+--
+----------------------------------------------------------------------------------
+
+
+library IEEE;
+use IEEE.STD_LOGIC_1164.ALL;
+
+use work.jumpnrun_sizes.all;
+
+-- Uncomment the following library declaration if using
+-- arithmetic functions with Signed or Unsigned values
+--use IEEE.NUMERIC_STD.ALL;
+
+-- Uncomment the following library declaration if instantiating
+-- any Xilinx leaf cells in this code.
+--library UNISIM;
+--use UNISIM.VComponents.all;
+
+entity obstacle_S is
+ Port (clk_pixel: in std_logic;
+ btnCpuReset_o : in std_logic;
+ HCounter_o : in integer range 1 to 800;
+ VCounter_o : in integer range 1 to 525;
+ FCounter_o : in integer range 0 to MAX_FCOUNNT-1;
+ FStrobe_o : in std_logic;
+ color_obstacle : out std_logic_vector (11 downto 0);
+ exists_obstacle : out boolean
+ );end obstacle_S;
+
+architecture Behavioral of obstacle_S is
+-- Signals
+signal pos_object_x_actual : integer range 1 to 640;
+signal pos_object_x_target : integer range 1 to VIRTUAL_SCREEN_LENGTH;
+
+signal pos_object_y_actual : integer range 1 to 480;
+signal pos_object_y_target: integer range 1 to 480;
+
+
+-- Constants
+
+
+
+begin
+-- Logic
+pos_object_y_target <= GROUND_LEVEL;
+
+
+
+-- detect Frame Strobe
+process(clk_pixel)
+begin
+ if rising_edge(clk_pixel) then
+ if FStrobe_o = '1' then
+ pos_object_x_actual <= pos_object_x_target;
+ pos_object_y_actual <= pos_object_y_target;
+ else
+ pos_object_y_actual <= pos_object_y_actual;
+ pos_object_x_actual <= pos_object_x_actual;
+ end if;
+ end if;
+end process;
+
+-- Draw object
+process(HCounter_o, VCounter_o)
+begin
+if (HCounter_o < (pos_object_x_actual + LENGTH_SMALL_OBSTACLE) and HCounter_o >= pos_object_x_actual and VCounter_o > (pos_object_y_actual - HEIGTH_SMALL_OBSTACLE) and VCounter_o <= pos_object_y_actual) then
+ exists_obstacle <= true;
+ color_obstacle <= x"D33";
+ else
+ exists_obstacle <= false;
+ color_obstacle <= x"000";
+ end if;
+end process;
+
+-- Move object
+process(clk_pixel)
+begin
+ if btnCpuReset_o = '0' then
+ pos_object_x_target <= 640;
+ elsif rising_edge(clk_pixel) then
+ if FStrobe_o = '1' then
+ if pos_object_x_target <= 1 or pos_object_x_target >= VIRTUAL_SCREEN_LENGTH then
+ pos_object_x_target <= 640;
+ else
+ pos_object_x_target <= pos_object_x_target - MOVE_INCREMENT;
+ end if;
+ else
+ pos_object_x_target <= pos_object_x_target;
+ end if;
+ end if;
+end process;
+
+end Behavioral;
diff --git a/game.srcs/sources_1/new/obstacle2.vhd b/game.srcs/sources_1/new/obstacle2.vhd
new file mode 100644
index 0000000000000000000000000000000000000000..939d3804756dbd63e6584bd98b875fd91b3dbbe5
--- /dev/null
+++ b/game.srcs/sources_1/new/obstacle2.vhd
@@ -0,0 +1,110 @@
+----------------------------------------------------------------------------------
+-- Company:
+-- Engineer:
+--
+-- Create Date: 02/28/2023 01:35:16 PM
+-- Design Name:
+-- Module Name: obstacle2 - Behavioral
+-- Project Name:
+-- Target Devices:
+-- Tool Versions:
+-- Description:
+--
+-- Dependencies:
+--
+-- Revision:
+-- Revision 0.01 - File Created
+-- Additional Comments:
+--
+----------------------------------------------------------------------------------
+
+
+library IEEE;
+use IEEE.STD_LOGIC_1164.ALL;
+
+use work.jumpnrun_sizes.all;
+
+-- Uncomment the following library declaration if using
+-- arithmetic functions with Signed or Unsigned values
+--use IEEE.NUMERIC_STD.ALL;
+
+-- Uncomment the following library declaration if instantiating
+-- any Xilinx leaf cells in this code.
+--library UNISIM;
+--use UNISIM.VComponents.all;
+
+entity obstacle_L is
+ Port (clk_pixel: in std_logic;
+ btnCpuReset_o : in std_logic;
+ HCounter_o : in integer range 1 to 800;
+ VCounter_o : in integer range 1 to 525;
+ FCounter_o : in integer range 0 to MAX_FCOUNNT-1;
+ FStrobe_o : in std_logic;
+ color_obstacle : out std_logic_vector (11 downto 0);
+ exists_obstacle : out boolean
+ );end obstacle_L;
+
+architecture Behavioral of obstacle_L is
+-- Signals
+signal pos_object_x_actual : integer range 1 to 640;
+signal pos_object_x_target : integer range 1 to VIRTUAL_SCREEN_LENGTH;
+
+signal pos_object_y_actual : integer range 1 to 480;
+signal pos_object_y_target: integer range 1 to 480;
+
+
+-- Constants
+
+
+
+begin
+-- Logic
+pos_object_y_target <= GROUND_LEVEL;
+
+
+
+-- detect Frame Strobe
+process(clk_pixel)
+begin
+ if rising_edge(clk_pixel) then
+ if FStrobe_o = '1' then
+ pos_object_x_actual <= pos_object_x_target;
+ pos_object_y_actual <= pos_object_y_target;
+ else
+ pos_object_y_actual <= pos_object_y_actual;
+ pos_object_x_actual <= pos_object_x_actual;
+ end if;
+ end if;
+end process;
+
+-- Draw object
+process(HCounter_o, VCounter_o)
+begin
+if (HCounter_o < (pos_object_x_actual + LENGTH_BIG_OBSTACLE) and HCounter_o >= pos_object_x_actual and VCounter_o > (pos_object_y_actual - HEIGTH_BIG_OBSTACLE) and VCounter_o <= pos_object_y_actual) then
+ exists_obstacle <= true;
+ color_obstacle <= x"D33";
+ else
+ exists_obstacle <= false;
+ color_obstacle <= x"000";
+ end if;
+end process;
+
+-- Move object
+process(clk_pixel)
+begin
+ if btnCpuReset_o = '0' then
+ pos_object_x_target <= OBST_L_START;
+ elsif rising_edge(clk_pixel) then
+ if FStrobe_o = '1' then
+ if pos_object_x_target <= 1 or pos_object_x_target >= VIRTUAL_SCREEN_LENGTH then
+ pos_object_x_target <= OBST_L_START;
+ else
+ pos_object_x_target <= pos_object_x_target - MOVE_INCREMENT;
+ end if;
+ else
+ pos_object_x_target <= pos_object_x_target;
+ end if;
+ end if;
+end process;
+
+end Behavioral;
diff --git a/game.srcs/sources_1/new/priority.vhd b/game.srcs/sources_1/new/priority.vhd
new file mode 100644
index 0000000000000000000000000000000000000000..1323426eb7b6bdd70323d716c73df57197f908d5
--- /dev/null
+++ b/game.srcs/sources_1/new/priority.vhd
@@ -0,0 +1,67 @@
+----------------------------------------------------------------------------------
+-- Company:
+-- Engineer:
+--
+-- Create Date: 02/27/2023 03:21:55 PM
+-- Design Name:
+-- Module Name: priority - Behavioral
+-- Project Name:
+-- Target Devices:
+-- Tool Versions:
+-- Description:
+--
+-- Dependencies:
+--
+-- Revision:
+-- Revision 0.01 - File Created
+-- Additional Comments:
+--
+----------------------------------------------------------------------------------
+
+
+library IEEE;
+use IEEE.STD_LOGIC_1164.ALL;
+
+-- Uncomment the following library declaration if using
+-- arithmetic functions with Signed or Unsigned values
+--use IEEE.NUMERIC_STD.ALL;
+
+-- Uncomment the following library declaration if instantiating
+-- any Xilinx leaf cells in this code.
+--library UNISIM;
+--use UNISIM.VComponents.all;
+
+entity priority is
+ Port (
+ color_prio : out std_logic_vector(11 downto 0);
+ en_runner : in boolean;
+ en_back : in boolean;
+ en_obstacleS: in boolean;
+ en_obstacleL: in boolean;
+ color_runner : in std_logic_vector(11 downto 0);
+ color_back : in std_logic_vector(11 downto 0);
+ color_obstacleS: in std_logic_vector(11 downto 0);
+ color_obstacleL: in std_logic_vector(11 downto 0)
+ );
+end priority;
+
+architecture Behavioral of priority is
+
+begin
+
+process(en_runner)
+begin
+ if en_runner = true then
+ color_prio <= color_runner;
+ elsif en_obstacleS = true then
+ color_prio <= color_obstacleS;
+ elsif en_obstacleL = true then
+ color_prio <= color_obstacleL;
+ elsif en_back = true then
+ color_prio <= color_back;
+ else
+ color_prio <= x"000";
+ end if;
+end process;
+
+end Behavioral;
diff --git a/game.srcs/sources_1/new/runner.vhd b/game.srcs/sources_1/new/runner.vhd
new file mode 100644
index 0000000000000000000000000000000000000000..d490f2fbc7b52a82c30639133f1b4b9c6bcc4a7d
--- /dev/null
+++ b/game.srcs/sources_1/new/runner.vhd
@@ -0,0 +1,147 @@
+----------------------------------------------------------------------------------
+-- Company:
+-- Engineer:
+--
+-- Create Date: 02/27/2023 03:21:55 PM
+-- Design Name:
+-- Module Name: runner - Behavioral
+-- Project Name:
+-- Target Devices:
+-- Tool Versions:
+-- Description:
+--
+-- Dependencies:
+--
+-- Revision:
+-- Revision 0.01 - File Created
+-- Additional Comments:
+--
+----------------------------------------------------------------------------------
+
+
+library IEEE;
+use IEEE.STD_LOGIC_1164.ALL;
+
+use work.jumpnrun_sizes.all;
+
+-- Uncomment the following library declaration if using
+-- arithmetic functions with Signed or Unsigned values
+--use IEEE.NUMERIC_STD.ALL;
+
+-- Uncomment the following library declaration if instantiating
+-- any Xilinx leaf cells in this code.
+--library UNISIM;
+--use UNISIM.VComponents.all;
+
+entity runner is
+ Port (clk_pixel: in std_logic;
+ btnU_r : in std_logic;
+ btnCpuReset_r : in std_logic;
+ HCounter_r : in integer range 1 to 800;
+ VCounter_r : in integer range 1 to 525;
+ FCounter_r : in integer range 0 to MAX_FCOUNNT-1;
+ FStrobe_r : in std_logic;
+ color_runner : out std_logic_vector (11 downto 0);
+ exists_runner : out boolean
+ );
+
+end runner;
+
+architecture Behavioral of runner is
+
+
+signal pos_object_x_actual : integer range 1 to 640;
+signal pos_object_x_target : integer range 1 to 640;
+
+signal pos_object_y_actual : integer range 1 to 480;
+signal pos_object_y_target: integer range 1 to 480;
+
+signal fcount_edge : integer range 0 to MAX_FCOUNNT-1;
+signal FCounter_17bit : integer range 0 to MAX_FCOUNNT-1 * 2;
+signal runner_not_landed : std_logic; -- after jump finished
+
+
+signal button_up_shift_reg : std_logic_vector(1 downto 0);
+
+
+
+begin
+pos_object_x_target <= POS_X_RUNNER;
+FCounter_17bit <= MAX_FCOUNNT-1 + FCounter_r;
+
+-- Draw object
+process(HCounter_r, VCounter_r)
+begin
+if (HCounter_r < (pos_object_x_actual + LENGTH_RUNNER) and HCounter_r >= pos_object_x_actual and VCounter_r > (pos_object_y_actual - HEIGTH_RUNNER) and VCounter_r <= pos_object_y_actual) then
+ exists_runner <= true;
+ color_runner <= x"E2F";
+ else
+ exists_runner <= false;
+ color_runner <= x"000";
+ end if;
+end process;
+
+-- detect edge Button UP
+process(clk_pixel)
+begin
+ if btnCpuReset_r = '0' then
+ fcount_edge <= 0;
+ button_up_shift_reg <= "00";
+ elsif rising_edge(clk_pixel) then
+ button_up_shift_reg <= button_up_shift_reg(0) & btnU_r; -- put current button value into shift register
+ if (btnU_r = '1') and (button_up_shift_reg(0)= '0') and runner_not_landed = '0' then -- if rising edge (btnU)
+ fcount_edge <= FCounter_r;
+ else
+ fcount_edge <= fcount_edge;
+ end if;
+ end if;
+end process;
+
+-- Jump process
+process(clk_pixel)
+begin
+ if rising_edge(clk_pixel) then
+ if FStrobe_r = '1' then
+ if ((FCounter_17bit - fcount_edge) mod MAX_FCOUNNT-1) < JUMP_HEIGTH/JUMP_INCREMENT then
+ if pos_object_y_target > 0 then
+ pos_object_y_target <= pos_object_y_target - JUMP_INCREMENT;
+ else
+ pos_object_y_target <= pos_object_y_target;
+ end if;
+ runner_not_landed <= '1';
+ elsif (((FCounter_17bit - fcount_edge) mod MAX_FCOUNNT-1) >= JUMP_HEIGTH/JUMP_INCREMENT) and (((FCounter_17bit - fcount_edge) mod MAX_FCOUNNT-1) < 2 * JUMP_HEIGTH/JUMP_INCREMENT) then
+ if pos_object_y_target < 480 then
+ pos_object_y_target <= pos_object_y_target + JUMP_INCREMENT;
+ else
+ pos_object_y_target <= pos_object_y_target;
+ end if;
+ runner_not_landed <= '1';
+ else
+ pos_object_y_target <= GROUND_LEVEL;
+ runner_not_landed <= '0';
+ end if;
+ else
+ pos_object_y_target <= pos_object_y_target;
+ runner_not_landed <= runner_not_landed;
+ end if;
+ end if;
+end process;
+
+
+
+-- detect Frame Strobe
+process(clk_pixel)
+begin
+ if rising_edge(clk_pixel) then
+ if FStrobe_r = '1' then
+ pos_object_y_actual <= pos_object_y_target;
+ pos_object_x_actual <= pos_object_x_target;
+ else
+ pos_object_y_actual <= pos_object_y_actual;
+ pos_object_x_actual <= pos_object_x_actual;
+ end if;
+ end if;
+end process;
+
+
+end Behavioral;
diff --git a/game.srcs/sources_1/new/vga.vhd b/game.srcs/sources_1/new/vga.vhd
new file mode 100644
index 0000000000000000000000000000000000000000..2674f22259ad7dd3182187ff75e47dd0779cf213
--- /dev/null
+++ b/game.srcs/sources_1/new/vga.vhd
@@ -0,0 +1,144 @@
+----------------------------------------------------------------------------------
+-- Company:
+-- Engineer:
+--
+-- Create Date: 02/27/2023 11:46:01 AM
+-- Design Name:
+-- Module Name: vga - Behavioral
+-- Project Name:
+-- Target Devices:
+-- Tool Versions:
+-- Description:
+--
+-- Dependencies:
+--
+-- Revision:
+-- Revision 0.01 - File Created
+-- Additional Comments:
+--
+----------------------------------------------------------------------------------
+
+
+library IEEE;
+use IEEE.STD_LOGIC_1164.ALL;
+
+-- Uncomment the following library declaration if using
+-- arithmetic functions with Signed or Unsigned values
+--use IEEE.NUMERIC_STD.ALL;
+
+-- Uncomment the following library declaration if instantiating
+-- any Xilinx leaf cells in this code.
+--library UNISIM;
+--use UNISIM.VComponents.all;
+
+entity vga is
+ Port ( clk_pixel, btnCpuReset_v : in std_logic;
+ color : in std_logic_vector (11 downto 0);
+ vgaRed_v : out std_logic_vector(3 downto 0);
+ vgaBlue_v : out std_logic_vector(3 downto 0);
+ vgaGreen_v : out std_logic_vector(3 downto 0);
+ Hsync_v, Vsync_v : out std_logic;
+ HCounter : out integer range 1 to 800;
+ VCounter : out integer range 1 to 525;
+ FCounter : out integer range 0 to 4095;
+ FStrobe : out std_logic
+ );
+end vga;
+
+architecture Behavioral of vga is
+-- Components
+
+
+-- Signals
+signal counter_h : integer range 1 to 800;
+signal counter_v : integer range 1 to 525;
+signal counter_f : integer range 0 to 4095;
+
+
+begin
+
+
+-- Horicontal counter
+process(clk_pixel, btnCpuReset_v)
+
+begin
+ if (btnCpuReset_v = '0') then
+ counter_h <= 1;
+ counter_v <= 1;
+ counter_f <= 0;
+ elsif rising_edge(clk_pixel) then
+ if (counter_h < 800) then
+ counter_h <= counter_h + 1;
+ else
+ counter_h <= 1;
+ --Vertical counter
+ if (counter_v < 525) then
+ counter_v <= counter_v + 1;
+ else
+ counter_v <= 1;
+ --Frame counter
+ if (counter_f < 4095) then
+ counter_f <= counter_f + 1;
+ else
+ counter_f <= 0;
+ end if;
+ end if;
+ end if;
+ end if;
+end process;
+
+-- Hsync logic
+process(counter_h, counter_v)
+begin
+ if counter_h > 656 and counter_h <= 752 then
+ Hsync_v <= '0';
+ else
+ Hsync_v <= '1';
+ end if;
+
+ if counter_v > 490 and counter_v <= 492 then
+ Vsync_v <= '0';
+ else
+ Vsync_v <= '1';
+ end if;
+
+
+ if (counter_h <= 640 and counter_v <= 480) then
+ vgaRed_v <= color (11 downto 8);
+ vgaGreen_v <= color (7 downto 4);
+ vgaBlue_v <= color (3 downto 0);
+ else
+ vgaRed_v <= x"0";
+ vgaGreen_v <= x"0";
+ vgaBlue_v <= x"0";
+ end if;
+
+ -- TEST
+ if (counter_h = 640 or counter_v = 480 or counter_h = 1 or counter_v = 1) then
+ vgaRed_v <= x"0";
+ vgaGreen_v <= x"0";
+ vgaBlue_v <= x"F";
+ end if;
+
+ if (counter_h > 640 or counter_v > 480) then
+ vgaRed_v <= x"0";
+ vgaGreen_v <= x"0";
+ vgaBlue_v <= x"0";
+ end if;
+
+ -- TEST END
+
+ if (counter_h = 800 and counter_v = 525) then
+ FStrobe <= '1';
+ else
+ FStrobe <= '0';
+ end if;
+
+ end process;
+
+Vcounter <= counter_v;
+Hcounter <= counter_h;
+FCounter <= counter_f;
+
+
+end Behavioral;
diff --git a/game.srcs/utils_1/imports/synth_1/TopModule.dcp b/game.srcs/utils_1/imports/synth_1/TopModule.dcp
new file mode 100755
index 0000000000000000000000000000000000000000..20fa75c97f7424a88a9c20eb25782e289e6afb6b
Binary files /dev/null and b/game.srcs/utils_1/imports/synth_1/TopModule.dcp differ
diff --git a/game.xpr b/game.xpr
new file mode 100644
index 0000000000000000000000000000000000000000..f0c9509cff0290d38d943fe510fa8bc3b8b7e0bc
--- /dev/null
+++ b/game.xpr
@@ -0,0 +1,346 @@
+<?xml version="1.0" encoding="UTF-8"?>
+<!-- Product Version: Vivado v2022.2 (64-bit) -->
+<!-- -->
+<!-- Copyright 1986-2022 Xilinx, Inc. All Rights Reserved. -->
+
+<Project Version="7" Minor="61" Path="/home/prasic/game/game.xpr">
+ <DefaultLaunch Dir="$PRUNDIR"/>
+ <Configuration>
+ <Option Name="Id" Val="f61f24e91dfd467ea269621e05d60a9e"/>
+ <Option Name="Part" Val="xc7a100tcsg324-1"/>
+ <Option Name="CompiledLibDir" Val="$PCACHEDIR/compile_simlib"/>
+ <Option Name="CompiledLibDirXSim" Val=""/>
+ <Option Name="CompiledLibDirModelSim" Val="$PCACHEDIR/compile_simlib/modelsim"/>
+ <Option Name="CompiledLibDirQuesta" Val="$PCACHEDIR/compile_simlib/questa"/>
+ <Option Name="CompiledLibDirXcelium" Val="$PCACHEDIR/compile_simlib/xcelium"/>
+ <Option Name="CompiledLibDirVCS" Val="$PCACHEDIR/compile_simlib/vcs"/>
+ <Option Name="CompiledLibDirRiviera" Val="$PCACHEDIR/compile_simlib/riviera"/>
+ <Option Name="CompiledLibDirActivehdl" Val="$PCACHEDIR/compile_simlib/activehdl"/>
+ <Option Name="SimulatorInstallDirModelSim" Val=""/>
+ <Option Name="SimulatorInstallDirQuesta" Val=""/>
+ <Option Name="SimulatorInstallDirXcelium" Val=""/>
+ <Option Name="SimulatorInstallDirVCS" Val=""/>
+ <Option Name="SimulatorInstallDirRiviera" Val=""/>
+ <Option Name="SimulatorInstallDirActiveHdl" Val=""/>
+ <Option Name="SimulatorGccInstallDirModelSim" Val=""/>
+ <Option Name="SimulatorGccInstallDirQuesta" Val=""/>
+ <Option Name="SimulatorGccInstallDirXcelium" Val=""/>
+ <Option Name="SimulatorGccInstallDirVCS" Val=""/>
+ <Option Name="SimulatorGccInstallDirRiviera" Val=""/>
+ <Option Name="SimulatorGccInstallDirActiveHdl" Val=""/>
+ <Option Name="SimulatorVersionXsim" Val="2022.2"/>
+ <Option Name="SimulatorVersionModelSim" Val="2022.2"/>
+ <Option Name="SimulatorVersionQuesta" Val="2022.2"/>
+ <Option Name="SimulatorVersionXcelium" Val="21.09.009"/>
+ <Option Name="SimulatorVersionVCS" Val="S-2021.09"/>
+ <Option Name="SimulatorVersionRiviera" Val="2022.04"/>
+ <Option Name="SimulatorVersionActiveHdl" Val="13.0"/>
+ <Option Name="SimulatorGccVersionXsim" Val="6.2.0"/>
+ <Option Name="SimulatorGccVersionModelSim" Val="7.4.0"/>
+ <Option Name="SimulatorGccVersionQuesta" Val="7.4.0"/>
+ <Option Name="SimulatorGccVersionXcelium" Val="9.3.0"/>
+ <Option Name="SimulatorGccVersionVCS" Val="9.2.0"/>
+ <Option Name="SimulatorGccVersionRiviera" Val="9.3.0"/>
+ <Option Name="SimulatorGccVersionActiveHdl" Val="9.3.0"/>
+ <Option Name="TargetLanguage" Val="VHDL"/>
+ <Option Name="SimulatorLanguage" Val="VHDL"/>
+ <Option Name="BoardPart" Val=""/>
+ <Option Name="ActiveSimSet" Val="sim_1"/>
+ <Option Name="DefaultLib" Val="xil_defaultlib"/>
+ <Option Name="ProjectType" Val="Default"/>
+ <Option Name="IPOutputRepo" Val="$PCACHEDIR/ip"/>
+ <Option Name="IPDefaultOutputPath" Val="$PGENDIR/sources_1"/>
+ <Option Name="IPCachePermission" Val="read"/>
+ <Option Name="IPCachePermission" Val="write"/>
+ <Option Name="EnableCoreContainer" Val="FALSE"/>
+ <Option Name="EnableResourceEstimation" Val="FALSE"/>
+ <Option Name="SimCompileState" Val="TRUE"/>
+ <Option Name="CreateRefXciForCoreContainers" Val="FALSE"/>
+ <Option Name="IPUserFilesDir" Val="$PIPUSERFILESDIR"/>
+ <Option Name="IPStaticSourceDir" Val="$PIPUSERFILESDIR/ipstatic"/>
+ <Option Name="EnableBDX" Val="FALSE"/>
+ <Option Name="WTXSimLaunchSim" Val="32"/>
+ <Option Name="WTModelSimLaunchSim" Val="0"/>
+ <Option Name="WTQuestaLaunchSim" Val="0"/>
+ <Option Name="WTIesLaunchSim" Val="0"/>
+ <Option Name="WTVcsLaunchSim" Val="0"/>
+ <Option Name="WTRivieraLaunchSim" Val="0"/>
+ <Option Name="WTActivehdlLaunchSim" Val="0"/>
+ <Option Name="WTXSimExportSim" Val="2"/>
+ <Option Name="WTModelSimExportSim" Val="2"/>
+ <Option Name="WTQuestaExportSim" Val="2"/>
+ <Option Name="WTIesExportSim" Val="0"/>
+ <Option Name="WTVcsExportSim" Val="2"/>
+ <Option Name="WTRivieraExportSim" Val="2"/>
+ <Option Name="WTActivehdlExportSim" Val="2"/>
+ <Option Name="GenerateIPUpgradeLog" Val="TRUE"/>
+ <Option Name="XSimRadix" Val="hex"/>
+ <Option Name="XSimTimeUnit" Val="ns"/>
+ <Option Name="XSimArrayDisplayLimit" Val="1024"/>
+ <Option Name="XSimTraceLimit" Val="65536"/>
+ <Option Name="SimTypes" Val="rtl"/>
+ <Option Name="SimTypes" Val="bfm"/>
+ <Option Name="SimTypes" Val="tlm"/>
+ <Option Name="SimTypes" Val="tlm_dpi"/>
+ <Option Name="MEMEnableMemoryMapGeneration" Val="TRUE"/>
+ <Option Name="DcpsUptoDate" Val="TRUE"/>
+ <Option Name="ClassicSocBoot" Val="FALSE"/>
+ <Option Name="LocalIPRepoLeafDirName" Val="ip_repo"/>
+ </Configuration>
+ <FileSets Version="1" Minor="31">
+ <FileSet Name="sources_1" Type="DesignSrcs" RelSrcDir="$PSRCDIR/sources_1" RelGenDir="$PGENDIR/sources_1">
+ <Filter Type="Srcs"/>
+ <File Path="$PSRCDIR/sources_1/new/header.vhd">
+ <FileInfo>
+ <Attr Name="UsedIn" Val="synthesis"/>
+ <Attr Name="UsedIn" Val="simulation"/>
+ </FileInfo>
+ </File>
+ <File Path="$PSRCDIR/sources_1/new/background.vhd">
+ <FileInfo>
+ <Attr Name="UsedIn" Val="synthesis"/>
+ <Attr Name="UsedIn" Val="simulation"/>
+ </FileInfo>
+ </File>
+ <File Path="$PSRCDIR/sources_1/new/collision.vhd">
+ <FileInfo>
+ <Attr Name="UsedIn" Val="synthesis"/>
+ <Attr Name="UsedIn" Val="simulation"/>
+ </FileInfo>
+ </File>
+ <File Path="$PSRCDIR/sources_1/new/obstacle.vhd">
+ <FileInfo>
+ <Attr Name="UsedIn" Val="synthesis"/>
+ <Attr Name="UsedIn" Val="simulation"/>
+ </FileInfo>
+ </File>
+ <File Path="$PSRCDIR/sources_1/new/obstacle2.vhd">
+ <FileInfo>
+ <Attr Name="UsedIn" Val="synthesis"/>
+ <Attr Name="UsedIn" Val="simulation"/>
+ </FileInfo>
+ </File>
+ <File Path="$PSRCDIR/sources_1/new/priority.vhd">
+ <FileInfo>
+ <Attr Name="UsedIn" Val="synthesis"/>
+ <Attr Name="UsedIn" Val="simulation"/>
+ </FileInfo>
+ </File>
+ <File Path="$PSRCDIR/sources_1/new/runner.vhd">
+ <FileInfo>
+ <Attr Name="UsedIn" Val="synthesis"/>
+ <Attr Name="UsedIn" Val="simulation"/>
+ </FileInfo>
+ </File>
+ <File Path="$PSRCDIR/sources_1/new/vga.vhd">
+ <FileInfo>
+ <Attr Name="UsedIn" Val="synthesis"/>
+ <Attr Name="UsedIn" Val="simulation"/>
+ </FileInfo>
+ </File>
+ <File Path="$PSRCDIR/sources_1/new/TopModule.vhd">
+ <FileInfo>
+ <Attr Name="UsedIn" Val="synthesis"/>
+ <Attr Name="UsedIn" Val="simulation"/>
+ </FileInfo>
+ </File>
+ <File Path="$PSRCDIR/sources_1/ip/clk_wiz_1/clk_wiz_1.xci">
+ <FileInfo>
+ <Attr Name="AutoDisabled" Val="1"/>
+ <Attr Name="UsedIn" Val="synthesis"/>
+ <Attr Name="UsedIn" Val="implementation"/>
+ <Attr Name="UsedIn" Val="simulation"/>
+ </FileInfo>
+ </File>
+ <Config>
+ <Option Name="DesignMode" Val="RTL"/>
+ <Option Name="TopModule" Val="TopModule"/>
+ <Option Name="TopAutoSet" Val="TRUE"/>
+ </Config>
+ </FileSet>
+ <FileSet Name="constrs_1" Type="Constrs" RelSrcDir="$PSRCDIR/constrs_1" RelGenDir="$PGENDIR/constrs_1">
+ <Filter Type="Constrs"/>
+ <File Path="$PSRCDIR/constrs_1/imports/PrASIC_Data/Nexys4_Master.xdc">
+ <FileInfo>
+ <Attr Name="ImportPath" Val="$PPRDIR/../Schreibtisch/PrASIC_Data/Nexys4_Master.xdc"/>
+ <Attr Name="ImportTime" Val="1378293982"/>
+ <Attr Name="UsedIn" Val="synthesis"/>
+ <Attr Name="UsedIn" Val="implementation"/>
+ </FileInfo>
+ </File>
+ <Config>
+ <Option Name="ConstrsType" Val="XDC"/>
+ </Config>
+ </FileSet>
+ <FileSet Name="sim_1" Type="SimulationSrcs" RelSrcDir="$PSRCDIR/sim_1" RelGenDir="$PGENDIR/sim_1">
+ <Filter Type="Srcs"/>
+ <File Path="$PSRCDIR/sim_1/new/TopModule_tb.vhd">
+ <FileInfo>
+ <Attr Name="UsedIn" Val="synthesis"/>
+ <Attr Name="UsedIn" Val="simulation"/>
+ </FileInfo>
+ </File>
+ <File Path="$PSRCDIR/sim_1/new/vga_tb.vhd">
+ <FileInfo>
+ <Attr Name="AutoDisabled" Val="1"/>
+ <Attr Name="UsedIn" Val="synthesis"/>
+ <Attr Name="UsedIn" Val="simulation"/>
+ </FileInfo>
+ </File>
+ <File Path="$PPRDIR/TopModule_tb_behav.wcfg">
+ <FileInfo>
+ <Attr Name="UsedIn" Val="simulation"/>
+ </FileInfo>
+ </File>
+ <Config>
+ <Option Name="DesignMode" Val="RTL"/>
+ <Option Name="TopModule" Val="TopModule_tb"/>
+ <Option Name="TopLib" Val="xil_defaultlib"/>
+ <Option Name="TransportPathDelay" Val="0"/>
+ <Option Name="TransportIntDelay" Val="0"/>
+ <Option Name="SelectedSimModel" Val="rtl"/>
+ <Option Name="PamDesignTestbench" Val=""/>
+ <Option Name="PamDutBypassFile" Val="xil_dut_bypass"/>
+ <Option Name="PamSignalDriverFile" Val="xil_bypass_driver"/>
+ <Option Name="PamPseudoTop" Val="pseudo_tb"/>
+ <Option Name="SrcSet" Val="sources_1"/>
+ <Option Name="XSimWcfgFile" Val="$PPRDIR/TopModule_tb_behav.wcfg"/>
+ </Config>
+ </FileSet>
+ <FileSet Name="utils_1" Type="Utils" RelSrcDir="$PSRCDIR/utils_1" RelGenDir="$PGENDIR/utils_1">
+ <Filter Type="Utils"/>
+ <File Path="$PSRCDIR/utils_1/imports/synth_1/TopModule.dcp">
+ <FileInfo>
+ <Attr Name="UsedIn" Val="synthesis"/>
+ <Attr Name="UsedIn" Val="implementation"/>
+ <Attr Name="UsedInSteps" Val="synth_1"/>
+ <Attr Name="AutoDcp" Val="1"/>
+ </FileInfo>
+ </File>
+ <Config>
+ <Option Name="TopAutoSet" Val="TRUE"/>
+ </Config>
+ </FileSet>
+ <FileSet Name="clk_wiz_0" Type="BlockSrcs" RelSrcDir="$PSRCDIR/clk_wiz_0" RelGenDir="$PGENDIR/clk_wiz_0">
+ <File Path="$PSRCDIR/sources_1/ip/clk_wiz_0/clk_wiz_0.xci">
+ <FileInfo>
+ <Attr Name="UsedIn" Val="synthesis"/>
+ <Attr Name="UsedIn" Val="implementation"/>
+ <Attr Name="UsedIn" Val="simulation"/>
+ </FileInfo>
+ </File>
+ <Config>
+ <Option Name="TopModule" Val="clk_wiz_0"/>
+ <Option Name="UseBlackboxStub" Val="1"/>
+ </Config>
+ </FileSet>
+ </FileSets>
+ <Simulators>
+ <Simulator Name="XSim">
+ <Option Name="Description" Val="Vivado Simulator"/>
+ <Option Name="CompiledLib" Val="0"/>
+ </Simulator>
+ <Simulator Name="ModelSim">
+ <Option Name="Description" Val="ModelSim Simulator"/>
+ </Simulator>
+ <Simulator Name="Questa">
+ <Option Name="Description" Val="Questa Advanced Simulator"/>
+ </Simulator>
+ <Simulator Name="Xcelium">
+ <Option Name="Description" Val="Xcelium Parallel Simulator"/>
+ </Simulator>
+ <Simulator Name="VCS">
+ <Option Name="Description" Val="Verilog Compiler Simulator (VCS)"/>
+ </Simulator>
+ <Simulator Name="Riviera">
+ <Option Name="Description" Val="Riviera-PRO Simulator"/>
+ </Simulator>
+ </Simulators>
+ <Runs Version="1" Minor="19">
+ <Run Id="synth_1" Type="Ft3:Synth" SrcSet="sources_1" Part="xc7a100tcsg324-1" ConstrsSet="constrs_1" Description="Vivado Synthesis Defaults" AutoIncrementalCheckpoint="true" IncrementalCheckpoint="$PSRCDIR/utils_1/imports/synth_1/TopModule.dcp" WriteIncrSynthDcp="false" State="current" Dir="$PRUNDIR/synth_1" IncludeInArchive="true" IsChild="false" AutoIncrementalDir="$PSRCDIR/utils_1/imports/synth_1" AutoRQSDir="$PSRCDIR/utils_1/imports/synth_1">
+ <Strategy Version="1" Minor="2">
+ <StratHandle Name="Vivado Synthesis Defaults" Flow="Vivado Synthesis 2022"/>
+ <Step Id="synth_design"/>
+ </Strategy>
+ <GeneratedRun Dir="$PRUNDIR" File="gen_run.xml"/>
+ <ReportStrategy Name="Vivado Synthesis Default Reports" Flow="Vivado Synthesis 2022"/>
+ <Report Name="ROUTE_DESIGN.REPORT_METHODOLOGY" Enabled="1"/>
+ <RQSFiles/>
+ </Run>
+ <Run Id="clk_wiz_0_synth_1" Type="Ft3:Synth" SrcSet="clk_wiz_0" Part="xc7a100tcsg324-1" ConstrsSet="clk_wiz_0" Description="Vivado Synthesis Defaults" AutoIncrementalCheckpoint="false" WriteIncrSynthDcp="false" Dir="$PRUNDIR/clk_wiz_0_synth_1" IncludeInArchive="true" IsChild="false" AutoIncrementalDir="$PSRCDIR/utils_1/imports/clk_wiz_0_synth_1" AutoRQSDir="$PSRCDIR/utils_1/imports/clk_wiz_0_synth_1">
+ <Strategy Version="1" Minor="2">
+ <StratHandle Name="Vivado Synthesis Defaults" Flow="Vivado Synthesis 2022"/>
+ <Step Id="synth_design"/>
+ </Strategy>
+ <GeneratedRun Dir="$PRUNDIR" File="gen_run.xml"/>
+ <ReportStrategy Name="Vivado Synthesis Default Reports" Flow="Vivado Synthesis 2022"/>
+ <Report Name="ROUTE_DESIGN.REPORT_METHODOLOGY" Enabled="1"/>
+ <RQSFiles/>
+ </Run>
+ <Run Id="impl_1" Type="Ft2:EntireDesign" Part="xc7a100tcsg324-1" ConstrsSet="constrs_1" Description="Default settings for Implementation." AutoIncrementalCheckpoint="false" WriteIncrSynthDcp="false" State="current" Dir="$PRUNDIR/impl_1" SynthRun="synth_1" IncludeInArchive="true" IsChild="false" GenFullBitstream="true" AutoIncrementalDir="$PSRCDIR/utils_1/imports/impl_1" AutoRQSDir="$PSRCDIR/utils_1/imports/impl_1">
+ <Strategy Version="1" Minor="2">
+ <StratHandle Name="Vivado Implementation Defaults" Flow="Vivado Implementation 2022"/>
+ <Step Id="init_design"/>
+ <Step Id="opt_design"/>
+ <Step Id="power_opt_design"/>
+ <Step Id="place_design"/>
+ <Step Id="post_place_power_opt_design"/>
+ <Step Id="phys_opt_design"/>
+ <Step Id="route_design"/>
+ <Step Id="post_route_phys_opt_design"/>
+ <Step Id="write_bitstream"/>
+ </Strategy>
+ <GeneratedRun Dir="$PRUNDIR" File="gen_run.xml"/>
+ <ReportStrategy Name="Vivado Implementation Default Reports" Flow="Vivado Implementation 2022"/>
+ <Report Name="ROUTE_DESIGN.REPORT_METHODOLOGY" Enabled="1"/>
+ <RQSFiles/>
+ </Run>
+ <Run Id="clk_wiz_0_impl_1" Type="Ft2:EntireDesign" Part="xc7a100tcsg324-1" ConstrsSet="clk_wiz_0" Description="Default settings for Implementation." AutoIncrementalCheckpoint="false" WriteIncrSynthDcp="false" SynthRun="clk_wiz_0_synth_1" IncludeInArchive="false" IsChild="false" GenFullBitstream="true" AutoIncrementalDir="$PSRCDIR/utils_1/imports/clk_wiz_0_impl_1" AutoRQSDir="$PSRCDIR/utils_1/imports/clk_wiz_0_impl_1">
+ <Strategy Version="1" Minor="2">
+ <StratHandle Name="Vivado Implementation Defaults" Flow="Vivado Implementation 2022"/>
+ <Step Id="init_design"/>
+ <Step Id="opt_design"/>
+ <Step Id="power_opt_design"/>
+ <Step Id="place_design"/>
+ <Step Id="post_place_power_opt_design"/>
+ <Step Id="phys_opt_design"/>
+ <Step Id="route_design"/>
+ <Step Id="post_route_phys_opt_design"/>
+ <Step Id="write_bitstream"/>
+ </Strategy>
+ <ReportStrategy Name="Vivado Implementation Default Reports" Flow="Vivado Implementation 2022"/>
+ <Report Name="ROUTE_DESIGN.REPORT_METHODOLOGY" Enabled="1"/>
+ <RQSFiles/>
+ </Run>
+ </Runs>
+ <Board/>
+ <DashboardSummary Version="1" Minor="0">
+ <Dashboards>
+ <Dashboard Name="default_dashboard">
+ <Gadgets>
+ <Gadget Name="drc_1" Type="drc" Version="1" Row="2" Column="0">
+ <GadgetParam Name="REPORTS" Type="string_list" Value="impl_1#impl_1_route_report_drc_0 "/>
+ </Gadget>
+ <Gadget Name="methodology_1" Type="methodology" Version="1" Row="2" Column="1">
+ <GadgetParam Name="REPORTS" Type="string_list" Value="impl_1#impl_1_route_report_methodology_0 "/>
+ </Gadget>
+ <Gadget Name="power_1" Type="power" Version="1" Row="1" Column="0">
+ <GadgetParam Name="REPORTS" Type="string_list" Value="impl_1#impl_1_route_report_power_0 "/>
+ </Gadget>
+ <Gadget Name="timing_1" Type="timing" Version="1" Row="0" Column="1">
+ <GadgetParam Name="REPORTS" Type="string_list" Value="impl_1#impl_1_route_report_timing_summary_0 "/>
+ </Gadget>
+ <Gadget Name="utilization_1" Type="utilization" Version="1" Row="0" Column="0">
+ <GadgetParam Name="REPORTS" Type="string_list" Value="synth_1#synth_1_synth_report_utilization_0 "/>
+ <GadgetParam Name="RUN.STEP" Type="string" Value="synth_design"/>
+ <GadgetParam Name="RUN.TYPE" Type="string" Value="synthesis"/>
+ </Gadget>
+ <Gadget Name="utilization_2" Type="utilization" Version="1" Row="1" Column="1">
+ <GadgetParam Name="REPORTS" Type="string_list" Value="impl_1#impl_1_place_report_utilization_0 "/>
+ </Gadget>
+ </Gadgets>
+ </Dashboard>
+ <CurrentDashboard>default_dashboard</CurrentDashboard>
+ </Dashboards>
+ </DashboardSummary>
+</Project>