Commit 1a101f8d authored by Scott Beamer's avatar Scott Beamer Committed by Yunsup Lee
Browse files

don't use latches on mem ports for fpga

parent f4e6cd75
......@@ -6,7 +6,7 @@
import sys
import math
use_latches = 1
use_latches = False
module_template = '''module %s(
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