Commit 30d97673 authored by Christian Dietrich's avatar Christian Dietrich
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Update README for Repository

parent a3c9daac
Rocket Chip Generator
=====================
Rocket Chip Generator -- OSEK-V Variant
=======================================
This repository contains the Rocket chip generator necessary to instantiate
the RISC-V Rocket Core.
**Important: This is a fork of the Rocket chip generator!**
## Table of Contents
+ [Quick instructions](#quick) for those who want to dive directly into the details without knowing exactly what's in the repository.
......@@ -19,11 +21,9 @@ the RISC-V Rocket Core.
### Checkout The Code
$ git clone https://github.com/ucb-bar/rocket-chip.git
$ cd rocket-chip
$ git clone https://gitlab.cs.fau.de/osek-v/osek-v.git
$ cd osek-v
$ git submodule update --init
$ cd riscv-tools
$ git submodule update --init --recursive riscv-tests
### Setting up the RISCV environment variable
......@@ -33,46 +33,27 @@ do not yet have riscv-tools installed, please follow the directions in
the
[riscv-tools/README](https://github.com/riscv/riscv-tools/blob/master/README.md).
**Please be aware, that you need the modified gnu-binutils to support the osek instruction.**
$ export RISCV=/path/to/riscv/toolchain/installation
### Building The Project
First, to build the C simulator:
First, to build the dOSEK baseline variant, other variants are
{config_normal, config_specialized, config_fsm}. For the I4Copter, you
need to set the OSEK_APP variable to "bench-coptermock"
$ make config_fsm_alarms
$ export OSEK_APP=bcc1_alarm1a
$ cd emulator
$ make
$ make run timeout_cycles=10000000
Or to build the VCS simulator:
$ cd vsim
$ make
In either case, you can run a set of assembly tests or simple benchmarks
(Assuming you have N cores on your host system):
$ make -jN run-asm-tests
$ make -jN run-bmark-tests
To build a C simulator that is capable of VCD waveform generation:
$ cd emulator
$ make debug
And to run the assembly tests on the C simulator and generate waveforms:
$ make -jN run-asm-tests-debug
$ make -jN run-bmark-tests-debug
To generate FPGA-synthesizable verilog (output will be in `fsim/generated-src`):
$ cd fsim
$ make verilog
Similarly, to generate VLSI-synthesizable verilog (output will be in `vsim/generated-src`):
------------------
$ cd vsim
$ make verilog
**From here it is the normal Rocket chip README. Be careful.**
------------------
### Updating To A Newer Version Of Chisel
To grab a newer version of chisel:
......
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