Commit d3a8a224 authored by Scott Beamer's avatar Scott Beamer
Browse files

README updated for new fpga flow

parent e390eba8
......@@ -58,6 +58,11 @@ And to run the assembly tests on the C simulator and generate waveforms:
$ make run-vecasm-timer-tests-debug
$ make run-bmarks-test-debug
To FPGA-synthesizable verilog (output will be in `/fpga/generated-src`):
$ cd fpga/build/syn
$ make
Updating To A Newer Version Of Chisel
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