From bdce3c74eaf103b3f33cbc418051e5d9304963e3 Mon Sep 17 00:00:00 2001
From: Luis Gerhorst <privat@luisgerhorst.de>
Date: Wed, 9 Dec 2020 09:49:24 +0100
Subject: [PATCH] Inline PBASE 0x3f000000
---
boards/arm/qemu_raspi3/bcm2835-common.dtsi | 48 +++++------
boards/arm/qemu_raspi3/bcm2835-rpi.dtsi | 4 +-
boards/arm/qemu_raspi3/bcm2837.dtsi | 4 +-
boards/arm/qemu_raspi3/bcm283x.dtsi | 92 +++++++++++-----------
4 files changed, 73 insertions(+), 75 deletions(-)
diff --git a/boards/arm/qemu_raspi3/bcm2835-common.dtsi b/boards/arm/qemu_raspi3/bcm2835-common.dtsi
index 4119271c979..5b4aa25d09a 100644
--- a/boards/arm/qemu_raspi3/bcm2835-common.dtsi
+++ b/boards/arm/qemu_raspi3/bcm2835-common.dtsi
@@ -8,9 +8,9 @@
interrupt-parent = <&intc>;
soc {
- dma: dma@7e007000 {
+ dma: dma@3f007000 {
compatible = "brcm,bcm2835-dma";
- reg = <0x7e007000 0xf00>;
+ reg = <0x3f007000 0xf00>;
interrupts = <1 16>,
<1 17>,
<1 18>,
@@ -49,19 +49,19 @@
brcm,dma-channel-mask = <0x7f35>;
};
- intc: interrupt-controller@7e00b200 {
+ intc: interrupt-controller@3f00b200 {
compatible = "brcm,bcm2835-armctrl-ic";
- reg = <0x7e00b200 0x200>;
+ reg = <0x3f00b200 0x200>;
interrupt-controller;
#interrupt-cells = <2>;
};
- pm: watchdog@7e100000 {
+ pm: watchdog@3f100000 {
compatible = "brcm,bcm2835-pm", "brcm,bcm2835-pm-wdt";
#power-domain-cells = <1>;
#reset-cells = <1>;
- reg = <0x7e100000 0x114>,
- <0x7e00a000 0x24>;
+ reg = <0x3f100000 0x114>,
+ <0x3f00a000 0x24>;
clocks = <&clocks BCM2835_CLOCK_V3D>,
<&clocks BCM2835_CLOCK_PERI_IMAGE>,
<&clocks BCM2835_CLOCK_H264>,
@@ -70,35 +70,35 @@
system-power-controller;
};
- rng@7e104000 {
+ rng@3f104000 {
compatible = "brcm,bcm2835-rng";
- reg = <0x7e104000 0x10>;
+ reg = <0x3f104000 0x10>;
interrupts = <2 29>;
};
- pixelvalve@7e206000 {
+ pixelvalve@3f206000 {
compatible = "brcm,bcm2835-pixelvalve0";
- reg = <0x7e206000 0x100>;
+ reg = <0x3f206000 0x100>;
interrupts = <2 13>; /* pwa0 */
};
- pixelvalve@7e207000 {
+ pixelvalve@3f207000 {
compatible = "brcm,bcm2835-pixelvalve1";
- reg = <0x7e207000 0x100>;
+ reg = <0x3f207000 0x100>;
interrupts = <2 14>; /* pwa1 */
};
- thermal: thermal@7e212000 {
+ thermal: thermal@3f212000 {
compatible = "brcm,bcm2835-thermal";
- reg = <0x7e212000 0x8>;
+ reg = <0x3f212000 0x8>;
clocks = <&clocks BCM2835_CLOCK_TSENS>;
#thermal-sensor-cells = <0>;
status = "disabled";
};
- i2c2: i2c@7e805000 {
+ i2c2: i2c@3f805000 {
compatible = "brcm,bcm2835-i2c";
- reg = <0x7e805000 0x1000>;
+ reg = <0x3f805000 0x1000>;
interrupts = <2 21>;
clocks = <&clocks BCM2835_CLOCK_VPU>;
#address-cells = <1>;
@@ -106,16 +106,16 @@
status = "okay";
};
- pixelvalve@7e807000 {
+ pixelvalve@3f807000 {
compatible = "brcm,bcm2835-pixelvalve2";
- reg = <0x7e807000 0x100>;
+ reg = <0x3f807000 0x100>;
interrupts = <2 10>; /* pixelvalve */
};
- hdmi: hdmi@7e902000 {
+ hdmi: hdmi@3f902000 {
compatible = "brcm,bcm2835-hdmi";
- reg = <0x7e902000 0x600>,
- <0x7e808000 0x100>;
+ reg = <0x3f902000 0x600>,
+ <0x3f808000 0x100>;
interrupts = <2 8>, <2 9>;
ddc = <&i2c2>;
clocks = <&clocks BCM2835_PLLH_PIX>,
@@ -126,9 +126,9 @@
status = "disabled";
};
- v3d: v3d@7ec00000 {
+ v3d: v3d@3fc00000 {
compatible = "brcm,bcm2835-v3d";
- reg = <0x7ec00000 0x1000>;
+ reg = <0x3fc00000 0x1000>;
interrupts = <1 10>;
};
diff --git a/boards/arm/qemu_raspi3/bcm2835-rpi.dtsi b/boards/arm/qemu_raspi3/bcm2835-rpi.dtsi
index 559fcdefd24..3dce4828279 100644
--- a/boards/arm/qemu_raspi3/bcm2835-rpi.dtsi
+++ b/boards/arm/qemu_raspi3/bcm2835-rpi.dtsi
@@ -27,9 +27,9 @@
#power-domain-cells = <1>;
};
- vchiq: mailbox@7e00b840 {
+ vchiq: mailbox@3f00b840 {
compatible = "brcm,bcm2835-vchiq";
- reg = <0x7e00b840 0x3c>;
+ reg = <0x3f00b840 0x3c>;
interrupts = <0 2>;
};
};
diff --git a/boards/arm/qemu_raspi3/bcm2837.dtsi b/boards/arm/qemu_raspi3/bcm2837.dtsi
index 0199ec98cd6..2e1eb7c1ad7 100644
--- a/boards/arm/qemu_raspi3/bcm2837.dtsi
+++ b/boards/arm/qemu_raspi3/bcm2837.dtsi
@@ -6,8 +6,6 @@
compatible = "brcm,bcm2837";
soc {
- ranges = <0x7e000000 0x3f000000 0x1000000>,
- <0x40000000 0x40000000 0x00001000>;
dma-ranges = <0xc0000000 0x00000000 0x3f000000>;
local_intc: local_intc@40000000 {
@@ -79,7 +77,7 @@
*/
&intc {
compatible = "brcm,bcm2836-armctrl-ic";
- reg = <0x7e00b200 0x200>;
+ reg = <0x3f00b200 0x200>;
interrupt-parent = <&local_intc>;
interrupts = <8 IRQ_TYPE_LEVEL_HIGH>;
};
diff --git a/boards/arm/qemu_raspi3/bcm283x.dtsi b/boards/arm/qemu_raspi3/bcm283x.dtsi
index 1be1299c302..375349f85f4 100644
--- a/boards/arm/qemu_raspi3/bcm283x.dtsi
+++ b/boards/arm/qemu_raspi3/bcm283x.dtsi
@@ -66,9 +66,9 @@
#address-cells = <1>;
#size-cells = <1>;
- system_timer: timer@7e003000 {
+ system_timer: timer@3f003000 {
compatible = "brcm,bcm2835-system-timer";
- reg = <0x7e003000 0x1000>;
+ reg = <0x3f003000 0x1000>;
interrupts = <1 0>, <1 1>, <1 2>, <1 3>;
/* This could be a reference to BCM2835_CLOCK_TIMER,
* but we don't have the driver using the common clock
@@ -77,16 +77,16 @@
clock-frequency = <1000000>;
};
- txp: txp@7e004000 {
+ txp: txp@3f004000 {
compatible = "brcm,bcm2835-txp";
- reg = <0x7e004000 0x20>;
+ reg = <0x3f004000 0x20>;
interrupts = <1 11>;
};
- clocks: cprman@7e101000 {
+ clocks: cprman@3f101000 {
compatible = "brcm,bcm2835-cprman";
#clock-cells = <1>;
- reg = <0x7e101000 0x2000>;
+ reg = <0x3f101000 0x2000>;
/* CPRMAN derives almost everything from the
* platform's oscillator. However, the DSI
@@ -97,16 +97,16 @@
<&dsi1 0>, <&dsi1 1>, <&dsi1 2>;
};
- mailbox: mailbox@7e00b880 {
+ mailbox: mailbox@3f00b880 {
compatible = "brcm,bcm2835-mbox";
- reg = <0x7e00b880 0x40>;
+ reg = <0x3f00b880 0x40>;
interrupts = <0 1>;
#mbox-cells = <0>;
};
- gpio: gpio@7e200000 {
+ gpio: gpio@3f200000 {
compatible = "brcm,bcm2835-gpio";
- reg = <0x7e200000 0xb4>;
+ reg = <0x3f200000 0xb4>;
/*
* The GPIO IP block is designed for 3 banks of GPIOs.
* Each bank has a GPIO interrupt for itself.
@@ -299,9 +299,9 @@
};
};
- uart0: serial@7e201000 {
+ uart0: serial@3f201000 {
compatible = "arm,pl011", "arm,primecell";
- reg = <0x7e201000 0x200>;
+ reg = <0x3f201000 0x200>;
interrupts = <2 25>;
clocks = <&clocks BCM2835_CLOCK_UART>,
<&clocks BCM2835_CLOCK_VPU>;
@@ -309,24 +309,24 @@
arm,primecell-periphid = <0x00241011>;
};
- sdhost: mmc@7e202000 {
+ sdhost: mmc@3f202000 {
compatible = "brcm,bcm2835-sdhost";
- reg = <0x7e202000 0x100>;
+ reg = <0x3f202000 0x100>;
interrupts = <2 24>;
clocks = <&clocks BCM2835_CLOCK_VPU>;
status = "disabled";
};
- i2s: i2s@7e203000 {
+ i2s: i2s@3f203000 {
compatible = "brcm,bcm2835-i2s";
- reg = <0x7e203000 0x24>;
+ reg = <0x3f203000 0x24>;
clocks = <&clocks BCM2835_CLOCK_PCM>;
status = "disabled";
};
- spi: spi@7e204000 {
+ spi: spi@3f204000 {
compatible = "brcm,bcm2835-spi";
- reg = <0x7e204000 0x200>;
+ reg = <0x3f204000 0x200>;
interrupts = <2 22>;
clocks = <&clocks BCM2835_CLOCK_VPU>;
#address-cells = <1>;
@@ -334,9 +334,9 @@
status = "disabled";
};
- i2c0: i2c@7e205000 {
+ i2c0: i2c@3f205000 {
compatible = "brcm,bcm2835-i2c";
- reg = <0x7e205000 0x200>;
+ reg = <0x3f205000 0x200>;
interrupts = <2 21>;
clocks = <&clocks BCM2835_CLOCK_VPU>;
#address-cells = <1>;
@@ -344,9 +344,9 @@
status = "disabled";
};
- dpi: dpi@7e208000 {
+ dpi: dpi@3f208000 {
compatible = "brcm,bcm2835-dpi";
- reg = <0x7e208000 0x8c>;
+ reg = <0x3f208000 0x8c>;
clocks = <&clocks BCM2835_CLOCK_VPU>,
<&clocks BCM2835_CLOCK_DPI>;
clock-names = "core", "pixel";
@@ -355,9 +355,9 @@
status = "disabled";
};
- dsi0: dsi@7e209000 {
+ dsi0: dsi@3f209000 {
compatible = "brcm,bcm2835-dsi0";
- reg = <0x7e209000 0x78>;
+ reg = <0x3f209000 0x78>;
interrupts = <2 4>;
#address-cells = <1>;
#size-cells = <0>;
@@ -375,24 +375,24 @@
status = "disabled";
};
- aux: aux@7e215000 {
+ aux: aux@3f215000 {
compatible = "brcm,bcm2835-aux";
#clock-cells = <1>;
- reg = <0x7e215000 0x8>;
+ reg = <0x3f215000 0x8>;
clocks = <&clocks BCM2835_CLOCK_VPU>;
};
- uart1: serial@7e215040 {
+ uart1: serial@3f215040 {
compatible = "brcm,bcm2835-aux-uart";
- reg = <0x7e215040 0x40>;
+ reg = <0x3f215040 0x40>;
interrupts = <1 29>;
clocks = <&aux BCM2835_AUX_CLOCK_UART>;
status = "disabled";
};
- spi1: spi@7e215080 {
+ spi1: spi@3f215080 {
compatible = "brcm,bcm2835-aux-spi";
- reg = <0x7e215080 0x40>;
+ reg = <0x3f215080 0x40>;
interrupts = <1 29>;
clocks = <&aux BCM2835_AUX_CLOCK_SPI1>;
#address-cells = <1>;
@@ -400,9 +400,9 @@
status = "disabled";
};
- spi2: spi@7e2150c0 {
+ spi2: spi@3f2150c0 {
compatible = "brcm,bcm2835-aux-spi";
- reg = <0x7e2150c0 0x40>;
+ reg = <0x3f2150c0 0x40>;
interrupts = <1 29>;
clocks = <&aux BCM2835_AUX_CLOCK_SPI2>;
#address-cells = <1>;
@@ -410,9 +410,9 @@
status = "disabled";
};
- pwm: pwm@7e20c000 {
+ pwm: pwm@3f20c000 {
compatible = "brcm,bcm2835-pwm";
- reg = <0x7e20c000 0x28>;
+ reg = <0x3f20c000 0x28>;
clocks = <&clocks BCM2835_CLOCK_PWM>;
assigned-clocks = <&clocks BCM2835_CLOCK_PWM>;
assigned-clock-rates = <10000000>;
@@ -420,23 +420,23 @@
status = "disabled";
};
- sdhci: sdhci@7e300000 {
+ sdhci: sdhci@3f300000 {
compatible = "brcm,bcm2835-sdhci";
- reg = <0x7e300000 0x100>;
+ reg = <0x3f300000 0x100>;
interrupts = <2 30>;
clocks = <&clocks BCM2835_CLOCK_EMMC>;
status = "disabled";
};
- hvs@7e400000 {
+ hvs@3f400000 {
compatible = "brcm,bcm2835-hvs";
- reg = <0x7e400000 0x6000>;
+ reg = <0x3f400000 0x6000>;
interrupts = <2 1>;
};
- dsi1: dsi@7e700000 {
+ dsi1: dsi@3f700000 {
compatible = "brcm,bcm2835-dsi1";
- reg = <0x7e700000 0x8c>;
+ reg = <0x3f700000 0x8c>;
interrupts = <2 12>;
#address-cells = <1>;
#size-cells = <0>;
@@ -454,9 +454,9 @@
status = "disabled";
};
- i2c1: i2c@7e804000 {
+ i2c1: i2c@3f804000 {
compatible = "brcm,bcm2835-i2c";
- reg = <0x7e804000 0x1000>;
+ reg = <0x3f804000 0x1000>;
interrupts = <2 21>;
clocks = <&clocks BCM2835_CLOCK_VPU>;
#address-cells = <1>;
@@ -464,17 +464,17 @@
status = "disabled";
};
- vec: vec@7e806000 {
+ vec: vec@3f806000 {
compatible = "brcm,bcm2835-vec";
- reg = <0x7e806000 0x1000>;
+ reg = <0x3f806000 0x1000>;
clocks = <&clocks BCM2835_CLOCK_VEC>;
interrupts = <2 27>;
status = "disabled";
};
- usb: usb@7e980000 {
+ usb: usb@3f980000 {
compatible = "brcm,bcm2835-usb";
- reg = <0x7e980000 0x10000>;
+ reg = <0x3f980000 0x10000>;
interrupts = <1 9>;
#address-cells = <1>;
#size-cells = <0>;
--
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