From e6d8dcb4010ef6d19a7c18f3b978cacdc03c0621 Mon Sep 17 00:00:00 2001
From: Luis Gerhorst <privat@luisgerhorst.de>
Date: Fri, 11 Dec 2020 14:34:49 +0100
Subject: [PATCH] Debug prints for arm_mmu

---
 arch/arm/core/aarch64/arm_mmu.c | 5 ++++-
 1 file changed, 4 insertions(+), 1 deletion(-)

diff --git a/arch/arm/core/aarch64/arm_mmu.c b/arch/arm/core/aarch64/arm_mmu.c
index 2445d551072..a8128cb37d4 100644
--- a/arch/arm/core/aarch64/arm_mmu.c
+++ b/arch/arm/core/aarch64/arm_mmu.c
@@ -405,6 +405,8 @@ static void enable_mmu_el1(unsigned int flags)
 	/* Ensure these changes are seen before MMU is enabled */
 	__ISB();
 
+	MMU_DEBUG("Set MAIR, TCR and TBBR registers.\n");
+
 	/* Enable the MMU and data cache */
 	__asm__ volatile("mrs %0, sctlr_el1" : "=r" (val));
 	__asm__ volatile("msr sctlr_el1, %0"
@@ -415,6 +417,8 @@ static void enable_mmu_el1(unsigned int flags)
 	/* Ensure the MMU enable takes effect immediately */
 	__ISB();
 
+	/* TODO: raspi3: why is uart broken after this? */
+
 	MMU_DEBUG("MMU enabled with dcache\n");
 }
 
@@ -450,7 +454,6 @@ static int arm_mmu_init(const struct device *arg)
 	setup_page_tables();
 
 	/* currently only EL1 is supported */
-	MMU_DEBUG("enable_mmu_el1\n");
 	enable_mmu_el1(flags);
 
 	return 0;
-- 
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