Fix LDM addressing mode disassembly

The Pixelflinger disassembler does not handle LDM addressing modes correctly,
assuming that the P and U bits in the instruction mean the same in both LDM and
STM. This results in the disassembler producing sequences like:

  stmfd r13!, {r4-r11, r14}
  ...
  ...
  ...
  ldmea r13!, {r4-r11, r14}

This small patch fixes it by EORing the P and U bits with the Load/Store bit.

Change-Id: Ic7a1556642c4e29415fc3697019f1239b6c26fc2

libpixelflinger/codeflinger/disassem.c

@@ -278,7 +278,7 @@ static char const insn_fpaconstants[][8] = {
 
 #define insn_condition(x)	arm32_insn_conditions[(x >> 28) & 0x0f]
 #define insn_blktrans(x)	insn_block_transfers[(x >> 23) & 3]
-#define insn_stkblktrans(x)	insn_stack_block_transfers[(x >> 23) & 3]
+#define insn_stkblktrans(x)	insn_stack_block_transfers[(3*((x >> 20)&1))^((x >> 23)&3)]
 #define op2_shift(x)		op_shifts[(x >> 5) & 3]
 #define insn_fparnd(x)		insn_fpa_rounding[(x >> 5) & 0x03]
 #define insn_fpaprec(x)		insn_fpa_precision[(((x >> 18) & 2)|(x >> 7)) & 1]