added lecture 5

Lectures/lecture_03/lecture_03.tex

@@ -28,7 +28,7 @@ $\Longrightarrow$ good pipelining support
     \item
         Each instruction has to pass sequentially through all units
     \item
-        parallel execution of instructions\\\\
+        parallel execution of instructions $\rightarrow$ increases instruction throughput\\\\
         \includegraphics[width=\textwidth]{Lectures/lecture_03/images/Pipelining.png}
     \item
         requisites:

Lectures/lecture_04/lecture_04.tex

@@ -4,13 +4,13 @@
 \begin{itemize}[leftmargin=*]
     \item
         \textbf{Structural Hazard}
-        \begin{itemize}
+        \begin{itemize}[leftmargin=*]
             \item 
                 two (or more) instructions that are already in pipeline need the same resource 
         \end{itemize}
     \item 
         \textbf{Data Hazards}
-        \begin{itemize}
+        \begin{itemize}[leftmargin=*]
             \item
                 Read after Write (RAW) - true dependency\\
                 instr2 reads operand before instr1 writes it back, e.g.:
@@ -53,7 +53,7 @@
             \clearpage
             \item
                 \underline{Countermeasures:}
-                \begin{itemize}
+                \begin{itemize}[leftmargin=*]
                     \item 
                         forwarding:
                         \begin{itemize}
@@ -86,13 +86,13 @@
         \end{itemize}
     \item
         \textbf{Control Hazard}
-        \begin{itemize}
+        \begin{itemize}[leftmargin=*]
             \item 
                 instructions in the pipeline are not the right ones due to branching; 
                 branch address only available at later pipeline stages
             \item
                 Solution: dynamic branch prediction         
-                \begin{itemize}
+                \begin{itemize}[leftmargin=*]
                     \item
                         \begin{minipage}{0.7\textwidth}
                             \begin{itemize}[leftmargin=*]
@@ -104,7 +104,7 @@
                             \end{itemize}
                         \end{minipage}
                         \begin{minipage}{0.2\textwidth}
-                            \includegraphics[width=\textwidth]{Lectures/lecture_04/image/twoBitHistory.png}
+                            \includegraphics[width=\textwidth]{Lectures/lecture_04/images/twoBitHistory.png}
                         \end{minipage}
                     \item
                             \underline{Branch Prediction Buffer:}

Lectures/lecture_05/lecture_05.tex

+\section{Lecture 5}
+
+\underline{\textbf{Superscalar}}
+\begin{itemize}[leftmargin=*]
+    \item 
+        grouping and dispatching multiple instructions to different execution units
+    \item[]
+        \begin{center}
+            \includegraphics[width=0.5\textwidth]{Lectures/lecture_05/images/superscalar.png}
+        \end{center}
+    \item
+        \underline{requirements:}
+        \begin{itemize}[leftmargin=*]
+            \item 
+                hardware that determines which instructions can be executed in parallel:
+                out-of-order execution
+            \item
+                fetching of multiple instructions per cycle:\\
+                increasing the width of data path
+            \item
+                decoding and executing of multiple instructions per cycle:\\
+                increasing number of decode and execution units
+            \item
+                writing back of multiple instructions per cycle:\\
+                multiple data paths from ALU to register
+        \end{itemize}
+\end{itemize}
+\underline{\textbf{DRAM vs. SRAM}}
+\begin{itemize}[leftmargin=*]
+    \item 
+        main memory is typically made from DRAM (dynamic RAM)
+    \item
+        caches are typically made from SRAM (static RAM)
+\end{itemize}
+\begin{center}
+    \begin{tabular}{c|c|c}
+        & DRAM & SRAM\\\hline
+        speed & slow & fast\\
+        cost & less expensive & more expensive\\
+        size & smaller & bigger\\
+        storage capacity & in GB & in MB\\
+        power consumption & high (needs to refresh data) & low\\
+\end{tabular}
+\end{center}
+\clearpage
+\underline{\textbf{memory hierarchy}}
+\begin{itemize}[leftmargin=*]
+    \item 
+        problem: memory-processor gap due to processor clock speed increasing at a higher rate than memory clock speed $\rightarrow$ processor starved of data, idle most of the time
+    \item
+        solution: most programs exhibit \textbf{temporal} and \textbf{spatial locality}
+        \begin{itemize}[leftmargin=*]
+            \item 
+                temporal locality: if data at address x has been used before, it is likely to be used again 
+                (e.g., accessing important data structures repeatedly)
+            \item
+                spacial locality: If data at address y has been accessed, it is likely that data at address 
+                y+1 will be accessed in the future (e.g., accessing arrays)
+        \end{itemize}
+        $\Longrightarrow$ caches can speed up program
+    \item[]
+        \includegraphics[width=\textwidth]{Lectures/lecture_05/images/memoryHierarchy.png}
+\end{itemize}
+

main.tex

@@ -48,5 +48,7 @@
 \input{Lectures/lecture_03/lecture_03}
 \clearpage
 \input{Lectures/lecture_04/lecture_04}
+\clearpage
+\input{Lectures/lecture_05/lecture_05}
 
 \end{document}
\ No newline at end of file